sys/net/i4b/layer1/iwic/i4b_iwic_dchan.c

   1 /*
   2  * Copyright (c) 1999, 2000 Dave Boyce. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  *---------------------------------------------------------------------------
  26  *
  27  *      i4b_iwic - isdn4bsd Winbond W6692 driver
  28  *      ----------------------------------------
  29  *
  30  * $FreeBSD: src/sys/i4b/layer1/iwic/i4b_iwic_dchan.c,v 1.4.2.1 2001/08/10 14:08:40 obrien Exp $
  31  *
  32  *      last edit-date: [Tue Jan 16 13:20:14 2001]
  33  *
  34  *---------------------------------------------------------------------------*/
  35
  36 #include "iwic.h"
  37 #include "opt_i4b.h"
  38 #include "pci.h"
  39
  40 #if (NIWIC > 0) && (NPCI > 0)
  41
  42 #include <sys/param.h>
  43 #include <sys/systm.h>
  44 #include <sys/mbuf.h>
  45 #include <sys/socket.h>
  46
  47 #include <net/if.h>
  48
  49
  50 #include <machine/i4b_debug.h>
  51 #include <machine/i4b_ioctl.h>
  52 #include <machine/i4b_trace.h>
  53
  54 #include <i4b/layer1/i4b_l1.h>
  55
  56 #include <i4b/include/i4b_global.h>
  57 #include <i4b/include/i4b_l3l4.h>
  58 #include <i4b/include/i4b_mbuf.h>
  59
  60 #include <i4b/layer1/iwic/i4b_iwic.h>
  61 #include <i4b/layer1/iwic/i4b_w6692.h>
  62
  63 #define MAX_DFRAME_LEN  264
  64
  65 static void dchan_receive(struct iwic_softc *sc, int ista);
  66
  67 /*---------------------------------------------------------------------------*
  68  *      initialize D-channel variables and registers
  69  *---------------------------------------------------------------------------*/
  70 void
  71 iwic_dchan_init(struct iwic_softc *sc)
  72 {
  73         sc->sc_dchan.ibuf = NULL;
  74         sc->sc_dchan.rx_count = 0;
  75
  76         sc->sc_dchan.obuf = NULL;
  77         sc->sc_dchan.obuf2 = NULL;
  78         sc->sc_dchan.tx_count = 0;
  79         sc->sc_dchan.tx_ready = 0;
  80
  81         IWIC_WRITE(sc, D_CTL, D_CTL_SRST);
  82
  83         DELAY(5000);
  84
  85         IWIC_WRITE(sc, D_CTL, 0);
  86
  87         IWIC_WRITE(sc, SQX, SQX_SCIE);
  88
  89         IWIC_WRITE(sc, PCTL, 0x00);
  90         IWIC_WRITE(sc, MOCR, 0x00);
  91         IWIC_WRITE(sc, GCR, 0x00);
  92
  93         IWIC_WRITE(sc, D_CMDR, D_CMDR_RRST | D_CMDR_XRST);
  94         IWIC_WRITE(sc, D_MODE, D_MODE_RACT);
  95
  96         IWIC_WRITE(sc, D_SAM, 0xff);
  97         IWIC_WRITE(sc, D_TAM, 0xff);
  98
  99         IWIC_WRITE(sc, D_EXIM, 0x00);
 100 }
 101
 102 /*---------------------------------------------------------------------------*
 103  *      Extended IRQ handler for the D-channel
 104  *---------------------------------------------------------------------------*/
 105 void
 106 iwic_dchan_xirq(struct iwic_softc *sc)
 107 {
 108         int irq_stat;
 109         int stat;
 110
 111         irq_stat = IWIC_READ(sc, D_EXIR);
 112
 113         if (irq_stat & D_EXIR_RDOV)
 114         {
 115                 NDBGL1(L1_I_ERR, "RDOV in state %s", iwic_printstate(sc));
 116                 IWIC_WRITE(sc, D_CMDR, D_CMDR_RRST);
 117         }
 118         if (irq_stat & D_EXIR_XDUN)
 119         {
 120                 NDBGL1(L1_I_ERR, "XDUN in state %s", iwic_printstate(sc));
 121                 sc->sc_dchan.tx_ready = 0;
 122         }
 123         if (irq_stat & D_EXIR_XCOL)
 124         {
 125                 NDBGL1(L1_I_ERR, "XCOL in state %s", iwic_printstate(sc));
 126                 IWIC_WRITE(sc, D_CMDR, D_CMDR_XRST);
 127                 sc->sc_dchan.tx_ready = 0;
 128         }
 129         if (irq_stat & D_EXIR_TIN2)
 130         {
 131                 NDBGL1(L1_I_ERR, "TIN2 in state %s", iwic_printstate(sc));
 132         }
 133         if (irq_stat & D_EXIR_MOC)
 134         {
 135                 stat = IWIC_READ(sc, MOR);
 136                 NDBGL1(L1_I_ERR, "MOC in state %s, byte = 0x%x", iwic_printstate(sc), stat);
 137         }
 138
 139         if (irq_stat & D_EXIR_ISC)
 140         {
 141                 stat = (IWIC_READ(sc, CIR)) & 0x0f;
 142
 143                 switch (stat)
 144                 {
 145                         case CIR_CE:
 146                                 NDBGL1(L1_I_CICO, "rx CE in state %s", iwic_printstate(sc));
 147                                 iwic_next_state(sc, EV_CE);
 148                                 break;
 149                         case CIR_DRD:
 150                                 NDBGL1(L1_I_CICO, "rx DRD in state %s", iwic_printstate(sc));
 151                                 iwic_next_state(sc, EV_INFO0);
 152                                 i4b_l1_mph_status_ind(L0IWICUNIT(sc->sc_unit), STI_L1STAT, LAYER_IDLE, NULL);
 153                                 break;
 154                         case CIR_LD:
 155                                 NDBGL1(L1_I_CICO, "rx LD in state %s", iwic_printstate(sc));
 156                                 iwic_next_state(sc, EV_RSY);
 157                                 break;
 158                         case CIR_ARD:
 159                                 NDBGL1(L1_I_CICO, "rx ARD in state %s", iwic_printstate(sc));
 160                                 iwic_next_state(sc, EV_INFO2);
 161                                 break;
 162                         case CIR_TI:
 163                                 NDBGL1(L1_I_CICO, "rx TI in state %s", iwic_printstate(sc));
 164                                 iwic_next_state(sc, EV_INFO0);
 165                                 break;
 166                         case CIR_ATI:
 167                                 NDBGL1(L1_I_CICO, "rx ATI in state %s", iwic_printstate(sc));
 168                                 iwic_next_state(sc, EV_INFO0);
 169                                 break;
 170                         case CIR_AI8:
 171                                 NDBGL1(L1_I_CICO, "rx AI8 in state %s", iwic_printstate(sc));
 172                                 i4b_l1_mph_status_ind(L0IWICUNIT(sc->sc_unit), STI_L1STAT, LAYER_ACTIVE, NULL);
 173                                 iwic_next_state(sc, EV_INFO48);
 174                                 break;
 175                         case CIR_AI10:
 176                                 NDBGL1(L1_I_CICO, "rx AI10 in state %s", iwic_printstate(sc));
 177                                 i4b_l1_mph_status_ind(L0IWICUNIT(sc->sc_unit), STI_L1STAT, LAYER_ACTIVE, NULL);
 178                                 iwic_next_state(sc, EV_INFO410);
 179                                 break;
 180                         case CIR_CD:
 181                                 NDBGL1(L1_I_CICO, "rx DIS in state %s", iwic_printstate(sc));
 182                                 iwic_next_state(sc, EV_DIS);
 183                                 break;
 184                         default:
 185                                 NDBGL1(L1_I_ERR, "ERROR, unknown indication 0x%x in state %s", stat, iwic_printstate(sc));
 186                                 iwic_next_state(sc, EV_INFO0);
 187                                 break;
 188                 }
 189         }
 190
 191         if (irq_stat & D_EXIR_TEXP)
 192         {
 193                 NDBGL1(L1_I_ERR, "TEXP in state %s", iwic_printstate(sc));
 194         }
 195
 196         if (irq_stat & D_EXIR_WEXP)
 197         {
 198                 NDBGL1(L1_I_ERR, "WEXP in state %s", iwic_printstate(sc));
 199         }
 200 }
 201
 202 /*---------------------------------------------------------------------------*
 203  *      All receiving and transmitting takes place here.
 204  *---------------------------------------------------------------------------*/
 205 void
 206 iwic_dchan_xfer_irq(struct iwic_softc *sc, int ista)
 207 {
 208         NDBGL1(L1_I_MSG, "ISTA = 0x%x", ista);
 209
 210         if (ista & (ISTA_D_RMR | ISTA_D_RME))
 211         {
 212                 /* Receive message ready */
 213                 dchan_receive(sc, ista);
 214         }
 215         if (ista & ISTA_D_XFR)
 216         {
 217                 /* Transmitter ready */
 218                 sc->sc_dchan.tx_ready = 1;
 219
 220                 iwic_dchan_transmit(sc);
 221         }
 222 }
 223
 224 /*---------------------------------------------------------------------------*
 225  *      disable D-channel
 226  *---------------------------------------------------------------------------*/
 227 void
 228 iwic_dchan_disable(struct iwic_softc *sc)
 229 {
 230         int s;
 231
 232         s = SPLI4B();
 233
 234         if (sc->sc_dchan.obuf)
 235         {
 236                 if (sc->sc_dchan.free_obuf)
 237                         i4b_Dfreembuf(sc->sc_dchan.obuf);
 238                 sc->sc_dchan.obuf = NULL;
 239         }
 240
 241         if (sc->sc_dchan.obuf2)
 242         {
 243                 if (sc->sc_dchan.free_obuf2)
 244                         i4b_Dfreembuf(sc->sc_dchan.obuf2);
 245                 sc->sc_dchan.obuf2 = NULL;
 246         }
 247
 248         splx(s);
 249
 250         IWIC_WRITE(sc, CIX, CIX_DRC);
 251 }
 252
 253 /*---------------------------------------------------------------------------*
 254  *      queue D-channel message for transmission
 255  *---------------------------------------------------------------------------*/
 256 int
 257 iwic_dchan_data_req(struct iwic_softc *sc, struct mbuf *m, int freeflag)
 258 {
 259         int s;
 260
 261         if (!m)
 262                 return 0;
 263
 264         s = SPLI4B();
 265
 266         /* Queue message */
 267
 268         if (sc->sc_dchan.obuf)
 269         {
 270                 if (sc->sc_dchan.obuf2)
 271                 {
 272                         NDBGL1(L1_I_ERR, "no buffer space!");
 273                 }
 274                 else
 275                 {
 276                         sc->sc_dchan.obuf2 = m;
 277                         sc->sc_dchan.free_obuf2 = freeflag;
 278                 }
 279         }
 280         else
 281         {
 282                 sc->sc_dchan.obuf = m;
 283                 sc->sc_dchan.obuf_ptr = m->m_data;
 284                 sc->sc_dchan.obuf_len = m->m_len;
 285                 sc->sc_dchan.free_obuf = freeflag;
 286         }
 287
 288         iwic_dchan_transmit(sc);
 289
 290         splx(s);
 291
 292         return (0);
 293 }
 294
 295 /*---------------------------------------------------------------------------*
 296  *      allocate an mbuf
 297  *---------------------------------------------------------------------------*/
 298 static void
 299 dchan_get_mbuf(struct iwic_softc *sc, int len)
 300 {
 301         sc->sc_dchan.ibuf = i4b_Dgetmbuf(len);
 302
 303         if (!sc->sc_dchan.ibuf)
 304                 panic("dchan_get_mbuf: unable to allocate %d bytes for mbuf!\n", len);
 305
 306         sc->sc_dchan.ibuf_ptr = sc->sc_dchan.ibuf->m_data;
 307         sc->sc_dchan.ibuf_max_len = sc->sc_dchan.ibuf->m_len;
 308         sc->sc_dchan.ibuf_len = 0;
 309 }
 310
 311 /*---------------------------------------------------------------------------*
 312  *      D-channel receive data interrupt
 313  *---------------------------------------------------------------------------*/
 314 static void
 315 dchan_receive(struct iwic_softc *sc, int ista)
 316 {
 317         int command = D_CMDR_RACK;
 318
 319         if (ista & ISTA_D_RMR)
 320         {
 321                 /* Got 64 bytes in FIFO */
 322
 323                 if (!sc->sc_dchan.ibuf)
 324                 {
 325                         dchan_get_mbuf(sc, MAX_DFRAME_LEN);
 326
 327                 }
 328                 else if ((sc->sc_dchan.ibuf_len + MAX_DFRAME_LEN) >
 329                          sc->sc_dchan.ibuf_max_len)
 330                 {
 331                         panic("dchan_receive: not enough space in buffer!\n");
 332                 }
 333
 334                 IWIC_RDDFIFO(sc, sc->sc_dchan.ibuf_ptr, 64);
 335
 336                 sc->sc_dchan.ibuf_ptr += 64;
 337                 sc->sc_dchan.ibuf_len += 64;
 338                 sc->sc_dchan.rx_count += 64;
 339         }
 340         if (ista & ISTA_D_RME)
 341         {
 342                 /* Got end of frame */
 343                 int status;
 344
 345                 status = IWIC_READ(sc, D_RSTA);
 346
 347                 if (status & (D_RSTA_RDOV | D_RSTA_CRCE | D_RSTA_RMB))
 348                 {
 349                         if (status & D_RSTA_RDOV)
 350                                 NDBGL1(L1_I_ERR, "iwic%d: D-channel Receive Data Overflow", sc->sc_unit);
 351                         if (status & D_RSTA_CRCE)
 352                                 NDBGL1(L1_I_ERR, "iwic%d: D-channel CRC Error", sc->sc_unit);
 353                         if (status & D_RSTA_RMB)
 354                                 NDBGL1(L1_I_ERR, "iwic%d: D-channel Receive Message Aborted", sc->sc_unit);
 355                         command |= D_CMDR_RRST;
 356                 }
 357                 else
 358                 {
 359                         int hi, lo;
 360                         int total_frame_len;
 361
 362                         lo = IWIC_READ(sc, D_RBCL);
 363                         hi = IWIC_READ(sc, D_RBCH);
 364                         total_frame_len = D_RBC(hi, lo);
 365                         lo = lo & 0x3f;
 366
 367                         if (lo == 0)
 368                                 lo = IWIC_DCHAN_FIFO_LEN;
 369
 370                         if (!sc->sc_dchan.ibuf)
 371                         {
 372                                 dchan_get_mbuf(sc, lo);
 373                         }
 374                         else if ((sc->sc_dchan.ibuf_len + lo) >
 375                                  sc->sc_dchan.ibuf_max_len)
 376                         {
 377                                 panic("dchan_receive: buffer not long enough");
 378                         }
 379
 380                         IWIC_RDDFIFO(sc, sc->sc_dchan.ibuf_ptr, lo);
 381                         sc->sc_dchan.ibuf_len += lo;
 382                         sc->sc_dchan.rx_count += lo;
 383
 384                         sc->sc_dchan.ibuf->m_len = sc->sc_dchan.ibuf_len;
 385
 386                         if(sc->sc_trace & TRACE_D_RX)
 387                         {
 388                                 i4b_trace_hdr_t hdr;
 389                                 hdr.unit = L0IWICUNIT(sc->sc_unit);
 390                                 hdr.type = TRC_CH_D;
 391                                 hdr.dir = FROM_NT;
 392                                 hdr.count = ++sc->sc_dchan.trace_count;
 393                                 MICROTIME(hdr.time);
 394                                 i4b_l1_trace_ind(&hdr, sc->sc_dchan.ibuf->m_len, sc->sc_dchan.ibuf->m_data);
 395                         }
 396                         i4b_l1_ph_data_ind(L0IWICUNIT(sc->sc_unit), sc->sc_dchan.ibuf);
 397
 398                         sc->sc_dchan.ibuf = NULL;
 399                 }
 400         }
 401         IWIC_WRITE(sc, D_CMDR, command);
 402 }
 403
 404 /*---------------------------------------------------------------------------*
 405  *      transmit D-channel frame
 406  *---------------------------------------------------------------------------*/
 407 void
 408 iwic_dchan_transmit(struct iwic_softc *sc)
 409 {
 410         int cmd;
 411         u_char *ptr;
 412         int len;
 413
 414         if (!sc->sc_dchan.tx_ready)
 415                 return;
 416
 417         if (!sc->sc_dchan.obuf)
 418                 return;
 419
 420         if (sc->sc_I430state != ST_F7)
 421                 return;
 422
 423         ptr = sc->sc_dchan.obuf_ptr;
 424         len = min(sc->sc_dchan.obuf_len, IWIC_DCHAN_FIFO_LEN);
 425
 426         if(sc->sc_trace & TRACE_D_TX)
 427         {
 428                 i4b_trace_hdr_t hdr;
 429                 hdr.unit = L0IWICUNIT(sc->sc_unit);
 430                 hdr.type = TRC_CH_D;
 431                 hdr.dir = FROM_TE;
 432                 hdr.count = ++sc->sc_dchan.trace_count;
 433                 MICROTIME(hdr.time);
 434                 i4b_l1_trace_ind(&hdr, len, ptr);
 435         }
 436
 437         IWIC_WRDFIFO(sc, ptr, len);
 438
 439         sc->sc_dchan.tx_count += len;
 440
 441         if (len < sc->sc_dchan.obuf_len)
 442         {
 443                 sc->sc_dchan.obuf_ptr += len;
 444                 sc->sc_dchan.obuf_len -= len;
 445
 446                 cmd = D_CMDR_XMS;
 447
 448         }
 449         else
 450         {
 451                 if (sc->sc_dchan.free_obuf)
 452                         i4b_Dfreembuf(sc->sc_dchan.obuf);
 453
 454                 sc->sc_dchan.obuf = NULL;
 455                 sc->sc_dchan.obuf_ptr = NULL;
 456                 sc->sc_dchan.obuf_len = 0;
 457
 458                 if (sc->sc_dchan.obuf2)
 459                 {
 460                         sc->sc_dchan.obuf = sc->sc_dchan.obuf2;
 461                         sc->sc_dchan.obuf_ptr = sc->sc_dchan.obuf->m_data;
 462                         sc->sc_dchan.obuf_len = sc->sc_dchan.obuf->m_len;
 463                         sc->sc_dchan.free_obuf = sc->sc_dchan.free_obuf2;
 464
 465                         sc->sc_dchan.obuf2 = NULL;
 466                 }
 467                 cmd = D_CMDR_XMS | D_CMDR_XME;
 468         }
 469         sc->sc_dchan.tx_ready = 0;
 470         IWIC_WRITE(sc, D_CMDR, cmd);
 471 }
 472
 473 #endif  /* (NIWIC > 0) && (NPCI > 0) */