sys/dev/netif/bce/if_bce.c

   1 /*-
   2  * Copyright (c) 2006-2007 Broadcom Corporation
   3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written consent.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  28  * THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
  31  * $DragonFly: src/sys/dev/netif/bce/if_bce.c,v 1.6 2008/05/26 14:23:25 sephe Exp $
  32  */
  33
  34 /*
  35  * The following controllers are supported by this driver:
  36  *   BCM5706C A2, A3
  37  *   BCM5708C B1, B2
  38  *
  39  * The following controllers are not supported by this driver:
  40  *   BCM5706C A0, A1
  41  *   BCM5706S A0, A1, A2, A3
  42  *   BCM5708C A0, B0
  43  *   BCM5708S A0, B0, B1, B2
  44  */
  45
  46 #include "opt_bce.h"
  47 #include "opt_polling.h"
  48
  49 #include <sys/param.h>
  50 #include <sys/bus.h>
  51 #include <sys/endian.h>
  52 #include <sys/kernel.h>
  53 #include <sys/interrupt.h>
  54 #include <sys/mbuf.h>
  55 #include <sys/malloc.h>
  56 #include <sys/queue.h>
  57 #ifdef BCE_DEBUG
  58 #include <sys/random.h>
  59 #endif
  60 #include <sys/rman.h>
  61 #include <sys/serialize.h>
  62 #include <sys/socket.h>
  63 #include <sys/sockio.h>
  64 #include <sys/sysctl.h>
  65
  66 #include <net/bpf.h>
  67 #include <net/ethernet.h>
  68 #include <net/if.h>
  69 #include <net/if_arp.h>
  70 #include <net/if_dl.h>
  71 #include <net/if_media.h>
  72 #include <net/if_types.h>
  73 #include <net/ifq_var.h>
  74 #include <net/vlan/if_vlan_var.h>
  75 #include <net/vlan/if_vlan_ether.h>
  76
  77 #include <dev/netif/mii_layer/mii.h>
  78 #include <dev/netif/mii_layer/miivar.h>
  79
  80 #include <bus/pci/pcireg.h>
  81 #include <bus/pci/pcivar.h>
  82
  83 #include "miibus_if.h"
  84
  85 #include "if_bcereg.h"
  86 #include "if_bcefw.h"
  87
  88 /****************************************************************************/
  89 /* BCE Debug Options                                                        */
  90 /****************************************************************************/
  91 #ifdef BCE_DEBUG
  92
  93 static uint32_t bce_debug = BCE_WARN;
  94
  95 /*
  96  *          0 = Never
  97  *          1 = 1 in 2,147,483,648
  98  *        256 = 1 in     8,388,608
  99  *       2048 = 1 in     1,048,576
 100  *      65536 = 1 in        32,768
 101  *    1048576 = 1 in         2,048
 102  *  268435456 = 1 in             8
 103  *  536870912 = 1 in             4
 104  * 1073741824 = 1 in             2
 105  *
 106  * bce_debug_l2fhdr_status_check:
 107  *     How often the l2_fhdr frame error check will fail.
 108  *
 109  * bce_debug_unexpected_attention:
 110  *     How often the unexpected attention check will fail.
 111  *
 112  * bce_debug_mbuf_allocation_failure:
 113  *     How often to simulate an mbuf allocation failure.
 114  *
 115  * bce_debug_dma_map_addr_failure:
 116  *     How often to simulate a DMA mapping failure.
 117  *
 118  * bce_debug_bootcode_running_failure:
 119  *     How often to simulate a bootcode failure.
 120  */
 121 static int      bce_debug_l2fhdr_status_check = 0;
 122 static int      bce_debug_unexpected_attention = 0;
 123 static int      bce_debug_mbuf_allocation_failure = 0;
 124 static int      bce_debug_dma_map_addr_failure = 0;
 125 static int      bce_debug_bootcode_running_failure = 0;
 126
 127 #endif  /* BCE_DEBUG */
 128
 129
 130 /****************************************************************************/
 131 /* PCI Device ID Table                                                      */
 132 /*                                                                          */
 133 /* Used by bce_probe() to identify the devices supported by this driver.    */
 134 /****************************************************************************/
 135 #define BCE_DEVDESC_MAX         64
 136
 137 static struct bce_type bce_devs[] = {
 138         /* BCM5706C Controllers and OEM boards. */
 139         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
 140                 "HP NC370T Multifunction Gigabit Server Adapter" },
 141         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
 142                 "HP NC370i Multifunction Gigabit Server Adapter" },
 143         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 144                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
 145
 146         /* BCM5706S controllers and OEM boards. */
 147         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 148                 "HP NC370F Multifunction Gigabit Server Adapter" },
 149         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 150                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 151
 152         /* BCM5708C controllers and OEM boards. */
 153         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 154                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
 155
 156         /* BCM5708S controllers and OEM boards. */
 157         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 158                 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
 159         { 0, 0, 0, 0, NULL }
 160 };
 161
 162
 163 /****************************************************************************/
 164 /* Supported Flash NVRAM device data.                                       */
 165 /****************************************************************************/
 166 static const struct flash_spec flash_table[] =
 167 {
 168         /* Slow EEPROM */
 169         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 170          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 171          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 172          "EEPROM - slow"},
 173         /* Expansion entry 0001 */
 174         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 175          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 176          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 177          "Entry 0001"},
 178         /* Saifun SA25F010 (non-buffered flash) */
 179         /* strap, cfg1, & write1 need updates */
 180         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 181          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 182          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 183          "Non-buffered flash (128kB)"},
 184         /* Saifun SA25F020 (non-buffered flash) */
 185         /* strap, cfg1, & write1 need updates */
 186         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 187          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 188          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 189          "Non-buffered flash (256kB)"},
 190         /* Expansion entry 0100 */
 191         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 192          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 193          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 194          "Entry 0100"},
 195         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 196         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 197          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 198          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 199          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 200         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 201         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 202          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 203          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 204          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 205         /* Saifun SA25F005 (non-buffered flash) */
 206         /* strap, cfg1, & write1 need updates */
 207         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 208          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 209          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 210          "Non-buffered flash (64kB)"},
 211         /* Fast EEPROM */
 212         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 213          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 214          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 215          "EEPROM - fast"},
 216         /* Expansion entry 1001 */
 217         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 218          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 219          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 220          "Entry 1001"},
 221         /* Expansion entry 1010 */
 222         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 223          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 224          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 225          "Entry 1010"},
 226         /* ATMEL AT45DB011B (buffered flash) */
 227         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 228          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 229          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 230          "Buffered flash (128kB)"},
 231         /* Expansion entry 1100 */
 232         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 233          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 234          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 235          "Entry 1100"},
 236         /* Expansion entry 1101 */
 237         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 238          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 239          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 240          "Entry 1101"},
 241         /* Ateml Expansion entry 1110 */
 242         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 243          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 244          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 245          "Entry 1110 (Atmel)"},
 246         /* ATMEL AT45DB021B (buffered flash) */
 247         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 248          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 249          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 250          "Buffered flash (256kB)"},
 251 };
 252
 253
 254 /****************************************************************************/
 255 /* DragonFly device entry points.                                           */
 256 /****************************************************************************/
 257 static int      bce_probe(device_t);
 258 static int      bce_attach(device_t);
 259 static int      bce_detach(device_t);
 260 static void     bce_shutdown(device_t);
 261
 262 /****************************************************************************/
 263 /* BCE Debug Data Structure Dump Routines                                   */
 264 /****************************************************************************/
 265 #ifdef BCE_DEBUG
 266 static void     bce_dump_mbuf(struct bce_softc *, struct mbuf *);
 267 static void     bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
 268 static void     bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
 269 static void     bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
 270 static void     bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
 271 static void     bce_dump_l2fhdr(struct bce_softc *, int,
 272                                 struct l2_fhdr *) __unused;
 273 static void     bce_dump_tx_chain(struct bce_softc *, int, int);
 274 static void     bce_dump_rx_chain(struct bce_softc *, int, int);
 275 static void     bce_dump_status_block(struct bce_softc *);
 276 static void     bce_dump_driver_state(struct bce_softc *);
 277 static void     bce_dump_stats_block(struct bce_softc *) __unused;
 278 static void     bce_dump_hw_state(struct bce_softc *);
 279 static void     bce_dump_txp_state(struct bce_softc *);
 280 static void     bce_dump_rxp_state(struct bce_softc *) __unused;
 281 static void     bce_dump_tpat_state(struct bce_softc *) __unused;
 282 static void     bce_freeze_controller(struct bce_softc *) __unused;
 283 static void     bce_unfreeze_controller(struct bce_softc *) __unused;
 284 static void     bce_breakpoint(struct bce_softc *);
 285 #endif  /* BCE_DEBUG */
 286
 287
 288 /****************************************************************************/
 289 /* BCE Register/Memory Access Routines                                      */
 290 /****************************************************************************/
 291 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
 292 static void     bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
 293 static void     bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
 294 static int      bce_miibus_read_reg(device_t, int, int);
 295 static int      bce_miibus_write_reg(device_t, int, int, int);
 296 static void     bce_miibus_statchg(device_t);
 297
 298
 299 /****************************************************************************/
 300 /* BCE NVRAM Access Routines                                                */
 301 /****************************************************************************/
 302 static int      bce_acquire_nvram_lock(struct bce_softc *);
 303 static int      bce_release_nvram_lock(struct bce_softc *);
 304 static void     bce_enable_nvram_access(struct bce_softc *);
 305 static void     bce_disable_nvram_access(struct bce_softc *);
 306 static int      bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
 307                                      uint32_t);
 308 static int      bce_init_nvram(struct bce_softc *);
 309 static int      bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
 310 static int      bce_nvram_test(struct bce_softc *);
 311 #ifdef BCE_NVRAM_WRITE_SUPPORT
 312 static int      bce_enable_nvram_write(struct bce_softc *);
 313 static void     bce_disable_nvram_write(struct bce_softc *);
 314 static int      bce_nvram_erase_page(struct bce_softc *, uint32_t);
 315 static int      bce_nvram_write_dword(struct bce_softc *, uint32_t, uint8_t *,                                        uint32_t);
 316 static int      bce_nvram_write(struct bce_softc *, uint32_t, uint8_t *,
 317                                 int) __unused;
 318 #endif
 319
 320 /****************************************************************************/
 321 /* BCE DMA Allocate/Free Routines                                           */
 322 /****************************************************************************/
 323 static int      bce_dma_alloc(struct bce_softc *);
 324 static void     bce_dma_free(struct bce_softc *);
 325 static void     bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 326 static void     bce_dma_map_mbuf(void *, bus_dma_segment_t *, int,
 327                                  bus_size_t, int);
 328
 329 /****************************************************************************/
 330 /* BCE Firmware Synchronization and Load                                    */
 331 /****************************************************************************/
 332 static int      bce_fw_sync(struct bce_softc *, uint32_t);
 333 static void     bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
 334                                  uint32_t, uint32_t);
 335 static void     bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
 336                                 struct fw_info *);
 337 static void     bce_init_cpus(struct bce_softc *);
 338
 339 static void     bce_stop(struct bce_softc *);
 340 static int      bce_reset(struct bce_softc *, uint32_t);
 341 static int      bce_chipinit(struct bce_softc *);
 342 static int      bce_blockinit(struct bce_softc *);
 343 static int      bce_newbuf_std(struct bce_softc *, struct mbuf *,
 344                                uint16_t *, uint16_t *, uint32_t *);
 345
 346 static int      bce_init_tx_chain(struct bce_softc *);
 347 static int      bce_init_rx_chain(struct bce_softc *);
 348 static void     bce_free_rx_chain(struct bce_softc *);
 349 static void     bce_free_tx_chain(struct bce_softc *);
 350
 351 static int      bce_encap(struct bce_softc *, struct mbuf **);
 352 static void     bce_start(struct ifnet *);
 353 static int      bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 354 static void     bce_watchdog(struct ifnet *);
 355 static int      bce_ifmedia_upd(struct ifnet *);
 356 static void     bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 357 static void     bce_init(void *);
 358 static void     bce_mgmt_init(struct bce_softc *);
 359
 360 static void     bce_init_context(struct bce_softc *);
 361 static void     bce_get_mac_addr(struct bce_softc *);
 362 static void     bce_set_mac_addr(struct bce_softc *);
 363 static void     bce_phy_intr(struct bce_softc *);
 364 static void     bce_rx_intr(struct bce_softc *, int);
 365 static void     bce_tx_intr(struct bce_softc *);
 366 static void     bce_disable_intr(struct bce_softc *);
 367 static void     bce_enable_intr(struct bce_softc *);
 368
 369 #ifdef DEVICE_POLLING
 370 static void     bce_poll(struct ifnet *, enum poll_cmd, int);
 371 #endif
 372 static void     bce_intr(void *);
 373 static void     bce_set_rx_mode(struct bce_softc *);
 374 static void     bce_stats_update(struct bce_softc *);
 375 static void     bce_tick(void *);
 376 static void     bce_tick_serialized(struct bce_softc *);
 377 static void     bce_add_sysctls(struct bce_softc *);
 378
 379
 380 /****************************************************************************/
 381 /* DragonFly device dispatch table.                                         */
 382 /****************************************************************************/
 383 static device_method_t bce_methods[] = {
 384         /* Device interface */
 385         DEVMETHOD(device_probe,         bce_probe),
 386         DEVMETHOD(device_attach,        bce_attach),
 387         DEVMETHOD(device_detach,        bce_detach),
 388         DEVMETHOD(device_shutdown,      bce_shutdown),
 389
 390         /* bus interface */
 391         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 392         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 393
 394         /* MII interface */
 395         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 396         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 397         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 398
 399         { 0, 0 }
 400 };
 401
 402 static driver_t bce_driver = {
 403         "bce",
 404         bce_methods,
 405         sizeof(struct bce_softc)
 406 };
 407
 408 static devclass_t bce_devclass;
 409
 410 MODULE_DEPEND(bce, pci, 1, 1, 1);
 411 MODULE_DEPEND(bce, ether, 1, 1, 1);
 412 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 413
 414 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0);
 415 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0);
 416
 417
 418 /****************************************************************************/
 419 /* Device probe function.                                                   */
 420 /*                                                                          */
 421 /* Compares the device to the driver's list of supported devices and        */
 422 /* reports back to the OS whether this is the right driver for the device.  */
 423 /*                                                                          */
 424 /* Returns:                                                                 */
 425 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 426 /****************************************************************************/
 427 static int
 428 bce_probe(device_t dev)
 429 {
 430         struct bce_type *t;
 431         uint16_t vid, did, svid, sdid;
 432
 433         /* Get the data for the device to be probed. */
 434         vid  = pci_get_vendor(dev);
 435         did  = pci_get_device(dev);
 436         svid = pci_get_subvendor(dev);
 437         sdid = pci_get_subdevice(dev);
 438
 439         /* Look through the list of known devices for a match. */
 440         for (t = bce_devs; t->bce_name != NULL; ++t) {
 441                 if (vid == t->bce_vid && did == t->bce_did &&
 442                     (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
 443                     (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
 444                         uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
 445                         char *descbuf;
 446
 447                         descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
 448
 449                         /* Print out the device identity. */
 450                         ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 451                                   t->bce_name,
 452                                   ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
 453
 454                         device_set_desc_copy(dev, descbuf);
 455                         kfree(descbuf, M_TEMP);
 456                         return 0;
 457                 }
 458         }
 459         return ENXIO;
 460 }
 461
 462
 463 /****************************************************************************/
 464 /* Device attach function.                                                  */
 465 /*                                                                          */
 466 /* Allocates device resources, performs secondary chip identification,      */
 467 /* resets and initializes the hardware, and initializes driver instance     */
 468 /* variables.                                                               */
 469 /*                                                                          */
 470 /* Returns:                                                                 */
 471 /*   0 on success, positive value on failure.                               */
 472 /****************************************************************************/
 473 static int
 474 bce_attach(device_t dev)
 475 {
 476         struct bce_softc *sc = device_get_softc(dev);
 477         struct ifnet *ifp = &sc->arpcom.ac_if;
 478         uint32_t val;
 479         int rid, rc = 0;
 480 #ifdef notyet
 481         int count;
 482 #endif
 483
 484         sc->bce_dev = dev;
 485         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 486
 487         pci_enable_busmaster(dev);
 488
 489         /* Allocate PCI memory resources. */
 490         rid = PCIR_BAR(0);
 491         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 492                                                  RF_ACTIVE | PCI_RF_DENSE);
 493         if (sc->bce_res_mem == NULL) {
 494                 device_printf(dev, "PCI memory allocation failed\n");
 495                 return ENXIO;
 496         }
 497         sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
 498         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
 499
 500         /* Allocate PCI IRQ resources. */
 501 #ifdef notyet
 502         count = pci_msi_count(dev);
 503         if (count == 1 && pci_alloc_msi(dev, &count) == 0) {
 504                 rid = 1;
 505                 sc->bce_flags |= BCE_USING_MSI_FLAG;
 506         } else
 507 #endif
 508         rid = 0;
 509         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 510                                                  RF_SHAREABLE | RF_ACTIVE);
 511         if (sc->bce_res_irq == NULL) {
 512                 device_printf(dev, "PCI map interrupt failed\n");
 513                 rc = ENXIO;
 514                 goto fail;
 515         }
 516
 517         /*
 518          * Configure byte swap and enable indirect register access.
 519          * Rely on CPU to do target byte swapping on big endian systems.
 520          * Access to registers outside of PCI configurtion space are not
 521          * valid until this is done.
 522          */
 523         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
 524                          BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
 525                          BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
 526
 527         /* Save ASIC revsion info. */
 528         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
 529
 530         /* Weed out any non-production controller revisions. */
 531         switch(BCE_CHIP_ID(sc)) {
 532         case BCE_CHIP_ID_5706_A0:
 533         case BCE_CHIP_ID_5706_A1:
 534         case BCE_CHIP_ID_5708_A0:
 535         case BCE_CHIP_ID_5708_B0:
 536                 device_printf(dev, "Unsupported chip id 0x%08x!\n",
 537                               BCE_CHIP_ID(sc));
 538                 rc = ENODEV;
 539                 goto fail;
 540         }
 541
 542         /*
 543          * The embedded PCIe to PCI-X bridge (EPB)
 544          * in the 5708 cannot address memory above
 545          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
 546          */
 547         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
 548                 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR;
 549         else
 550                 sc->max_bus_addr = BUS_SPACE_MAXADDR;
 551
 552         /*
 553          * Find the base address for shared memory access.
 554          * Newer versions of bootcode use a signature and offset
 555          * while older versions use a fixed address.
 556          */
 557         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
 558         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG)
 559                 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0);
 560         else
 561                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
 562
 563         DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
 564
 565         /* Get PCI bus information (speed and type). */
 566         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
 567         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
 568                 uint32_t clkreg;
 569
 570                 sc->bce_flags |= BCE_PCIX_FLAG;
 571
 572                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
 573                          BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
 574                 switch (clkreg) {
 575                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
 576                         sc->bus_speed_mhz = 133;
 577                         break;
 578
 579                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
 580                         sc->bus_speed_mhz = 100;
 581                         break;
 582
 583                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
 584                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
 585                         sc->bus_speed_mhz = 66;
 586                         break;
 587
 588                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
 589                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
 590                         sc->bus_speed_mhz = 50;
 591                         break;
 592
 593                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
 594                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
 595                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
 596                         sc->bus_speed_mhz = 33;
 597                         break;
 598                 }
 599         } else {
 600                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
 601                         sc->bus_speed_mhz = 66;
 602                 else
 603                         sc->bus_speed_mhz = 33;
 604         }
 605
 606         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
 607                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
 608
 609         device_printf(dev, "ASIC ID 0x%08X; Revision (%c%d); PCI%s %s %dMHz\n",
 610                       sc->bce_chipid,
 611                       ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
 612                       (BCE_CHIP_ID(sc) & 0x0ff0) >> 4,
 613                       (sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : "",
 614                       (sc->bce_flags & BCE_PCI_32BIT_FLAG) ?
 615                       "32-bit" : "64-bit", sc->bus_speed_mhz);
 616
 617         /* Reset the controller. */
 618         rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
 619         if (rc != 0)
 620                 goto fail;
 621
 622         /* Initialize the controller. */
 623         rc = bce_chipinit(sc);
 624         if (rc != 0) {
 625                 device_printf(dev, "Controller initialization failed!\n");
 626                 goto fail;
 627         }
 628
 629         /* Perform NVRAM test. */
 630         rc = bce_nvram_test(sc);
 631         if (rc != 0) {
 632                 device_printf(dev, "NVRAM test failed!\n");
 633                 goto fail;
 634         }
 635
 636         /* Fetch the permanent Ethernet MAC address. */
 637         bce_get_mac_addr(sc);
 638
 639         /*
 640          * Trip points control how many BDs
 641          * should be ready before generating an
 642          * interrupt while ticks control how long
 643          * a BD can sit in the chain before
 644          * generating an interrupt.  Set the default
 645          * values for the RX and TX rings.
 646          */
 647
 648 #ifdef BCE_DRBUG
 649         /* Force more frequent interrupts. */
 650         sc->bce_tx_quick_cons_trip_int = 1;
 651         sc->bce_tx_quick_cons_trip     = 1;
 652         sc->bce_tx_ticks_int           = 0;
 653         sc->bce_tx_ticks               = 0;
 654
 655         sc->bce_rx_quick_cons_trip_int = 1;
 656         sc->bce_rx_quick_cons_trip     = 1;
 657         sc->bce_rx_ticks_int           = 0;
 658         sc->bce_rx_ticks               = 0;
 659 #else
 660         sc->bce_tx_quick_cons_trip_int = 20;
 661         sc->bce_tx_quick_cons_trip     = 20;
 662         sc->bce_tx_ticks_int           = 80;
 663         sc->bce_tx_ticks               = 80;
 664
 665         sc->bce_rx_quick_cons_trip_int = 6;
 666         sc->bce_rx_quick_cons_trip     = 6;
 667         sc->bce_rx_ticks_int           = 18;
 668         sc->bce_rx_ticks               = 18;
 669 #endif
 670
 671         /* Update statistics once every second. */
 672         sc->bce_stats_ticks = 1000000 & 0xffff00;
 673
 674         /*
 675          * The copper based NetXtreme II controllers
 676          * use an integrated PHY at address 1 while
 677          * the SerDes controllers use a PHY at
 678          * address 2.
 679          */
 680         sc->bce_phy_addr = 1;
 681
 682         if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
 683                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
 684                 sc->bce_flags |= BCE_NO_WOL_FLAG;
 685                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) {
 686                         sc->bce_phy_addr = 2;
 687                         val = REG_RD_IND(sc, sc->bce_shmem_base +
 688                                          BCE_SHARED_HW_CFG_CONFIG);
 689                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
 690                                 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
 691                 }
 692         }
 693
 694         /* Allocate DMA memory resources. */
 695         rc = bce_dma_alloc(sc);
 696         if (rc != 0) {
 697                 device_printf(dev, "DMA resource allocation failed!\n");
 698                 goto fail;
 699         }
 700
 701         /* Initialize the ifnet interface. */
 702         ifp->if_softc = sc;
 703         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 704         ifp->if_ioctl = bce_ioctl;
 705         ifp->if_start = bce_start;
 706         ifp->if_init = bce_init;
 707         ifp->if_watchdog = bce_watchdog;
 708 #ifdef DEVICE_POLLING
 709         ifp->if_poll = bce_poll;
 710 #endif
 711         ifp->if_mtu = ETHERMTU;
 712         ifp->if_hwassist = BCE_IF_HWASSIST;
 713         ifp->if_capabilities = BCE_IF_CAPABILITIES;
 714         ifp->if_capenable = ifp->if_capabilities;
 715         ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD);
 716         ifq_set_ready(&ifp->if_snd);
 717
 718         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 719                 ifp->if_baudrate = IF_Gbps(2.5);
 720         else
 721                 ifp->if_baudrate = IF_Gbps(1);
 722
 723         /* Assume a standard 1500 byte MTU size for mbuf allocations. */
 724         sc->mbuf_alloc_size  = MCLBYTES;
 725
 726         /* Look for our PHY. */
 727         rc = mii_phy_probe(dev, &sc->bce_miibus,
 728                            bce_ifmedia_upd, bce_ifmedia_sts);
 729         if (rc != 0) {
 730                 device_printf(dev, "PHY probe failed!\n");
 731                 goto fail;
 732         }
 733
 734         /* Attach to the Ethernet interface list. */
 735         ether_ifattach(ifp, sc->eaddr, NULL);
 736
 737         callout_init(&sc->bce_stat_ch);
 738
 739         /* Hookup IRQ last. */
 740         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_NETSAFE, bce_intr, sc,
 741                             &sc->bce_intrhand, ifp->if_serializer);
 742         if (rc != 0) {
 743                 device_printf(dev, "Failed to setup IRQ!\n");
 744                 ether_ifdetach(ifp);
 745                 goto fail;
 746         }
 747
 748         ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bce_res_irq));
 749         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
 750
 751         /* Print some important debugging info. */
 752         DBRUN(BCE_INFO, bce_dump_driver_state(sc));
 753
 754         /* Add the supported sysctls to the kernel. */
 755         bce_add_sysctls(sc);
 756
 757         /* Get the firmware running so IPMI still works */
 758         bce_mgmt_init(sc);
 759
 760         return 0;
 761 fail:
 762         bce_detach(dev);
 763         return(rc);
 764 }
 765
 766
 767 /****************************************************************************/
 768 /* Device detach function.                                                  */
 769 /*                                                                          */
 770 /* Stops the controller, resets the controller, and releases resources.     */
 771 /*                                                                          */
 772 /* Returns:                                                                 */
 773 /*   0 on success, positive value on failure.                               */
 774 /****************************************************************************/
 775 static int
 776 bce_detach(device_t dev)
 777 {
 778         struct bce_softc *sc = device_get_softc(dev);
 779
 780         if (device_is_attached(dev)) {
 781                 struct ifnet *ifp = &sc->arpcom.ac_if;
 782
 783                 /* Stop and reset the controller. */
 784                 lwkt_serialize_enter(ifp->if_serializer);
 785                 bce_stop(sc);
 786                 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
 787                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
 788                 lwkt_serialize_exit(ifp->if_serializer);
 789
 790                 ether_ifdetach(ifp);
 791         }
 792
 793         /* If we have a child device on the MII bus remove it too. */
 794         if (sc->bce_miibus)
 795                 device_delete_child(dev, sc->bce_miibus);
 796         bus_generic_detach(dev);
 797
 798         if (sc->bce_res_irq != NULL) {
 799                 bus_release_resource(dev, SYS_RES_IRQ,
 800                         sc->bce_flags & BCE_USING_MSI_FLAG ? 1 : 0,
 801                         sc->bce_res_irq);
 802         }
 803
 804 #ifdef notyet
 805         if (sc->bce_flags & BCE_USING_MSI_FLAG)
 806                 pci_release_msi(dev);
 807 #endif
 808
 809         if (sc->bce_res_mem != NULL) {
 810                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
 811                                      sc->bce_res_mem);
 812         }
 813
 814         bce_dma_free(sc);
 815
 816         if (sc->bce_sysctl_tree != NULL)
 817                 sysctl_ctx_free(&sc->bce_sysctl_ctx);
 818
 819         return 0;
 820 }
 821
 822
 823 /****************************************************************************/
 824 /* Device shutdown function.                                                */
 825 /*                                                                          */
 826 /* Stops and resets the controller.                                         */
 827 /*                                                                          */
 828 /* Returns:                                                                 */
 829 /*   Nothing                                                                */
 830 /****************************************************************************/
 831 static void
 832 bce_shutdown(device_t dev)
 833 {
 834         struct bce_softc *sc = device_get_softc(dev);
 835         struct ifnet *ifp = &sc->arpcom.ac_if;
 836
 837         lwkt_serialize_enter(ifp->if_serializer);
 838         bce_stop(sc);
 839         bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
 840         lwkt_serialize_exit(ifp->if_serializer);
 841 }
 842
 843
 844 /****************************************************************************/
 845 /* Indirect register read.                                                  */
 846 /*                                                                          */
 847 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
 848 /* configuration space.  Using this mechanism avoids issues with posted     */
 849 /* reads but is much slower than memory-mapped I/O.                         */
 850 /*                                                                          */
 851 /* Returns:                                                                 */
 852 /*   The value of the register.                                             */
 853 /****************************************************************************/
 854 static uint32_t
 855 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
 856 {
 857         device_t dev = sc->bce_dev;
 858
 859         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
 860 #ifdef BCE_DEBUG
 861         {
 862                 uint32_t val;
 863                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
 864                 DBPRINT(sc, BCE_EXCESSIVE,
 865                         "%s(); offset = 0x%08X, val = 0x%08X\n",
 866                         __func__, offset, val);
 867                 return val;
 868         }
 869 #else
 870         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
 871 #endif
 872 }
 873
 874
 875 /****************************************************************************/
 876 /* Indirect register write.                                                 */
 877 /*                                                                          */
 878 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
 879 /* configuration space.  Using this mechanism avoids issues with posted     */
 880 /* writes but is muchh slower than memory-mapped I/O.                       */
 881 /*                                                                          */
 882 /* Returns:                                                                 */
 883 /*   Nothing.                                                               */
 884 /****************************************************************************/
 885 static void
 886 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
 887 {
 888         device_t dev = sc->bce_dev;
 889
 890         DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
 891                 __func__, offset, val);
 892
 893         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
 894         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
 895 }
 896
 897
 898 /****************************************************************************/
 899 /* Context memory write.                                                    */
 900 /*                                                                          */
 901 /* The NetXtreme II controller uses context memory to track connection      */
 902 /* information for L2 and higher network protocols.                         */
 903 /*                                                                          */
 904 /* Returns:                                                                 */
 905 /*   Nothing.                                                               */
 906 /****************************************************************************/
 907 static void
 908 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t offset,
 909            uint32_t val)
 910 {
 911         DBPRINT(sc, BCE_EXCESSIVE, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
 912                 "val = 0x%08X\n", __func__, cid_addr, offset, val);
 913
 914         offset += cid_addr;
 915         REG_WR(sc, BCE_CTX_DATA_ADR, offset);
 916         REG_WR(sc, BCE_CTX_DATA, val);
 917 }
 918
 919
 920 /****************************************************************************/
 921 /* PHY register read.                                                       */
 922 /*                                                                          */
 923 /* Implements register reads on the MII bus.                                */
 924 /*                                                                          */
 925 /* Returns:                                                                 */
 926 /*   The value of the register.                                             */
 927 /****************************************************************************/
 928 static int
 929 bce_miibus_read_reg(device_t dev, int phy, int reg)
 930 {
 931         struct bce_softc *sc = device_get_softc(dev);
 932         uint32_t val;
 933         int i;
 934
 935         /* Make sure we are accessing the correct PHY address. */
 936         if (phy != sc->bce_phy_addr) {
 937                 DBPRINT(sc, BCE_VERBOSE,
 938                         "Invalid PHY address %d for PHY read!\n", phy);
 939                 return 0;
 940         }
 941
 942         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
 943                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
 944                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
 945
 946                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
 947                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
 948
 949                 DELAY(40);
 950         }
 951
 952         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
 953               BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
 954               BCE_EMAC_MDIO_COMM_START_BUSY;
 955         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
 956
 957         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
 958                 DELAY(10);
 959
 960                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
 961                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
 962                         DELAY(5);
 963
 964                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
 965                         val &= BCE_EMAC_MDIO_COMM_DATA;
 966                         break;
 967                 }
 968         }
 969
 970         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
 971                 if_printf(&sc->arpcom.ac_if,
 972                           "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
 973                           phy, reg);
 974                 val = 0x0;
 975         } else {
 976                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
 977         }
 978
 979         DBPRINT(sc, BCE_EXCESSIVE,
 980                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
 981                 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
 982
 983         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
 984                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
 985                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
 986
 987                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
 988                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
 989
 990                 DELAY(40);
 991         }
 992         return (val & 0xffff);
 993 }
 994
 995
 996 /****************************************************************************/
 997 /* PHY register write.                                                      */
 998 /*                                                                          */
 999 /* Implements register writes on the MII bus.                               */
1000 /*                                                                          */
1001 /* Returns:                                                                 */
1002 /*   The value of the register.                                             */
1003 /****************************************************************************/
1004 static int
1005 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1006 {
1007         struct bce_softc *sc = device_get_softc(dev);
1008         uint32_t val1;
1009         int i;
1010
1011         /* Make sure we are accessing the correct PHY address. */
1012         if (phy != sc->bce_phy_addr) {
1013                 DBPRINT(sc, BCE_WARN,
1014                         "Invalid PHY address %d for PHY write!\n", phy);
1015                 return(0);
1016         }
1017
1018         DBPRINT(sc, BCE_EXCESSIVE,
1019                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1020                 __func__, phy, (uint16_t)(reg & 0xffff),
1021                 (uint16_t)(val & 0xffff));
1022
1023         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1024                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1025                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1026
1027                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1028                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1029
1030                 DELAY(40);
1031         }
1032
1033         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1034                 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1035                 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1036         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1037
1038         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1039                 DELAY(10);
1040
1041                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1042                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1043                         DELAY(5);
1044                         break;
1045                 }
1046         }
1047
1048         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1049                 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1050
1051         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1052                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1053                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1054
1055                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1056                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1057
1058                 DELAY(40);
1059         }
1060         return 0;
1061 }
1062
1063
1064 /****************************************************************************/
1065 /* MII bus status change.                                                   */
1066 /*                                                                          */
1067 /* Called by the MII bus driver when the PHY establishes link to set the    */
1068 /* MAC interface registers.                                                 */
1069 /*                                                                          */
1070 /* Returns:                                                                 */
1071 /*   Nothing.                                                               */
1072 /****************************************************************************/
1073 static void
1074 bce_miibus_statchg(device_t dev)
1075 {
1076         struct bce_softc *sc = device_get_softc(dev);
1077         struct mii_data *mii = device_get_softc(sc->bce_miibus);
1078
1079         DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1080                 mii->mii_media_active);
1081
1082 #ifdef BCE_DEBUG
1083         /* Decode the interface media flags. */
1084         if_printf(&sc->arpcom.ac_if, "Media: ( ");
1085         switch(IFM_TYPE(mii->mii_media_active)) {
1086         case IFM_ETHER:
1087                 kprintf("Ethernet )");
1088                 break;
1089         default:
1090                 kprintf("Unknown )");
1091                 break;
1092         }
1093
1094         kprintf(" Media Options: ( ");
1095         switch(IFM_SUBTYPE(mii->mii_media_active)) {
1096         case IFM_AUTO:
1097                 kprintf("Autoselect )");
1098                 break;
1099         case IFM_MANUAL:
1100                 kprintf("Manual )");
1101                 break;
1102         case IFM_NONE:
1103                 kprintf("None )");
1104                 break;
1105         case IFM_10_T:
1106                 kprintf("10Base-T )");
1107                 break;
1108         case IFM_100_TX:
1109                 kprintf("100Base-TX )");
1110                 break;
1111         case IFM_1000_SX:
1112                 kprintf("1000Base-SX )");
1113                 break;
1114         case IFM_1000_T:
1115                 kprintf("1000Base-T )");
1116                 break;
1117         default:
1118                 kprintf("Other )");
1119                 break;
1120         }
1121
1122         kprintf(" Global Options: (");
1123         if (mii->mii_media_active & IFM_FDX)
1124                 kprintf(" FullDuplex");
1125         if (mii->mii_media_active & IFM_HDX)
1126                 kprintf(" HalfDuplex");
1127         if (mii->mii_media_active & IFM_LOOP)
1128                 kprintf(" Loopback");
1129         if (mii->mii_media_active & IFM_FLAG0)
1130                 kprintf(" Flag0");
1131         if (mii->mii_media_active & IFM_FLAG1)
1132                 kprintf(" Flag1");
1133         if (mii->mii_media_active & IFM_FLAG2)
1134                 kprintf(" Flag2");
1135         kprintf(" )\n");
1136 #endif
1137
1138         BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1139
1140         /*
1141          * Set MII or GMII interface based on the speed negotiated
1142          * by the PHY.
1143          */
1144         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1145             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1146                 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1147                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1148         } else {
1149                 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1150                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1151         }
1152
1153         /*
1154          * Set half or full duplex based on the duplicity negotiated
1155          * by the PHY.
1156          */
1157         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1158                 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1159                 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1160         } else {
1161                 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1162                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1163         }
1164 }
1165
1166
1167 /****************************************************************************/
1168 /* Acquire NVRAM lock.                                                      */
1169 /*                                                                          */
1170 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1171 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1172 /* for use by the driver.                                                   */
1173 /*                                                                          */
1174 /* Returns:                                                                 */
1175 /*   0 on success, positive value on failure.                               */
1176 /****************************************************************************/
1177 static int
1178 bce_acquire_nvram_lock(struct bce_softc *sc)
1179 {
1180         uint32_t val;
1181         int j;
1182
1183         DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1184
1185         /* Request access to the flash interface. */
1186         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1187         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1188                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1189                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1190                         break;
1191
1192                 DELAY(5);
1193         }
1194
1195         if (j >= NVRAM_TIMEOUT_COUNT) {
1196                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1197                 return EBUSY;
1198         }
1199         return 0;
1200 }
1201
1202
1203 /****************************************************************************/
1204 /* Release NVRAM lock.                                                      */
1205 /*                                                                          */
1206 /* When the caller is finished accessing NVRAM the lock must be released.   */
1207 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1208 /* for use by the driver.                                                   */
1209 /*                                                                          */
1210 /* Returns:                                                                 */
1211 /*   0 on success, positive value on failure.                               */
1212 /****************************************************************************/
1213 static int
1214 bce_release_nvram_lock(struct bce_softc *sc)
1215 {
1216         int j;
1217         uint32_t val;
1218
1219         DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1220
1221         /*
1222          * Relinquish nvram interface.
1223          */
1224         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1225
1226         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1227                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1228                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1229                         break;
1230
1231                 DELAY(5);
1232         }
1233
1234         if (j >= NVRAM_TIMEOUT_COUNT) {
1235                 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1236                 return EBUSY;
1237         }
1238         return 0;
1239 }
1240
1241
1242 #ifdef BCE_NVRAM_WRITE_SUPPORT
1243 /****************************************************************************/
1244 /* Enable NVRAM write access.                                               */
1245 /*                                                                          */
1246 /* Before writing to NVRAM the caller must enable NVRAM writes.             */
1247 /*                                                                          */
1248 /* Returns:                                                                 */
1249 /*   0 on success, positive value on failure.                               */
1250 /****************************************************************************/
1251 static int
1252 bce_enable_nvram_write(struct bce_softc *sc)
1253 {
1254         uint32_t val;
1255
1256         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM write.\n");
1257
1258         val = REG_RD(sc, BCE_MISC_CFG);
1259         REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);
1260
1261         if (!sc->bce_flash_info->buffered) {
1262                 int j;
1263
1264                 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1265                 REG_WR(sc, BCE_NVM_COMMAND,
1266                        BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT);
1267
1268                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1269                         DELAY(5);
1270
1271                         val = REG_RD(sc, BCE_NVM_COMMAND);
1272                         if (val & BCE_NVM_COMMAND_DONE)
1273                                 break;
1274                 }
1275
1276                 if (j >= NVRAM_TIMEOUT_COUNT) {
1277                         DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n");
1278                         return EBUSY;
1279                 }
1280         }
1281         return 0;
1282 }
1283
1284
1285 /****************************************************************************/
1286 /* Disable NVRAM write access.                                              */
1287 /*                                                                          */
1288 /* When the caller is finished writing to NVRAM write access must be        */
1289 /* disabled.                                                                */
1290 /*                                                                          */
1291 /* Returns:                                                                 */
1292 /*   Nothing.                                                               */
1293 /****************************************************************************/
1294 static void
1295 bce_disable_nvram_write(struct bce_softc *sc)
1296 {
1297         uint32_t val;
1298
1299         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM write.\n");
1300
1301         val = REG_RD(sc, BCE_MISC_CFG);
1302         REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);
1303 }
1304 #endif  /* BCE_NVRAM_WRITE_SUPPORT */
1305
1306
1307 /****************************************************************************/
1308 /* Enable NVRAM access.                                                     */
1309 /*                                                                          */
1310 /* Before accessing NVRAM for read or write operations the caller must      */
1311 /* enabled NVRAM access.                                                    */
1312 /*                                                                          */
1313 /* Returns:                                                                 */
1314 /*   Nothing.                                                               */
1315 /****************************************************************************/
1316 static void
1317 bce_enable_nvram_access(struct bce_softc *sc)
1318 {
1319         uint32_t val;
1320
1321         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1322
1323         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1324         /* Enable both bits, even on read. */
1325         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1326                val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1327 }
1328
1329
1330 /****************************************************************************/
1331 /* Disable NVRAM access.                                                    */
1332 /*                                                                          */
1333 /* When the caller is finished accessing NVRAM access must be disabled.     */
1334 /*                                                                          */
1335 /* Returns:                                                                 */
1336 /*   Nothing.                                                               */
1337 /****************************************************************************/
1338 static void
1339 bce_disable_nvram_access(struct bce_softc *sc)
1340 {
1341         uint32_t val;
1342
1343         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1344
1345         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1346
1347         /* Disable both bits, even after read. */
1348         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1349                val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1350 }
1351
1352
1353 #ifdef BCE_NVRAM_WRITE_SUPPORT
1354 /****************************************************************************/
1355 /* Erase NVRAM page before writing.                                         */
1356 /*                                                                          */
1357 /* Non-buffered flash parts require that a page be erased before it is      */
1358 /* written.                                                                 */
1359 /*                                                                          */
1360 /* Returns:                                                                 */
1361 /*   0 on success, positive value on failure.                               */
1362 /****************************************************************************/
1363 static int
1364 bce_nvram_erase_page(struct bce_softc *sc, uint32_t offset)
1365 {
1366         uint32_t cmd;
1367         int j;
1368
1369         /* Buffered flash doesn't require an erase. */
1370         if (sc->bce_flash_info->buffered)
1371                 return 0;
1372
1373         DBPRINT(sc, BCE_VERBOSE, "Erasing NVRAM page.\n");
1374
1375         /* Build an erase command. */
1376         cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR |
1377               BCE_NVM_COMMAND_DOIT;
1378
1379         /*
1380          * Clear the DONE bit separately, set the NVRAM adress to erase,
1381          * and issue the erase command.
1382          */
1383         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1384         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1385         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1386
1387         /* Wait for completion. */
1388         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1389                 uint32_t val;
1390
1391                 DELAY(5);
1392
1393                 val = REG_RD(sc, BCE_NVM_COMMAND);
1394                 if (val & BCE_NVM_COMMAND_DONE)
1395                         break;
1396         }
1397
1398         if (j >= NVRAM_TIMEOUT_COUNT) {
1399                 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n");
1400                 return EBUSY;
1401         }
1402         return 0;
1403 }
1404 #endif /* BCE_NVRAM_WRITE_SUPPORT */
1405
1406
1407 /****************************************************************************/
1408 /* Read a dword (32 bits) from NVRAM.                                       */
1409 /*                                                                          */
1410 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
1411 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
1412 /*                                                                          */
1413 /* Returns:                                                                 */
1414 /*   0 on success and the 32 bit value read, positive value on failure.     */
1415 /****************************************************************************/
1416 static int
1417 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1418                      uint32_t cmd_flags)
1419 {
1420         uint32_t cmd;
1421         int i, rc = 0;
1422
1423         /* Build the command word. */
1424         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1425
1426         /* Calculate the offset for buffered flash. */
1427         if (sc->bce_flash_info->buffered) {
1428                 offset = ((offset / sc->bce_flash_info->page_size) <<
1429                           sc->bce_flash_info->page_bits) +
1430                          (offset % sc->bce_flash_info->page_size);
1431         }
1432
1433         /*
1434          * Clear the DONE bit separately, set the address to read,
1435          * and issue the read.
1436          */
1437         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1438         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1439         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1440
1441         /* Wait for completion. */
1442         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1443                 uint32_t val;
1444
1445                 DELAY(5);
1446
1447                 val = REG_RD(sc, BCE_NVM_COMMAND);
1448                 if (val & BCE_NVM_COMMAND_DONE) {
1449                         val = REG_RD(sc, BCE_NVM_READ);
1450
1451                         val = be32toh(val);
1452                         memcpy(ret_val, &val, 4);
1453                         break;
1454                 }
1455         }
1456
1457         /* Check for errors. */
1458         if (i >= NVRAM_TIMEOUT_COUNT) {
1459                 if_printf(&sc->arpcom.ac_if,
1460                           "Timeout error reading NVRAM at offset 0x%08X!\n",
1461                           offset);
1462                 rc = EBUSY;
1463         }
1464         return rc;
1465 }
1466
1467
1468 #ifdef BCE_NVRAM_WRITE_SUPPORT
1469 /****************************************************************************/
1470 /* Write a dword (32 bits) to NVRAM.                                        */
1471 /*                                                                          */
1472 /* Write a 32 bit word to NVRAM.  The caller is assumed to have already     */
1473 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and    */
1474 /* enabled NVRAM write access.                                              */
1475 /*                                                                          */
1476 /* Returns:                                                                 */
1477 /*   0 on success, positive value on failure.                               */
1478 /****************************************************************************/
1479 static int
1480 bce_nvram_write_dword(struct bce_softc *sc, uint32_t offset, uint8_t *val,
1481                       uint32_t cmd_flags)
1482 {
1483         uint32_t cmd, val32;
1484         int j;
1485
1486         /* Build the command word. */
1487         cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags;
1488
1489         /* Calculate the offset for buffered flash. */
1490         if (sc->bce_flash_info->buffered) {
1491                 offset = ((offset / sc->bce_flash_info->page_size) <<
1492                           sc->bce_flash_info->page_bits) +
1493                          (offset % sc->bce_flash_info->page_size);
1494         }
1495
1496         /*
1497          * Clear the DONE bit separately, convert NVRAM data to big-endian,
1498          * set the NVRAM address to write, and issue the write command
1499          */
1500         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1501         memcpy(&val32, val, 4);
1502         val32 = htobe32(val32);
1503         REG_WR(sc, BCE_NVM_WRITE, val32);
1504         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1505         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1506
1507         /* Wait for completion. */
1508         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1509                 DELAY(5);
1510
1511                 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE)
1512                         break;
1513         }
1514         if (j >= NVRAM_TIMEOUT_COUNT) {
1515                 if_printf(&sc->arpcom.ac_if,
1516                           "Timeout error writing NVRAM at offset 0x%08X\n",
1517                           offset);
1518                 return EBUSY;
1519         }
1520         return 0;
1521 }
1522 #endif /* BCE_NVRAM_WRITE_SUPPORT */
1523
1524
1525 /****************************************************************************/
1526 /* Initialize NVRAM access.                                                 */
1527 /*                                                                          */
1528 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
1529 /* access that device.                                                      */
1530 /*                                                                          */
1531 /* Returns:                                                                 */
1532 /*   0 on success, positive value on failure.                               */
1533 /****************************************************************************/
1534 static int
1535 bce_init_nvram(struct bce_softc *sc)
1536 {
1537         uint32_t val;
1538         int j, entry_count, rc = 0;
1539         const struct flash_spec *flash;
1540
1541         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1542
1543         /* Determine the selected interface. */
1544         val = REG_RD(sc, BCE_NVM_CFG1);
1545
1546         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1547
1548         /*
1549          * Flash reconfiguration is required to support additional
1550          * NVRAM devices not directly supported in hardware.
1551          * Check if the flash interface was reconfigured
1552          * by the bootcode.
1553          */
1554
1555         if (val & 0x40000000) {
1556                 /* Flash interface reconfigured by bootcode. */
1557
1558                 DBPRINT(sc, BCE_INFO_LOAD,
1559                         "%s(): Flash WAS reconfigured.\n", __func__);
1560
1561                 for (j = 0, flash = flash_table; j < entry_count;
1562                      j++, flash++) {
1563                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1564                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1565                                 sc->bce_flash_info = flash;
1566                                 break;
1567                         }
1568                 }
1569         } else {
1570                 /* Flash interface not yet reconfigured. */
1571                 uint32_t mask;
1572
1573                 DBPRINT(sc, BCE_INFO_LOAD,
1574                         "%s(): Flash was NOT reconfigured.\n", __func__);
1575
1576                 if (val & (1 << 23))
1577                         mask = FLASH_BACKUP_STRAP_MASK;
1578                 else
1579                         mask = FLASH_STRAP_MASK;
1580
1581                 /* Look for the matching NVRAM device configuration data. */
1582                 for (j = 0, flash = flash_table; j < entry_count;
1583                      j++, flash++) {
1584                         /* Check if the device matches any of the known devices. */
1585                         if ((val & mask) == (flash->strapping & mask)) {
1586                                 /* Found a device match. */
1587                                 sc->bce_flash_info = flash;
1588
1589                                 /* Request access to the flash interface. */
1590                                 rc = bce_acquire_nvram_lock(sc);
1591                                 if (rc != 0)
1592                                         return rc;
1593
1594                                 /* Reconfigure the flash interface. */
1595                                 bce_enable_nvram_access(sc);
1596                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1597                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1598                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1599                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1600                                 bce_disable_nvram_access(sc);
1601                                 bce_release_nvram_lock(sc);
1602                                 break;
1603                         }
1604                 }
1605         }
1606
1607         /* Check if a matching device was found. */
1608         if (j == entry_count) {
1609                 sc->bce_flash_info = NULL;
1610                 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1611                 rc = ENODEV;
1612         }
1613
1614         /* Write the flash config data to the shared memory interface. */
1615         val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_SHARED_HW_CFG_CONFIG2) &
1616               BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1617         if (val)
1618                 sc->bce_flash_size = val;
1619         else
1620                 sc->bce_flash_size = sc->bce_flash_info->total_size;
1621
1622         DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1623                 __func__, sc->bce_flash_info->total_size);
1624
1625         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1626
1627         return rc;
1628 }
1629
1630
1631 /****************************************************************************/
1632 /* Read an arbitrary range of data from NVRAM.                              */
1633 /*                                                                          */
1634 /* Prepares the NVRAM interface for access and reads the requested data     */
1635 /* into the supplied buffer.                                                */
1636 /*                                                                          */
1637 /* Returns:                                                                 */
1638 /*   0 on success and the data read, positive value on failure.             */
1639 /****************************************************************************/
1640 static int
1641 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1642                int buf_size)
1643 {
1644         uint32_t cmd_flags, offset32, len32, extra;
1645         int rc = 0;
1646
1647         if (buf_size == 0)
1648                 return 0;
1649
1650         /* Request access to the flash interface. */
1651         rc = bce_acquire_nvram_lock(sc);
1652         if (rc != 0)
1653                 return rc;
1654
1655         /* Enable access to flash interface */
1656         bce_enable_nvram_access(sc);
1657
1658         len32 = buf_size;
1659         offset32 = offset;
1660         extra = 0;
1661
1662         cmd_flags = 0;
1663
1664         /* XXX should we release nvram lock if read_dword() fails? */
1665         if (offset32 & 3) {
1666                 uint8_t buf[4];
1667                 uint32_t pre_len;
1668
1669                 offset32 &= ~3;
1670                 pre_len = 4 - (offset & 3);
1671
1672                 if (pre_len >= len32) {
1673                         pre_len = len32;
1674                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1675                 } else {
1676                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1677                 }
1678
1679                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1680                 if (rc)
1681                         return rc;
1682
1683                 memcpy(ret_buf, buf + (offset & 3), pre_len);
1684
1685                 offset32 += 4;
1686                 ret_buf += pre_len;
1687                 len32 -= pre_len;
1688         }
1689
1690         if (len32 & 3) {
1691                 extra = 4 - (len32 & 3);
1692                 len32 = (len32 + 4) & ~3;
1693         }
1694
1695         if (len32 == 4) {
1696                 uint8_t buf[4];
1697
1698                 if (cmd_flags)
1699                         cmd_flags = BCE_NVM_COMMAND_LAST;
1700                 else
1701                         cmd_flags = BCE_NVM_COMMAND_FIRST |
1702                                     BCE_NVM_COMMAND_LAST;
1703
1704                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1705
1706                 memcpy(ret_buf, buf, 4 - extra);
1707         } else if (len32 > 0) {
1708                 uint8_t buf[4];
1709
1710                 /* Read the first word. */
1711                 if (cmd_flags)
1712                         cmd_flags = 0;
1713                 else
1714                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1715
1716                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1717
1718                 /* Advance to the next dword. */
1719                 offset32 += 4;
1720                 ret_buf += 4;
1721                 len32 -= 4;
1722
1723                 while (len32 > 4 && rc == 0) {
1724                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1725
1726                         /* Advance to the next dword. */
1727                         offset32 += 4;
1728                         ret_buf += 4;
1729                         len32 -= 4;
1730                 }
1731
1732                 if (rc)
1733                         return rc;
1734
1735                 cmd_flags = BCE_NVM_COMMAND_LAST;
1736                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1737
1738                 memcpy(ret_buf, buf, 4 - extra);
1739         }
1740
1741         /* Disable access to flash interface and release the lock. */
1742         bce_disable_nvram_access(sc);
1743         bce_release_nvram_lock(sc);
1744
1745         return rc;
1746 }
1747
1748
1749 #ifdef BCE_NVRAM_WRITE_SUPPORT
1750 /****************************************************************************/
1751 /* Write an arbitrary range of data from NVRAM.                             */
1752 /*                                                                          */
1753 /* Prepares the NVRAM interface for write access and writes the requested   */
1754 /* data from the supplied buffer.  The caller is responsible for            */
1755 /* calculating any appropriate CRCs.                                        */
1756 /*                                                                          */
1757 /* Returns:                                                                 */
1758 /*   0 on success, positive value on failure.                               */
1759 /****************************************************************************/
1760 static int
1761 bce_nvram_write(struct bce_softc *sc, uint32_t offset, uint8_t *data_buf,
1762                 int buf_size)
1763 {
1764         uint32_t written, offset32, len32;
1765         uint8_t *buf, start[4], end[4];
1766         int rc = 0;
1767         int align_start, align_end;
1768
1769         buf = data_buf;
1770         offset32 = offset;
1771         len32 = buf_size;
1772         align_end = 0;
1773         align_start = (offset32 & 3);
1774
1775         if (align_start) {
1776                 offset32 &= ~3;
1777                 len32 += align_start;
1778                 rc = bce_nvram_read(sc, offset32, start, 4);
1779                 if (rc)
1780                         return rc;
1781         }
1782
1783         if (len32 & 3) {
1784                 if (len32 > 4 || !align_start) {
1785                         align_end = 4 - (len32 & 3);
1786                         len32 += align_end;
1787                         rc = bce_nvram_read(sc, offset32 + len32 - 4, end, 4);
1788                         if (rc)
1789                                 return rc;
1790                 }
1791         }
1792
1793         if (align_start || align_end) {
1794                 buf = kmalloc(len32, M_DEVBUF, M_NOWAIT);
1795                 if (buf == NULL)
1796                         return ENOMEM;
1797                 if (align_start)
1798                         memcpy(buf, start, 4);
1799                 if (align_end)
1800                         memcpy(buf + len32 - 4, end, 4);
1801                 memcpy(buf + align_start, data_buf, buf_size);
1802         }
1803
1804         written = 0;
1805         while (written < len32 && rc == 0) {
1806                 uint32_t page_start, page_end, data_start, data_end;
1807                 uint32_t addr, cmd_flags;
1808                 int i;
1809                 uint8_t flash_buffer[264];
1810
1811                 /* Find the page_start addr */
1812                 page_start = offset32 + written;
1813                 page_start -= (page_start % sc->bce_flash_info->page_size);
1814                 /* Find the page_end addr */
1815                 page_end = page_start + sc->bce_flash_info->page_size;
1816                 /* Find the data_start addr */
1817                 data_start = (written == 0) ? offset32 : page_start;
1818                 /* Find the data_end addr */
1819                 data_end = (page_end > offset32 + len32) ? (offset32 + len32)
1820                                                          : page_end;
1821
1822                 /* Request access to the flash interface. */
1823                 rc = bce_acquire_nvram_lock(sc);
1824                 if (rc != 0)
1825                         goto nvram_write_end;
1826
1827                 /* Enable access to flash interface */
1828                 bce_enable_nvram_access(sc);
1829
1830                 cmd_flags = BCE_NVM_COMMAND_FIRST;
1831                 if (sc->bce_flash_info->buffered == 0) {
1832                         int j;
1833
1834                         /*
1835                          * Read the whole page into the buffer
1836                          * (non-buffer flash only)
1837                          */
1838                         for (j = 0; j < sc->bce_flash_info->page_size; j += 4) {
1839                                 if (j == (sc->bce_flash_info->page_size - 4))
1840                                         cmd_flags |= BCE_NVM_COMMAND_LAST;
1841
1842                                 rc = bce_nvram_read_dword(sc, page_start + j,
1843                                                           &flash_buffer[j],
1844                                                           cmd_flags);
1845                                 if (rc)
1846                                         goto nvram_write_end;
1847
1848                                 cmd_flags = 0;
1849                         }
1850                 }
1851
1852                 /* Enable writes to flash interface (unlock write-protect) */
1853                 rc = bce_enable_nvram_write(sc);
1854                 if (rc != 0)
1855                         goto nvram_write_end;
1856
1857                 /* Erase the page */
1858                 rc = bce_nvram_erase_page(sc, page_start);
1859                 if (rc != 0)
1860                         goto nvram_write_end;
1861
1862                 /* Re-enable the write again for the actual write */
1863                 bce_enable_nvram_write(sc);
1864
1865                 /* Loop to write back the buffer data from page_start to
1866                  * data_start */
1867                 i = 0;
1868                 if (sc->bce_flash_info->buffered == 0) {
1869                         for (addr = page_start; addr < data_start;
1870                              addr += 4, i += 4) {
1871                                 rc = bce_nvram_write_dword(sc, addr,
1872                                                            &flash_buffer[i],
1873                                                            cmd_flags);
1874                                 if (rc != 0)
1875                                         goto nvram_write_end;
1876
1877                                 cmd_flags = 0;
1878                         }
1879                 }
1880
1881                 /* Loop to write the new data from data_start to data_end */
1882                 for (addr = data_start; addr < data_end; addr += 4, i++) {
1883                         if (addr == page_end - 4 ||
1884                             (sc->bce_flash_info->buffered &&
1885                              addr == data_end - 4))
1886                                 cmd_flags |= BCE_NVM_COMMAND_LAST;
1887
1888                         rc = bce_nvram_write_dword(sc, addr, buf, cmd_flags);
1889                         if (rc != 0)
1890                                 goto nvram_write_end;
1891
1892                         cmd_flags = 0;
1893                         buf += 4;
1894                 }
1895
1896                 /* Loop to write back the buffer data from data_end
1897                  * to page_end */
1898                 if (sc->bce_flash_info->buffered == 0) {
1899                         for (addr = data_end; addr < page_end;
1900                              addr += 4, i += 4) {
1901                                 if (addr == page_end-4)
1902                                         cmd_flags = BCE_NVM_COMMAND_LAST;
1903
1904                                 rc = bce_nvram_write_dword(sc, addr,
1905                                         &flash_buffer[i], cmd_flags);
1906                                 if (rc != 0)
1907                                         goto nvram_write_end;
1908
1909                                 cmd_flags = 0;
1910                         }
1911                 }
1912
1913                 /* Disable writes to flash interface (lock write-protect) */
1914                 bce_disable_nvram_write(sc);
1915
1916                 /* Disable access to flash interface */
1917                 bce_disable_nvram_access(sc);
1918                 bce_release_nvram_lock(sc);
1919
1920                 /* Increment written */
1921                 written += data_end - data_start;
1922         }
1923
1924 nvram_write_end:
1925         if (align_start || align_end)
1926                 kfree(buf, M_DEVBUF);
1927         return rc;
1928 }
1929 #endif /* BCE_NVRAM_WRITE_SUPPORT */
1930
1931
1932 /****************************************************************************/
1933 /* Verifies that NVRAM is accessible and contains valid data.               */
1934 /*                                                                          */
1935 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
1936 /* correct.                                                                 */
1937 /*                                                                          */
1938 /* Returns:                                                                 */
1939 /*   0 on success, positive value on failure.                               */
1940 /****************************************************************************/
1941 static int
1942 bce_nvram_test(struct bce_softc *sc)
1943 {
1944         uint32_t buf[BCE_NVRAM_SIZE / 4];
1945         uint32_t magic, csum;
1946         uint8_t *data = (uint8_t *)buf;
1947         int rc = 0;
1948
1949         /*
1950          * Check that the device NVRAM is valid by reading
1951          * the magic value at offset 0.
1952          */
1953         rc = bce_nvram_read(sc, 0, data, 4);
1954         if (rc != 0)
1955                 return rc;
1956
1957         magic = be32toh(buf[0]);
1958         if (magic != BCE_NVRAM_MAGIC) {
1959                 if_printf(&sc->arpcom.ac_if,
1960                           "Invalid NVRAM magic value! Expected: 0x%08X, "
1961                           "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1962                 return ENODEV;
1963         }
1964
1965         /*
1966          * Verify that the device NVRAM includes valid
1967          * configuration data.
1968          */
1969         rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1970         if (rc != 0)
1971                 return rc;
1972
1973         csum = ether_crc32_le(data, 0x100);
1974         if (csum != BCE_CRC32_RESIDUAL) {
1975                 if_printf(&sc->arpcom.ac_if,
1976                           "Invalid Manufacturing Information NVRAM CRC! "
1977                           "Expected: 0x%08X, Found: 0x%08X\n",
1978                           BCE_CRC32_RESIDUAL, csum);
1979                 return ENODEV;
1980         }
1981
1982         csum = ether_crc32_le(data + 0x100, 0x100);
1983         if (csum != BCE_CRC32_RESIDUAL) {
1984                 if_printf(&sc->arpcom.ac_if,
1985                           "Invalid Feature Configuration Information "
1986                           "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1987                           BCE_CRC32_RESIDUAL, csum);
1988                 rc = ENODEV;
1989         }
1990         return rc;
1991 }
1992
1993
1994 /****************************************************************************/
1995 /* Free any DMA memory owned by the driver.                                 */
1996 /*                                                                          */
1997 /* Scans through each data structre that requires DMA memory and frees      */
1998 /* the memory if allocated.                                                 */
1999 /*                                                                          */
2000 /* Returns:                                                                 */
2001 /*   Nothing.                                                               */
2002 /****************************************************************************/
2003 static void
2004 bce_dma_free(struct bce_softc *sc)
2005 {
2006         int i;
2007
2008         /* Destroy the status block. */
2009         if (sc->status_tag != NULL) {
2010                 if (sc->status_block != NULL) {
2011                         bus_dmamap_unload(sc->status_tag, sc->status_map);
2012                         bus_dmamem_free(sc->status_tag, sc->status_block,
2013                                         sc->status_map);
2014                 }
2015                 bus_dma_tag_destroy(sc->status_tag);
2016         }
2017
2018
2019         /* Destroy the statistics block. */
2020         if (sc->stats_tag != NULL) {
2021                 if (sc->stats_block != NULL) {
2022                         bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2023                         bus_dmamem_free(sc->stats_tag, sc->stats_block,
2024                                         sc->stats_map);
2025                 }
2026                 bus_dma_tag_destroy(sc->stats_tag);
2027         }
2028
2029         /* Destroy the TX buffer descriptor DMA stuffs. */
2030         if (sc->tx_bd_chain_tag != NULL) {
2031                 for (i = 0; i < TX_PAGES; i++) {
2032                         if (sc->tx_bd_chain[i] != NULL) {
2033                                 bus_dmamap_unload(sc->tx_bd_chain_tag,
2034                                                   sc->tx_bd_chain_map[i]);
2035                                 bus_dmamem_free(sc->tx_bd_chain_tag,
2036                                                 sc->tx_bd_chain[i],
2037                                                 sc->tx_bd_chain_map[i]);
2038                         }
2039                 }
2040                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2041         }
2042
2043         /* Destroy the RX buffer descriptor DMA stuffs. */
2044         if (sc->rx_bd_chain_tag != NULL) {
2045                 for (i = 0; i < RX_PAGES; i++) {
2046                         if (sc->rx_bd_chain[i] != NULL) {
2047                                 bus_dmamap_unload(sc->rx_bd_chain_tag,
2048                                                   sc->rx_bd_chain_map[i]);
2049                                 bus_dmamem_free(sc->rx_bd_chain_tag,
2050                                                 sc->rx_bd_chain[i],
2051                                                 sc->rx_bd_chain_map[i]);
2052                         }
2053                 }
2054                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2055         }
2056
2057         /* Destroy the TX mbuf DMA stuffs. */
2058         if (sc->tx_mbuf_tag != NULL) {
2059                 for (i = 0; i < TOTAL_TX_BD; i++) {
2060                         /* Must have been unloaded in bce_stop() */
2061                         KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2062                         bus_dmamap_destroy(sc->tx_mbuf_tag,
2063                                            sc->tx_mbuf_map[i]);
2064                 }
2065                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2066         }
2067
2068         /* Destroy the RX mbuf DMA stuffs. */
2069         if (sc->rx_mbuf_tag != NULL) {
2070                 for (i = 0; i < TOTAL_RX_BD; i++) {
2071                         /* Must have been unloaded in bce_stop() */
2072                         KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2073                         bus_dmamap_destroy(sc->rx_mbuf_tag,
2074                                            sc->rx_mbuf_map[i]);
2075                 }
2076                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2077         }
2078
2079         /* Destroy the parent tag */
2080         if (sc->parent_tag != NULL)
2081                 bus_dma_tag_destroy(sc->parent_tag);
2082 }
2083
2084
2085 /****************************************************************************/
2086 /* Get DMA memory from the OS.                                              */
2087 /*                                                                          */
2088 /* Validates that the OS has provided DMA buffers in response to a          */
2089 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
2090 /* When the callback is used the OS will return 0 for the mapping function  */
2091 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
2092 /* failures back to the caller.                                             */
2093 /*                                                                          */
2094 /* Returns:                                                                 */
2095 /*   Nothing.                                                               */
2096 /****************************************************************************/
2097 static void
2098 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2099 {
2100         bus_addr_t *busaddr = arg;
2101
2102         /*
2103          * Simulate a mapping failure.
2104          * XXX not correct.
2105          */
2106         DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2107                 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2108                         __FILE__, __LINE__);
2109                 error = ENOMEM);
2110
2111         /* Check for an error and signal the caller that an error occurred. */
2112         if (error)
2113                 return;
2114
2115         KASSERT(nseg == 1, ("only one segment is allowed\n"));
2116         *busaddr = segs->ds_addr;
2117 }
2118
2119
2120 static void
2121 bce_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nsegs,
2122                  bus_size_t mapsz __unused, int error)
2123 {
2124         struct bce_dmamap_arg *ctx = arg;
2125         int i;
2126
2127         if (error)
2128                 return;
2129
2130         if (nsegs > ctx->bce_maxsegs) {
2131                 ctx->bce_maxsegs = 0;
2132                 return;
2133         }
2134
2135         ctx->bce_maxsegs = nsegs;
2136         for (i = 0; i < nsegs; ++i)
2137                 ctx->bce_segs[i] = segs[i];
2138 }
2139
2140
2141 /****************************************************************************/
2142 /* Allocate any DMA memory needed by the driver.                            */
2143 /*                                                                          */
2144 /* Allocates DMA memory needed for the various global structures needed by  */
2145 /* hardware.                                                                */
2146 /*                                                                          */
2147 /* Returns:                                                                 */
2148 /*   0 for success, positive value for failure.                             */
2149 /****************************************************************************/
2150 static int
2151 bce_dma_alloc(struct bce_softc *sc)
2152 {
2153         struct ifnet *ifp = &sc->arpcom.ac_if;
2154         int i, j, rc = 0;
2155         bus_addr_t busaddr;
2156
2157         /*
2158          * Allocate the parent bus DMA tag appropriate for PCI.
2159          */
2160         rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2161                                 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2162                                 NULL, NULL,
2163                                 MAXBSIZE, BUS_SPACE_UNRESTRICTED,
2164                                 BUS_SPACE_MAXSIZE_32BIT,
2165                                 0, &sc->parent_tag);
2166         if (rc != 0) {
2167                 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2168                 return rc;
2169         }
2170
2171         /*
2172          * Create a DMA tag for the status block, allocate and clear the
2173          * memory, map the memory into DMA space, and fetch the physical
2174          * address of the block.
2175          */
2176         rc = bus_dma_tag_create(sc->parent_tag,
2177                                 BCE_DMA_ALIGN, BCE_DMA_BOUNDARY,
2178                                 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2179                                 NULL, NULL,
2180                                 BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ,
2181                                 0, &sc->status_tag);
2182         if (rc != 0) {
2183                 if_printf(ifp, "Could not allocate status block DMA tag!\n");
2184                 return rc;
2185         }
2186
2187         rc = bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block,
2188                               BUS_DMA_WAITOK | BUS_DMA_ZERO,
2189                               &sc->status_map);
2190         if (rc != 0) {
2191                 if_printf(ifp, "Could not allocate status block DMA memory!\n");
2192                 return rc;
2193         }
2194
2195         rc = bus_dmamap_load(sc->status_tag, sc->status_map,
2196                              sc->status_block, BCE_STATUS_BLK_SZ,
2197                              bce_dma_map_addr, &busaddr, BUS_DMA_WAITOK);
2198         if (rc != 0) {
2199                 if_printf(ifp, "Could not map status block DMA memory!\n");
2200                 bus_dmamem_free(sc->status_tag, sc->status_block,
2201                                 sc->status_map);
2202                 sc->status_block = NULL;
2203                 return rc;
2204         }
2205
2206         sc->status_block_paddr = busaddr;
2207         /* DRC - Fix for 64 bit addresses. */
2208         DBPRINT(sc, BCE_INFO, "status_block_paddr = 0x%08X\n",
2209                 (uint32_t)sc->status_block_paddr);
2210
2211         /*
2212          * Create a DMA tag for the statistics block, allocate and clear the
2213          * memory, map the memory into DMA space, and fetch the physical
2214          * address of the block.
2215          */
2216         rc = bus_dma_tag_create(sc->parent_tag,
2217                                 BCE_DMA_ALIGN, BCE_DMA_BOUNDARY,
2218                                 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2219                                 NULL, NULL,
2220                                 BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ,
2221                                 0, &sc->stats_tag);
2222         if (rc != 0) {
2223                 if_printf(ifp, "Could not allocate "
2224                           "statistics block DMA tag!\n");
2225                 return rc;
2226         }
2227
2228         rc = bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block,
2229                               BUS_DMA_WAITOK | BUS_DMA_ZERO,
2230                               &sc->stats_map);
2231         if (rc != 0) {
2232                 if_printf(ifp, "Could not allocate "
2233                           "statistics block DMA memory!\n");
2234                 return rc;
2235         }
2236
2237         rc = bus_dmamap_load(sc->stats_tag, sc->stats_map,
2238                              sc->stats_block, BCE_STATS_BLK_SZ,
2239                              bce_dma_map_addr, &busaddr, BUS_DMA_WAITOK);
2240         if (rc != 0) {
2241                 if_printf(ifp, "Could not map statistics block DMA memory!\n");
2242                 bus_dmamem_free(sc->stats_tag, sc->stats_block, sc->stats_map);
2243                 sc->stats_block = NULL;
2244                 return rc;
2245         }
2246
2247         sc->stats_block_paddr = busaddr;
2248         /* DRC - Fix for 64 bit address. */
2249         DBPRINT(sc, BCE_INFO, "stats_block_paddr = 0x%08X\n",
2250                 (uint32_t)sc->stats_block_paddr);
2251
2252         /*
2253          * Create a DMA tag for the TX buffer descriptor chain,
2254          * allocate and clear the  memory, and fetch the
2255          * physical address of the block.
2256          */
2257         rc = bus_dma_tag_create(sc->parent_tag,
2258                                 BCM_PAGE_SIZE, BCE_DMA_BOUNDARY,
2259                                 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2260                                 NULL, NULL,
2261                                 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2262                                 0, &sc->tx_bd_chain_tag);
2263         if (rc != 0) {
2264                 if_printf(ifp, "Could not allocate "
2265                           "TX descriptor chain DMA tag!\n");
2266                 return rc;
2267         }
2268
2269         for (i = 0; i < TX_PAGES; i++) {
2270                 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2271                                       (void **)&sc->tx_bd_chain[i],
2272                                       BUS_DMA_WAITOK, &sc->tx_bd_chain_map[i]);
2273                 if (rc != 0) {
2274                         if_printf(ifp, "Could not allocate %dth TX descriptor "
2275                                   "chain DMA memory!\n", i);
2276                         return rc;
2277                 }
2278
2279                 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2280                                      sc->tx_bd_chain_map[i],
2281                                      sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2282                                      bce_dma_map_addr, &busaddr,
2283                                      BUS_DMA_WAITOK);
2284                 if (rc != 0) {
2285                         if_printf(ifp, "Could not map %dth TX descriptor "
2286                                   "chain DMA memory!\n", i);
2287                         bus_dmamem_free(sc->tx_bd_chain_tag,
2288                                         sc->tx_bd_chain[i],
2289                                         sc->tx_bd_chain_map[i]);
2290                         sc->tx_bd_chain[i] = NULL;
2291                         return rc;
2292                 }
2293
2294                 sc->tx_bd_chain_paddr[i] = busaddr;
2295                 /* DRC - Fix for 64 bit systems. */
2296                 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2297                         i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2298         }
2299
2300         /* Create a DMA tag for TX mbufs. */
2301         rc = bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
2302                                 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2303                                 NULL, NULL,
2304                                 MCLBYTES * BCE_MAX_SEGMENTS,
2305                                 BCE_MAX_SEGMENTS, MCLBYTES,
2306                                 0, &sc->tx_mbuf_tag);
2307         if (rc != 0) {
2308                 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2309                 return rc;
2310         }
2311
2312         /* Create DMA maps for the TX mbufs clusters. */
2313         for (i = 0; i < TOTAL_TX_BD; i++) {
2314                 rc = bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_WAITOK,
2315                                        &sc->tx_mbuf_map[i]);
2316                 if (rc != 0) {
2317                         for (j = 0; j < i; ++j) {
2318                                 bus_dmamap_destroy(sc->tx_mbuf_tag,
2319                                                    sc->tx_mbuf_map[i]);
2320                         }
2321                         bus_dma_tag_destroy(sc->tx_mbuf_tag);
2322                         sc->tx_mbuf_tag = NULL;
2323
2324                         if_printf(ifp, "Unable to create "
2325                                   "%dth TX mbuf DMA map!\n", i);
2326                         return rc;
2327                 }
2328         }
2329
2330         /*
2331          * Create a DMA tag for the RX buffer descriptor chain,
2332          * allocate and clear the  memory, and fetch the physical
2333          * address of the blocks.
2334          */
2335         rc = bus_dma_tag_create(sc->parent_tag,
2336                                 BCM_PAGE_SIZE, BCE_DMA_BOUNDARY,
2337                                 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2338                                 NULL, NULL,
2339                                 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2340                                 0, &sc->rx_bd_chain_tag);
2341         if (rc != 0) {
2342                 if_printf(ifp, "Could not allocate "
2343                           "RX descriptor chain DMA tag!\n");
2344                 return rc;
2345         }
2346
2347         for (i = 0; i < RX_PAGES; i++) {
2348                 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2349                                       (void **)&sc->rx_bd_chain[i],
2350                                       BUS_DMA_WAITOK | BUS_DMA_ZERO,
2351                                       &sc->rx_bd_chain_map[i]);
2352                 if (rc != 0) {
2353                         if_printf(ifp, "Could not allocate %dth RX descriptor "
2354                                   "chain DMA memory!\n", i);
2355                         return rc;
2356                 }
2357
2358                 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2359                                      sc->rx_bd_chain_map[i],
2360                                      sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2361                                      bce_dma_map_addr, &busaddr,
2362                                      BUS_DMA_WAITOK);
2363                 if (rc != 0) {
2364                         if_printf(ifp, "Could not map %dth RX descriptor "
2365                                   "chain DMA memory!\n", i);
2366                         bus_dmamem_free(sc->rx_bd_chain_tag,
2367                                         sc->rx_bd_chain[i],
2368                                         sc->rx_bd_chain_map[i]);
2369                         sc->rx_bd_chain[i] = NULL;
2370                         return rc;
2371                 }
2372
2373                 sc->rx_bd_chain_paddr[i] = busaddr;
2374                 /* DRC - Fix for 64 bit systems. */
2375                 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2376                         i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2377         }
2378
2379         /* Create a DMA tag for RX mbufs. */
2380         rc = bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
2381                                 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2382                                 NULL, NULL,
2383                                 MCLBYTES, 1/* BCE_MAX_SEGMENTS */, MCLBYTES,
2384                                 0, &sc->rx_mbuf_tag);
2385         if (rc != 0) {
2386                 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2387                 return rc;
2388         }
2389
2390         /* Create DMA maps for the RX mbuf clusters. */
2391         for (i = 0; i < TOTAL_RX_BD; i++) {
2392                 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2393                                        &sc->rx_mbuf_map[i]);
2394                 if (rc != 0) {
2395                         for (j = 0; j < i; ++j) {
2396                                 bus_dmamap_destroy(sc->rx_mbuf_tag,
2397                                                    sc->rx_mbuf_map[j]);
2398                         }
2399                         bus_dma_tag_destroy(sc->rx_mbuf_tag);
2400                         sc->rx_mbuf_tag = NULL;
2401
2402                         if_printf(ifp, "Unable to create "
2403                                   "%dth RX mbuf DMA map!\n", i);
2404                         return rc;
2405                 }
2406         }
2407         return 0;
2408 }
2409
2410
2411 /****************************************************************************/
2412 /* Firmware synchronization.                                                */
2413 /*                                                                          */
2414 /* Before performing certain events such as a chip reset, synchronize with  */
2415 /* the firmware first.                                                      */
2416 /*                                                                          */
2417 /* Returns:                                                                 */
2418 /*   0 for success, positive value for failure.                             */
2419 /****************************************************************************/
2420 static int
2421 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2422 {
2423         int i, rc = 0;
2424         uint32_t val;
2425
2426         /* Don't waste any time if we've timed out before. */
2427         if (sc->bce_fw_timed_out)
2428                 return EBUSY;
2429
2430         /* Increment the message sequence number. */
2431         sc->bce_fw_wr_seq++;
2432         msg_data |= sc->bce_fw_wr_seq;
2433
2434         DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2435
2436         /* Send the message to the bootcode driver mailbox. */
2437         REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
2438
2439         /* Wait for the bootcode to acknowledge the message. */
2440         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2441                 /* Check for a response in the bootcode firmware mailbox. */
2442                 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_FW_MB);
2443                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2444                         break;
2445                 DELAY(1000);
2446         }
2447
2448         /* If we've timed out, tell the bootcode that we've stopped waiting. */
2449         if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2450             (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2451                 if_printf(&sc->arpcom.ac_if,
2452                           "Firmware synchronization timeout! "
2453                           "msg_data = 0x%08X\n", msg_data);
2454
2455                 msg_data &= ~BCE_DRV_MSG_CODE;
2456                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2457
2458                 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
2459
2460                 sc->bce_fw_timed_out = 1;
2461                 rc = EBUSY;
2462         }
2463         return rc;
2464 }
2465
2466
2467 /****************************************************************************/
2468 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
2469 /*                                                                          */
2470 /* Returns:                                                                 */
2471 /*   Nothing.                                                               */
2472 /****************************************************************************/
2473 static void
2474 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2475                  uint32_t rv2p_code_len, uint32_t rv2p_proc)
2476 {
2477         int i;
2478         uint32_t val;
2479
2480         for (i = 0; i < rv2p_code_len; i += 8) {
2481                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2482                 rv2p_code++;
2483                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2484                 rv2p_code++;
2485
2486                 if (rv2p_proc == RV2P_PROC1) {
2487                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2488                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2489                 } else {
2490                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2491                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2492                 }
2493         }
2494
2495         /* Reset the processor, un-stall is done later. */
2496         if (rv2p_proc == RV2P_PROC1)
2497                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2498         else
2499                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2500 }
2501
2502
2503 /****************************************************************************/
2504 /* Load RISC processor firmware.                                            */
2505 /*                                                                          */
2506 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
2507 /* associated with a particular processor.                                  */
2508 /*                                                                          */
2509 /* Returns:                                                                 */
2510 /*   Nothing.                                                               */
2511 /****************************************************************************/
2512 static void
2513 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2514                 struct fw_info *fw)
2515 {
2516         uint32_t offset, val;
2517         int j;
2518
2519         /* Halt the CPU. */
2520         val = REG_RD_IND(sc, cpu_reg->mode);
2521         val |= cpu_reg->mode_value_halt;
2522         REG_WR_IND(sc, cpu_reg->mode, val);
2523         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2524
2525         /* Load the Text area. */
2526         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2527         if (fw->text) {
2528                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2529                         REG_WR_IND(sc, offset, fw->text[j]);
2530         }
2531
2532         /* Load the Data area. */
2533         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2534         if (fw->data) {
2535                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2536                         REG_WR_IND(sc, offset, fw->data[j]);
2537         }
2538
2539         /* Load the SBSS area. */
2540         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2541         if (fw->sbss) {
2542                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2543                         REG_WR_IND(sc, offset, fw->sbss[j]);
2544         }
2545
2546         /* Load the BSS area. */
2547         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2548         if (fw->bss) {
2549                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2550                         REG_WR_IND(sc, offset, fw->bss[j]);
2551         }
2552
2553         /* Load the Read-Only area. */
2554         offset = cpu_reg->spad_base +
2555                 (fw->rodata_addr - cpu_reg->mips_view_base);
2556         if (fw->rodata) {
2557                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2558                         REG_WR_IND(sc, offset, fw->rodata[j]);
2559         }
2560
2561         /* Clear the pre-fetch instruction. */
2562         REG_WR_IND(sc, cpu_reg->inst, 0);
2563         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2564
2565         /* Start the CPU. */
2566         val = REG_RD_IND(sc, cpu_reg->mode);
2567         val &= ~cpu_reg->mode_value_halt;
2568         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2569         REG_WR_IND(sc, cpu_reg->mode, val);
2570 }
2571
2572
2573 /****************************************************************************/
2574 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs.                         */
2575 /*                                                                          */
2576 /* Loads the firmware for each CPU and starts the CPU.                      */
2577 /*                                                                          */
2578 /* Returns:                                                                 */
2579 /*   Nothing.                                                               */
2580 /****************************************************************************/
2581 static void
2582 bce_init_cpus(struct bce_softc *sc)
2583 {
2584         struct cpu_reg cpu_reg;
2585         struct fw_info fw;
2586
2587         /* Initialize the RV2P processor. */
2588         bce_load_rv2p_fw(sc, bce_rv2p_proc1, sizeof(bce_rv2p_proc1), RV2P_PROC1);
2589         bce_load_rv2p_fw(sc, bce_rv2p_proc2, sizeof(bce_rv2p_proc2), RV2P_PROC2);
2590
2591         /* Initialize the RX Processor. */
2592         cpu_reg.mode = BCE_RXP_CPU_MODE;
2593         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2594         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2595         cpu_reg.state = BCE_RXP_CPU_STATE;
2596         cpu_reg.state_value_clear = 0xffffff;
2597         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2598         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2599         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2600         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2601         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2602         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2603         cpu_reg.mips_view_base = 0x8000000;
2604
2605         fw.ver_major = bce_RXP_b06FwReleaseMajor;
2606         fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2607         fw.ver_fix = bce_RXP_b06FwReleaseFix;
2608         fw.start_addr = bce_RXP_b06FwStartAddr;
2609
2610         fw.text_addr = bce_RXP_b06FwTextAddr;
2611         fw.text_len = bce_RXP_b06FwTextLen;
2612         fw.text_index = 0;
2613         fw.text = bce_RXP_b06FwText;
2614
2615         fw.data_addr = bce_RXP_b06FwDataAddr;
2616         fw.data_len = bce_RXP_b06FwDataLen;
2617         fw.data_index = 0;
2618         fw.data = bce_RXP_b06FwData;
2619
2620         fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2621         fw.sbss_len = bce_RXP_b06FwSbssLen;
2622         fw.sbss_index = 0;
2623         fw.sbss = bce_RXP_b06FwSbss;
2624
2625         fw.bss_addr = bce_RXP_b06FwBssAddr;
2626         fw.bss_len = bce_RXP_b06FwBssLen;
2627         fw.bss_index = 0;
2628         fw.bss = bce_RXP_b06FwBss;
2629
2630         fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2631         fw.rodata_len = bce_RXP_b06FwRodataLen;
2632         fw.rodata_index = 0;
2633         fw.rodata = bce_RXP_b06FwRodata;
2634
2635         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2636         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2637
2638         /* Initialize the TX Processor. */
2639         cpu_reg.mode = BCE_TXP_CPU_MODE;
2640         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2641         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2642         cpu_reg.state = BCE_TXP_CPU_STATE;
2643         cpu_reg.state_value_clear = 0xffffff;
2644         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2645         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2646         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2647         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2648         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2649         cpu_reg.spad_base = BCE_TXP_SCRATCH;
2650         cpu_reg.mips_view_base = 0x8000000;
2651
2652         fw.ver_major = bce_TXP_b06FwReleaseMajor;
2653         fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2654         fw.ver_fix = bce_TXP_b06FwReleaseFix;
2655         fw.start_addr = bce_TXP_b06FwStartAddr;
2656
2657         fw.text_addr = bce_TXP_b06FwTextAddr;
2658         fw.text_len = bce_TXP_b06FwTextLen;
2659         fw.text_index = 0;
2660         fw.text = bce_TXP_b06FwText;
2661
2662         fw.data_addr = bce_TXP_b06FwDataAddr;
2663         fw.data_len = bce_TXP_b06FwDataLen;
2664         fw.data_index = 0;
2665         fw.data = bce_TXP_b06FwData;
2666
2667         fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2668         fw.sbss_len = bce_TXP_b06FwSbssLen;
2669         fw.sbss_index = 0;
2670         fw.sbss = bce_TXP_b06FwSbss;
2671
2672         fw.bss_addr = bce_TXP_b06FwBssAddr;
2673         fw.bss_len = bce_TXP_b06FwBssLen;
2674         fw.bss_index = 0;
2675         fw.bss = bce_TXP_b06FwBss;
2676
2677         fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2678         fw.rodata_len = bce_TXP_b06FwRodataLen;
2679         fw.rodata_index = 0;
2680         fw.rodata = bce_TXP_b06FwRodata;
2681
2682         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2683         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2684
2685         /* Initialize the TX Patch-up Processor. */
2686         cpu_reg.mode = BCE_TPAT_CPU_MODE;
2687         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2688         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2689         cpu_reg.state = BCE_TPAT_CPU_STATE;
2690         cpu_reg.state_value_clear = 0xffffff;
2691         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2692         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2693         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2694         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2695         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2696         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2697         cpu_reg.mips_view_base = 0x8000000;
2698
2699         fw.ver_major = bce_TPAT_b06FwReleaseMajor;
2700         fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
2701         fw.ver_fix = bce_TPAT_b06FwReleaseFix;
2702         fw.start_addr = bce_TPAT_b06FwStartAddr;
2703
2704         fw.text_addr = bce_TPAT_b06FwTextAddr;
2705         fw.text_len = bce_TPAT_b06FwTextLen;
2706         fw.text_index = 0;
2707         fw.text = bce_TPAT_b06FwText;
2708
2709         fw.data_addr = bce_TPAT_b06FwDataAddr;
2710         fw.data_len = bce_TPAT_b06FwDataLen;
2711         fw.data_index = 0;
2712         fw.data = bce_TPAT_b06FwData;
2713
2714         fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
2715         fw.sbss_len = bce_TPAT_b06FwSbssLen;
2716         fw.sbss_index = 0;
2717         fw.sbss = bce_TPAT_b06FwSbss;
2718
2719         fw.bss_addr = bce_TPAT_b06FwBssAddr;
2720         fw.bss_len = bce_TPAT_b06FwBssLen;
2721         fw.bss_index = 0;
2722         fw.bss = bce_TPAT_b06FwBss;
2723
2724         fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
2725         fw.rodata_len = bce_TPAT_b06FwRodataLen;
2726         fw.rodata_index = 0;
2727         fw.rodata = bce_TPAT_b06FwRodata;
2728
2729         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
2730         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2731
2732         /* Initialize the Completion Processor. */
2733         cpu_reg.mode = BCE_COM_CPU_MODE;
2734         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
2735         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
2736         cpu_reg.state = BCE_COM_CPU_STATE;
2737         cpu_reg.state_value_clear = 0xffffff;
2738         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
2739         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
2740         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
2741         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
2742         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
2743         cpu_reg.spad_base = BCE_COM_SCRATCH;
2744         cpu_reg.mips_view_base = 0x8000000;
2745
2746         fw.ver_major = bce_COM_b06FwReleaseMajor;
2747         fw.ver_minor = bce_COM_b06FwReleaseMinor;
2748         fw.ver_fix = bce_COM_b06FwReleaseFix;
2749         fw.start_addr = bce_COM_b06FwStartAddr;
2750
2751         fw.text_addr = bce_COM_b06FwTextAddr;
2752         fw.text_len = bce_COM_b06FwTextLen;
2753         fw.text_index = 0;
2754         fw.text = bce_COM_b06FwText;
2755
2756         fw.data_addr = bce_COM_b06FwDataAddr;
2757         fw.data_len = bce_COM_b06FwDataLen;
2758         fw.data_index = 0;
2759         fw.data = bce_COM_b06FwData;
2760
2761         fw.sbss_addr = bce_COM_b06FwSbssAddr;
2762         fw.sbss_len = bce_COM_b06FwSbssLen;
2763         fw.sbss_index = 0;
2764         fw.sbss = bce_COM_b06FwSbss;
2765
2766         fw.bss_addr = bce_COM_b06FwBssAddr;
2767         fw.bss_len = bce_COM_b06FwBssLen;
2768         fw.bss_index = 0;
2769         fw.bss = bce_COM_b06FwBss;
2770
2771         fw.rodata_addr = bce_COM_b06FwRodataAddr;
2772         fw.rodata_len = bce_COM_b06FwRodataLen;
2773         fw.rodata_index = 0;
2774         fw.rodata = bce_COM_b06FwRodata;
2775
2776         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
2777         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2778 }
2779
2780
2781 /****************************************************************************/
2782 /* Initialize context memory.                                               */
2783 /*                                                                          */
2784 /* Clears the memory associated with each Context ID (CID).                 */
2785 /*                                                                          */
2786 /* Returns:                                                                 */
2787 /*   Nothing.                                                               */
2788 /****************************************************************************/
2789 static void
2790 bce_init_context(struct bce_softc *sc)
2791 {
2792         uint32_t vcid;
2793
2794         vcid = 96;
2795         while (vcid) {
2796                 uint32_t vcid_addr, pcid_addr, offset;
2797
2798                 vcid--;
2799
2800                 vcid_addr = GET_CID_ADDR(vcid);
2801                 pcid_addr = vcid_addr;
2802
2803                 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0x00);
2804                 REG_WR(sc, BCE_CTX_PAGE_TBL, pcid_addr);
2805
2806                 /* Zero out the context. */
2807                 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2808                         CTX_WR(sc, 0x00, offset, 0);
2809
2810                 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
2811                 REG_WR(sc, BCE_CTX_PAGE_TBL, pcid_addr);
2812         }
2813 }
2814
2815
2816 /****************************************************************************/
2817 /* Fetch the permanent MAC address of the controller.                       */
2818 /*                                                                          */
2819 /* Returns:                                                                 */
2820 /*   Nothing.                                                               */
2821 /****************************************************************************/
2822 static void
2823 bce_get_mac_addr(struct bce_softc *sc)
2824 {
2825         uint32_t mac_lo = 0, mac_hi = 0;
2826
2827         /*
2828          * The NetXtreme II bootcode populates various NIC
2829          * power-on and runtime configuration items in a
2830          * shared memory area.  The factory configured MAC
2831          * address is available from both NVRAM and the
2832          * shared memory area so we'll read the value from
2833          * shared memory for speed.
2834          */
2835
2836         mac_hi = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_HW_CFG_MAC_UPPER);
2837         mac_lo = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_HW_CFG_MAC_LOWER);
2838
2839         if (mac_lo == 0 && mac_hi == 0) {
2840                 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
2841         } else {
2842                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
2843                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
2844                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
2845                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
2846                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
2847                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
2848         }
2849
2850         DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
2851 }
2852
2853
2854 /****************************************************************************/
2855 /* Program the MAC address.                                                 */
2856 /*                                                                          */
2857 /* Returns:                                                                 */
2858 /*   Nothing.                                                               */
2859 /****************************************************************************/
2860 static void
2861 bce_set_mac_addr(struct bce_softc *sc)
2862 {
2863         const uint8_t *mac_addr = sc->eaddr;
2864         uint32_t val;
2865
2866         DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
2867                 sc->eaddr, ":");
2868
2869         val = (mac_addr[0] << 8) | mac_addr[1];
2870         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
2871
2872         val = (mac_addr[2] << 24) |
2873               (mac_addr[3] << 16) |
2874               (mac_addr[4] << 8) |
2875               mac_addr[5];
2876         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
2877 }
2878
2879
2880 /****************************************************************************/
2881 /* Stop the controller.                                                     */
2882 /*                                                                          */
2883 /* Returns:                                                                 */
2884 /*   Nothing.                                                               */
2885 /****************************************************************************/
2886 static void
2887 bce_stop(struct bce_softc *sc)
2888 {
2889         struct ifnet *ifp = &sc->arpcom.ac_if;
2890         struct mii_data *mii = device_get_softc(sc->bce_miibus);
2891         struct ifmedia_entry *ifm;
2892         int mtmp, itmp;
2893
2894         ASSERT_SERIALIZED(ifp->if_serializer);
2895
2896         callout_stop(&sc->bce_stat_ch);
2897
2898         /* Disable the transmit/receive blocks. */
2899         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 0x5ffffff);
2900         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
2901         DELAY(20);
2902
2903         bce_disable_intr(sc);
2904
2905         /* Tell firmware that the driver is going away. */
2906         bce_reset(sc, BCE_DRV_MSG_CODE_SUSPEND_NO_WOL);
2907
2908         /* Free the RX lists. */
2909         bce_free_rx_chain(sc);
2910
2911         /* Free TX buffers. */
2912         bce_free_tx_chain(sc);
2913
2914         /*
2915          * Isolate/power down the PHY, but leave the media selection
2916          * unchanged so that things will be put back to normal when
2917          * we bring the interface back up.
2918          *
2919          * 'mii' may be NULL if bce_stop() is called by bce_detach().
2920          */
2921         if (mii != NULL) {
2922                 itmp = ifp->if_flags;
2923                 ifp->if_flags |= IFF_UP;
2924                 ifm = mii->mii_media.ifm_cur;
2925                 mtmp = ifm->ifm_media;
2926                 ifm->ifm_media = IFM_ETHER | IFM_NONE;
2927                 mii_mediachg(mii);
2928                 ifm->ifm_media = mtmp;
2929                 ifp->if_flags = itmp;
2930         }
2931
2932         sc->bce_link = 0;
2933
2934         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2935         ifp->if_timer = 0;
2936
2937         bce_mgmt_init(sc);
2938 }
2939
2940
2941 static int
2942 bce_reset(struct bce_softc *sc, uint32_t reset_code)
2943 {
2944         uint32_t val;
2945         int i, rc = 0;
2946
2947         /* Wait for pending PCI transactions to complete. */
2948         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
2949                BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
2950                BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
2951                BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
2952                BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
2953         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
2954         DELAY(5);
2955
2956         /* Assume bootcode is running. */
2957         sc->bce_fw_timed_out = 0;
2958
2959         /* Give the firmware a chance to prepare for the reset. */
2960         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
2961         if (rc) {
2962                 if_printf(&sc->arpcom.ac_if,
2963                           "Firmware is not ready for reset\n");
2964                 return rc;
2965         }
2966
2967         /* Set a firmware reminder that this is a soft reset. */
2968         REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_RESET_SIGNATURE,
2969                    BCE_DRV_RESET_SIGNATURE_MAGIC);
2970
2971         /* Dummy read to force the chip to complete all current transactions. */
2972         val = REG_RD(sc, BCE_MISC_ID);
2973
2974         /* Chip reset. */
2975         val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2976               BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
2977               BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
2978         REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
2979
2980         /* Allow up to 30us for reset to complete. */
2981         for (i = 0; i < 10; i++) {
2982                 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
2983                 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2984                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
2985                         break;
2986                 }
2987                 DELAY(10);
2988         }
2989
2990         /* Check that reset completed successfully. */
2991         if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2992                    BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
2993                 if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
2994                 return EBUSY;
2995         }
2996
2997         /* Make sure byte swapping is properly configured. */
2998         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
2999         if (val != 0x01020304) {
3000                 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3001                 return ENODEV;
3002         }
3003
3004         /* Just completed a reset, assume that firmware is running again. */
3005         sc->bce_fw_timed_out = 0;
3006
3007         /* Wait for the firmware to finish its initialization. */
3008         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3009         if (rc) {
3010                 if_printf(&sc->arpcom.ac_if,
3011                           "Firmware did not complete initialization!\n");
3012         }
3013         return rc;
3014 }
3015
3016
3017 static int
3018 bce_chipinit(struct bce_softc *sc)
3019 {
3020         uint32_t val;
3021         int rc = 0;
3022
3023         /* Make sure the interrupt is not active. */
3024         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3025
3026         /*
3027          * Initialize DMA byte/word swapping, configure the number of DMA
3028          * channels and PCI clock compensation delay.
3029          */
3030         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3031               BCE_DMA_CONFIG_DATA_WORD_SWAP |
3032 #if BYTE_ORDER == BIG_ENDIAN
3033               BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3034 #endif
3035               BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3036               DMA_READ_CHANS << 12 |
3037               DMA_WRITE_CHANS << 16;
3038
3039         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3040
3041         if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3042                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3043
3044         /*
3045          * This setting resolves a problem observed on certain Intel PCI
3046          * chipsets that cannot handle multiple outstanding DMA operations.
3047          * See errata E9_5706A1_65.
3048          */
3049         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3050             BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3051             !(sc->bce_flags & BCE_PCIX_FLAG))
3052                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3053
3054         REG_WR(sc, BCE_DMA_CONFIG, val);
3055
3056         /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */
3057         if (sc->bce_flags & BCE_PCIX_FLAG) {
3058                 uint16_t cmd;
3059
3060                 cmd = pci_read_config(sc->bce_dev, BCE_PCI_PCIX_CMD, 2);
3061                 pci_write_config(sc->bce_dev, BCE_PCI_PCIX_CMD, cmd & ~0x2, 2);
3062         }
3063
3064         /* Enable the RX_V2P and Context state machines before access. */
3065         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3066                BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3067                BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3068                BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3069
3070         /* Initialize context mapping and zero out the quick contexts. */
3071         bce_init_context(sc);
3072
3073         /* Initialize the on-boards CPUs */
3074         bce_init_cpus(sc);
3075
3076         /* Prepare NVRAM for access. */
3077         rc = bce_init_nvram(sc);
3078         if (rc != 0)
3079                 return rc;
3080
3081         /* Set the kernel bypass block size */
3082         val = REG_RD(sc, BCE_MQ_CONFIG);
3083         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3084         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3085         REG_WR(sc, BCE_MQ_CONFIG, val);
3086
3087         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3088         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3089         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3090
3091         /* Set the page size and clear the RV2P processor stall bits. */
3092         val = (BCM_PAGE_BITS - 8) << 24;
3093         REG_WR(sc, BCE_RV2P_CONFIG, val);
3094
3095         /* Configure page size. */
3096         val = REG_RD(sc, BCE_TBDR_CONFIG);
3097         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3098         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3099         REG_WR(sc, BCE_TBDR_CONFIG, val);
3100
3101         return 0;
3102 }
3103
3104
3105 /****************************************************************************/
3106 /* Initialize the controller in preparation to send/receive traffic.        */
3107 /*                                                                          */
3108 /* Returns:                                                                 */
3109 /*   0 for success, positive value for failure.                             */
3110 /****************************************************************************/
3111 static int
3112 bce_blockinit(struct bce_softc *sc)
3113 {
3114         uint32_t reg, val;
3115         int rc = 0;
3116
3117         /* Load the hardware default MAC address. */
3118         bce_set_mac_addr(sc);
3119
3120         /* Set the Ethernet backoff seed value */
3121         val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3122               sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3123         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3124
3125         sc->last_status_idx = 0;
3126         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3127
3128         /* Set up link change interrupt generation. */
3129         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3130
3131         /* Program the physical address of the status block. */
3132         REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3133         REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3134
3135         /* Program the physical address of the statistics block. */
3136         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3137                BCE_ADDR_LO(sc->stats_block_paddr));
3138         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3139                BCE_ADDR_HI(sc->stats_block_paddr));
3140
3141         /* Program various host coalescing parameters. */
3142         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3143                (sc->bce_tx_quick_cons_trip_int << 16) |
3144                sc->bce_tx_quick_cons_trip);
3145         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3146                (sc->bce_rx_quick_cons_trip_int << 16) |
3147                sc->bce_rx_quick_cons_trip);
3148         REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3149                (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3150         REG_WR(sc, BCE_HC_TX_TICKS,
3151                (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3152         REG_WR(sc, BCE_HC_RX_TICKS,
3153                (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3154         REG_WR(sc, BCE_HC_COM_TICKS,
3155                (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3156         REG_WR(sc, BCE_HC_CMD_TICKS,
3157                (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3158         REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3159         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);   /* 3ms */
3160         REG_WR(sc, BCE_HC_CONFIG,
3161                BCE_HC_CONFIG_RX_TMR_MODE |
3162                BCE_HC_CONFIG_TX_TMR_MODE |
3163                BCE_HC_CONFIG_COLLECT_STATS);
3164
3165         /* Clear the internal statistics counters. */
3166         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3167
3168         /* Verify that bootcode is running. */
3169         reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_SIGNATURE);
3170
3171         DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3172                 if_printf(&sc->arpcom.ac_if,
3173                           "%s(%d): Simulating bootcode failure.\n",
3174                           __FILE__, __LINE__);
3175                 reg = 0);
3176
3177         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3178             BCE_DEV_INFO_SIGNATURE_MAGIC) {
3179                 if_printf(&sc->arpcom.ac_if,
3180                           "Bootcode not running! Found: 0x%08X, "
3181                           "Expected: 08%08X\n",
3182                           reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3183                           BCE_DEV_INFO_SIGNATURE_MAGIC);
3184                 return ENODEV;
3185         }
3186
3187         /* Check if any management firmware is running. */
3188         reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_FEATURE);
3189         if (reg & (BCE_PORT_FEATURE_ASF_ENABLED |
3190                    BCE_PORT_FEATURE_IMD_ENABLED)) {
3191                 DBPRINT(sc, BCE_INFO, "Management F/W Enabled.\n");
3192                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
3193         }
3194
3195         sc->bce_fw_ver =
3196                 REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_BC_REV);
3197         DBPRINT(sc, BCE_INFO, "bootcode rev = 0x%08X\n", sc->bce_fw_ver);
3198
3199         /* Allow bootcode to apply any additional fixes before enabling MAC. */
3200         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3201
3202         /* Enable link state change interrupt generation. */
3203         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3204
3205         /* Enable all remaining blocks in the MAC. */
3206         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 0x5ffffff);
3207         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3208         DELAY(20);
3209
3210         return 0;
3211 }
3212
3213
3214 /****************************************************************************/
3215 /* Encapsulate an mbuf cluster into the rx_bd chain.                        */
3216 /*                                                                          */
3217 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's.     */
3218 /* This routine will map an mbuf cluster into 1 or more rx_bd's as          */
3219 /* necessary.                                                               */
3220 /*                                                                          */
3221 /* Returns:                                                                 */
3222 /*   0 for success, positive value for failure.                             */
3223 /****************************************************************************/
3224 static int
3225 bce_newbuf_std(struct bce_softc *sc, struct mbuf *m,
3226                uint16_t *prod, uint16_t *chain_prod, uint32_t *prod_bseq)
3227 {
3228         bus_dmamap_t map;
3229         struct bce_dmamap_arg ctx;
3230         bus_dma_segment_t seg;
3231         struct mbuf *m_new;
3232         struct rx_bd *rxbd;
3233         int error;
3234 #ifdef BCE_DEBUG
3235         uint16_t debug_chain_prod = *chain_prod;
3236 #endif
3237
3238         /* Make sure the inputs are valid. */
3239         DBRUNIF((*chain_prod > MAX_RX_BD),
3240                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3241                           "RX producer out of range: 0x%04X > 0x%04X\n",
3242                           __FILE__, __LINE__,
3243                           *chain_prod, (uint16_t)MAX_RX_BD));
3244
3245         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3246                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3247
3248         if (m == NULL) {
3249                 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3250                         if_printf(&sc->arpcom.ac_if, "%s(%d): "
3251                                   "Simulating mbuf allocation failure.\n",
3252                                   __FILE__, __LINE__);
3253                         sc->mbuf_alloc_failed++;
3254                         return ENOBUFS);
3255
3256                 /* This is a new mbuf allocation. */
3257                 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
3258                 if (m_new == NULL)
3259                         return ENOBUFS;
3260                 DBRUNIF(1, sc->rx_mbuf_alloc++);
3261         } else {
3262                 m_new = m;
3263                 m_new->m_data = m_new->m_ext.ext_buf;
3264         }
3265         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3266
3267         /* Map the mbuf cluster into device memory. */
3268         map = sc->rx_mbuf_map[*chain_prod];
3269
3270         ctx.bce_maxsegs = 1;
3271         ctx.bce_segs = &seg;
3272         error = bus_dmamap_load_mbuf(sc->rx_mbuf_tag, map, m_new,
3273                                      bce_dma_map_mbuf, &ctx, BUS_DMA_NOWAIT);
3274         if (error || ctx.bce_maxsegs == 0) {
3275                 if_printf(&sc->arpcom.ac_if,
3276                           "Error mapping mbuf into RX chain!\n");
3277
3278                 if (m == NULL)
3279                         m_freem(m_new);
3280
3281                 DBRUNIF(1, sc->rx_mbuf_alloc--);
3282                 return ENOBUFS;
3283         }
3284
3285         /* Watch for overflow. */
3286         DBRUNIF((sc->free_rx_bd > USABLE_RX_BD),
3287                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3288                           "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3289                           __FILE__, __LINE__, sc->free_rx_bd,
3290                           (uint16_t)USABLE_RX_BD));
3291
3292         /* Update some debug statistic counters */
3293         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3294                 sc->rx_low_watermark = sc->free_rx_bd);
3295         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3296
3297         /* Setup the rx_bd for the first segment. */
3298         rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)];
3299
3300         rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(seg.ds_addr));
3301         rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(seg.ds_addr));
3302         rxbd->rx_bd_len = htole32(seg.ds_len);
3303         rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3304         *prod_bseq += seg.ds_len;
3305
3306         rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3307
3308         /* Save the mbuf and update our counter. */
3309         sc->rx_mbuf_ptr[*chain_prod] = m_new;
3310         sc->free_rx_bd--;
3311
3312         DBRUN(BCE_VERBOSE_RECV,
3313               bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3314
3315         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3316                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3317
3318         return 0;
3319 }
3320
3321
3322 /****************************************************************************/
3323 /* Allocate memory and initialize the TX data structures.                   */
3324 /*                                                                          */
3325 /* Returns:                                                                 */
3326 /*   0 for success, positive value for failure.                             */
3327 /****************************************************************************/
3328 static int
3329 bce_init_tx_chain(struct bce_softc *sc)
3330 {
3331         struct tx_bd *txbd;
3332         uint32_t val;
3333         int i, rc = 0;
3334
3335         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3336
3337         /* Set the initial TX producer/consumer indices. */
3338         sc->tx_prod = 0;
3339         sc->tx_cons = 0;
3340         sc->tx_prod_bseq   = 0;
3341         sc->used_tx_bd = 0;
3342         sc->max_tx_bd = USABLE_TX_BD;
3343         DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD);
3344         DBRUNIF(1, sc->tx_full_count = 0);
3345
3346         /*
3347          * The NetXtreme II supports a linked-list structre called
3348          * a Buffer Descriptor Chain (or BD chain).  A BD chain
3349          * consists of a series of 1 or more chain pages, each of which
3350          * consists of a fixed number of BD entries.
3351          * The last BD entry on each page is a pointer to the next page
3352          * in the chain, and the last pointer in the BD chain
3353          * points back to the beginning of the chain.
3354          */
3355
3356         /* Set the TX next pointer chain entries. */
3357         for (i = 0; i < TX_PAGES; i++) {
3358                 int j;
3359
3360                 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
3361
3362                 /* Check if we've reached the last page. */
3363                 if (i == (TX_PAGES - 1))
3364                         j = 0;
3365                 else
3366                         j = i + 1;
3367
3368                 txbd->tx_bd_haddr_hi =
3369                         htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
3370                 txbd->tx_bd_haddr_lo =
3371                         htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
3372         }
3373
3374         for (i = 0; i < TX_PAGES; ++i) {
3375                 bus_dmamap_sync(sc->tx_bd_chain_tag, sc->tx_bd_chain_map[i],
3376                                 BUS_DMASYNC_PREWRITE);
3377         }
3378
3379         /* Initialize the context ID for an L2 TX chain. */
3380         val = BCE_L2CTX_TYPE_TYPE_L2;
3381         val |= BCE_L2CTX_TYPE_SIZE_L2;
3382         CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TYPE, val);
3383
3384         val = BCE_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
3385         CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_CMD_TYPE, val);
3386
3387         /* Point the hardware to the first page in the chain. */
3388         val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3389         CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_HI, val);
3390         val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3391         CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_LO, val);
3392
3393         DBRUN(BCE_VERBOSE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD));
3394
3395         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3396
3397         return(rc);
3398 }
3399
3400
3401 /****************************************************************************/
3402 /* Free memory and clear the TX data structures.                            */
3403 /*                                                                          */
3404 /* Returns:                                                                 */
3405 /*   Nothing.                                                               */
3406 /****************************************************************************/
3407 static void
3408 bce_free_tx_chain(struct bce_softc *sc)
3409 {
3410         int i;
3411
3412         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3413
3414         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
3415         for (i = 0; i < TOTAL_TX_BD; i++) {
3416                 if (sc->tx_mbuf_ptr[i] != NULL) {
3417                         bus_dmamap_sync(sc->tx_mbuf_tag, sc->tx_mbuf_map[i],
3418                                         BUS_DMASYNC_POSTWRITE);
3419                         bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]);
3420                         m_freem(sc->tx_mbuf_ptr[i]);
3421                         sc->tx_mbuf_ptr[i] = NULL;
3422                         DBRUNIF(1, sc->tx_mbuf_alloc--);
3423                 }
3424         }
3425
3426         /* Clear each TX chain page. */
3427         for (i = 0; i < TX_PAGES; i++)
3428                 bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
3429
3430         /* Check if we lost any mbufs in the process. */
3431         DBRUNIF((sc->tx_mbuf_alloc),
3432                 if_printf(&sc->arpcom.ac_if,
3433                           "%s(%d): Memory leak! "
3434                           "Lost %d mbufs from tx chain!\n",
3435                           __FILE__, __LINE__, sc->tx_mbuf_alloc));
3436
3437         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3438 }
3439
3440
3441 /****************************************************************************/
3442 /* Allocate memory and initialize the RX data structures.                   */
3443 /*                                                                          */
3444 /* Returns:                                                                 */
3445 /*   0 for success, positive value for failure.                             */
3446 /****************************************************************************/
3447 static int
3448 bce_init_rx_chain(struct bce_softc *sc)
3449 {
3450         struct rx_bd *rxbd;
3451         int i, rc = 0;
3452         uint16_t prod, chain_prod;
3453         uint32_t prod_bseq, val;
3454
3455         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3456
3457         /* Initialize the RX producer and consumer indices. */
3458         sc->rx_prod = 0;
3459         sc->rx_cons = 0;
3460         sc->rx_prod_bseq = 0;
3461         sc->free_rx_bd = USABLE_RX_BD;
3462         sc->max_rx_bd = USABLE_RX_BD;
3463         DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD);
3464         DBRUNIF(1, sc->rx_empty_count = 0);
3465
3466         /* Initialize the RX next pointer chain entries. */
3467         for (i = 0; i < RX_PAGES; i++) {
3468                 int j;
3469
3470                 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
3471
3472                 /* Check if we've reached the last page. */
3473                 if (i == (RX_PAGES - 1))
3474                         j = 0;
3475                 else
3476                         j = i + 1;
3477
3478                 /* Setup the chain page pointers. */
3479                 rxbd->rx_bd_haddr_hi =
3480                         htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
3481                 rxbd->rx_bd_haddr_lo =
3482                         htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
3483         }
3484
3485         /* Initialize the context ID for an L2 RX chain. */
3486         val = BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3487         val |= BCE_L2CTX_CTX_TYPE_SIZE_L2;
3488         val |= 0x02 << 8;
3489         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_CTX_TYPE, val);
3490
3491         /* Point the hardware to the first page in the chain. */
3492         /* XXX shouldn't this after RX descriptor initialization? */
3493         val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
3494         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_HI, val);
3495         val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
3496         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_LO, val);
3497
3498         /* Allocate mbuf clusters for the rx_bd chain. */
3499         prod = prod_bseq = 0;
3500         while (prod < TOTAL_RX_BD) {
3501                 chain_prod = RX_CHAIN_IDX(prod);
3502                 if (bce_newbuf_std(sc, NULL, &prod, &chain_prod, &prod_bseq)) {
3503                         if_printf(&sc->arpcom.ac_if,
3504                                   "Error filling RX chain: rx_bd[0x%04X]!\n",
3505                                   chain_prod);
3506                         rc = ENOBUFS;
3507                         break;
3508                 }
3509                 prod = NEXT_RX_BD(prod);
3510         }
3511
3512         /* Save the RX chain producer index. */
3513         sc->rx_prod = prod;
3514         sc->rx_prod_bseq = prod_bseq;
3515
3516         for (i = 0; i < RX_PAGES; i++) {
3517                 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i],
3518                                 BUS_DMASYNC_PREWRITE);
3519         }
3520
3521         /* Tell the chip about the waiting rx_bd's. */
3522         REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BDIDX, sc->rx_prod);
3523         REG_WR(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BSEQ, sc->rx_prod_bseq);
3524
3525         DBRUN(BCE_VERBOSE_RECV, bce_dump_rx_chain(sc, 0, TOTAL_RX_BD));
3526
3527         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3528
3529         return(rc);
3530 }
3531
3532
3533 /****************************************************************************/
3534 /* Free memory and clear the RX data structures.                            */
3535 /*                                                                          */
3536 /* Returns:                                                                 */
3537 /*   Nothing.                                                               */
3538 /****************************************************************************/
3539 static void
3540 bce_free_rx_chain(struct bce_softc *sc)
3541 {
3542         int i;
3543
3544         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3545
3546         /* Free any mbufs still in the RX mbuf chain. */
3547         for (i = 0; i < TOTAL_RX_BD; i++) {
3548                 if (sc->rx_mbuf_ptr[i] != NULL) {
3549                         bus_dmamap_sync(sc->rx_mbuf_tag, sc->rx_mbuf_map[i],
3550                                         BUS_DMASYNC_POSTREAD);
3551                         bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]);
3552                         m_freem(sc->rx_mbuf_ptr[i]);
3553                         sc->rx_mbuf_ptr[i] = NULL;
3554                         DBRUNIF(1, sc->rx_mbuf_alloc--);
3555                 }
3556         }
3557
3558         /* Clear each RX chain page. */
3559         for (i = 0; i < RX_PAGES; i++)
3560                 bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
3561
3562         /* Check if we lost any mbufs in the process. */
3563         DBRUNIF((sc->rx_mbuf_alloc),
3564                 if_printf(&sc->arpcom.ac_if,
3565                           "%s(%d): Memory leak! "
3566                           "Lost %d mbufs from rx chain!\n",
3567                           __FILE__, __LINE__, sc->rx_mbuf_alloc));
3568
3569         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3570 }
3571
3572
3573 /****************************************************************************/
3574 /* Set media options.                                                       */
3575 /*                                                                          */
3576 /* Returns:                                                                 */
3577 /*   0 for success, positive value for failure.                             */
3578 /****************************************************************************/
3579 static int
3580 bce_ifmedia_upd(struct ifnet *ifp)
3581 {
3582         struct bce_softc *sc = ifp->if_softc;
3583         struct mii_data *mii = device_get_softc(sc->bce_miibus);
3584
3585         /*
3586          * 'mii' will be NULL, when this function is called on following
3587          * code path: bce_attach() -> bce_mgmt_init()
3588          */
3589         if (mii != NULL) {
3590                 /* Make sure the MII bus has been enumerated. */
3591                 sc->bce_link = 0;
3592                 if (mii->mii_instance) {
3593                         struct mii_softc *miisc;
3594
3595                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3596                                 mii_phy_reset(miisc);
3597                 }
3598                 mii_mediachg(mii);
3599         }
3600         return 0;
3601 }
3602
3603
3604 /****************************************************************************/
3605 /* Reports current media status.                                            */
3606 /*                                                                          */
3607 /* Returns:                                                                 */
3608 /*   Nothing.                                                               */
3609 /****************************************************************************/
3610 static void
3611 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3612 {
3613         struct bce_softc *sc = ifp->if_softc;
3614         struct mii_data *mii = device_get_softc(sc->bce_miibus);
3615
3616         mii_pollstat(mii);
3617         ifmr->ifm_active = mii->mii_media_active;
3618         ifmr->ifm_status = mii->mii_media_status;
3619 }
3620
3621
3622 /****************************************************************************/
3623 /* Handles PHY generated interrupt events.                                  */
3624 /*                                                                          */
3625 /* Returns:                                                                 */
3626 /*   Nothing.                                                               */
3627 /****************************************************************************/
3628 static void
3629 bce_phy_intr(struct bce_softc *sc)
3630 {
3631         uint32_t new_link_state, old_link_state;
3632         struct ifnet *ifp = &sc->arpcom.ac_if;
3633
3634         ASSERT_SERIALIZED(ifp->if_serializer);
3635
3636         new_link_state = sc->status_block->status_attn_bits &
3637                          STATUS_ATTN_BITS_LINK_STATE;
3638         old_link_state = sc->status_block->status_attn_bits_ack &
3639                          STATUS_ATTN_BITS_LINK_STATE;
3640
3641         /* Handle any changes if the link state has changed. */
3642         if (new_link_state != old_link_state) { /* XXX redundant? */
3643                 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
3644
3645                 sc->bce_link = 0;
3646                 callout_stop(&sc->bce_stat_ch);
3647                 bce_tick_serialized(sc);
3648
3649                 /* Update the status_attn_bits_ack field in the status block. */
3650                 if (new_link_state) {
3651                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
3652                                STATUS_ATTN_BITS_LINK_STATE);
3653                         if (bootverbose)
3654                                 if_printf(ifp, "Link is now UP.\n");
3655                 } else {
3656                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
3657                                STATUS_ATTN_BITS_LINK_STATE);
3658                         if (bootverbose)
3659                                 if_printf(ifp, "Link is now DOWN.\n");
3660                 }
3661         }
3662
3663         /* Acknowledge the link change interrupt. */
3664         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
3665 }
3666
3667
3668 /****************************************************************************/
3669 /* Handles received frame interrupt events.                                 */
3670 /*                                                                          */
3671 /* Returns:                                                                 */
3672 /*   Nothing.                                                               */
3673 /****************************************************************************/
3674 static void
3675 bce_rx_intr(struct bce_softc *sc, int count)
3676 {
3677         struct status_block *sblk = sc->status_block;
3678         struct ifnet *ifp = &sc->arpcom.ac_if;
3679         uint16_t hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
3680         uint32_t sw_prod_bseq;
3681         int i;
3682
3683         ASSERT_SERIALIZED(ifp->if_serializer);
3684
3685         DBRUNIF(1, sc->rx_interrupts++);
3686
3687         /* Prepare the RX chain pages to be accessed by the host CPU. */
3688         for (i = 0; i < RX_PAGES; i++) {
3689                 bus_dmamap_sync(sc->rx_bd_chain_tag,
3690                                 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
3691         }
3692
3693         /* Get the hardware's view of the RX consumer index. */
3694         hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
3695         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
3696                 hw_cons++;
3697
3698         /* Get working copies of the driver's view of the RX indices. */
3699         sw_cons = sc->rx_cons;
3700         sw_prod = sc->rx_prod;
3701         sw_prod_bseq = sc->rx_prod_bseq;
3702
3703         DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, "
3704                 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n",
3705                 __func__, sw_prod, sw_cons, sw_prod_bseq);
3706
3707         /* Prevent speculative reads from getting ahead of the status block. */
3708         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
3709                           BUS_SPACE_BARRIER_READ);
3710
3711         /* Update some debug statistics counters */
3712         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3713                 sc->rx_low_watermark = sc->free_rx_bd);
3714         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3715
3716         /* Scan through the receive chain as long as there is work to do. */
3717         while (sw_cons != hw_cons) {
3718                 struct mbuf *m = NULL;
3719                 struct l2_fhdr *l2fhdr = NULL;
3720                 struct rx_bd *rxbd;
3721                 unsigned int len;
3722                 uint32_t status = 0;
3723
3724 #ifdef foo /* DEVICE_POLLING */
3725                 /*
3726                  * Even if polling(4) is enabled, we can't just reap
3727                  * 'count' RX descriptors and leave.  It seems that RX
3728                  * engine would be left in a wired state, if we broke
3729                  * out the loop in the middle.
3730                  */
3731                 if (count >= 0 && count-- == 0)
3732                         break;
3733 #endif
3734
3735                 /*
3736                  * Convert the producer/consumer indices
3737                  * to an actual rx_bd index.
3738                  */
3739                 sw_chain_cons = RX_CHAIN_IDX(sw_cons);
3740                 sw_chain_prod = RX_CHAIN_IDX(sw_prod);
3741
3742                 /* Get the used rx_bd. */
3743                 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)]
3744                                        [RX_IDX(sw_chain_cons)];
3745                 sc->free_rx_bd++;
3746
3747                 DBRUN(BCE_VERBOSE_RECV,
3748                       if_printf(ifp, "%s(): ", __func__);
3749                       bce_dump_rxbd(sc, sw_chain_cons, rxbd));
3750
3751                 /* The mbuf is stored with the last rx_bd entry of a packet. */
3752                 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
3753                         /* Validate that this is the last rx_bd. */
3754                         DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)),
3755                                 if_printf(ifp, "%s(%d): "
3756                                 "Unexpected mbuf found in rx_bd[0x%04X]!\n",
3757                                 __FILE__, __LINE__, sw_chain_cons);
3758                                 bce_breakpoint(sc));
3759
3760                         /*
3761                          * ToDo: If the received packet is small enough
3762                          * to fit into a single, non-M_EXT mbuf,
3763                          * allocate a new mbuf here, copy the data to
3764                          * that mbuf, and recycle the mapped jumbo frame.
3765                          */
3766
3767                         /* Unmap the mbuf from DMA space. */
3768                         bus_dmamap_sync(sc->rx_mbuf_tag,
3769                                         sc->rx_mbuf_map[sw_chain_cons],
3770                                         BUS_DMASYNC_POSTREAD);
3771                         bus_dmamap_unload(sc->rx_mbuf_tag,
3772                                           sc->rx_mbuf_map[sw_chain_cons]);
3773
3774                         /* Remove the mbuf from the driver's chain. */
3775                         m = sc->rx_mbuf_ptr[sw_chain_cons];
3776                         sc->rx_mbuf_ptr[sw_chain_cons] = NULL;
3777
3778                         /*
3779                          * Frames received on the NetXteme II are prepended
3780                          * with an l2_fhdr structure which provides status
3781                          * information about the received frame (including
3782                          * VLAN tags and checksum info).  The frames are also
3783                          * automatically adjusted to align the IP header
3784                          * (i.e. two null bytes are inserted before the
3785                          * Ethernet header).
3786                          */
3787                         l2fhdr = mtod(m, struct l2_fhdr *);
3788
3789                         len = l2fhdr->l2_fhdr_pkt_len;
3790                         status = l2fhdr->l2_fhdr_status;
3791
3792                         DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
3793                                 if_printf(ifp,
3794                                 "Simulating l2_fhdr status error.\n");
3795                                 status = status | L2_FHDR_ERRORS_PHY_DECODE);
3796
3797                         /* Watch for unusual sized frames. */
3798                         DBRUNIF((len < BCE_MIN_MTU ||
3799                                  len > BCE_MAX_JUMBO_ETHER_MTU_VLAN),
3800                                 if_printf(ifp,
3801                                 "%s(%d): Unusual frame size found. "
3802                                 "Min(%d), Actual(%d), Max(%d)\n",
3803                                 __FILE__, __LINE__,
3804                                 (int)BCE_MIN_MTU, len,
3805                                 (int)BCE_MAX_JUMBO_ETHER_MTU_VLAN);
3806                                 bce_dump_mbuf(sc, m);
3807                                 bce_breakpoint(sc));
3808
3809                         len -= ETHER_CRC_LEN;
3810
3811                         /* Check the received frame for errors. */
3812                         if (status & (L2_FHDR_ERRORS_BAD_CRC |
3813                                       L2_FHDR_ERRORS_PHY_DECODE |
3814                                       L2_FHDR_ERRORS_ALIGNMENT |
3815                                       L2_FHDR_ERRORS_TOO_SHORT |
3816                                       L2_FHDR_ERRORS_GIANT_FRAME)) {
3817                                 ifp->if_ierrors++;
3818                                 DBRUNIF(1, sc->l2fhdr_status_errors++);
3819
3820                                 /* Reuse the mbuf for a new frame. */
3821                                 if (bce_newbuf_std(sc, m, &sw_prod,
3822                                                    &sw_chain_prod,
3823                                                    &sw_prod_bseq)) {
3824                                         DBRUNIF(1, bce_breakpoint(sc));
3825                                         /* XXX */
3826                                         panic("%s: Can't reuse RX mbuf!\n",
3827                                               ifp->if_xname);
3828                                 }
3829                                 m = NULL;
3830                                 goto bce_rx_int_next_rx;
3831                         }
3832
3833                         /*
3834                          * Get a new mbuf for the rx_bd.   If no new
3835                          * mbufs are available then reuse the current mbuf,
3836                          * log an ierror on the interface, and generate
3837                          * an error in the system log.
3838                          */
3839                         if (bce_newbuf_std(sc, NULL, &sw_prod, &sw_chain_prod,
3840                                            &sw_prod_bseq)) {
3841                                 DBRUN(BCE_WARN,
3842                                       if_printf(ifp,
3843                                       "%s(%d): Failed to allocate new mbuf, "
3844                                       "incoming frame dropped!\n",
3845                                       __FILE__, __LINE__));
3846
3847                                 ifp->if_ierrors++;
3848
3849                                 /* Try and reuse the exisitng mbuf. */
3850                                 if (bce_newbuf_std(sc, m, &sw_prod,
3851                                                    &sw_chain_prod,
3852                                                    &sw_prod_bseq)) {
3853                                         DBRUNIF(1, bce_breakpoint(sc));
3854                                         /* XXX */
3855                                         panic("%s: Double mbuf allocation "
3856                                               "failure!", ifp->if_xname);
3857                                 }
3858                                 m = NULL;
3859                                 goto bce_rx_int_next_rx;
3860                         }
3861
3862                         /*
3863                          * Skip over the l2_fhdr when passing
3864                          * the data up the stack.
3865                          */
3866                         m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
3867
3868                         m->m_pkthdr.len = m->m_len = len;
3869                         m->m_pkthdr.rcvif = ifp;
3870
3871                         DBRUN(BCE_VERBOSE_RECV,
3872                               struct ether_header *eh;
3873                               eh = mtod(m, struct ether_header *);
3874                               if_printf(ifp, "%s(): to: %6D, from: %6D, "
3875                                         "type: 0x%04X\n", __func__,
3876                                         eh->ether_dhost, ":",
3877                                         eh->ether_shost, ":",
3878                                         htons(eh->ether_type)));
3879
3880                         /* Validate the checksum if offload enabled. */
3881                         if (ifp->if_capenable & IFCAP_RXCSUM) {
3882                                 /* Check for an IP datagram. */
3883                                 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
3884                                         m->m_pkthdr.csum_flags |=
3885                                                 CSUM_IP_CHECKED;
3886
3887                                         /* Check if the IP checksum is valid. */
3888                                         if ((l2fhdr->l2_fhdr_ip_xsum ^
3889                                              0xffff) == 0) {
3890                                                 m->m_pkthdr.csum_flags |=
3891                                                         CSUM_IP_VALID;
3892                                         } else {
3893                                                 DBPRINT(sc, BCE_WARN_RECV,
3894                                                         "%s(): Invalid IP checksum = 0x%04X!\n",
3895                                                         __func__, l2fhdr->l2_fhdr_ip_xsum);
3896                                         }
3897                                 }
3898
3899                                 /* Check for a valid TCP/UDP frame. */
3900                                 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3901                                               L2_FHDR_STATUS_UDP_DATAGRAM)) {
3902
3903                                         /* Check for a good TCP/UDP checksum. */
3904                                         if ((status &
3905                                              (L2_FHDR_ERRORS_TCP_XSUM |
3906                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
3907                                                 m->m_pkthdr.csum_data =
3908                                                 l2fhdr->l2_fhdr_tcp_udp_xsum;
3909                                                 m->m_pkthdr.csum_flags |=
3910                                                         CSUM_DATA_VALID |
3911                                                         CSUM_PSEUDO_HDR;
3912                                         } else {
3913                                                 DBPRINT(sc, BCE_WARN_RECV,
3914                                                         "%s(): Invalid TCP/UDP checksum = 0x%04X!\n",
3915                                                         __func__, l2fhdr->l2_fhdr_tcp_udp_xsum);
3916                                         }
3917                                 }
3918                         }
3919
3920                         ifp->if_ipackets++;
3921 bce_rx_int_next_rx:
3922                         sw_prod = NEXT_RX_BD(sw_prod);
3923                 }
3924
3925                 sw_cons = NEXT_RX_BD(sw_cons);
3926
3927                 /* If we have a packet, pass it up the stack */
3928                 if (m) {
3929                         DBPRINT(sc, BCE_VERBOSE_RECV,
3930                                 "%s(): Passing received frame up.\n", __func__);
3931
3932                         if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
3933                                 m->m_flags |= M_VLANTAG;
3934                                 m->m_pkthdr.ether_vlantag =
3935                                         l2fhdr->l2_fhdr_vlan_tag;
3936                         }
3937                         ifp->if_input(ifp, m);
3938
3939                         DBRUNIF(1, sc->rx_mbuf_alloc--);
3940                 }
3941
3942                 /*
3943                  * If polling(4) is not enabled, refresh hw_cons to see
3944                  * whether there's new work.
3945                  *
3946                  * If polling(4) is enabled, i.e count >= 0, refreshing
3947                  * should not be performed, so that we would not spend
3948                  * too much time in RX processing.
3949                  */
3950                 if (count < 0 && sw_cons == hw_cons) {
3951                         hw_cons = sc->hw_rx_cons =
3952                                 sblk->status_rx_quick_consumer_index0;
3953                         if ((hw_cons & USABLE_RX_BD_PER_PAGE) ==
3954                             USABLE_RX_BD_PER_PAGE)
3955                                 hw_cons++;
3956                 }
3957
3958                 /*
3959                  * Prevent speculative reads from getting ahead
3960                  * of the status block.
3961                  */
3962                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
3963                                   BUS_SPACE_BARRIER_READ);
3964         }
3965
3966         for (i = 0; i < RX_PAGES; i++) {
3967                 bus_dmamap_sync(sc->rx_bd_chain_tag,
3968                                 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
3969         }
3970
3971         sc->rx_cons = sw_cons;
3972         sc->rx_prod = sw_prod;
3973         sc->rx_prod_bseq = sw_prod_bseq;
3974
3975         REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BDIDX, sc->rx_prod);
3976         REG_WR(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BSEQ, sc->rx_prod_bseq);
3977
3978         DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, "
3979                 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
3980                 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
3981 }
3982
3983
3984 /****************************************************************************/
3985 /* Handles transmit completion interrupt events.                            */
3986 /*                                                                          */
3987 /* Returns:                                                                 */
3988 /*   Nothing.                                                               */
3989 /****************************************************************************/
3990 static void
3991 bce_tx_intr(struct bce_softc *sc)
3992 {
3993         struct status_block *sblk = sc->status_block;
3994         struct ifnet *ifp = &sc->arpcom.ac_if;
3995         uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
3996
3997         ASSERT_SERIALIZED(ifp->if_serializer);
3998
3999         DBRUNIF(1, sc->tx_interrupts++);
4000
4001         /* Get the hardware's view of the TX consumer index. */
4002         hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
4003
4004         /* Skip to the next entry if this is a chain page pointer. */
4005         if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4006                 hw_tx_cons++;
4007
4008         sw_tx_cons = sc->tx_cons;
4009
4010         /* Prevent speculative reads from getting ahead of the status block. */
4011         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4012                           BUS_SPACE_BARRIER_READ);
4013
4014         /* Cycle through any completed TX chain page entries. */
4015         while (sw_tx_cons != hw_tx_cons) {
4016 #ifdef BCE_DEBUG
4017                 struct tx_bd *txbd = NULL;
4018 #endif
4019                 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
4020
4021                 DBPRINT(sc, BCE_INFO_SEND,
4022                         "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
4023                         "sw_tx_chain_cons = 0x%04X\n",
4024                         __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
4025
4026                 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD),
4027                         if_printf(ifp, "%s(%d): "
4028                                   "TX chain consumer out of range! "
4029                                   " 0x%04X > 0x%04X\n",
4030                                   __FILE__, __LINE__, sw_tx_chain_cons,
4031                                   (int)MAX_TX_BD);
4032                         bce_breakpoint(sc));
4033
4034                 DBRUNIF(1, txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
4035                                 [TX_IDX(sw_tx_chain_cons)]);
4036
4037                 DBRUNIF((txbd == NULL),
4038                         if_printf(ifp, "%s(%d): "
4039                                   "Unexpected NULL tx_bd[0x%04X]!\n",
4040                                   __FILE__, __LINE__, sw_tx_chain_cons);
4041                         bce_breakpoint(sc));
4042
4043                 DBRUN(BCE_INFO_SEND,
4044                       if_printf(ifp, "%s(): ", __func__);
4045                       bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
4046
4047                 /*
4048                  * Free the associated mbuf. Remember
4049                  * that only the last tx_bd of a packet
4050                  * has an mbuf pointer and DMA map.
4051                  */
4052                 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4053                         /* Validate that this is the last tx_bd. */
4054                         DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
4055                                 if_printf(ifp, "%s(%d): "
4056                                 "tx_bd END flag not set but "
4057                                 "txmbuf == NULL!\n", __FILE__, __LINE__);
4058                                 bce_breakpoint(sc));
4059
4060                         DBRUN(BCE_INFO_SEND,
4061                               if_printf(ifp, "%s(): Unloading map/freeing mbuf "
4062                                         "from tx_bd[0x%04X]\n", __func__,
4063                                         sw_tx_chain_cons));
4064
4065                         /* Unmap the mbuf. */
4066                         bus_dmamap_unload(sc->tx_mbuf_tag,
4067                                           sc->tx_mbuf_map[sw_tx_chain_cons]);
4068
4069                         /* Free the mbuf. */
4070                         m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
4071                         sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4072                         DBRUNIF(1, sc->tx_mbuf_alloc--);
4073
4074                         ifp->if_opackets++;
4075                 }
4076
4077                 sc->used_tx_bd--;
4078                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4079
4080                 if (sw_tx_cons == hw_tx_cons) {
4081                         /* Refresh hw_cons to see if there's new work. */
4082                         hw_tx_cons = sc->hw_tx_cons =
4083                                 sblk->status_tx_quick_consumer_index0;
4084                         if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) ==
4085                             USABLE_TX_BD_PER_PAGE)
4086                                 hw_tx_cons++;
4087                 }
4088
4089                 /*
4090                  * Prevent speculative reads from getting
4091                  * ahead of the status block.
4092                  */
4093                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4094                                   BUS_SPACE_BARRIER_READ);
4095         }
4096
4097         if (sc->used_tx_bd == 0) {
4098                 /* Clear the TX timeout timer. */
4099                 ifp->if_timer = 0;
4100         }
4101
4102         /* Clear the tx hardware queue full flag. */
4103         if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE) {
4104                 DBRUNIF((ifp->if_flags & IFF_OACTIVE),
4105                         DBPRINT(sc, BCE_WARN_SEND,
4106                                 "%s(): Open TX chain! %d/%d (used/total)\n",
4107                                 __func__, sc->used_tx_bd, sc->max_tx_bd));
4108                 ifp->if_flags &= ~IFF_OACTIVE;
4109         }
4110         sc->tx_cons = sw_tx_cons;
4111 }
4112
4113
4114 /****************************************************************************/
4115 /* Disables interrupt generation.                                           */
4116 /*                                                                          */
4117 /* Returns:                                                                 */
4118 /*   Nothing.                                                               */
4119 /****************************************************************************/
4120 static void
4121 bce_disable_intr(struct bce_softc *sc)
4122 {
4123         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4124         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4125         lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
4126 }
4127
4128
4129 /****************************************************************************/
4130 /* Enables interrupt generation.                                            */
4131 /*                                                                          */
4132 /* Returns:                                                                 */
4133 /*   Nothing.                                                               */
4134 /****************************************************************************/
4135 static void
4136 bce_enable_intr(struct bce_softc *sc)
4137 {
4138         uint32_t val;
4139
4140         lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
4141
4142         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4143                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4144                BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4145
4146         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4147                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4148
4149         val = REG_RD(sc, BCE_HC_COMMAND);
4150         REG_WR(sc, BCE_HC_COMMAND, val | BCE_HC_COMMAND_COAL_NOW);
4151 }
4152
4153
4154 /****************************************************************************/
4155 /* Handles controller initialization.                                       */
4156 /*                                                                          */
4157 /* Returns:                                                                 */
4158 /*   Nothing.                                                               */
4159 /****************************************************************************/
4160 static void
4161 bce_init(void *xsc)
4162 {
4163         struct bce_softc *sc = xsc;
4164         struct ifnet *ifp = &sc->arpcom.ac_if;
4165         uint32_t ether_mtu;
4166         int error;
4167
4168         ASSERT_SERIALIZED(ifp->if_serializer);
4169
4170         /* Check if the driver is still running and bail out if it is. */
4171         if (ifp->if_flags & IFF_RUNNING)
4172                 return;
4173
4174         bce_stop(sc);
4175
4176         error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4177         if (error) {
4178                 if_printf(ifp, "Controller reset failed!\n");
4179                 goto back;
4180         }
4181
4182         error = bce_chipinit(sc);
4183         if (error) {
4184                 if_printf(ifp, "Controller initialization failed!\n");
4185                 goto back;
4186         }
4187
4188         error = bce_blockinit(sc);
4189         if (error) {
4190                 if_printf(ifp, "Block initialization failed!\n");
4191                 goto back;
4192         }
4193
4194         /* Load our MAC address. */
4195         bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4196         bce_set_mac_addr(sc);
4197
4198         /* Calculate and program the Ethernet MTU size. */
4199         ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4200
4201         DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu);
4202
4203         /*
4204          * Program the mtu, enabling jumbo frame
4205          * support if necessary.  Also set the mbuf
4206          * allocation count for RX frames.
4207          */
4208         if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4209 #ifdef notyet
4210                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4211                        min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4212                        BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4213                 sc->mbuf_alloc_size = MJUM9BYTES;
4214 #else
4215                 panic("jumbo buffer is not supported yet\n");
4216 #endif
4217         } else {
4218                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4219                 sc->mbuf_alloc_size = MCLBYTES;
4220         }
4221
4222         /* Calculate the RX Ethernet frame size for rx_bd's. */
4223         sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4224
4225         DBPRINT(sc, BCE_INFO,
4226                 "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4227                 "max_frame_size = %d\n",
4228                 __func__, (int)MCLBYTES, sc->mbuf_alloc_size,
4229                 sc->max_frame_size);
4230
4231         /* Program appropriate promiscuous/multicast filtering. */
4232         bce_set_rx_mode(sc);
4233
4234         /* Init RX buffer descriptor chain. */
4235         bce_init_rx_chain(sc);  /* XXX return value */
4236
4237         /* Init TX buffer descriptor chain. */
4238         bce_init_tx_chain(sc);  /* XXX return value */
4239
4240 #ifdef DEVICE_POLLING
4241         /* Disable interrupts if we are polling. */
4242         if (ifp->if_flags & IFF_POLLING) {
4243                 bce_disable_intr(sc);
4244
4245                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4246                        (1 << 16) | sc->bce_rx_quick_cons_trip);
4247                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4248                        (1 << 16) | sc->bce_tx_quick_cons_trip);
4249         } else
4250 #endif
4251         /* Enable host interrupts. */
4252         bce_enable_intr(sc);
4253
4254         bce_ifmedia_upd(ifp);
4255
4256         ifp->if_flags |= IFF_RUNNING;
4257         ifp->if_flags &= ~IFF_OACTIVE;
4258
4259         callout_reset(&sc->bce_stat_ch, hz, bce_tick, sc);
4260 back:
4261         if (error)
4262                 bce_stop(sc);
4263 }
4264
4265
4266 /****************************************************************************/
4267 /* Initialize the controller just enough so that any management firmware    */
4268 /* running on the device will continue to operate corectly.                 */
4269 /*                                                                          */
4270 /* Returns:                                                                 */
4271 /*   Nothing.                                                               */
4272 /****************************************************************************/
4273 static void
4274 bce_mgmt_init(struct bce_softc *sc)
4275 {
4276         struct ifnet *ifp = &sc->arpcom.ac_if;
4277         uint32_t val;
4278
4279         /* Check if the driver is still running and bail out if it is. */
4280         if (ifp->if_flags & IFF_RUNNING)
4281                 return;
4282
4283         /* Initialize the on-boards CPUs */
4284         bce_init_cpus(sc);
4285
4286         /* Set the page size and clear the RV2P processor stall bits. */
4287         val = (BCM_PAGE_BITS - 8) << 24;
4288         REG_WR(sc, BCE_RV2P_CONFIG, val);
4289
4290         /* Enable all critical blocks in the MAC. */
4291         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4292                BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE |
4293                BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE |
4294                BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE);
4295         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4296         DELAY(20);
4297
4298         bce_ifmedia_upd(ifp);
4299 }
4300
4301
4302 /****************************************************************************/
4303 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4304 /* memory visible to the controller.                                        */
4305 /*                                                                          */
4306 /* Returns:                                                                 */
4307 /*   0 for success, positive value for failure.                             */
4308 /****************************************************************************/
4309 static int
4310 bce_encap(struct bce_softc *sc, struct mbuf **m_head)
4311 {
4312         struct bce_dmamap_arg ctx;
4313         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4314         bus_dmamap_t map, tmp_map;
4315         struct mbuf *m0 = *m_head;
4316         struct tx_bd *txbd = NULL;
4317         uint16_t vlan_tag = 0, flags = 0;
4318         uint16_t chain_prod, chain_prod_start, prod;
4319         uint32_t prod_bseq;
4320         int i, error, maxsegs;
4321 #ifdef BCE_DEBUG
4322         uint16_t debug_prod;
4323 #endif
4324
4325         /* Transfer any checksum offload flags to the bd. */
4326         if (m0->m_pkthdr.csum_flags) {
4327                 if (m0->m_pkthdr.csum_flags & CSUM_IP)
4328                         flags |= TX_BD_FLAGS_IP_CKSUM;
4329                 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
4330                         flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4331         }
4332
4333         /* Transfer any VLAN tags to the bd. */
4334         if (m0->m_flags & M_VLANTAG) {
4335                 flags |= TX_BD_FLAGS_VLAN_TAG;
4336                 vlan_tag = m0->m_pkthdr.ether_vlantag;
4337         }
4338
4339         prod = sc->tx_prod;
4340         chain_prod_start = chain_prod = TX_CHAIN_IDX(prod);
4341
4342         /* Map the mbuf into DMAable memory. */
4343         map = sc->tx_mbuf_map[chain_prod_start];
4344
4345         maxsegs = sc->max_tx_bd - sc->used_tx_bd;
4346         KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
4347                 ("not enough segements %d\n", maxsegs));
4348         if (maxsegs > BCE_MAX_SEGMENTS)
4349                 maxsegs = BCE_MAX_SEGMENTS;
4350
4351         /* Map the mbuf into our DMA address space. */
4352         ctx.bce_maxsegs = maxsegs;
4353         ctx.bce_segs = segs;
4354         error = bus_dmamap_load_mbuf(sc->tx_mbuf_tag, map, m0,
4355                                      bce_dma_map_mbuf, &ctx, BUS_DMA_NOWAIT);
4356         if (error == EFBIG || ctx.bce_maxsegs == 0) {
4357                 DBPRINT(sc, BCE_WARN, "%s(): fragmented mbuf\n", __func__);
4358                 DBRUNIF(1, bce_dump_mbuf(sc, m0););
4359
4360                 m0 = m_defrag(*m_head, MB_DONTWAIT);
4361                 if (m0 == NULL) {
4362                         error = ENOBUFS;
4363                         goto back;
4364                 }
4365                 *m_head = m0;
4366
4367                 ctx.bce_maxsegs = maxsegs;
4368                 ctx.bce_segs = segs;
4369                 error = bus_dmamap_load_mbuf(sc->tx_mbuf_tag, map, m0,
4370                                              bce_dma_map_mbuf, &ctx,
4371                                              BUS_DMA_NOWAIT);
4372                 if (error || ctx.bce_maxsegs == 0) {
4373                         if_printf(&sc->arpcom.ac_if,
4374                                   "Error mapping mbuf into TX chain\n");
4375                         if (error == 0)
4376                                 error = EFBIG;
4377                         goto back;
4378                 }
4379         } else if (error) {
4380                 if_printf(&sc->arpcom.ac_if,
4381                           "Error mapping mbuf into TX chain\n");
4382                 goto back;
4383         }
4384
4385         /* prod points to an empty tx_bd at this point. */
4386         prod_bseq  = sc->tx_prod_bseq;
4387
4388 #ifdef BCE_DEBUG
4389         debug_prod = chain_prod;
4390 #endif
4391
4392         DBPRINT(sc, BCE_INFO_SEND,
4393                 "%s(): Start: prod = 0x%04X, chain_prod = %04X, "
4394                 "prod_bseq = 0x%08X\n",
4395                 __func__, prod, chain_prod, prod_bseq);
4396
4397         /*
4398          * Cycle through each mbuf segment that makes up
4399          * the outgoing frame, gathering the mapping info
4400          * for that segment and creating a tx_bd to for
4401          * the mbuf.
4402          */
4403         for (i = 0; i < ctx.bce_maxsegs; i++) {
4404                 chain_prod = TX_CHAIN_IDX(prod);
4405                 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
4406
4407                 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
4408                 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
4409                 txbd->tx_bd_mss_nbytes = htole16(segs[i].ds_len);
4410                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
4411                 txbd->tx_bd_flags = htole16(flags);
4412                 prod_bseq += segs[i].ds_len;
4413                 if (i == 0)
4414                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
4415                 prod = NEXT_TX_BD(prod);
4416         }
4417
4418         /* Set the END flag on the last TX buffer descriptor. */
4419         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
4420
4421         DBRUN(BCE_EXCESSIVE_SEND,
4422               bce_dump_tx_chain(sc, debug_prod, ctx.bce_maxsegs));
4423
4424         DBPRINT(sc, BCE_INFO_SEND,
4425                 "%s(): End: prod = 0x%04X, chain_prod = %04X, "
4426                 "prod_bseq = 0x%08X\n",
4427                 __func__, prod, chain_prod, prod_bseq);
4428
4429         bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
4430
4431         /*
4432          * Ensure that the mbuf pointer for this transmission
4433          * is placed at the array index of the last
4434          * descriptor in this chain.  This is done
4435          * because a single map is used for all
4436          * segments of the mbuf and we don't want to
4437          * unload the map before all of the segments
4438          * have been freed.
4439          */
4440         sc->tx_mbuf_ptr[chain_prod] = m0;
4441
4442         tmp_map = sc->tx_mbuf_map[chain_prod];
4443         sc->tx_mbuf_map[chain_prod] = map;
4444         sc->tx_mbuf_map[chain_prod_start] = tmp_map;
4445
4446         sc->used_tx_bd += ctx.bce_maxsegs;
4447
4448         /* Update some debug statistic counters */
4449         DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
4450                 sc->tx_hi_watermark = sc->used_tx_bd);
4451         DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
4452         DBRUNIF(1, sc->tx_mbuf_alloc++);
4453
4454         DBRUN(BCE_VERBOSE_SEND,
4455               bce_dump_tx_mbuf_chain(sc, chain_prod, ctx.bce_maxsegs));
4456
4457         /* prod points to the next free tx_bd at this point. */
4458         sc->tx_prod = prod;
4459         sc->tx_prod_bseq = prod_bseq;
4460 back:
4461         if (error) {
4462                 m_freem(*m_head);
4463                 *m_head = NULL;
4464         }
4465         return error;
4466 }
4467
4468
4469 /****************************************************************************/
4470 /* Main transmit routine when called from another routine with a lock.      */
4471 /*                                                                          */
4472 /* Returns:                                                                 */
4473 /*   Nothing.                                                               */
4474 /****************************************************************************/
4475 static void
4476 bce_start(struct ifnet *ifp)
4477 {
4478         struct bce_softc *sc = ifp->if_softc;
4479         int count = 0;
4480
4481         ASSERT_SERIALIZED(ifp->if_serializer);
4482
4483         /* If there's no link or the transmit queue is empty then just exit. */
4484         if (!sc->bce_link) {
4485                 ifq_purge(&ifp->if_snd);
4486                 return;
4487         }
4488
4489         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
4490                 return;
4491
4492         DBPRINT(sc, BCE_INFO_SEND,
4493                 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04X, "
4494                 "tx_prod_bseq = 0x%08X\n",
4495                 __func__,
4496                 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
4497
4498         for (;;) {
4499                 struct mbuf *m_head;
4500
4501                 /*
4502                  * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
4503                  * unlikely to fail.
4504                  */
4505                 if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) {
4506                         ifp->if_flags |= IFF_OACTIVE;
4507                         break;
4508                 }
4509
4510                 /* Check for any frames to send. */
4511                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
4512                 if (m_head == NULL)
4513                         break;
4514
4515                 /*
4516                  * Pack the data into the transmit ring. If we
4517                  * don't have room, place the mbuf back at the
4518                  * head of the queue and set the OACTIVE flag
4519                  * to wait for the NIC to drain the chain.
4520                  */
4521                 if (bce_encap(sc, &m_head)) {
4522                         ifp->if_flags |= IFF_OACTIVE;
4523                         DBPRINT(sc, BCE_INFO_SEND,
4524                                 "TX chain is closed for business! "
4525                                 "Total tx_bd used = %d\n",
4526                                 sc->used_tx_bd);
4527                         break;
4528                 }
4529
4530                 count++;
4531
4532                 /* Send a copy of the frame to any BPF listeners. */
4533                 ETHER_BPF_MTAP(ifp, m_head);
4534         }
4535
4536         if (count == 0) {
4537                 /* no packets were dequeued */
4538                 DBPRINT(sc, BCE_VERBOSE_SEND,
4539                         "%s(): No packets were dequeued\n", __func__);
4540                 return;
4541         }
4542
4543         DBPRINT(sc, BCE_INFO_SEND,
4544                 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
4545                 "tx_prod_bseq = 0x%08X\n",
4546                 __func__,
4547                 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
4548
4549         /* Start the transmit. */
4550         REG_WR16(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
4551         REG_WR(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
4552
4553         /* Set the tx timeout. */
4554         ifp->if_timer = BCE_TX_TIMEOUT;
4555 }
4556
4557
4558 /****************************************************************************/
4559 /* Handles any IOCTL calls from the operating system.                       */
4560 /*                                                                          */
4561 /* Returns:                                                                 */
4562 /*   0 for success, positive value for failure.                             */
4563 /****************************************************************************/
4564 static int
4565 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
4566 {
4567         struct bce_softc *sc = ifp->if_softc;
4568         struct ifreq *ifr = (struct ifreq *)data;
4569         struct mii_data *mii;
4570         int mask, error = 0;
4571
4572         ASSERT_SERIALIZED(ifp->if_serializer);
4573
4574         switch(command) {
4575         case SIOCSIFMTU:
4576                 /* Check that the MTU setting is supported. */
4577                 if (ifr->ifr_mtu < BCE_MIN_MTU ||
4578 #ifdef notyet
4579                     ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
4580 #else
4581                     ifr->ifr_mtu > ETHERMTU
4582 #endif
4583                    ) {
4584                         error = EINVAL;
4585                         break;
4586                 }
4587
4588                 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu);
4589
4590                 ifp->if_mtu = ifr->ifr_mtu;
4591                 ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
4592                 bce_init(sc);
4593                 break;
4594
4595         case SIOCSIFFLAGS:
4596                 if (ifp->if_flags & IFF_UP) {
4597                         if (ifp->if_flags & IFF_RUNNING) {
4598                                 mask = ifp->if_flags ^ sc->bce_if_flags;
4599
4600                                 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
4601                                         bce_set_rx_mode(sc);
4602                         } else {
4603                                 bce_init(sc);
4604                         }
4605                 } else if (ifp->if_flags & IFF_RUNNING) {
4606                         bce_stop(sc);
4607                 }
4608                 sc->bce_if_flags = ifp->if_flags;
4609                 break;
4610
4611         case SIOCADDMULTI:
4612         case SIOCDELMULTI:
4613                 if (ifp->if_flags & IFF_RUNNING)
4614                         bce_set_rx_mode(sc);
4615                 break;
4616
4617         case SIOCSIFMEDIA:
4618         case SIOCGIFMEDIA:
4619                 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n",
4620                         sc->bce_phy_flags);
4621                 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n");
4622
4623                 mii = device_get_softc(sc->bce_miibus);
4624                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
4625                 break;
4626
4627         case SIOCSIFCAP:
4628                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
4629                 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n",
4630                         (uint32_t) mask);
4631
4632                 if (mask & IFCAP_HWCSUM) {
4633                         ifp->if_capenable ^= IFCAP_HWCSUM;
4634                         if (IFCAP_HWCSUM & ifp->if_capenable)
4635                                 ifp->if_hwassist = BCE_IF_HWASSIST;
4636                         else
4637                                 ifp->if_hwassist = 0;
4638                 }
4639                 break;
4640
4641         default:
4642                 error = ether_ioctl(ifp, command, data);
4643                 break;
4644         }
4645         return error;
4646 }
4647
4648
4649 /****************************************************************************/
4650 /* Transmit timeout handler.                                                */
4651 /*                                                                          */
4652 /* Returns:                                                                 */
4653 /*   Nothing.                                                               */
4654 /****************************************************************************/
4655 static void
4656 bce_watchdog(struct ifnet *ifp)
4657 {
4658         struct bce_softc *sc = ifp->if_softc;
4659
4660         ASSERT_SERIALIZED(ifp->if_serializer);
4661
4662         DBRUN(BCE_VERBOSE_SEND,
4663               bce_dump_driver_state(sc);
4664               bce_dump_status_block(sc));
4665
4666         /*
4667          * If we are in this routine because of pause frames, then
4668          * don't reset the hardware.
4669          */
4670         if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
4671                 return;
4672
4673         if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
4674
4675         /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
4676
4677         ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
4678         bce_init(sc);
4679
4680         ifp->if_oerrors++;
4681
4682         if (!ifq_is_empty(&ifp->if_snd))
4683                 if_devstart(ifp);
4684 }
4685
4686
4687 #ifdef DEVICE_POLLING
4688
4689 static void
4690 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
4691 {
4692         struct bce_softc *sc = ifp->if_softc;
4693         struct status_block *sblk = sc->status_block;
4694
4695         ASSERT_SERIALIZED(ifp->if_serializer);
4696
4697         switch (cmd) {
4698         case POLL_REGISTER:
4699                 bce_disable_intr(sc);
4700
4701                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4702                        (1 << 16) | sc->bce_rx_quick_cons_trip);
4703                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4704                        (1 << 16) | sc->bce_tx_quick_cons_trip);
4705                 return;
4706         case POLL_DEREGISTER:
4707                 bce_enable_intr(sc);
4708
4709                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4710                        (sc->bce_tx_quick_cons_trip_int << 16) |
4711                        sc->bce_tx_quick_cons_trip);
4712                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4713                        (sc->bce_rx_quick_cons_trip_int << 16) |
4714                        sc->bce_rx_quick_cons_trip);
4715                 return;
4716         default:
4717                 break;
4718         }
4719
4720         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
4721
4722         if (cmd == POLL_AND_CHECK_STATUS) {
4723                 uint32_t status_attn_bits;
4724
4725                 status_attn_bits = sblk->status_attn_bits;
4726
4727                 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
4728                         if_printf(ifp,
4729                         "Simulating unexpected status attention bit set.");
4730                         status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
4731
4732                 /* Was it a link change interrupt? */
4733                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
4734                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
4735                         bce_phy_intr(sc);
4736
4737                 /*
4738                  * If any other attention is asserted then
4739                  * the chip is toast.
4740                  */
4741                 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
4742                      (sblk->status_attn_bits_ack &
4743                       ~STATUS_ATTN_BITS_LINK_STATE)) {
4744                         DBRUN(1, sc->unexpected_attentions++);
4745
4746                         if_printf(ifp, "Fatal attention detected: 0x%08X\n",
4747                                   sblk->status_attn_bits);
4748
4749                         DBRUN(BCE_FATAL,
4750                         if (bce_debug_unexpected_attention == 0)
4751                                 bce_breakpoint(sc));
4752
4753                         bce_init(sc);
4754                         return;
4755                 }
4756         }
4757
4758         /* Check for any completed RX frames. */
4759         if (sblk->status_rx_quick_consumer_index0 != sc->hw_rx_cons)
4760                 bce_rx_intr(sc, count);
4761
4762         /* Check for any completed TX frames. */
4763         if (sblk->status_tx_quick_consumer_index0 != sc->hw_tx_cons)
4764                 bce_tx_intr(sc);
4765
4766         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREWRITE);
4767
4768         /* Check for new frames to transmit. */
4769         if (!ifq_is_empty(&ifp->if_snd))
4770                 if_devstart(ifp);
4771 }
4772
4773 #endif  /* DEVICE_POLLING */
4774
4775
4776 #if 0
4777 static inline int
4778 bce_has_work(struct bce_softc *sc)
4779 {
4780         struct status_block *stat = sc->status_block;
4781
4782         if ((stat->status_rx_quick_consumer_index0 != sc->hw_rx_cons) ||
4783             (stat->status_tx_quick_consumer_index0 != sc->hw_tx_cons))
4784                 return 1;
4785
4786         if (((stat->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) !=
4787             bp->link_up)
4788                 return 1;
4789
4790         return 0;
4791 }
4792 #endif
4793
4794
4795 /*
4796  * Interrupt handler.
4797  */
4798 /****************************************************************************/
4799 /* Main interrupt entry point.  Verifies that the controller generated the  */
4800 /* interrupt and then calls a separate routine for handle the various       */
4801 /* interrupt causes (PHY, TX, RX).                                          */
4802 /*                                                                          */
4803 /* Returns:                                                                 */
4804 /*   0 for success, positive value for failure.                             */
4805 /****************************************************************************/
4806 static void
4807 bce_intr(void *xsc)
4808 {
4809         struct bce_softc *sc = xsc;
4810         struct ifnet *ifp = &sc->arpcom.ac_if;
4811         struct status_block *sblk;
4812
4813         ASSERT_SERIALIZED(ifp->if_serializer);
4814
4815         DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
4816         DBRUNIF(1, sc->interrupts_generated++);
4817
4818         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
4819         sblk = sc->status_block;
4820
4821         /*
4822          * If the hardware status block index matches the last value
4823          * read by the driver and we haven't asserted our interrupt
4824          * then there's nothing to do.
4825          */
4826         if (sblk->status_idx == sc->last_status_idx &&
4827             (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
4828              BCE_PCICFG_MISC_STATUS_INTA_VALUE))
4829                 return;
4830
4831         /* Ack the interrupt and stop others from occuring. */
4832         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4833                BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
4834                BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4835
4836         /* Keep processing data as long as there is work to do. */
4837         for (;;) {
4838                 uint32_t status_attn_bits;
4839
4840                 status_attn_bits = sblk->status_attn_bits;
4841
4842                 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
4843                         if_printf(ifp,
4844                         "Simulating unexpected status attention bit set.");
4845                         status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
4846
4847                 /* Was it a link change interrupt? */
4848                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
4849                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
4850                         bce_phy_intr(sc);
4851
4852                 /*
4853                  * If any other attention is asserted then
4854                  * the chip is toast.
4855                  */
4856                 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
4857                      (sblk->status_attn_bits_ack &
4858                       ~STATUS_ATTN_BITS_LINK_STATE)) {
4859                         DBRUN(1, sc->unexpected_attentions++);
4860
4861                         if_printf(ifp, "Fatal attention detected: 0x%08X\n",
4862                                   sblk->status_attn_bits);
4863
4864                         DBRUN(BCE_FATAL,
4865                         if (bce_debug_unexpected_attention == 0)
4866                                 bce_breakpoint(sc));
4867
4868                         bce_init(sc);
4869                         return;
4870                 }
4871
4872                 /* Check for any completed RX frames. */
4873                 if (sblk->status_rx_quick_consumer_index0 != sc->hw_rx_cons)
4874                         bce_rx_intr(sc, -1);
4875
4876                 /* Check for any completed TX frames. */
4877                 if (sblk->status_tx_quick_consumer_index0 != sc->hw_tx_cons)
4878                         bce_tx_intr(sc);
4879
4880                 /*
4881                  * Save the status block index value
4882                  * for use during the next interrupt.
4883                  */
4884                 sc->last_status_idx = sblk->status_idx;
4885
4886                 /*
4887                  * Prevent speculative reads from getting
4888                  * ahead of the status block.
4889                  */
4890                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4891                                   BUS_SPACE_BARRIER_READ);
4892
4893                 /*
4894                  * If there's no work left then exit the
4895                  * interrupt service routine.
4896                  */
4897                 if (sblk->status_rx_quick_consumer_index0 == sc->hw_rx_cons &&
4898                     sblk->status_tx_quick_consumer_index0 == sc->hw_tx_cons)
4899                         break;
4900         }
4901
4902         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREWRITE);
4903
4904         /* Re-enable interrupts. */
4905         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4906                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx |
4907                BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4908         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4909                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4910
4911         /* Handle any frames that arrived while handling the interrupt. */
4912         if (!ifq_is_empty(&ifp->if_snd))
4913                 if_devstart(ifp);
4914 }
4915
4916
4917 /****************************************************************************/
4918 /* Programs the various packet receive modes (broadcast and multicast).     */
4919 /*                                                                          */
4920 /* Returns:                                                                 */
4921 /*   Nothing.                                                               */
4922 /****************************************************************************/
4923 static void
4924 bce_set_rx_mode(struct bce_softc *sc)
4925 {
4926         struct ifnet *ifp = &sc->arpcom.ac_if;
4927         struct ifmultiaddr *ifma;
4928         uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
4929         uint32_t rx_mode, sort_mode;
4930         int h, i;
4931
4932         ASSERT_SERIALIZED(ifp->if_serializer);
4933
4934         /* Initialize receive mode default settings. */
4935         rx_mode = sc->rx_mode &
4936                   ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
4937                     BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
4938         sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
4939
4940         /*
4941          * ASF/IPMI/UMP firmware requires that VLAN tag stripping
4942          * be enbled.
4943          */
4944         if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
4945             !(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
4946                 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
4947
4948         /*
4949          * Check for promiscuous, all multicast, or selected
4950          * multicast address filtering.
4951          */
4952         if (ifp->if_flags & IFF_PROMISC) {
4953                 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n");
4954
4955                 /* Enable promiscuous mode. */
4956                 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
4957                 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
4958         } else if (ifp->if_flags & IFF_ALLMULTI) {
4959                 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n");
4960
4961                 /* Enable all multicast addresses. */
4962                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
4963                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
4964                                0xffffffff);
4965                 }
4966                 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
4967         } else {
4968                 /* Accept one or more multicast(s). */
4969                 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n");
4970
4971                 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
4972                         if (ifma->ifma_addr->sa_family != AF_LINK)
4973                                 continue;
4974                         h = ether_crc32_le(
4975                             LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
4976                             ETHER_ADDR_LEN) & 0xFF;
4977                         hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
4978                 }
4979
4980                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
4981                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
4982                                hashes[i]);
4983                 }
4984                 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
4985         }
4986
4987         /* Only make changes if the recive mode has actually changed. */
4988         if (rx_mode != sc->rx_mode) {
4989                 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n",
4990                         rx_mode);
4991
4992                 sc->rx_mode = rx_mode;
4993                 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
4994         }
4995
4996         /* Disable and clear the exisitng sort before enabling a new sort. */
4997         REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
4998         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
4999         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
5000 }
5001
5002
5003 /****************************************************************************/
5004 /* Called periodically to updates statistics from the controllers           */
5005 /* statistics block.                                                        */
5006 /*                                                                          */
5007 /* Returns:                                                                 */
5008 /*   Nothing.                                                               */
5009 /****************************************************************************/
5010 static void
5011 bce_stats_update(struct bce_softc *sc)
5012 {
5013         struct ifnet *ifp = &sc->arpcom.ac_if;
5014         struct statistics_block *stats = sc->stats_block;
5015
5016         DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5017
5018         ASSERT_SERIALIZED(ifp->if_serializer);
5019
5020         /*
5021          * Update the interface statistics from the hardware statistics.
5022          */
5023         ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions;
5024
5025         ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts +
5026                           (u_long)stats->stat_EtherStatsOverrsizePkts +
5027                           (u_long)stats->stat_IfInMBUFDiscards +
5028                           (u_long)stats->stat_Dot3StatsAlignmentErrors +
5029                           (u_long)stats->stat_Dot3StatsFCSErrors;
5030
5031         ifp->if_oerrors =
5032         (u_long)stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
5033         (u_long)stats->stat_Dot3StatsExcessiveCollisions +
5034         (u_long)stats->stat_Dot3StatsLateCollisions;
5035
5036         /*
5037          * Certain controllers don't report carrier sense errors correctly.
5038          * See errata E11_5708CA0_1165.
5039          */
5040         if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5041             !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) {
5042                 ifp->if_oerrors +=
5043                         (u_long)stats->stat_Dot3StatsCarrierSenseErrors;
5044         }
5045
5046         /*
5047          * Update the sysctl statistics from the hardware statistics.
5048          */
5049         sc->stat_IfHCInOctets =
5050                 ((uint64_t)stats->stat_IfHCInOctets_hi << 32) +
5051                  (uint64_t)stats->stat_IfHCInOctets_lo;
5052
5053         sc->stat_IfHCInBadOctets =
5054                 ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) +
5055                  (uint64_t)stats->stat_IfHCInBadOctets_lo;
5056
5057         sc->stat_IfHCOutOctets =
5058                 ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) +
5059                  (uint64_t)stats->stat_IfHCOutOctets_lo;
5060
5061         sc->stat_IfHCOutBadOctets =
5062                 ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) +
5063                  (uint64_t)stats->stat_IfHCOutBadOctets_lo;
5064
5065         sc->stat_IfHCInUcastPkts =
5066                 ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) +
5067                  (uint64_t)stats->stat_IfHCInUcastPkts_lo;
5068
5069         sc->stat_IfHCInMulticastPkts =
5070                 ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) +
5071                  (uint64_t)stats->stat_IfHCInMulticastPkts_lo;
5072
5073         sc->stat_IfHCInBroadcastPkts =
5074                 ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) +
5075                  (uint64_t)stats->stat_IfHCInBroadcastPkts_lo;
5076
5077         sc->stat_IfHCOutUcastPkts =
5078                 ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) +
5079                  (uint64_t)stats->stat_IfHCOutUcastPkts_lo;
5080
5081         sc->stat_IfHCOutMulticastPkts =
5082                 ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) +
5083                  (uint64_t)stats->stat_IfHCOutMulticastPkts_lo;
5084
5085         sc->stat_IfHCOutBroadcastPkts =
5086                 ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) +
5087                  (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo;
5088
5089         sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
5090                 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5091
5092         sc->stat_Dot3StatsCarrierSenseErrors =
5093                 stats->stat_Dot3StatsCarrierSenseErrors;
5094
5095         sc->stat_Dot3StatsFCSErrors =
5096                 stats->stat_Dot3StatsFCSErrors;
5097
5098         sc->stat_Dot3StatsAlignmentErrors =
5099                 stats->stat_Dot3StatsAlignmentErrors;
5100
5101         sc->stat_Dot3StatsSingleCollisionFrames =
5102                 stats->stat_Dot3StatsSingleCollisionFrames;
5103
5104         sc->stat_Dot3StatsMultipleCollisionFrames =
5105                 stats->stat_Dot3StatsMultipleCollisionFrames;
5106
5107         sc->stat_Dot3StatsDeferredTransmissions =
5108                 stats->stat_Dot3StatsDeferredTransmissions;
5109
5110         sc->stat_Dot3StatsExcessiveCollisions =
5111                 stats->stat_Dot3StatsExcessiveCollisions;
5112
5113         sc->stat_Dot3StatsLateCollisions =
5114                 stats->stat_Dot3StatsLateCollisions;
5115
5116         sc->stat_EtherStatsCollisions =
5117                 stats->stat_EtherStatsCollisions;
5118
5119         sc->stat_EtherStatsFragments =
5120                 stats->stat_EtherStatsFragments;
5121
5122         sc->stat_EtherStatsJabbers =
5123                 stats->stat_EtherStatsJabbers;
5124
5125         sc->stat_EtherStatsUndersizePkts =
5126                 stats->stat_EtherStatsUndersizePkts;
5127
5128         sc->stat_EtherStatsOverrsizePkts =
5129                 stats->stat_EtherStatsOverrsizePkts;
5130
5131         sc->stat_EtherStatsPktsRx64Octets =
5132                 stats->stat_EtherStatsPktsRx64Octets;
5133
5134         sc->stat_EtherStatsPktsRx65Octetsto127Octets =
5135                 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
5136
5137         sc->stat_EtherStatsPktsRx128Octetsto255Octets =
5138                 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
5139
5140         sc->stat_EtherStatsPktsRx256Octetsto511Octets =
5141                 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
5142
5143         sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
5144                 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
5145
5146         sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
5147                 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
5148
5149         sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
5150                 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
5151
5152         sc->stat_EtherStatsPktsTx64Octets =
5153                 stats->stat_EtherStatsPktsTx64Octets;
5154
5155         sc->stat_EtherStatsPktsTx65Octetsto127Octets =
5156                 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
5157
5158         sc->stat_EtherStatsPktsTx128Octetsto255Octets =
5159                 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
5160
5161         sc->stat_EtherStatsPktsTx256Octetsto511Octets =
5162                 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
5163
5164         sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
5165                 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
5166
5167         sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
5168                 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
5169
5170         sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
5171                 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
5172
5173         sc->stat_XonPauseFramesReceived =
5174                 stats->stat_XonPauseFramesReceived;
5175
5176         sc->stat_XoffPauseFramesReceived =
5177                 stats->stat_XoffPauseFramesReceived;
5178
5179         sc->stat_OutXonSent =
5180                 stats->stat_OutXonSent;
5181
5182         sc->stat_OutXoffSent =
5183                 stats->stat_OutXoffSent;
5184
5185         sc->stat_FlowControlDone =
5186                 stats->stat_FlowControlDone;
5187
5188         sc->stat_MacControlFramesReceived =
5189                 stats->stat_MacControlFramesReceived;
5190
5191         sc->stat_XoffStateEntered =
5192                 stats->stat_XoffStateEntered;
5193
5194         sc->stat_IfInFramesL2FilterDiscards =
5195                 stats->stat_IfInFramesL2FilterDiscards;
5196
5197         sc->stat_IfInRuleCheckerDiscards =
5198                 stats->stat_IfInRuleCheckerDiscards;
5199
5200         sc->stat_IfInFTQDiscards =
5201                 stats->stat_IfInFTQDiscards;
5202
5203         sc->stat_IfInMBUFDiscards =
5204                 stats->stat_IfInMBUFDiscards;
5205
5206         sc->stat_IfInRuleCheckerP4Hit =
5207                 stats->stat_IfInRuleCheckerP4Hit;
5208
5209         sc->stat_CatchupInRuleCheckerDiscards =
5210                 stats->stat_CatchupInRuleCheckerDiscards;
5211
5212         sc->stat_CatchupInFTQDiscards =
5213                 stats->stat_CatchupInFTQDiscards;
5214
5215         sc->stat_CatchupInMBUFDiscards =
5216                 stats->stat_CatchupInMBUFDiscards;
5217
5218         sc->stat_CatchupInRuleCheckerP4Hit =
5219                 stats->stat_CatchupInRuleCheckerP4Hit;
5220
5221         sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
5222
5223         DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __func__);
5224 }
5225
5226
5227 /****************************************************************************/
5228 /* Periodic function to perform maintenance tasks.                          */
5229 /*                                                                          */
5230 /* Returns:                                                                 */
5231 /*   Nothing.                                                               */
5232 /****************************************************************************/
5233 static void
5234 bce_tick_serialized(struct bce_softc *sc)
5235 {
5236         struct ifnet *ifp = &sc->arpcom.ac_if;
5237         struct mii_data *mii;
5238         uint32_t msg;
5239
5240         ASSERT_SERIALIZED(ifp->if_serializer);
5241
5242         /* Tell the firmware that the driver is still running. */
5243 #ifdef BCE_DEBUG
5244         msg = (uint32_t)BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE;
5245 #else
5246         msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq;
5247 #endif
5248         REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_PULSE_MB, msg);
5249
5250         /* Update the statistics from the hardware statistics block. */
5251         bce_stats_update(sc);
5252
5253         /* Schedule the next tick. */
5254         callout_reset(&sc->bce_stat_ch, hz, bce_tick, sc);
5255
5256         /* If link is up already up then we're done. */
5257         if (sc->bce_link)
5258                 return;
5259
5260         mii = device_get_softc(sc->bce_miibus);
5261         mii_tick(mii);
5262
5263         /* Check if the link has come up. */
5264         if (!sc->bce_link && (mii->mii_media_status & IFM_ACTIVE) &&
5265             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5266                 sc->bce_link++;
5267                 /* Now that link is up, handle any outstanding TX traffic. */
5268                 if (!ifq_is_empty(&ifp->if_snd))
5269                         if_devstart(ifp);
5270         }
5271 }
5272
5273
5274 static void
5275 bce_tick(void *xsc)
5276 {
5277         struct bce_softc *sc = xsc;
5278         struct ifnet *ifp = &sc->arpcom.ac_if;
5279
5280         lwkt_serialize_enter(ifp->if_serializer);
5281         bce_tick_serialized(sc);
5282         lwkt_serialize_exit(ifp->if_serializer);
5283 }
5284
5285
5286 #ifdef BCE_DEBUG
5287 /****************************************************************************/
5288 /* Allows the driver state to be dumped through the sysctl interface.       */
5289 /*                                                                          */
5290 /* Returns:                                                                 */
5291 /*   0 for success, positive value for failure.                             */
5292 /****************************************************************************/
5293 static int
5294 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
5295 {
5296         int error;
5297         int result;
5298         struct bce_softc *sc;
5299
5300         result = -1;
5301         error = sysctl_handle_int(oidp, &result, 0, req);
5302
5303         if (error || !req->newptr)
5304                 return (error);
5305
5306         if (result == 1) {
5307                 sc = (struct bce_softc *)arg1;
5308                 bce_dump_driver_state(sc);
5309         }
5310
5311         return error;
5312 }
5313
5314
5315 /****************************************************************************/
5316 /* Allows the hardware state to be dumped through the sysctl interface.     */
5317 /*                                                                          */
5318 /* Returns:                                                                 */
5319 /*   0 for success, positive value for failure.                             */
5320 /****************************************************************************/
5321 static int
5322 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
5323 {
5324         int error;
5325         int result;
5326         struct bce_softc *sc;
5327
5328         result = -1;
5329         error = sysctl_handle_int(oidp, &result, 0, req);
5330
5331         if (error || !req->newptr)
5332                 return (error);
5333
5334         if (result == 1) {
5335                 sc = (struct bce_softc *)arg1;
5336                 bce_dump_hw_state(sc);
5337         }
5338
5339         return error;
5340 }
5341
5342
5343 /****************************************************************************/
5344 /* Provides a sysctl interface to allows dumping the RX chain.              */
5345 /*                                                                          */
5346 /* Returns:                                                                 */
5347 /*   0 for success, positive value for failure.                             */
5348 /****************************************************************************/
5349 static int
5350 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
5351 {
5352         int error;
5353         int result;
5354         struct bce_softc *sc;
5355
5356         result = -1;
5357         error = sysctl_handle_int(oidp, &result, 0, req);
5358
5359         if (error || !req->newptr)
5360                 return (error);
5361
5362         if (result == 1) {
5363                 sc = (struct bce_softc *)arg1;
5364                 bce_dump_rx_chain(sc, 0, USABLE_RX_BD);
5365         }
5366
5367         return error;
5368 }
5369
5370
5371 /****************************************************************************/
5372 /* Provides a sysctl interface to allows dumping the TX chain.              */
5373 /*                                                                          */
5374 /* Returns:                                                                 */
5375 /*   0 for success, positive value for failure.                             */
5376 /****************************************************************************/
5377 static int
5378 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
5379 {
5380         int error;
5381         int result;
5382         struct bce_softc *sc;
5383
5384         result = -1;
5385         error = sysctl_handle_int(oidp, &result, 0, req);
5386
5387         if (error || !req->newptr)
5388                 return (error);
5389
5390         if (result == 1) {
5391                 sc = (struct bce_softc *)arg1;
5392                 bce_dump_tx_chain(sc, 0, USABLE_TX_BD);
5393         }
5394
5395         return error;
5396 }
5397
5398
5399 /****************************************************************************/
5400 /* Provides a sysctl interface to allow reading arbitrary registers in the  */
5401 /* device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                            */
5402 /*                                                                          */
5403 /* Returns:                                                                 */
5404 /*   0 for success, positive value for failure.                             */
5405 /****************************************************************************/
5406 static int
5407 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5408 {
5409         struct bce_softc *sc;
5410         int error;
5411         uint32_t val, result;
5412
5413         result = -1;
5414         error = sysctl_handle_int(oidp, &result, 0, req);
5415         if (error || (req->newptr == NULL))
5416                 return (error);
5417
5418         /* Make sure the register is accessible. */
5419         if (result < 0x8000) {
5420                 sc = (struct bce_softc *)arg1;
5421                 val = REG_RD(sc, result);
5422                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
5423                           result, val);
5424         } else if (result < 0x0280000) {
5425                 sc = (struct bce_softc *)arg1;
5426                 val = REG_RD_IND(sc, result);
5427                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
5428                           result, val);
5429         }
5430         return (error);
5431 }
5432
5433
5434 /****************************************************************************/
5435 /* Provides a sysctl interface to allow reading arbitrary PHY registers in  */\r
5436 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */\r
5437 /*                                                                          */
5438 /* Returns:                                                                 */
5439 /*   0 for success, positive value for failure.                             */
5440 /****************************************************************************/
5441 static int
5442 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
5443 {
5444         struct bce_softc *sc;
5445         device_t dev;
5446         int error, result;
5447         uint16_t val;
5448
5449         result = -1;
5450         error = sysctl_handle_int(oidp, &result, 0, req);
5451         if (error || (req->newptr == NULL))
5452                 return (error);
5453
5454         /* Make sure the register is accessible. */
5455         if (result < 0x20) {
5456                 sc = (struct bce_softc *)arg1;
5457                 dev = sc->bce_dev;
5458                 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
5459                 if_printf(&sc->arpcom.ac_if,
5460                           "phy 0x%02X = 0x%04X\n", result, val);
5461         }
5462         return (error);
5463 }
5464
5465
5466 /****************************************************************************/
5467 /* Provides a sysctl interface to forcing the driver to dump state and      */\r
5468 /* enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                */
5469 /*                                                                          */
5470 /* Returns:                                                                 */
5471 /*   0 for success, positive value for failure.                             */
5472 /****************************************************************************/
5473 static int
5474 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
5475 {
5476         int error;
5477         int result;
5478         struct bce_softc *sc;
5479
5480         result = -1;
5481         error = sysctl_handle_int(oidp, &result, 0, req);
5482
5483         if (error || !req->newptr)
5484                 return (error);
5485
5486         if (result == 1) {
5487                 sc = (struct bce_softc *)arg1;
5488                 bce_breakpoint(sc);
5489         }
5490
5491         return error;
5492 }
5493 #endif
5494
5495
5496 /****************************************************************************/
5497 /* Adds any sysctl parameters for tuning or debugging purposes.             */
5498 /*                                                                          */
5499 /* Returns:                                                                 */
5500 /*   0 for success, positive value for failure.                             */
5501 /****************************************************************************/
5502 static void
5503 bce_add_sysctls(struct bce_softc *sc)
5504 {
5505         struct sysctl_ctx_list *ctx;
5506         struct sysctl_oid_list *children;
5507
5508         sysctl_ctx_init(&sc->bce_sysctl_ctx);
5509         sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx,
5510                                               SYSCTL_STATIC_CHILDREN(_hw),
5511                                               OID_AUTO,
5512                                               device_get_nameunit(sc->bce_dev),
5513                                               CTLFLAG_RD, 0, "");
5514         if (sc->bce_sysctl_tree == NULL) {
5515                 device_printf(sc->bce_dev, "can't add sysctl node\n");
5516                 return;
5517         }
5518
5519         ctx = &sc->bce_sysctl_ctx;
5520         children = SYSCTL_CHILDREN(sc->bce_sysctl_tree);
5521
5522 #ifdef BCE_DEBUG
5523         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5524                 "rx_low_watermark",
5525                 CTLFLAG_RD, &sc->rx_low_watermark,
5526                 0, "Lowest level of free rx_bd's");
5527
5528         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5529                 "rx_empty_count",
5530                 CTLFLAG_RD, &sc->rx_empty_count,
5531                 0, "Number of times the RX chain was empty");
5532
5533         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5534                 "tx_hi_watermark",
5535                 CTLFLAG_RD, &sc->tx_hi_watermark,
5536                 0, "Highest level of used tx_bd's");
5537
5538         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5539                 "tx_full_count",
5540                 CTLFLAG_RD, &sc->tx_full_count,
5541                 0, "Number of times the TX chain was full");
5542
5543         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5544                 "l2fhdr_status_errors",
5545                 CTLFLAG_RD, &sc->l2fhdr_status_errors,
5546                 0, "l2_fhdr status errors");
5547
5548         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5549                 "unexpected_attentions",
5550                 CTLFLAG_RD, &sc->unexpected_attentions,
5551                 0, "unexpected attentions");
5552
5553         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5554                 "lost_status_block_updates",
5555                 CTLFLAG_RD, &sc->lost_status_block_updates,
5556                 0, "lost status block updates");
5557
5558         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5559                 "mbuf_alloc_failed",
5560                 CTLFLAG_RD, &sc->mbuf_alloc_failed,
5561                 0, "mbuf cluster allocation failures");
5562 #endif
5563
5564         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5565                 "stat_IfHcInOctets",
5566                 CTLFLAG_RD, &sc->stat_IfHCInOctets,
5567                 "Bytes received");
5568
5569         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5570                 "stat_IfHCInBadOctets",
5571                 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
5572                 "Bad bytes received");
5573
5574         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5575                 "stat_IfHCOutOctets",
5576                 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
5577                 "Bytes sent");
5578
5579         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5580                 "stat_IfHCOutBadOctets",
5581                 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
5582                 "Bad bytes sent");
5583
5584         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5585                 "stat_IfHCInUcastPkts",
5586                 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
5587                 "Unicast packets received");
5588
5589         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5590                 "stat_IfHCInMulticastPkts",
5591                 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
5592                 "Multicast packets received");
5593
5594         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5595                 "stat_IfHCInBroadcastPkts",
5596                 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
5597                 "Broadcast packets received");
5598
5599         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5600                 "stat_IfHCOutUcastPkts",
5601                 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
5602                 "Unicast packets sent");
5603
5604         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5605                 "stat_IfHCOutMulticastPkts",
5606                 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
5607                 "Multicast packets sent");
5608
5609         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5610                 "stat_IfHCOutBroadcastPkts",
5611                 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
5612                 "Broadcast packets sent");
5613
5614         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5615                 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
5616                 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
5617                 0, "Internal MAC transmit errors");
5618
5619         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5620                 "stat_Dot3StatsCarrierSenseErrors",
5621                 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
5622                 0, "Carrier sense errors");
5623
5624         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5625                 "stat_Dot3StatsFCSErrors",
5626                 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
5627                 0, "Frame check sequence errors");
5628
5629         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5630                 "stat_Dot3StatsAlignmentErrors",
5631                 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
5632                 0, "Alignment errors");
5633
5634         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5635                 "stat_Dot3StatsSingleCollisionFrames",
5636                 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
5637                 0, "Single Collision Frames");
5638
5639         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5640                 "stat_Dot3StatsMultipleCollisionFrames",
5641                 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
5642                 0, "Multiple Collision Frames");
5643
5644         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5645                 "stat_Dot3StatsDeferredTransmissions",
5646                 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
5647                 0, "Deferred Transmissions");
5648
5649         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5650                 "stat_Dot3StatsExcessiveCollisions",
5651                 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
5652                 0, "Excessive Collisions");
5653
5654         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5655                 "stat_Dot3StatsLateCollisions",
5656                 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
5657                 0, "Late Collisions");
5658
5659         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5660                 "stat_EtherStatsCollisions",
5661                 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
5662                 0, "Collisions");
5663
5664         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5665                 "stat_EtherStatsFragments",
5666                 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
5667                 0, "Fragments");
5668
5669         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5670                 "stat_EtherStatsJabbers",
5671                 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
5672                 0, "Jabbers");
5673
5674         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5675                 "stat_EtherStatsUndersizePkts",
5676                 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
5677                 0, "Undersize packets");
5678
5679         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5680                 "stat_EtherStatsOverrsizePkts",
5681                 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
5682                 0, "stat_EtherStatsOverrsizePkts");
5683
5684         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5685                 "stat_EtherStatsPktsRx64Octets",
5686                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
5687                 0, "Bytes received in 64 byte packets");
5688
5689         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5690                 "stat_EtherStatsPktsRx65Octetsto127Octets",
5691                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
5692                 0, "Bytes received in 65 to 127 byte packets");
5693
5694         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5695                 "stat_EtherStatsPktsRx128Octetsto255Octets",
5696                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
5697                 0, "Bytes received in 128 to 255 byte packets");
5698
5699         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5700                 "stat_EtherStatsPktsRx256Octetsto511Octets",
5701                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
5702                 0, "Bytes received in 256 to 511 byte packets");
5703
5704         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5705                 "stat_EtherStatsPktsRx512Octetsto1023Octets",
5706                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
5707                 0, "Bytes received in 512 to 1023 byte packets");
5708
5709         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5710                 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
5711                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
5712                 0, "Bytes received in 1024 t0 1522 byte packets");
5713
5714         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5715                 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
5716                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
5717                 0, "Bytes received in 1523 to 9022 byte packets");
5718
5719         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5720                 "stat_EtherStatsPktsTx64Octets",
5721                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
5722                 0, "Bytes sent in 64 byte packets");
5723
5724         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5725                 "stat_EtherStatsPktsTx65Octetsto127Octets",
5726                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
5727                 0, "Bytes sent in 65 to 127 byte packets");
5728
5729         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5730                 "stat_EtherStatsPktsTx128Octetsto255Octets",
5731                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
5732                 0, "Bytes sent in 128 to 255 byte packets");
5733
5734         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5735                 "stat_EtherStatsPktsTx256Octetsto511Octets",
5736                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
5737                 0, "Bytes sent in 256 to 511 byte packets");
5738
5739         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5740                 "stat_EtherStatsPktsTx512Octetsto1023Octets",
5741                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
5742                 0, "Bytes sent in 512 to 1023 byte packets");
5743
5744         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5745                 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
5746                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
5747                 0, "Bytes sent in 1024 to 1522 byte packets");
5748
5749         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5750                 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
5751                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
5752                 0, "Bytes sent in 1523 to 9022 byte packets");
5753
5754         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5755                 "stat_XonPauseFramesReceived",
5756                 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
5757                 0, "XON pause frames receved");
5758
5759         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5760                 "stat_XoffPauseFramesReceived",
5761                 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
5762                 0, "XOFF pause frames received");
5763
5764         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5765                 "stat_OutXonSent",
5766                 CTLFLAG_RD, &sc->stat_OutXonSent,
5767                 0, "XON pause frames sent");
5768
5769         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5770                 "stat_OutXoffSent",
5771                 CTLFLAG_RD, &sc->stat_OutXoffSent,
5772                 0, "XOFF pause frames sent");
5773
5774         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5775                 "stat_FlowControlDone",
5776                 CTLFLAG_RD, &sc->stat_FlowControlDone,
5777                 0, "Flow control done");
5778
5779         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5780                 "stat_MacControlFramesReceived",
5781                 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
5782                 0, "MAC control frames received");
5783
5784         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5785                 "stat_XoffStateEntered",
5786                 CTLFLAG_RD, &sc->stat_XoffStateEntered,
5787                 0, "XOFF state entered");
5788
5789         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5790                 "stat_IfInFramesL2FilterDiscards",
5791                 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
5792                 0, "Received L2 packets discarded");
5793
5794         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5795                 "stat_IfInRuleCheckerDiscards",
5796                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
5797                 0, "Received packets discarded by rule");
5798
5799         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5800                 "stat_IfInFTQDiscards",
5801                 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
5802                 0, "Received packet FTQ discards");
5803
5804         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5805                 "stat_IfInMBUFDiscards",
5806                 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
5807                 0, "Received packets discarded due to lack of controller buffer memory");
5808
5809         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5810                 "stat_IfInRuleCheckerP4Hit",
5811                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
5812                 0, "Received packets rule checker hits");
5813
5814         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5815                 "stat_CatchupInRuleCheckerDiscards",
5816                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
5817                 0, "Received packets discarded in Catchup path");
5818
5819         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5820                 "stat_CatchupInFTQDiscards",
5821                 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
5822                 0, "Received packets discarded in FTQ in Catchup path");
5823
5824         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5825                 "stat_CatchupInMBUFDiscards",
5826                 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
5827                 0, "Received packets discarded in controller buffer memory in Catchup path");
5828
5829         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5830                 "stat_CatchupInRuleCheckerP4Hit",
5831                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
5832                 0, "Received packets rule checker hits in Catchup path");
5833
5834         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5835                 "com_no_buffers",
5836                 CTLFLAG_RD, &sc->com_no_buffers,
5837                 0, "Valid packets received but no RX buffers available");
5838
5839 #ifdef BCE_DEBUG
5840         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5841                 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
5842                 (void *)sc, 0,
5843                 bce_sysctl_driver_state, "I", "Drive state information");
5844
5845         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5846                 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
5847                 (void *)sc, 0,
5848                 bce_sysctl_hw_state, "I", "Hardware state information");
5849
5850         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5851                 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW,
5852                 (void *)sc, 0,
5853                 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain");
5854
5855         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5856                 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
5857                 (void *)sc, 0,
5858                 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
5859
5860         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5861                 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
5862                 (void *)sc, 0,
5863                 bce_sysctl_breakpoint, "I", "Driver breakpoint");
5864
5865         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5866                 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
5867                 (void *)sc, 0,
5868                 bce_sysctl_reg_read, "I", "Register read");
5869
5870         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, \r
5871                 "phy_read", CTLTYPE_INT | CTLFLAG_RW, \r
5872                 (void *)sc, 0, \r
5873                 bce_sysctl_phy_read, "I", "PHY register read");
5874
5875 #endif
5876
5877 }
5878
5879
5880 /****************************************************************************/
5881 /* BCE Debug Routines                                                       */
5882 /****************************************************************************/
5883 #ifdef BCE_DEBUG
5884
5885 /****************************************************************************/
5886 /* Freezes the controller to allow for a cohesive state dump.               */
5887 /*                                                                          */
5888 /* Returns:                                                                 */
5889 /*   Nothing.                                                               */
5890 /****************************************************************************/
5891 static void
5892 bce_freeze_controller(struct bce_softc *sc)
5893 {
5894         uint32_t val;
5895
5896         val = REG_RD(sc, BCE_MISC_COMMAND);
5897         val |= BCE_MISC_COMMAND_DISABLE_ALL;
5898         REG_WR(sc, BCE_MISC_COMMAND, val);
5899 }
5900
5901
5902 /****************************************************************************/
5903 /* Unfreezes the controller after a freeze operation.  This may not always  */\r
5904 /* work and the controller will require a reset!                            */
5905 /*                                                                          */
5906 /* Returns:                                                                 */
5907 /*   Nothing.                                                               */
5908 /****************************************************************************/
5909 static void
5910 bce_unfreeze_controller(struct bce_softc *sc)
5911 {
5912         uint32_t val;
5913
5914         val = REG_RD(sc, BCE_MISC_COMMAND);
5915         val |= BCE_MISC_COMMAND_ENABLE_ALL;
5916         REG_WR(sc, BCE_MISC_COMMAND, val);
5917 }
5918
5919
5920 /****************************************************************************/
5921 /* Prints out information about an mbuf.                                    */
5922 /*                                                                          */
5923 /* Returns:                                                                 */
5924 /*   Nothing.                                                               */
5925 /****************************************************************************/
5926 static void
5927 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
5928 {
5929         struct ifnet *ifp = &sc->arpcom.ac_if;
5930         uint32_t val_hi, val_lo;
5931         struct mbuf *mp = m;
5932
5933         if (m == NULL) {
5934                 /* Index out of range. */
5935                 if_printf(ifp, "mbuf: null pointer\n");
5936                 return;
5937         }
5938
5939         while (mp) {
5940                 val_hi = BCE_ADDR_HI(mp);
5941                 val_lo = BCE_ADDR_LO(mp);
5942                 if_printf(ifp, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, "
5943                           "m_flags = ( ", val_hi, val_lo, mp->m_len);
5944
5945                 if (mp->m_flags & M_EXT)
5946                         kprintf("M_EXT ");
5947                 if (mp->m_flags & M_PKTHDR)
5948                         kprintf("M_PKTHDR ");
5949                 if (mp->m_flags & M_EOR)
5950                         kprintf("M_EOR ");
5951 #ifdef M_RDONLY
5952                 if (mp->m_flags & M_RDONLY)
5953                         kprintf("M_RDONLY ");
5954 #endif
5955
5956                 val_hi = BCE_ADDR_HI(mp->m_data);
5957                 val_lo = BCE_ADDR_LO(mp->m_data);
5958                 kprintf(") m_data = 0x%08X:%08X\n", val_hi, val_lo);
5959
5960                 if (mp->m_flags & M_PKTHDR) {
5961                         if_printf(ifp, "- m_pkthdr: flags = ( ");
5962                         if (mp->m_flags & M_BCAST)
5963                                 kprintf("M_BCAST ");
5964                         if (mp->m_flags & M_MCAST)
5965                                 kprintf("M_MCAST ");
5966                         if (mp->m_flags & M_FRAG)
5967                                 kprintf("M_FRAG ");
5968                         if (mp->m_flags & M_FIRSTFRAG)
5969                                 kprintf("M_FIRSTFRAG ");
5970                         if (mp->m_flags & M_LASTFRAG)
5971                                 kprintf("M_LASTFRAG ");
5972 #ifdef M_VLANTAG
5973                         if (mp->m_flags & M_VLANTAG)
5974                                 kprintf("M_VLANTAG ");
5975 #endif
5976 #ifdef M_PROMISC
5977                         if (mp->m_flags & M_PROMISC)
5978                                 kprintf("M_PROMISC ");
5979 #endif
5980                         kprintf(") csum_flags = ( ");
5981                         if (mp->m_pkthdr.csum_flags & CSUM_IP)
5982                                 kprintf("CSUM_IP ");
5983                         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
5984                                 kprintf("CSUM_TCP ");
5985                         if (mp->m_pkthdr.csum_flags & CSUM_UDP)
5986                                 kprintf("CSUM_UDP ");
5987                         if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS)
5988                                 kprintf("CSUM_IP_FRAGS ");
5989                         if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT)
5990                                 kprintf("CSUM_FRAGMENT ");
5991 #ifdef CSUM_TSO
5992                         if (mp->m_pkthdr.csum_flags & CSUM_TSO)
5993                                 kprintf("CSUM_TSO ");
5994 #endif
5995                         if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED)
5996                                 kprintf("CSUM_IP_CHECKED ");
5997                         if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID)
5998                                 kprintf("CSUM_IP_VALID ");
5999                         if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID)
6000                                 kprintf("CSUM_DATA_VALID ");
6001                         kprintf(")\n");
6002                 }
6003
6004                 if (mp->m_flags & M_EXT) {
6005                         val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf);
6006                         val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf);
6007                         if_printf(ifp, "- m_ext: vaddr = 0x%08X:%08X, "
6008                                   "ext_size = %d\n",
6009                                   val_hi, val_lo, mp->m_ext.ext_size);
6010                 }
6011                 mp = mp->m_next;
6012         }
6013 }
6014
6015
6016 /****************************************************************************/
6017 /* Prints out the mbufs in the TX mbuf chain.                               */
6018 /*                                                                          */
6019 /* Returns:                                                                 */
6020 /*   Nothing.                                                               */
6021 /****************************************************************************/
6022 static void
6023 bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6024 {
6025         struct ifnet *ifp = &sc->arpcom.ac_if;
6026         int i;
6027
6028         if_printf(ifp,
6029         "----------------------------"
6030         "  tx mbuf data  "
6031         "----------------------------\n");
6032
6033         for (i = 0; i < count; i++) {
6034                 if_printf(ifp, "txmbuf[%d]\n", chain_prod);
6035                 bce_dump_mbuf(sc, sc->tx_mbuf_ptr[chain_prod]);
6036                 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
6037         }
6038
6039         if_printf(ifp,
6040         "----------------------------"
6041         "----------------"
6042         "----------------------------\n");
6043 }
6044
6045
6046 /****************************************************************************/
6047 /* Prints out the mbufs in the RX mbuf chain.                               */
6048 /*                                                                          */
6049 /* Returns:                                                                 */
6050 /*   Nothing.                                                               */
6051 /****************************************************************************/
6052 static void
6053 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6054 {
6055         struct ifnet *ifp = &sc->arpcom.ac_if;
6056         int i;
6057
6058         if_printf(ifp,
6059         "----------------------------"
6060         "  rx mbuf data  "
6061         "----------------------------\n");
6062
6063         for (i = 0; i < count; i++) {
6064                 if_printf(ifp, "rxmbuf[0x%04X]\n", chain_prod);
6065                 bce_dump_mbuf(sc, sc->rx_mbuf_ptr[chain_prod]);
6066                 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
6067         }
6068
6069         if_printf(ifp,
6070         "----------------------------"
6071         "----------------"
6072         "----------------------------\n");
6073 }
6074
6075
6076 /****************************************************************************/
6077 /* Prints out a tx_bd structure.                                            */
6078 /*                                                                          */
6079 /* Returns:                                                                 */
6080 /*   Nothing.                                                               */
6081 /****************************************************************************/
6082 static void
6083 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
6084 {
6085         struct ifnet *ifp = &sc->arpcom.ac_if;
6086
6087         if (idx > MAX_TX_BD) {
6088                 /* Index out of range. */
6089                 if_printf(ifp, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
6090         } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
6091                 /* TX Chain page pointer. */
6092                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6093                           "chain page pointer\n",
6094                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
6095         } else {
6096                 /* Normal tx_bd entry. */
6097                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6098                           "nbytes = 0x%08X, "
6099                           "vlan tag= 0x%04X, flags = 0x%04X (",
6100                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
6101                           txbd->tx_bd_mss_nbytes,
6102                           txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
6103
6104                 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
6105                         kprintf(" CONN_FAULT");
6106
6107                 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)
6108                         kprintf(" TCP_UDP_CKSUM");
6109
6110                 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM)
6111                         kprintf(" IP_CKSUM");
6112
6113                 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG)
6114                         kprintf("  VLAN");
6115
6116                 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW)
6117                         kprintf(" COAL_NOW");
6118
6119                 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC)
6120                         kprintf(" DONT_GEN_CRC");
6121
6122                 if (txbd->tx_bd_flags & TX_BD_FLAGS_START)
6123                         kprintf(" START");
6124
6125                 if (txbd->tx_bd_flags & TX_BD_FLAGS_END)
6126                         kprintf(" END");
6127
6128                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO)
6129                         kprintf(" LSO");
6130
6131                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD)
6132                         kprintf(" OPTION_WORD");
6133
6134                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
6135                         kprintf(" FLAGS");
6136
6137                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
6138                         kprintf(" SNAP");
6139
6140                 kprintf(" )\n");
6141         }
6142 }
6143
6144
6145 /****************************************************************************/
6146 /* Prints out a rx_bd structure.                                            */
6147 /*                                                                          */
6148 /* Returns:                                                                 */
6149 /*   Nothing.                                                               */
6150 /****************************************************************************/
6151 static void
6152 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
6153 {
6154         struct ifnet *ifp = &sc->arpcom.ac_if;
6155
6156         if (idx > MAX_RX_BD) {
6157                 /* Index out of range. */
6158                 if_printf(ifp, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
6159         } else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) {
6160                 /* TX Chain page pointer. */
6161                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6162                           "chain page pointer\n",
6163                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
6164         } else {
6165                 /* Normal tx_bd entry. */
6166                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6167                           "nbytes = 0x%08X, flags = 0x%08X\n",
6168                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
6169                           rxbd->rx_bd_len, rxbd->rx_bd_flags);
6170         }
6171 }
6172
6173
6174 /****************************************************************************/
6175 /* Prints out a l2_fhdr structure.                                          */
6176 /*                                                                          */
6177 /* Returns:                                                                 */
6178 /*   Nothing.                                                               */
6179 /****************************************************************************/
6180 static void
6181 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
6182 {
6183         if_printf(&sc->arpcom.ac_if, "l2_fhdr[0x%04X]: status = 0x%08X, "
6184                   "pkt_len = 0x%04X, vlan = 0x%04x, "
6185                   "ip_xsum = 0x%04X, tcp_udp_xsum = 0x%04X\n",
6186                   idx, l2fhdr->l2_fhdr_status,
6187                   l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
6188                   l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
6189 }
6190
6191
6192 /****************************************************************************/
6193 /* Prints out the tx chain.                                                 */
6194 /*                                                                          */
6195 /* Returns:                                                                 */
6196 /*   Nothing.                                                               */
6197 /****************************************************************************/
6198 static void
6199 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count)
6200 {
6201         struct ifnet *ifp = &sc->arpcom.ac_if;
6202         int i;
6203
6204         /* First some info about the tx_bd chain structure. */
6205         if_printf(ifp,
6206         "----------------------------"
6207         "  tx_bd  chain  "
6208         "----------------------------\n");
6209
6210         if_printf(ifp, "page size      = 0x%08X, "
6211                   "tx chain pages        = 0x%08X\n",
6212                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)TX_PAGES);
6213
6214         if_printf(ifp, "tx_bd per page = 0x%08X, "
6215                   "usable tx_bd per page = 0x%08X\n",
6216                   (uint32_t)TOTAL_TX_BD_PER_PAGE,
6217                   (uint32_t)USABLE_TX_BD_PER_PAGE);
6218
6219         if_printf(ifp, "total tx_bd    = 0x%08X\n", (uint32_t)TOTAL_TX_BD);
6220
6221         if_printf(ifp,
6222         "----------------------------"
6223         "  tx_bd data    "
6224         "----------------------------\n");
6225
6226         /* Now print out the tx_bd's themselves. */
6227         for (i = 0; i < count; i++) {
6228                 struct tx_bd *txbd;
6229
6230                 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
6231                 bce_dump_txbd(sc, tx_prod, txbd);
6232                 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod));
6233         }
6234
6235         if_printf(ifp,
6236         "----------------------------"
6237         "----------------"
6238         "----------------------------\n");
6239 }
6240
6241
6242 /****************************************************************************/
6243 /* Prints out the rx chain.                                                 */
6244 /*                                                                          */
6245 /* Returns:                                                                 */
6246 /*   Nothing.                                                               */
6247 /****************************************************************************/
6248 static void
6249 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count)
6250 {
6251         struct ifnet *ifp = &sc->arpcom.ac_if;
6252         int i;
6253
6254         /* First some info about the tx_bd chain structure. */
6255         if_printf(ifp,
6256         "----------------------------"
6257         "  rx_bd  chain  "
6258         "----------------------------\n");
6259
6260         if_printf(ifp, "page size      = 0x%08X, "
6261                   "rx chain pages        = 0x%08X\n",
6262                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES);
6263
6264         if_printf(ifp, "rx_bd per page = 0x%08X, "
6265                   "usable rx_bd per page = 0x%08X\n",
6266                   (uint32_t)TOTAL_RX_BD_PER_PAGE,
6267                   (uint32_t)USABLE_RX_BD_PER_PAGE);
6268
6269         if_printf(ifp, "total rx_bd    = 0x%08X\n", (uint32_t)TOTAL_RX_BD);
6270
6271         if_printf(ifp,
6272         "----------------------------"
6273         "   rx_bd data   "
6274         "----------------------------\n");
6275
6276         /* Now print out the rx_bd's themselves. */
6277         for (i = 0; i < count; i++) {
6278                 struct rx_bd *rxbd;
6279
6280                 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
6281                 bce_dump_rxbd(sc, rx_prod, rxbd);
6282                 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod));
6283         }
6284
6285         if_printf(ifp,
6286         "----------------------------"
6287         "----------------"
6288         "----------------------------\n");
6289 }
6290
6291
6292 /****************************************************************************/
6293 /* Prints out the status block from host memory.                            */
6294 /*                                                                          */
6295 /* Returns:                                                                 */
6296 /*   Nothing.                                                               */
6297 /****************************************************************************/
6298 static void
6299 bce_dump_status_block(struct bce_softc *sc)
6300 {
6301         struct status_block *sblk = sc->status_block;
6302         struct ifnet *ifp = &sc->arpcom.ac_if;
6303
6304         if_printf(ifp,
6305         "----------------------------"
6306         "  Status Block  "
6307         "----------------------------\n");
6308
6309         if_printf(ifp, "    0x%08X - attn_bits\n", sblk->status_attn_bits);
6310
6311         if_printf(ifp, "    0x%08X - attn_bits_ack\n",
6312                   sblk->status_attn_bits_ack);
6313
6314         if_printf(ifp, "0x%04X(0x%04X) - rx_cons0\n",
6315             sblk->status_rx_quick_consumer_index0,
6316             (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0));
6317
6318         if_printf(ifp, "0x%04X(0x%04X) - tx_cons0\n",
6319             sblk->status_tx_quick_consumer_index0,
6320             (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0));
6321
6322         if_printf(ifp, "        0x%04X - status_idx\n", sblk->status_idx);
6323
6324         /* Theses indices are not used for normal L2 drivers. */
6325         if (sblk->status_rx_quick_consumer_index1) {
6326                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons1\n",
6327                 sblk->status_rx_quick_consumer_index1,
6328                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index1));
6329         }
6330
6331         if (sblk->status_tx_quick_consumer_index1) {
6332                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons1\n",
6333                 sblk->status_tx_quick_consumer_index1,
6334                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index1));
6335         }
6336
6337         if (sblk->status_rx_quick_consumer_index2) {
6338                 if_printf(ifp, "0x%04X(0x%04X)- rx_cons2\n",
6339                 sblk->status_rx_quick_consumer_index2,
6340                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index2));
6341         }
6342
6343         if (sblk->status_tx_quick_consumer_index2) {
6344                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons2\n",
6345                 sblk->status_tx_quick_consumer_index2,
6346                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index2));
6347         }
6348
6349         if (sblk->status_rx_quick_consumer_index3) {
6350                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons3\n",
6351                 sblk->status_rx_quick_consumer_index3,
6352                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3));
6353         }
6354
6355         if (sblk->status_tx_quick_consumer_index3) {
6356                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons3\n",
6357                 sblk->status_tx_quick_consumer_index3,
6358                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3));
6359         }
6360
6361         if (sblk->status_rx_quick_consumer_index4 ||
6362             sblk->status_rx_quick_consumer_index5) {
6363                 if_printf(ifp, "rx_cons4  = 0x%08X, rx_cons5      = 0x%08X\n",
6364                           sblk->status_rx_quick_consumer_index4,
6365                           sblk->status_rx_quick_consumer_index5);
6366         }
6367
6368         if (sblk->status_rx_quick_consumer_index6 ||
6369             sblk->status_rx_quick_consumer_index7) {
6370                 if_printf(ifp, "rx_cons6  = 0x%08X, rx_cons7      = 0x%08X\n",
6371                           sblk->status_rx_quick_consumer_index6,
6372                           sblk->status_rx_quick_consumer_index7);
6373         }
6374
6375         if (sblk->status_rx_quick_consumer_index8 ||
6376             sblk->status_rx_quick_consumer_index9) {
6377                 if_printf(ifp, "rx_cons8  = 0x%08X, rx_cons9      = 0x%08X\n",
6378                           sblk->status_rx_quick_consumer_index8,
6379                           sblk->status_rx_quick_consumer_index9);
6380         }
6381
6382         if (sblk->status_rx_quick_consumer_index10 ||
6383             sblk->status_rx_quick_consumer_index11) {
6384                 if_printf(ifp, "rx_cons10 = 0x%08X, rx_cons11     = 0x%08X\n",
6385                           sblk->status_rx_quick_consumer_index10,
6386                           sblk->status_rx_quick_consumer_index11);
6387         }
6388
6389         if (sblk->status_rx_quick_consumer_index12 ||
6390             sblk->status_rx_quick_consumer_index13) {
6391                 if_printf(ifp, "rx_cons12 = 0x%08X, rx_cons13     = 0x%08X\n",
6392                           sblk->status_rx_quick_consumer_index12,
6393                           sblk->status_rx_quick_consumer_index13);
6394         }
6395
6396         if (sblk->status_rx_quick_consumer_index14 ||
6397             sblk->status_rx_quick_consumer_index15) {
6398                 if_printf(ifp, "rx_cons14 = 0x%08X, rx_cons15     = 0x%08X\n",
6399                           sblk->status_rx_quick_consumer_index14,
6400                           sblk->status_rx_quick_consumer_index15);
6401         }
6402
6403         if (sblk->status_completion_producer_index ||
6404             sblk->status_cmd_consumer_index) {
6405                 if_printf(ifp, "com_prod  = 0x%08X, cmd_cons      = 0x%08X\n",
6406                           sblk->status_completion_producer_index,
6407                           sblk->status_cmd_consumer_index);
6408         }
6409
6410         if_printf(ifp,
6411         "----------------------------"
6412         "----------------"
6413         "----------------------------\n");
6414 }
6415
6416
6417 /****************************************************************************/
6418 /* Prints out the statistics block.                                         */
6419 /*                                                                          */
6420 /* Returns:                                                                 */
6421 /*   Nothing.                                                               */
6422 /****************************************************************************/
6423 static void
6424 bce_dump_stats_block(struct bce_softc *sc)
6425 {
6426         struct statistics_block *sblk = sc->stats_block;
6427         struct ifnet *ifp = &sc->arpcom.ac_if;
6428
6429         if_printf(ifp,
6430         "---------------"
6431         " Stats Block  (All Stats Not Shown Are 0) "
6432         "---------------\n");
6433
6434         if (sblk->stat_IfHCInOctets_hi || sblk->stat_IfHCInOctets_lo) {
6435                 if_printf(ifp, "0x%08X:%08X : IfHcInOctets\n",
6436                           sblk->stat_IfHCInOctets_hi,
6437                           sblk->stat_IfHCInOctets_lo);
6438         }
6439
6440         if (sblk->stat_IfHCInBadOctets_hi || sblk->stat_IfHCInBadOctets_lo) {
6441                 if_printf(ifp, "0x%08X:%08X : IfHcInBadOctets\n",
6442                           sblk->stat_IfHCInBadOctets_hi,
6443                           sblk->stat_IfHCInBadOctets_lo);
6444         }
6445
6446         if (sblk->stat_IfHCOutOctets_hi || sblk->stat_IfHCOutOctets_lo) {
6447                 if_printf(ifp, "0x%08X:%08X : IfHcOutOctets\n",
6448                           sblk->stat_IfHCOutOctets_hi,
6449                           sblk->stat_IfHCOutOctets_lo);
6450         }
6451
6452         if (sblk->stat_IfHCOutBadOctets_hi || sblk->stat_IfHCOutBadOctets_lo) {
6453                 if_printf(ifp, "0x%08X:%08X : IfHcOutBadOctets\n",
6454                           sblk->stat_IfHCOutBadOctets_hi,
6455                           sblk->stat_IfHCOutBadOctets_lo);
6456         }
6457
6458         if (sblk->stat_IfHCInUcastPkts_hi || sblk->stat_IfHCInUcastPkts_lo) {
6459                 if_printf(ifp, "0x%08X:%08X : IfHcInUcastPkts\n",
6460                           sblk->stat_IfHCInUcastPkts_hi,
6461                           sblk->stat_IfHCInUcastPkts_lo);
6462         }
6463
6464         if (sblk->stat_IfHCInBroadcastPkts_hi ||
6465             sblk->stat_IfHCInBroadcastPkts_lo) {
6466                 if_printf(ifp, "0x%08X:%08X : IfHcInBroadcastPkts\n",
6467                           sblk->stat_IfHCInBroadcastPkts_hi,
6468                           sblk->stat_IfHCInBroadcastPkts_lo);
6469         }
6470
6471         if (sblk->stat_IfHCInMulticastPkts_hi ||
6472             sblk->stat_IfHCInMulticastPkts_lo) {
6473                 if_printf(ifp, "0x%08X:%08X : IfHcInMulticastPkts\n",
6474                           sblk->stat_IfHCInMulticastPkts_hi,
6475                           sblk->stat_IfHCInMulticastPkts_lo);
6476         }
6477
6478         if (sblk->stat_IfHCOutUcastPkts_hi || sblk->stat_IfHCOutUcastPkts_lo) {
6479                 if_printf(ifp, "0x%08X:%08X : IfHcOutUcastPkts\n",
6480                           sblk->stat_IfHCOutUcastPkts_hi,
6481                           sblk->stat_IfHCOutUcastPkts_lo);
6482         }
6483
6484         if (sblk->stat_IfHCOutBroadcastPkts_hi ||
6485             sblk->stat_IfHCOutBroadcastPkts_lo) {
6486                 if_printf(ifp, "0x%08X:%08X : IfHcOutBroadcastPkts\n",
6487                           sblk->stat_IfHCOutBroadcastPkts_hi,
6488                           sblk->stat_IfHCOutBroadcastPkts_lo);
6489         }
6490
6491         if (sblk->stat_IfHCOutMulticastPkts_hi ||
6492             sblk->stat_IfHCOutMulticastPkts_lo) {
6493                 if_printf(ifp, "0x%08X:%08X : IfHcOutMulticastPkts\n",
6494                           sblk->stat_IfHCOutMulticastPkts_hi,
6495                           sblk->stat_IfHCOutMulticastPkts_lo);
6496         }
6497
6498         if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) {
6499                 if_printf(ifp, "         0x%08X : "
6500                 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
6501                 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
6502         }
6503
6504         if (sblk->stat_Dot3StatsCarrierSenseErrors) {
6505                 if_printf(ifp, "         0x%08X : "
6506                           "Dot3StatsCarrierSenseErrors\n",
6507                           sblk->stat_Dot3StatsCarrierSenseErrors);
6508         }
6509
6510         if (sblk->stat_Dot3StatsFCSErrors) {
6511                 if_printf(ifp, "         0x%08X : Dot3StatsFCSErrors\n",
6512                           sblk->stat_Dot3StatsFCSErrors);
6513         }
6514
6515         if (sblk->stat_Dot3StatsAlignmentErrors) {
6516                 if_printf(ifp, "         0x%08X : Dot3StatsAlignmentErrors\n",
6517                           sblk->stat_Dot3StatsAlignmentErrors);
6518         }
6519
6520         if (sblk->stat_Dot3StatsSingleCollisionFrames) {
6521                 if_printf(ifp, "         0x%08X : "
6522                           "Dot3StatsSingleCollisionFrames\n",
6523                           sblk->stat_Dot3StatsSingleCollisionFrames);
6524         }
6525
6526         if (sblk->stat_Dot3StatsMultipleCollisionFrames) {
6527                 if_printf(ifp, "         0x%08X : "
6528                           "Dot3StatsMultipleCollisionFrames\n",
6529                           sblk->stat_Dot3StatsMultipleCollisionFrames);
6530         }
6531
6532         if (sblk->stat_Dot3StatsDeferredTransmissions) {
6533                 if_printf(ifp, "         0x%08X : "
6534                           "Dot3StatsDeferredTransmissions\n",
6535                           sblk->stat_Dot3StatsDeferredTransmissions);
6536         }
6537
6538         if (sblk->stat_Dot3StatsExcessiveCollisions) {
6539                 if_printf(ifp, "         0x%08X : "
6540                           "Dot3StatsExcessiveCollisions\n",
6541                           sblk->stat_Dot3StatsExcessiveCollisions);
6542         }
6543
6544         if (sblk->stat_Dot3StatsLateCollisions) {
6545                 if_printf(ifp, "         0x%08X : Dot3StatsLateCollisions\n",
6546                           sblk->stat_Dot3StatsLateCollisions);
6547         }
6548
6549         if (sblk->stat_EtherStatsCollisions) {
6550                 if_printf(ifp, "         0x%08X : EtherStatsCollisions\n",
6551                           sblk->stat_EtherStatsCollisions);
6552         }
6553
6554         if (sblk->stat_EtherStatsFragments)  {
6555                 if_printf(ifp, "         0x%08X : EtherStatsFragments\n",
6556                           sblk->stat_EtherStatsFragments);
6557         }
6558
6559         if (sblk->stat_EtherStatsJabbers) {
6560                 if_printf(ifp, "         0x%08X : EtherStatsJabbers\n",
6561                           sblk->stat_EtherStatsJabbers);
6562         }
6563
6564         if (sblk->stat_EtherStatsUndersizePkts) {
6565                 if_printf(ifp, "         0x%08X : EtherStatsUndersizePkts\n",
6566                           sblk->stat_EtherStatsUndersizePkts);
6567         }
6568
6569         if (sblk->stat_EtherStatsOverrsizePkts) {
6570                 if_printf(ifp, "         0x%08X : EtherStatsOverrsizePkts\n",
6571                           sblk->stat_EtherStatsOverrsizePkts);
6572         }
6573
6574         if (sblk->stat_EtherStatsPktsRx64Octets) {
6575                 if_printf(ifp, "         0x%08X : EtherStatsPktsRx64Octets\n",
6576                           sblk->stat_EtherStatsPktsRx64Octets);
6577         }
6578
6579         if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) {
6580                 if_printf(ifp, "         0x%08X : "
6581                           "EtherStatsPktsRx65Octetsto127Octets\n",
6582                           sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
6583         }
6584
6585         if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) {
6586                 if_printf(ifp, "         0x%08X : "
6587                           "EtherStatsPktsRx128Octetsto255Octets\n",
6588                           sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
6589         }
6590
6591         if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) {
6592                 if_printf(ifp, "         0x%08X : "
6593                           "EtherStatsPktsRx256Octetsto511Octets\n",
6594                           sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
6595         }
6596
6597         if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) {
6598                 if_printf(ifp, "         0x%08X : "
6599                           "EtherStatsPktsRx512Octetsto1023Octets\n",
6600                           sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
6601         }
6602
6603         if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) {
6604                 if_printf(ifp, "         0x%08X : "
6605                           "EtherStatsPktsRx1024Octetsto1522Octets\n",
6606                           sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
6607         }
6608
6609         if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) {
6610                 if_printf(ifp, "         0x%08X : "
6611                           "EtherStatsPktsRx1523Octetsto9022Octets\n",
6612                           sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
6613         }
6614
6615         if (sblk->stat_EtherStatsPktsTx64Octets) {
6616                 if_printf(ifp, "         0x%08X : EtherStatsPktsTx64Octets\n",
6617                           sblk->stat_EtherStatsPktsTx64Octets);
6618         }
6619
6620         if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) {
6621                 if_printf(ifp, "         0x%08X : "
6622                           "EtherStatsPktsTx65Octetsto127Octets\n",
6623                           sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
6624         }
6625
6626         if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) {
6627                 if_printf(ifp, "         0x%08X : "
6628                           "EtherStatsPktsTx128Octetsto255Octets\n",
6629                           sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
6630         }
6631
6632         if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) {
6633                 if_printf(ifp, "         0x%08X : "
6634                           "EtherStatsPktsTx256Octetsto511Octets\n",
6635                           sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
6636         }
6637
6638         if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) {
6639                 if_printf(ifp, "         0x%08X : "
6640                           "EtherStatsPktsTx512Octetsto1023Octets\n",
6641                           sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
6642         }
6643
6644         if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) {
6645                 if_printf(ifp, "         0x%08X : "
6646                           "EtherStatsPktsTx1024Octetsto1522Octets\n",
6647                           sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
6648         }
6649
6650         if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) {
6651                 if_printf(ifp, "         0x%08X : "
6652                           "EtherStatsPktsTx1523Octetsto9022Octets\n",
6653                           sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
6654         }
6655
6656         if (sblk->stat_XonPauseFramesReceived) {
6657                 if_printf(ifp, "         0x%08X : XonPauseFramesReceived\n",
6658                           sblk->stat_XonPauseFramesReceived);
6659         }
6660
6661         if (sblk->stat_XoffPauseFramesReceived) {
6662                 if_printf(ifp, "          0x%08X : XoffPauseFramesReceived\n",
6663                           sblk->stat_XoffPauseFramesReceived);
6664         }
6665
6666         if (sblk->stat_OutXonSent) {
6667                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
6668                           sblk->stat_OutXonSent);
6669         }
6670
6671         if (sblk->stat_OutXoffSent) {
6672                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
6673                           sblk->stat_OutXoffSent);
6674         }
6675
6676         if (sblk->stat_FlowControlDone) {
6677                 if_printf(ifp, "         0x%08X : FlowControlDone\n",
6678                           sblk->stat_FlowControlDone);
6679         }
6680
6681         if (sblk->stat_MacControlFramesReceived) {
6682                 if_printf(ifp, "         0x%08X : MacControlFramesReceived\n",
6683                           sblk->stat_MacControlFramesReceived);
6684         }
6685
6686         if (sblk->stat_XoffStateEntered) {
6687                 if_printf(ifp, "         0x%08X : XoffStateEntered\n",
6688                           sblk->stat_XoffStateEntered);
6689         }
6690
6691         if (sblk->stat_IfInFramesL2FilterDiscards) {
6692                 if_printf(ifp, "         0x%08X : IfInFramesL2FilterDiscards\n",                          sblk->stat_IfInFramesL2FilterDiscards);
6693         }
6694
6695         if (sblk->stat_IfInRuleCheckerDiscards) {
6696                 if_printf(ifp, "         0x%08X : IfInRuleCheckerDiscards\n",
6697                           sblk->stat_IfInRuleCheckerDiscards);
6698         }
6699
6700         if (sblk->stat_IfInFTQDiscards) {
6701                 if_printf(ifp, "         0x%08X : IfInFTQDiscards\n",
6702                           sblk->stat_IfInFTQDiscards);
6703         }
6704
6705         if (sblk->stat_IfInMBUFDiscards) {
6706                 if_printf(ifp, "         0x%08X : IfInMBUFDiscards\n",
6707                           sblk->stat_IfInMBUFDiscards);
6708         }
6709
6710         if (sblk->stat_IfInRuleCheckerP4Hit) {
6711                 if_printf(ifp, "         0x%08X : IfInRuleCheckerP4Hit\n",
6712                           sblk->stat_IfInRuleCheckerP4Hit);
6713         }
6714
6715         if (sblk->stat_CatchupInRuleCheckerDiscards) {
6716                 if_printf(ifp, "         0x%08X : "
6717                           "CatchupInRuleCheckerDiscards\n",
6718                           sblk->stat_CatchupInRuleCheckerDiscards);
6719         }
6720
6721         if (sblk->stat_CatchupInFTQDiscards) {
6722                 if_printf(ifp, "         0x%08X : CatchupInFTQDiscards\n",
6723                           sblk->stat_CatchupInFTQDiscards);
6724         }
6725
6726         if (sblk->stat_CatchupInMBUFDiscards) {
6727                 if_printf(ifp, "         0x%08X : CatchupInMBUFDiscards\n",
6728                           sblk->stat_CatchupInMBUFDiscards);
6729         }
6730
6731         if (sblk->stat_CatchupInRuleCheckerP4Hit) {
6732                 if_printf(ifp, "         0x%08X : CatchupInRuleCheckerP4Hit\n",
6733                           sblk->stat_CatchupInRuleCheckerP4Hit);
6734         }
6735
6736         if_printf(ifp,
6737         "----------------------------"
6738         "----------------"
6739         "----------------------------\n");
6740 }
6741
6742
6743 /****************************************************************************/
6744 /* Prints out a summary of the driver state.                                */
6745 /*                                                                          */
6746 /* Returns:                                                                 */
6747 /*   Nothing.                                                               */
6748 /****************************************************************************/
6749 static void
6750 bce_dump_driver_state(struct bce_softc *sc)
6751 {
6752         struct ifnet *ifp = &sc->arpcom.ac_if;
6753         uint32_t val_hi, val_lo;
6754
6755         if_printf(ifp,
6756         "-----------------------------"
6757         " Driver State "
6758         "-----------------------------\n");
6759
6760         val_hi = BCE_ADDR_HI(sc);
6761         val_lo = BCE_ADDR_LO(sc);
6762         if_printf(ifp, "0x%08X:%08X - (sc) driver softc structure "
6763                   "virtual address\n", val_hi, val_lo);
6764
6765         val_hi = BCE_ADDR_HI(sc->status_block);
6766         val_lo = BCE_ADDR_LO(sc->status_block);
6767         if_printf(ifp, "0x%08X:%08X - (sc->status_block) status block "
6768                   "virtual address\n", val_hi, val_lo);
6769
6770         val_hi = BCE_ADDR_HI(sc->stats_block);
6771         val_lo = BCE_ADDR_LO(sc->stats_block);
6772         if_printf(ifp, "0x%08X:%08X - (sc->stats_block) statistics block "
6773                   "virtual address\n", val_hi, val_lo);
6774
6775         val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
6776         val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
6777         if_printf(ifp, "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
6778                   "virtual adddress\n", val_hi, val_lo);
6779
6780         val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
6781         val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
6782         if_printf(ifp, "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
6783                   "virtual address\n", val_hi, val_lo);
6784
6785         val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
6786         val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
6787         if_printf(ifp, "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
6788                   "virtual address\n", val_hi, val_lo);
6789
6790         val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
6791         val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
6792         if_printf(ifp, "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
6793                   "virtual address\n", val_hi, val_lo);
6794
6795         if_printf(ifp, "         0x%08X - (sc->interrupts_generated) "
6796                   "h/w intrs\n", sc->interrupts_generated);
6797
6798         if_printf(ifp, "         0x%08X - (sc->rx_interrupts) "
6799                   "rx interrupts handled\n", sc->rx_interrupts);
6800
6801         if_printf(ifp, "         0x%08X - (sc->tx_interrupts) "
6802                   "tx interrupts handled\n", sc->tx_interrupts);
6803
6804         if_printf(ifp, "         0x%08X - (sc->last_status_idx) "
6805                   "status block index\n", sc->last_status_idx);
6806
6807         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_prod) "
6808                   "tx producer index\n",
6809                   sc->tx_prod, (uint16_t)TX_CHAIN_IDX(sc->tx_prod));
6810
6811         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_cons) "
6812                   "tx consumer index\n",
6813                   sc->tx_cons, (uint16_t)TX_CHAIN_IDX(sc->tx_cons));
6814
6815         if_printf(ifp, "         0x%08X - (sc->tx_prod_bseq) "
6816                   "tx producer bseq index\n", sc->tx_prod_bseq);
6817
6818         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_prod) "
6819                   "rx producer index\n",
6820                   sc->rx_prod, (uint16_t)RX_CHAIN_IDX(sc->rx_prod));
6821
6822         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_cons) "
6823                   "rx consumer index\n",
6824                   sc->rx_cons, (uint16_t)RX_CHAIN_IDX(sc->rx_cons));
6825
6826         if_printf(ifp, "         0x%08X - (sc->rx_prod_bseq) "
6827                   "rx producer bseq index\n", sc->rx_prod_bseq);
6828
6829         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
6830                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
6831
6832         if_printf(ifp, "         0x%08X - (sc->free_rx_bd) "
6833                   "free rx_bd's\n", sc->free_rx_bd);
6834
6835         if_printf(ifp, "0x%08X/%08X - (sc->rx_low_watermark) rx "
6836                   "low watermark\n", sc->rx_low_watermark, sc->max_rx_bd);
6837
6838         if_printf(ifp, "         0x%08X - (sc->txmbuf_alloc) "
6839                   "tx mbufs allocated\n", sc->tx_mbuf_alloc);
6840
6841         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
6842                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
6843
6844         if_printf(ifp, "         0x%08X - (sc->used_tx_bd) used tx_bd's\n",
6845                   sc->used_tx_bd);
6846
6847         if_printf(ifp, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
6848                   sc->tx_hi_watermark, sc->max_tx_bd);
6849
6850         if_printf(ifp, "         0x%08X - (sc->mbuf_alloc_failed) "
6851                   "failed mbuf alloc\n", sc->mbuf_alloc_failed);
6852
6853         if_printf(ifp,
6854         "----------------------------"
6855         "----------------"
6856         "----------------------------\n");
6857 }
6858
6859
6860 /****************************************************************************/
6861 /* Prints out the hardware state through a summary of important registers,  */\r
6862 /* followed by a complete register dump.                                    */
6863 /*                                                                          */
6864 /* Returns:                                                                 */
6865 /*   Nothing.                                                               */
6866 /****************************************************************************/
6867 static void
6868 bce_dump_hw_state(struct bce_softc *sc)
6869 {
6870         struct ifnet *ifp = &sc->arpcom.ac_if;
6871         uint32_t val1;
6872         int i;
6873
6874         if_printf(ifp,
6875         "----------------------------"
6876         " Hardware State "
6877         "----------------------------\n");
6878
6879         if_printf(ifp, "0x%08X - bootcode version\n", sc->bce_fw_ver);
6880
6881         val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
6882         if_printf(ifp, "0x%08X - (0x%06X) misc_enable_status_bits\n",
6883                   val1, BCE_MISC_ENABLE_STATUS_BITS);
6884
6885         val1 = REG_RD(sc, BCE_DMA_STATUS);
6886         if_printf(ifp, "0x%08X - (0x%04X) dma_status\n", val1, BCE_DMA_STATUS);
6887
6888         val1 = REG_RD(sc, BCE_CTX_STATUS);
6889         if_printf(ifp, "0x%08X - (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS);
6890
6891         val1 = REG_RD(sc, BCE_EMAC_STATUS);
6892         if_printf(ifp, "0x%08X - (0x%04X) emac_status\n",
6893                   val1, BCE_EMAC_STATUS);
6894
6895         val1 = REG_RD(sc, BCE_RPM_STATUS);
6896         if_printf(ifp, "0x%08X - (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS);
6897
6898         val1 = REG_RD(sc, BCE_TBDR_STATUS);
6899         if_printf(ifp, "0x%08X - (0x%04X) tbdr_status\n",
6900                   val1, BCE_TBDR_STATUS);
6901
6902         val1 = REG_RD(sc, BCE_TDMA_STATUS);
6903         if_printf(ifp, "0x%08X - (0x%04X) tdma_status\n",
6904                   val1, BCE_TDMA_STATUS);
6905
6906         val1 = REG_RD(sc, BCE_HC_STATUS);
6907         if_printf(ifp, "0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS);
6908
6909         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
6910         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
6911                   val1, BCE_TXP_CPU_STATE);
6912
6913         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
6914         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
6915                   val1, BCE_TPAT_CPU_STATE);
6916
6917         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
6918         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
6919                   val1, BCE_RXP_CPU_STATE);
6920
6921         val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE);
6922         if_printf(ifp, "0x%08X - (0x%06X) com_cpu_state\n",
6923                   val1, BCE_COM_CPU_STATE);
6924
6925         val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
6926         if_printf(ifp, "0x%08X - (0x%06X) mcp_cpu_state\n",
6927                   val1, BCE_MCP_CPU_STATE);
6928
6929         val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE);
6930         if_printf(ifp, "0x%08X - (0x%06X) cp_cpu_state\n",
6931                   val1, BCE_CP_CPU_STATE);
6932
6933         if_printf(ifp,
6934         "----------------------------"
6935         "----------------"
6936         "----------------------------\n");
6937
6938         if_printf(ifp,
6939         "----------------------------"
6940         " Register  Dump "
6941         "----------------------------\n");
6942
6943         for (i = 0x400; i < 0x8000; i += 0x10) {
6944                 if_printf(ifp, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
6945                           REG_RD(sc, i),
6946                           REG_RD(sc, i + 0x4),
6947                           REG_RD(sc, i + 0x8),
6948                           REG_RD(sc, i + 0xc));
6949         }
6950
6951         if_printf(ifp,
6952         "----------------------------"
6953         "----------------"
6954         "----------------------------\n");
6955 }
6956
6957
6958 /****************************************************************************/
6959 /* Prints out the TXP state.                                                */\r
6960 /*                                                                          */
6961 /* Returns:                                                                 */
6962 /*   Nothing.                                                               */
6963 /****************************************************************************/
6964 static void
6965 bce_dump_txp_state(struct bce_softc *sc)
6966 {
6967         struct ifnet *ifp = &sc->arpcom.ac_if;
6968         uint32_t val1;
6969         int i;
6970
6971         if_printf(ifp,
6972         "----------------------------"
6973         "   TXP  State   "
6974         "----------------------------\n");
6975
6976         val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
6977         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_mode\n",
6978                   val1, BCE_TXP_CPU_MODE);
6979
6980         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
6981         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
6982                   val1, BCE_TXP_CPU_STATE);
6983
6984         val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
6985         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_event_mask\n",
6986                   val1, BCE_TXP_CPU_EVENT_MASK);
6987
6988         if_printf(ifp,
6989         "----------------------------"
6990         " Register  Dump "
6991         "----------------------------\n");
6992
6993         for (i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
6994                 /* Skip the big blank spaces */
6995                 if (i < 0x454000 && i > 0x5ffff) {
6996                         if_printf(ifp, "0x%04X: "
6997                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
6998                                   REG_RD_IND(sc, i),
6999                                   REG_RD_IND(sc, i + 0x4),
7000                                   REG_RD_IND(sc, i + 0x8),
7001                                   REG_RD_IND(sc, i + 0xc));
7002                 }
7003         }
7004
7005         if_printf(ifp,
7006         "----------------------------"
7007         "----------------"
7008         "----------------------------\n");
7009 }
7010
7011
7012 /****************************************************************************/
7013 /* Prints out the RXP state.                                                */\r
7014 /*                                                                          */
7015 /* Returns:                                                                 */
7016 /*   Nothing.                                                               */
7017 /****************************************************************************/
7018 static void
7019 bce_dump_rxp_state(struct bce_softc *sc)
7020 {
7021         struct ifnet *ifp = &sc->arpcom.ac_if;
7022         uint32_t val1;
7023         int i;
7024
7025         if_printf(ifp,
7026         "----------------------------"
7027         "   RXP  State   "
7028         "----------------------------\n");
7029
7030         val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
7031         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_mode\n",
7032                   val1, BCE_RXP_CPU_MODE);
7033
7034         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7035         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7036                   val1, BCE_RXP_CPU_STATE);
7037
7038         val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
7039         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_event_mask\n",
7040                   val1, BCE_RXP_CPU_EVENT_MASK);
7041
7042         if_printf(ifp,
7043         "----------------------------"
7044         " Register  Dump "
7045         "----------------------------\n");
7046
7047         for (i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
7048                 /* Skip the big blank sapces */
7049                 if (i < 0xc5400 && i > 0xdffff) {
7050                         if_printf(ifp, "0x%04X: "
7051                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7052                                   REG_RD_IND(sc, i),
7053                                   REG_RD_IND(sc, i + 0x4),
7054                                   REG_RD_IND(sc, i + 0x8),
7055                                   REG_RD_IND(sc, i + 0xc));
7056                 }
7057         }
7058
7059         if_printf(ifp,
7060         "----------------------------"
7061         "----------------"
7062         "----------------------------\n");
7063 }
7064
7065
7066 /****************************************************************************/
7067 /* Prints out the TPAT state.                                               */\r
7068 /*                                                                          */
7069 /* Returns:                                                                 */
7070 /*   Nothing.                                                               */
7071 /****************************************************************************/
7072 static void
7073 bce_dump_tpat_state(struct bce_softc *sc)
7074 {
7075         struct ifnet *ifp = &sc->arpcom.ac_if;
7076         uint32_t val1;
7077         int i;
7078
7079         if_printf(ifp,
7080         "----------------------------"
7081         "   TPAT State   "
7082         "----------------------------\n");
7083
7084         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
7085         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_mode\n",
7086                   val1, BCE_TPAT_CPU_MODE);
7087
7088         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7089         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7090                   val1, BCE_TPAT_CPU_STATE);
7091
7092         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
7093         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_event_mask\n",
7094                   val1, BCE_TPAT_CPU_EVENT_MASK);
7095
7096         if_printf(ifp,
7097         "----------------------------"
7098         " Register  Dump "
7099         "----------------------------\n");
7100
7101         for (i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
7102                 /* Skip the big blank spaces */
7103                 if (i < 0x854000 && i > 0x9ffff) {
7104                         if_printf(ifp, "0x%04X: "
7105                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7106                                   REG_RD_IND(sc, i),
7107                                   REG_RD_IND(sc, i + 0x4),
7108                                   REG_RD_IND(sc, i + 0x8),
7109                                   REG_RD_IND(sc, i + 0xc));
7110                 }
7111         }
7112
7113         if_printf(ifp,
7114         "----------------------------"
7115         "----------------"
7116         "----------------------------\n");
7117 }
7118
7119
7120 /****************************************************************************/
7121 /* Prints out the driver state and then enters the debugger.                */
7122 /*                                                                          */
7123 /* Returns:                                                                 */
7124 /*   Nothing.                                                               */
7125 /****************************************************************************/
7126 static void
7127 bce_breakpoint(struct bce_softc *sc)
7128 {
7129 #if 0
7130         bce_freeze_controller(sc);
7131 #endif
7132
7133         bce_dump_driver_state(sc);
7134         bce_dump_status_block(sc);
7135         bce_dump_tx_chain(sc, 0, TOTAL_TX_BD);
7136         bce_dump_hw_state(sc);
7137         bce_dump_txp_state(sc);
7138
7139 #if 0
7140         bce_unfreeze_controller(sc);
7141 #endif
7142
7143         /* Call the debugger. */
7144         breakpoint();
7145 }
7146
7147 #endif  /* BCE_DEBUG */