sys/dev/netif/gx/if_gx.c

   1 /*-
   2  * Copyright (c) 1999,2000,2001 Jonathan Lemon
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. Neither the name of the author nor the names of any co-contributors
  14  *    may be used to endorse or promote products derived from this software
  15  *    without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  *
  29  * $FreeBSD: src/sys/dev/gx/if_gx.c,v 1.2.2.3 2001/12/14 19:51:39 jlemon Exp $
  30  * $DragonFly: src/sys/dev/netif/gx/Attic/if_gx.c,v 1.29 2008/01/05 14:02:37 swildner Exp $
  31  */
  32
  33 #include <sys/param.h>
  34 #include <sys/systm.h>
  35 #include <sys/sockio.h>
  36 #include <sys/mbuf.h>
  37 #include <sys/malloc.h>
  38 #include <sys/kernel.h>
  39 #include <sys/socket.h>
  40 #include <sys/queue.h>
  41 #include <sys/serialize.h>
  42 #include <sys/bus.h>
  43 #include <sys/rman.h>
  44 #include <sys/thread2.h>
  45
  46 #include <net/if.h>
  47 #include <net/ifq_var.h>
  48 #include <net/if_arp.h>
  49 #include <net/ethernet.h>
  50 #include <net/if_dl.h>
  51 #include <net/if_media.h>
  52
  53 #include <net/bpf.h>
  54 #include <net/if_types.h>
  55 #include <net/vlan/if_vlan_var.h>
  56
  57 #include <netinet/in_systm.h>
  58 #include <netinet/in.h>
  59 #include <netinet/ip.h>
  60 #include <netinet/tcp.h>
  61 #include <netinet/udp.h>
  62
  63 #include <vm/vm.h>              /* for vtophys */
  64 #include <vm/pmap.h>            /* for vtophys */
  65 #include <machine/clock.h>      /* for DELAY */
  66
  67 #include <bus/pci/pcidevs.h>
  68 #include <bus/pci/pcireg.h>
  69 #include <bus/pci/pcivar.h>
  70
  71 #include "../mii_layer/mii.h"
  72 #include "../mii_layer/miivar.h"
  73
  74 #include "if_gxreg.h"
  75 #include "if_gxvar.h"
  76
  77 #include "miibus_if.h"
  78
  79 #define TUNABLE_TX_INTR_DELAY   100
  80 #define TUNABLE_RX_INTR_DELAY   100
  81
  82 #define GX_CSUM_FEATURES        (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
  83
  84 /*
  85  * Various supported device vendors/types and their names.
  86  */
  87 struct gx_device {
  88         u_int16_t       vendor;
  89         u_int16_t       device;
  90         int             version_flags;
  91         u_int32_t       version_ipg;
  92         char            *name;
  93 };
  94
  95 static struct gx_device gx_devs[] = {
  96         { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542,
  97             GXF_FORCE_TBI | GXF_OLD_REGS,
  98             10 | 2 << 10 | 10 << 20,
  99             "Intel Gigabit Ethernet (82542)" },
 100         { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER,
 101             GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
 102             6 | 8 << 10 | 6 << 20,
 103             "Intel Gigabit Ethernet (82543GC-F)" },
 104         { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER,
 105             GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
 106             8 | 8 << 10 | 6 << 20,
 107             "Intel Gigabit Ethernet (82543GC-T)" },
 108 #if 0
 109 /* notyet.. */
 110         { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER,
 111             GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
 112             6 | 8 << 10 | 6 << 20,
 113             "Intel Gigabit Ethernet (82544EI-F)" },
 114         { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER,
 115             GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
 116             8 | 8 << 10 | 6 << 20,
 117             "Intel Gigabit Ethernet (82544EI-T)" },
 118         { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM,
 119             GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
 120             8 | 8 << 10 | 6 << 20,
 121             "Intel Gigabit Ethernet (82544GC-T)" },
 122 #endif
 123         { 0, 0, 0, NULL }
 124 };
 125
 126 static struct gx_regs new_regs = {
 127         GX_RX_RING_BASE, GX_RX_RING_LEN,
 128         GX_RX_RING_HEAD, GX_RX_RING_TAIL,
 129         GX_RX_INTR_DELAY, GX_RX_DMA_CTRL,
 130
 131         GX_TX_RING_BASE, GX_TX_RING_LEN,
 132         GX_TX_RING_HEAD, GX_TX_RING_TAIL,
 133         GX_TX_INTR_DELAY, GX_TX_DMA_CTRL,
 134 };
 135 static struct gx_regs old_regs = {
 136         GX_RX_OLD_RING_BASE, GX_RX_OLD_RING_LEN,
 137         GX_RX_OLD_RING_HEAD, GX_RX_OLD_RING_TAIL,
 138         GX_RX_OLD_INTR_DELAY, GX_RX_OLD_DMA_CTRL,
 139
 140         GX_TX_OLD_RING_BASE, GX_TX_OLD_RING_LEN,
 141         GX_TX_OLD_RING_HEAD, GX_TX_OLD_RING_TAIL,
 142         GX_TX_OLD_INTR_DELAY, GX_TX_OLD_DMA_CTRL,
 143 };
 144
 145 static int      gx_probe(device_t dev);
 146 static int      gx_attach(device_t dev);
 147 static int      gx_detach(device_t dev);
 148 static void     gx_shutdown(device_t dev);
 149
 150 static void     gx_intr(void *xsc);
 151 static void     gx_init(void *xsc);
 152
 153 static struct   gx_device *gx_match(device_t dev);
 154 static void     gx_eeprom_getword(struct gx_softc *gx, int addr,
 155                     u_int16_t *dest);
 156 static int      gx_read_eeprom(struct gx_softc *gx, caddr_t dest, int off,
 157                     int cnt);
 158 static int      gx_ifmedia_upd(struct ifnet *ifp);
 159 static void     gx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
 160 static int      gx_miibus_readreg(device_t dev, int phy, int reg);
 161 static void     gx_miibus_writereg(device_t dev, int phy, int reg, int value);
 162 static void     gx_miibus_statchg(device_t dev);
 163 static int      gx_ioctl(struct ifnet *ifp, u_long command, caddr_t data,
 164                     struct ucred *);
 165 static void     gx_setmulti(struct gx_softc *gx);
 166 static void     gx_reset(struct gx_softc *gx);
 167 static void     gx_phy_reset(struct gx_softc *gx);
 168 static void     gx_stop(struct gx_softc *gx);
 169 static void     gx_watchdog(struct ifnet *ifp);
 170 static void     gx_start(struct ifnet *ifp);
 171
 172 static int      gx_init_rx_ring(struct gx_softc *gx);
 173 static void     gx_free_rx_ring(struct gx_softc *gx);
 174 static int      gx_init_tx_ring(struct gx_softc *gx);
 175 static void     gx_free_tx_ring(struct gx_softc *gx);
 176
 177 static device_method_t gx_methods[] = {
 178         /* Device interface */
 179         DEVMETHOD(device_probe,         gx_probe),
 180         DEVMETHOD(device_attach,        gx_attach),
 181         DEVMETHOD(device_detach,        gx_detach),
 182         DEVMETHOD(device_shutdown,      gx_shutdown),
 183
 184         /* MII interface */
 185         DEVMETHOD(miibus_readreg,       gx_miibus_readreg),
 186         DEVMETHOD(miibus_writereg,      gx_miibus_writereg),
 187         DEVMETHOD(miibus_statchg,       gx_miibus_statchg),
 188
 189         { 0, 0 }
 190 };
 191
 192 static driver_t gx_driver = {
 193         "gx",
 194         gx_methods,
 195         sizeof(struct gx_softc)
 196 };
 197
 198 static devclass_t gx_devclass;
 199
 200 DECLARE_DUMMY_MODULE(if_gx);
 201 MODULE_DEPEND(if_gx, miibus, 1, 1, 1);
 202 DRIVER_MODULE(if_gx, pci, gx_driver, gx_devclass, 0, 0);
 203 DRIVER_MODULE(miibus, gx, miibus_driver, miibus_devclass, 0, 0);
 204
 205 static struct gx_device *
 206 gx_match(device_t dev)
 207 {
 208         int i;
 209
 210         for (i = 0; gx_devs[i].name != NULL; i++) {
 211                 if ((pci_get_vendor(dev) == gx_devs[i].vendor) &&
 212                     (pci_get_device(dev) == gx_devs[i].device))
 213                         return (&gx_devs[i]);
 214         }
 215         return (NULL);
 216 }
 217
 218 static int
 219 gx_probe(device_t dev)
 220 {
 221         struct gx_device *gx_dev;
 222
 223         gx_dev = gx_match(dev);
 224         if (gx_dev == NULL)
 225                 return (ENXIO);
 226
 227         device_set_desc(dev, gx_dev->name);
 228         return (0);
 229 }
 230
 231 static int
 232 gx_attach(device_t dev)
 233 {
 234         struct gx_softc *gx;
 235         struct gx_device *gx_dev;
 236         struct ifnet *ifp;
 237         u_int32_t command;
 238         int rid;
 239         int error = 0;
 240
 241         gx = device_get_softc(dev);
 242         gx->gx_dev = dev;
 243
 244         gx_dev = gx_match(dev);
 245         gx->gx_vflags = gx_dev->version_flags;
 246         gx->gx_ipg = gx_dev->version_ipg;
 247
 248         /*
 249          * Map control/status registers.
 250          */
 251         command = pci_read_config(dev, PCIR_COMMAND, 4);
 252         command |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
 253         if (gx->gx_vflags & GXF_ENABLE_MWI)
 254                 command |= PCIM_CMD_MWIEN;
 255         pci_write_config(dev, PCIR_COMMAND, command, 4);
 256         command = pci_read_config(dev, PCIR_COMMAND, 4);
 257
 258 /* XXX check cache line size? */
 259
 260         if ((command & PCIM_CMD_MEMEN) == 0) {
 261                 device_printf(dev, "failed to enable memory mapping!\n");
 262                 error = ENXIO;
 263                 goto fail;
 264         }
 265
 266         rid = GX_PCI_LOMEM;
 267         gx->gx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 268             RF_ACTIVE);
 269 #if 0
 270 /* support PIO mode */
 271         rid = PCI_LOIO;
 272         gx->gx_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
 273             RF_ACTIVE);
 274 #endif
 275
 276         if (gx->gx_res == NULL) {
 277                 device_printf(dev, "couldn't map memory\n");
 278                 error = ENXIO;
 279                 goto fail;
 280         }
 281
 282         gx->gx_btag = rman_get_bustag(gx->gx_res);
 283         gx->gx_bhandle = rman_get_bushandle(gx->gx_res);
 284
 285         /* Allocate interrupt */
 286         rid = 0;
 287         gx->gx_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 288             RF_SHAREABLE | RF_ACTIVE);
 289
 290         if (gx->gx_irq == NULL) {
 291                 device_printf(dev, "couldn't map interrupt\n");
 292                 error = ENXIO;
 293                 goto fail;
 294         }
 295
 296         /* compensate for different register mappings */
 297         if (gx->gx_vflags & GXF_OLD_REGS)
 298                 gx->gx_reg = old_regs;
 299         else
 300                 gx->gx_reg = new_regs;
 301
 302         if (gx_read_eeprom(gx, (caddr_t)&gx->arpcom.ac_enaddr,
 303             GX_EEMAP_MAC, 3)) {
 304                 device_printf(dev, "failed to read station address\n");
 305                 error = ENXIO;
 306                 goto fail;
 307         }
 308
 309         /* Allocate the ring buffers. */
 310         gx->gx_rdata = contigmalloc(sizeof(struct gx_ring_data), M_DEVBUF,
 311             M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
 312
 313         if (gx->gx_rdata == NULL) {
 314                 device_printf(dev, "no memory for list buffers!\n");
 315                 error = ENXIO;
 316                 goto fail;
 317         }
 318
 319         /* Set default tuneable values. */
 320         gx->gx_tx_intr_delay = TUNABLE_TX_INTR_DELAY;
 321         gx->gx_rx_intr_delay = TUNABLE_RX_INTR_DELAY;
 322
 323         /* Set up ifnet structure */
 324         ifp = &gx->arpcom.ac_if;
 325         ifp->if_softc = gx;
 326         if_initname(ifp, "gx", device_get_unit(dev));
 327         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 328         ifp->if_ioctl = gx_ioctl;
 329         ifp->if_start = gx_start;
 330         ifp->if_watchdog = gx_watchdog;
 331         ifp->if_init = gx_init;
 332         ifp->if_mtu = ETHERMTU;
 333         ifq_set_maxlen(&ifp->if_snd, GX_TX_RING_CNT - 1);
 334         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING;
 335         ifq_set_ready(&ifp->if_snd);
 336
 337         /* see if we can enable hardware checksumming */
 338         if (gx->gx_vflags & GXF_CSUM) {
 339                 ifp->if_capabilities |= IFCAP_HWCSUM;
 340                 ifp->if_capenable = ifp->if_capabilities;
 341         }
 342
 343         /* figure out transciever type */
 344         if (gx->gx_vflags & GXF_FORCE_TBI ||
 345             CSR_READ_4(gx, GX_STATUS) & GX_STAT_TBIMODE)
 346                 gx->gx_tbimode = 1;
 347
 348         if (gx->gx_tbimode) {
 349                 /* SERDES transceiver */
 350                 ifmedia_init(&gx->gx_media, IFM_IMASK, gx_ifmedia_upd,
 351                     gx_ifmedia_sts);
 352                 ifmedia_add(&gx->gx_media,
 353                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
 354                 ifmedia_add(&gx->gx_media, IFM_ETHER|IFM_AUTO, 0, NULL);
 355                 ifmedia_set(&gx->gx_media, IFM_ETHER|IFM_AUTO);
 356         } else {
 357                 /* GMII/MII transceiver */
 358                 gx_phy_reset(gx);
 359                 if (mii_phy_probe(dev, &gx->gx_miibus, gx_ifmedia_upd,
 360                     gx_ifmedia_sts)) {
 361                         device_printf(dev, "GMII/MII, PHY not detected\n");
 362                         error = ENXIO;
 363                         goto fail;
 364                 }
 365         }
 366
 367         /*
 368          * Call MI attach routines.
 369          */
 370         ether_ifattach(ifp, gx->arpcom.ac_enaddr, NULL);
 371
 372         error = bus_setup_intr(dev, gx->gx_irq, INTR_NETSAFE,
 373                                gx_intr, gx, &gx->gx_intrhand,
 374                                ifp->if_serializer);
 375         if (error) {
 376                 ether_ifdetach(ifp);
 377                 device_printf(dev, "couldn't setup irq\n");
 378                 goto fail;
 379         }
 380
 381         return (0);
 382
 383 fail:
 384         gx_detach(dev);
 385         return (error);
 386 }
 387
 388 static void
 389 gx_init(void *xsc)
 390 {
 391         struct gx_softc *gx = (struct gx_softc *)xsc;
 392         struct ifmedia *ifm;
 393         struct ifnet *ifp = &gx->arpcom.ac_if;
 394         u_int16_t *m;
 395         u_int32_t ctrl;
 396         int i, tmp;
 397
 398         /* Disable host interrupts, halt chip. */
 399         gx_reset(gx);
 400
 401         /* disable I/O, flush RX/TX FIFOs, and free RX/TX buffers */
 402         gx_stop(gx);
 403
 404         /* Load our MAC address, invalidate other 15 RX addresses. */
 405         m = (u_int16_t *)&gx->arpcom.ac_enaddr[0];
 406         CSR_WRITE_4(gx, GX_RX_ADDR_BASE, (m[1] << 16) | m[0]);
 407         CSR_WRITE_4(gx, GX_RX_ADDR_BASE + 4, m[2] | GX_RA_VALID);
 408         for (i = 1; i < 16; i++)
 409                 CSR_WRITE_8(gx, GX_RX_ADDR_BASE + i * 8, (u_quad_t)0);
 410
 411         /* Program multicast filter. */
 412         gx_setmulti(gx);
 413
 414         /* Init RX ring. */
 415         gx_init_rx_ring(gx);
 416
 417         /* Init TX ring. */
 418         gx_init_tx_ring(gx);
 419
 420         if (gx->gx_vflags & GXF_DMA) {
 421                 /* set up DMA control */
 422                 CSR_WRITE_4(gx, gx->gx_reg.r_rx_dma_ctrl, 0x00010000);
 423                 CSR_WRITE_4(gx, gx->gx_reg.r_tx_dma_ctrl, 0x00000000);
 424         }
 425
 426         /* enable receiver */
 427         ctrl = GX_RXC_ENABLE | GX_RXC_RX_THOLD_EIGHTH | GX_RXC_RX_BSIZE_2K;
 428         ctrl |= GX_RXC_BCAST_ACCEPT;
 429
 430         /* Enable or disable promiscuous mode as needed. */
 431         if (ifp->if_flags & IFF_PROMISC)
 432                 ctrl |= GX_RXC_UNI_PROMISC;
 433
 434         /* This is required if we want to accept jumbo frames */
 435         if (ifp->if_mtu > ETHERMTU)
 436                 ctrl |= GX_RXC_LONG_PKT_ENABLE;
 437
 438         /* setup receive checksum control */
 439         if (ifp->if_capenable & IFCAP_RXCSUM)
 440                 CSR_WRITE_4(gx, GX_RX_CSUM_CONTROL,
 441                     GX_CSUM_TCP/* | GX_CSUM_IP*/);
 442
 443         /* setup transmit checksum control */
 444         if (ifp->if_capenable & IFCAP_TXCSUM)
 445                 ifp->if_hwassist = GX_CSUM_FEATURES;
 446
 447         ctrl |= GX_RXC_STRIP_ETHERCRC;          /* not on 82542? */
 448         CSR_WRITE_4(gx, GX_RX_CONTROL, ctrl);
 449
 450         /* enable transmitter */
 451         ctrl = GX_TXC_ENABLE | GX_TXC_PAD_SHORT_PKTS | GX_TXC_COLL_RETRY_16;
 452
 453         /* XXX we should support half-duplex here too... */
 454         ctrl |= GX_TXC_COLL_TIME_FDX;
 455
 456         CSR_WRITE_4(gx, GX_TX_CONTROL, ctrl);
 457
 458         /*
 459          * set up recommended IPG times, which vary depending on chip type:
 460          *      IPG transmit time:  80ns
 461          *      IPG receive time 1: 20ns
 462          *      IPG receive time 2: 80ns
 463          */
 464         CSR_WRITE_4(gx, GX_TX_IPG, gx->gx_ipg);
 465
 466         /* set up 802.3x MAC flow control address -- 01:80:c2:00:00:01 */
 467         CSR_WRITE_4(gx, GX_FLOW_CTRL_BASE, 0x00C28001);
 468         CSR_WRITE_4(gx, GX_FLOW_CTRL_BASE+4, 0x00000100);
 469
 470         /* set up 802.3x MAC flow control type -- 88:08 */
 471         CSR_WRITE_4(gx, GX_FLOW_CTRL_TYPE, 0x8808);
 472
 473         /* Set up tuneables */
 474         CSR_WRITE_4(gx, gx->gx_reg.r_rx_delay, gx->gx_rx_intr_delay);
 475         CSR_WRITE_4(gx, gx->gx_reg.r_tx_delay, gx->gx_tx_intr_delay);
 476
 477         /*
 478          * Configure chip for correct operation.
 479          */
 480         ctrl = GX_CTRL_DUPLEX;
 481 #if BYTE_ORDER == BIG_ENDIAN
 482         ctrl |= GX_CTRL_BIGENDIAN;
 483 #endif
 484         ctrl |= GX_CTRL_VLAN_ENABLE;
 485
 486         if (gx->gx_tbimode) {
 487                 /*
 488                  * It seems that TXCW must be initialized from the EEPROM
 489                  * manually.
 490                  *
 491                  * XXX
 492                  * should probably read the eeprom and re-insert the
 493                  * values here.
 494                  */
 495 #define TXCONFIG_WORD   0x000001A0
 496                 CSR_WRITE_4(gx, GX_TX_CONFIG, TXCONFIG_WORD);
 497
 498                 /* turn on hardware autonegotiate */
 499                 GX_SETBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
 500         } else {
 501                 /*
 502                  * Auto-detect speed from PHY, instead of using direct
 503                  * indication.  The SLU bit doesn't force the link, but
 504                  * must be present for ASDE to work.
 505                  */
 506                 gx_phy_reset(gx);
 507                 ctrl |= GX_CTRL_SET_LINK_UP | GX_CTRL_AUTOSPEED;
 508         }
 509
 510         /*
 511          * Take chip out of reset and start it running.
 512          */
 513         CSR_WRITE_4(gx, GX_CTRL, ctrl);
 514
 515         /* Turn interrupts on. */
 516         CSR_WRITE_4(gx, GX_INT_MASK_SET, GX_INT_WANTED);
 517
 518         ifp->if_flags |= IFF_RUNNING;
 519         ifp->if_flags &= ~IFF_OACTIVE;
 520
 521         /*
 522          * Set the current media.
 523          */
 524         if (gx->gx_miibus != NULL) {
 525                 mii_mediachg(device_get_softc(gx->gx_miibus));
 526         } else {
 527                 ifm = &gx->gx_media;
 528                 tmp = ifm->ifm_media;
 529                 ifm->ifm_media = ifm->ifm_cur->ifm_media;
 530                 gx_ifmedia_upd(ifp);
 531                 ifm->ifm_media = tmp;
 532         }
 533
 534         /*
 535          * XXX
 536          * Have the LINK0 flag force the link in TBI mode.
 537          */
 538         if (gx->gx_tbimode && ifp->if_flags & IFF_LINK0) {
 539                 GX_CLRBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
 540                 GX_SETBIT(gx, GX_CTRL, GX_CTRL_SET_LINK_UP);
 541         }
 542
 543 #if 0
 544 kprintf("66mhz: %s  64bit: %s\n",
 545         CSR_READ_4(gx, GX_STATUS) & GX_STAT_PCI66 ? "yes" : "no",
 546         CSR_READ_4(gx, GX_STATUS) & GX_STAT_BUS64 ? "yes" : "no");
 547 #endif
 548 }
 549
 550 /*
 551  * Stop all chip I/O so that the kernel's probe routines don't
 552  * get confused by errant DMAs when rebooting.
 553  */
 554 static void
 555 gx_shutdown(device_t dev)
 556 {
 557         struct gx_softc *gx;
 558
 559         gx = device_get_softc(dev);
 560         gx_reset(gx);
 561         gx_stop(gx);
 562 }
 563
 564 static int
 565 gx_detach(device_t dev)
 566 {
 567         struct gx_softc *gx = device_get_softc(dev);
 568         struct ifnet *ifp = &gx->arpcom.ac_if;
 569
 570         if (device_is_attached(dev)) {
 571                 lwkt_serialize_enter(ifp->if_serializer);
 572                 gx_reset(gx);
 573                 gx_stop(gx);
 574                 bus_teardown_intr(gx->gx_dev, gx->gx_irq, gx->gx_intrhand);
 575                 lwkt_serialize_exit(ifp->if_serializer);
 576
 577                 ether_ifdetach(ifp);
 578         }
 579         if (gx->gx_miibus)
 580                 device_delete_child(gx->gx_dev, gx->gx_miibus);
 581         bus_generic_detach(gx->gx_dev);
 582
 583         if (gx->gx_irq)
 584                 bus_release_resource(gx->gx_dev, SYS_RES_IRQ, 0, gx->gx_irq);
 585         if (gx->gx_res)
 586                 bus_release_resource(gx->gx_dev, SYS_RES_MEMORY,
 587                     GX_PCI_LOMEM, gx->gx_res);
 588
 589         if (gx->gx_rdata)
 590                 contigfree(gx->gx_rdata, sizeof(struct gx_ring_data),
 591                            M_DEVBUF);
 592
 593         if (gx->gx_tbimode)
 594                 ifmedia_removeall(&gx->gx_media);
 595
 596         return (0);
 597 }
 598
 599 static void
 600 gx_eeprom_getword(struct gx_softc *gx, int addr, u_int16_t *dest)
 601 {
 602         u_int16_t word = 0;
 603         u_int32_t base, reg;
 604         int x;
 605
 606         addr = (GX_EE_OPC_READ << GX_EE_ADDR_SIZE) |
 607             (addr & ((1 << GX_EE_ADDR_SIZE) - 1));
 608
 609         base = CSR_READ_4(gx, GX_EEPROM_CTRL);
 610         base &= ~(GX_EE_DATA_OUT | GX_EE_DATA_IN | GX_EE_CLOCK);
 611         base |= GX_EE_SELECT;
 612
 613         CSR_WRITE_4(gx, GX_EEPROM_CTRL, base);
 614
 615         for (x = 1 << ((GX_EE_OPC_SIZE + GX_EE_ADDR_SIZE) - 1); x; x >>= 1) {
 616                 reg = base | (addr & x ? GX_EE_DATA_IN : 0);
 617                 CSR_WRITE_4(gx, GX_EEPROM_CTRL, reg);
 618                 DELAY(10);
 619                 CSR_WRITE_4(gx, GX_EEPROM_CTRL, reg | GX_EE_CLOCK);
 620                 DELAY(10);
 621                 CSR_WRITE_4(gx, GX_EEPROM_CTRL, reg);
 622                 DELAY(10);
 623         }
 624
 625         for (x = 1 << 15; x; x >>= 1) {
 626                 CSR_WRITE_4(gx, GX_EEPROM_CTRL, base | GX_EE_CLOCK);
 627                 DELAY(10);
 628                 reg = CSR_READ_4(gx, GX_EEPROM_CTRL);
 629                 if (reg & GX_EE_DATA_OUT)
 630                         word |= x;
 631                 CSR_WRITE_4(gx, GX_EEPROM_CTRL, base);
 632                 DELAY(10);
 633         }
 634
 635         CSR_WRITE_4(gx, GX_EEPROM_CTRL, base & ~GX_EE_SELECT);
 636         DELAY(10);
 637
 638         *dest = word;
 639 }
 640
 641 static int
 642 gx_read_eeprom(struct gx_softc *gx, caddr_t dest, int off, int cnt)
 643 {
 644         u_int16_t *word;
 645         int i;
 646
 647         word = (u_int16_t *)dest;
 648         for (i = 0; i < cnt; i ++) {
 649                 gx_eeprom_getword(gx, off + i, word);
 650                 word++;
 651         }
 652         return (0);
 653 }
 654
 655 /*
 656  * Set media options.
 657  */
 658 static int
 659 gx_ifmedia_upd(struct ifnet *ifp)
 660 {
 661         struct gx_softc *gx;
 662         struct ifmedia *ifm;
 663         struct mii_data *mii;
 664
 665         gx = ifp->if_softc;
 666
 667         if (gx->gx_tbimode) {
 668                 ifm = &gx->gx_media;
 669                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
 670                         return (EINVAL);
 671                 switch (IFM_SUBTYPE(ifm->ifm_media)) {
 672                 case IFM_AUTO:
 673                         GX_SETBIT(gx, GX_CTRL, GX_CTRL_LINK_RESET);
 674                         GX_SETBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
 675                         GX_CLRBIT(gx, GX_CTRL, GX_CTRL_LINK_RESET);
 676                         break;
 677                 case IFM_1000_SX:
 678                         device_printf(gx->gx_dev,
 679                             "manual config not supported yet.\n");
 680 #if 0
 681                         GX_CLRBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
 682                         config = /* bit symbols for 802.3z */0;
 683                         ctrl |= GX_CTRL_SET_LINK_UP;
 684                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
 685                                 ctrl |= GX_CTRL_DUPLEX;
 686 #endif
 687                         break;
 688                 default:
 689                         return (EINVAL);
 690                 }
 691         } else {
 692                 ifm = &gx->gx_media;
 693
 694                 /*
 695                  * 1000TX half duplex does not work.
 696                  */
 697                 if (IFM_TYPE(ifm->ifm_media) == IFM_ETHER &&
 698                     IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T &&
 699                     (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) == 0)
 700                         return (EINVAL);
 701                 mii = device_get_softc(gx->gx_miibus);
 702                 mii_mediachg(mii);
 703         }
 704         return (0);
 705 }
 706
 707 /*
 708  * Report current media status.
 709  */
 710 static void
 711 gx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 712 {
 713         struct gx_softc *gx;
 714         struct mii_data *mii;
 715         u_int32_t status;
 716
 717         gx = ifp->if_softc;
 718
 719         if (gx->gx_tbimode) {
 720                 ifmr->ifm_status = IFM_AVALID;
 721                 ifmr->ifm_active = IFM_ETHER;
 722
 723                 status = CSR_READ_4(gx, GX_STATUS);
 724                 if ((status & GX_STAT_LINKUP) == 0)
 725                         return;
 726
 727                 ifmr->ifm_status |= IFM_ACTIVE;
 728                 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
 729         } else {
 730                 mii = device_get_softc(gx->gx_miibus);
 731                 mii_pollstat(mii);
 732                 if ((mii->mii_media_active & (IFM_1000_T | IFM_HDX)) ==
 733                     (IFM_1000_T | IFM_HDX))
 734                         mii->mii_media_active = IFM_ETHER | IFM_NONE;
 735                 ifmr->ifm_active = mii->mii_media_active;
 736                 ifmr->ifm_status = mii->mii_media_status;
 737         }
 738 }
 739
 740 static void
 741 gx_mii_shiftin(struct gx_softc *gx, int data, int length)
 742 {
 743         u_int32_t reg, x;
 744
 745         /*
 746          * Set up default GPIO direction + PHY data out.
 747          */
 748         reg = CSR_READ_4(gx, GX_CTRL);
 749         reg &= ~(GX_CTRL_GPIO_DIR_MASK | GX_CTRL_PHY_IO | GX_CTRL_PHY_CLK);
 750         reg |= GX_CTRL_GPIO_DIR | GX_CTRL_PHY_IO_DIR;
 751
 752         /*
 753          * Shift in data to PHY.
 754          */
 755         for (x = 1 << (length - 1); x; x >>= 1) {
 756                 if (data & x)
 757                         reg |= GX_CTRL_PHY_IO;
 758                 else
 759                         reg &= ~GX_CTRL_PHY_IO;
 760                 CSR_WRITE_4(gx, GX_CTRL, reg);
 761                 DELAY(10);
 762                 CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
 763                 DELAY(10);
 764                 CSR_WRITE_4(gx, GX_CTRL, reg);
 765                 DELAY(10);
 766         }
 767 }
 768
 769 static u_int16_t
 770 gx_mii_shiftout(struct gx_softc *gx)
 771 {
 772         u_int32_t reg;
 773         u_int16_t data;
 774         int x;
 775
 776         /*
 777          * Set up default GPIO direction + PHY data in.
 778          */
 779         reg = CSR_READ_4(gx, GX_CTRL);
 780         reg &= ~(GX_CTRL_GPIO_DIR_MASK | GX_CTRL_PHY_IO | GX_CTRL_PHY_CLK);
 781         reg |= GX_CTRL_GPIO_DIR;
 782
 783         CSR_WRITE_4(gx, GX_CTRL, reg);
 784         DELAY(10);
 785         CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
 786         DELAY(10);
 787         CSR_WRITE_4(gx, GX_CTRL, reg);
 788         DELAY(10);
 789         /*
 790          * Shift out data from PHY.
 791          */
 792         data = 0;
 793         for (x = 1 << 15; x; x >>= 1) {
 794                 CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
 795                 DELAY(10);
 796                 if (CSR_READ_4(gx, GX_CTRL) & GX_CTRL_PHY_IO)
 797                         data |= x;
 798                 CSR_WRITE_4(gx, GX_CTRL, reg);
 799                 DELAY(10);
 800         }
 801         CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
 802         DELAY(10);
 803         CSR_WRITE_4(gx, GX_CTRL, reg);
 804         DELAY(10);
 805
 806         return (data);
 807 }
 808
 809 static int
 810 gx_miibus_readreg(device_t dev, int phy, int reg)
 811 {
 812         struct gx_softc *gx;
 813
 814         gx = device_get_softc(dev);
 815         if (gx->gx_tbimode)
 816                 return (0);
 817
 818         /*
 819          * XXX
 820          * Note: Cordova has a MDIC register. livingood and < have mii bits
 821          */
 822
 823         gx_mii_shiftin(gx, GX_PHY_PREAMBLE, GX_PHY_PREAMBLE_LEN);
 824         gx_mii_shiftin(gx, (GX_PHY_SOF << 12) | (GX_PHY_OP_READ << 10) |
 825             (phy << 5) | reg, GX_PHY_READ_LEN);
 826         return (gx_mii_shiftout(gx));
 827 }
 828
 829 static void
 830 gx_miibus_writereg(device_t dev, int phy, int reg, int value)
 831 {
 832         struct gx_softc *gx;
 833
 834         gx = device_get_softc(dev);
 835         if (gx->gx_tbimode)
 836                 return;
 837
 838         gx_mii_shiftin(gx, GX_PHY_PREAMBLE, GX_PHY_PREAMBLE_LEN);
 839         gx_mii_shiftin(gx, (GX_PHY_SOF << 30) | (GX_PHY_OP_WRITE << 28) |
 840             (phy << 23) | (reg << 18) | (GX_PHY_TURNAROUND << 16) |
 841             (value & 0xffff), GX_PHY_WRITE_LEN);
 842 }
 843
 844 static void
 845 gx_miibus_statchg(device_t dev)
 846 {
 847         struct gx_softc *gx = device_get_softc(dev);
 848         struct mii_data *mii;
 849         int reg;
 850
 851         if (gx->gx_tbimode)
 852                 return;
 853
 854         /*
 855          * Set flow control behavior to mirror what PHY negotiated.
 856          */
 857         mii = device_get_softc(gx->gx_miibus);
 858
 859         reg = CSR_READ_4(gx, GX_CTRL);
 860         if (mii->mii_media_active & IFM_FLAG0)
 861                 reg |= GX_CTRL_RX_FLOWCTRL;
 862         else
 863                 reg &= ~GX_CTRL_RX_FLOWCTRL;
 864         if (mii->mii_media_active & IFM_FLAG1)
 865                 reg |= GX_CTRL_TX_FLOWCTRL;
 866         else
 867                 reg &= ~GX_CTRL_TX_FLOWCTRL;
 868         CSR_WRITE_4(gx, GX_CTRL, reg);
 869 }
 870
 871 static int
 872 gx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
 873 {
 874         struct gx_softc *gx = ifp->if_softc;
 875         struct ifreq *ifr = (struct ifreq *)data;
 876         struct mii_data *mii;
 877         int mask, error = 0;
 878
 879         switch (command) {
 880         case SIOCSIFMTU:
 881                 if (ifr->ifr_mtu > GX_MAX_MTU) {
 882                         error = EINVAL;
 883                 } else {
 884                         ifp->if_mtu = ifr->ifr_mtu;
 885                         gx_init(gx);
 886                 }
 887                 break;
 888         case SIOCSIFFLAGS:
 889                 if ((ifp->if_flags & IFF_UP) == 0) {
 890                         gx_stop(gx);
 891                 } else if (ifp->if_flags & IFF_RUNNING &&
 892                     ((ifp->if_flags & IFF_PROMISC) !=
 893                     (gx->gx_if_flags & IFF_PROMISC))) {
 894                         if (ifp->if_flags & IFF_PROMISC)
 895                                 GX_SETBIT(gx, GX_RX_CONTROL, GX_RXC_UNI_PROMISC);
 896                         else
 897                                 GX_CLRBIT(gx, GX_RX_CONTROL, GX_RXC_UNI_PROMISC);
 898                 } else {
 899                         gx_init(gx);
 900                 }
 901                 gx->gx_if_flags = ifp->if_flags;
 902                 break;
 903         case SIOCADDMULTI:
 904         case SIOCDELMULTI:
 905                 if (ifp->if_flags & IFF_RUNNING)
 906                         gx_setmulti(gx);
 907                 break;
 908         case SIOCSIFMEDIA:
 909         case SIOCGIFMEDIA:
 910                 if (gx->gx_miibus != NULL) {
 911                         mii = device_get_softc(gx->gx_miibus);
 912                         error = ifmedia_ioctl(ifp, ifr,
 913                             &mii->mii_media, command);
 914                 } else {
 915                         error = ifmedia_ioctl(ifp, ifr, &gx->gx_media, command);
 916                 }
 917                 break;
 918         case SIOCSIFCAP:
 919                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 920                 if (mask & IFCAP_HWCSUM) {
 921                         if (IFCAP_HWCSUM & ifp->if_capenable)
 922                                 ifp->if_capenable &= ~IFCAP_HWCSUM;
 923                         else
 924                                 ifp->if_capenable |= IFCAP_HWCSUM;
 925                         if (ifp->if_flags & IFF_RUNNING)
 926                                 gx_init(gx);
 927                 }
 928                 break;
 929         default:
 930                 error = ether_ioctl(ifp, command, data);
 931                 break;
 932         }
 933         return (error);
 934 }
 935
 936 static void
 937 gx_phy_reset(struct gx_softc *gx)
 938 {
 939         int reg;
 940
 941         GX_SETBIT(gx, GX_CTRL, GX_CTRL_SET_LINK_UP);
 942
 943         /*
 944          * PHY reset is active low.
 945          */
 946         reg = CSR_READ_4(gx, GX_CTRL_EXT);
 947         reg &= ~(GX_CTRLX_GPIO_DIR_MASK | GX_CTRLX_PHY_RESET);
 948         reg |= GX_CTRLX_GPIO_DIR;
 949
 950         CSR_WRITE_4(gx, GX_CTRL_EXT, reg | GX_CTRLX_PHY_RESET);
 951         DELAY(10);
 952         CSR_WRITE_4(gx, GX_CTRL_EXT, reg);
 953         DELAY(10);
 954         CSR_WRITE_4(gx, GX_CTRL_EXT, reg | GX_CTRLX_PHY_RESET);
 955         DELAY(10);
 956
 957 #if 0
 958         /* post-livingood (cordova) only */
 959                 GX_SETBIT(gx, GX_CTRL, 0x80000000);
 960                 DELAY(1000);
 961                 GX_CLRBIT(gx, GX_CTRL, 0x80000000);
 962 #endif
 963 }
 964
 965 static void
 966 gx_reset(struct gx_softc *gx)
 967 {
 968
 969         /* Disable host interrupts. */
 970         CSR_WRITE_4(gx, GX_INT_MASK_CLR, GX_INT_ALL);
 971
 972         /* reset chip (THWAP!) */
 973         GX_SETBIT(gx, GX_CTRL, GX_CTRL_DEVICE_RESET);
 974         DELAY(10);
 975 }
 976
 977 static void
 978 gx_stop(struct gx_softc *gx)
 979 {
 980         struct ifnet *ifp;
 981
 982         ifp = &gx->arpcom.ac_if;
 983
 984         /* reset and flush transmitter */
 985         CSR_WRITE_4(gx, GX_TX_CONTROL, GX_TXC_RESET);
 986
 987         /* reset and flush receiver */
 988         CSR_WRITE_4(gx, GX_RX_CONTROL, GX_RXC_RESET);
 989
 990         /* reset link */
 991         if (gx->gx_tbimode)
 992                 GX_SETBIT(gx, GX_CTRL, GX_CTRL_LINK_RESET);
 993
 994         /* Free the RX lists. */
 995         gx_free_rx_ring(gx);
 996
 997         /* Free TX buffers. */
 998         gx_free_tx_ring(gx);
 999
1000         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1001 }
1002
1003 static void
1004 gx_watchdog(struct ifnet *ifp)
1005 {
1006         struct gx_softc *gx;
1007
1008         gx = ifp->if_softc;
1009
1010         device_printf(gx->gx_dev, "watchdog timeout -- resetting\n");
1011         gx_reset(gx);
1012         gx_init(gx);
1013
1014         ifp->if_oerrors++;
1015 }
1016
1017 /*
1018  * Intialize a receive ring descriptor.
1019  */
1020 static int
1021 gx_newbuf(struct gx_softc *gx, int idx, struct mbuf *m)
1022 {
1023         struct mbuf *m_new = NULL;
1024         struct gx_rx_desc *r;
1025
1026         if (m == NULL) {
1027                 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1028                 if (m_new == NULL) {
1029                         device_printf(gx->gx_dev,
1030                             "mbuf allocation failed -- packet dropped\n");
1031                         return (ENOBUFS);
1032                 }
1033                 MCLGET(m_new, MB_DONTWAIT);
1034                 if ((m_new->m_flags & M_EXT) == 0) {
1035                         device_printf(gx->gx_dev,
1036                             "cluster allocation failed -- packet dropped\n");
1037                         m_freem(m_new);
1038                         return (ENOBUFS);
1039                 }
1040                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1041         } else {
1042                 m->m_len = m->m_pkthdr.len = MCLBYTES;
1043                 m->m_data = m->m_ext.ext_buf;
1044                 m->m_next = NULL;
1045                 m_new = m;
1046         }
1047
1048         /*
1049          * XXX
1050          * this will _NOT_ work for large MTU's; it will overwrite
1051          * the end of the buffer.  E.g.: take this out for jumbograms,
1052          * but then that breaks alignment.
1053          */
1054         if (gx->arpcom.ac_if.if_mtu <= ETHERMTU)
1055                 m_adj(m_new, ETHER_ALIGN);
1056
1057         gx->gx_cdata.gx_rx_chain[idx] = m_new;
1058         r = &gx->gx_rdata->gx_rx_ring[idx];
1059         r->rx_addr = vtophys(mtod(m_new, caddr_t));
1060         r->rx_staterr = 0;
1061
1062         return (0);
1063 }
1064
1065 /*
1066  * The receive ring can have up to 64K descriptors, which at 2K per mbuf
1067  * cluster, could add up to 128M of memory.  Due to alignment constraints,
1068  * the number of descriptors must be a multiple of 8.  For now, we
1069  * allocate 256 entries and hope that our CPU is fast enough to keep up
1070  * with the NIC.
1071  */
1072 static int
1073 gx_init_rx_ring(struct gx_softc *gx)
1074 {
1075         int i, error;
1076
1077         for (i = 0; i < GX_RX_RING_CNT; i++) {
1078                 error = gx_newbuf(gx, i, NULL);
1079                 if (error)
1080                         return (error);
1081         }
1082
1083         /* bring receiver out of reset state, leave disabled */
1084         CSR_WRITE_4(gx, GX_RX_CONTROL, 0);
1085
1086         /* set up ring registers */
1087         CSR_WRITE_8(gx, gx->gx_reg.r_rx_base,
1088             (u_quad_t)vtophys(gx->gx_rdata->gx_rx_ring));
1089
1090         CSR_WRITE_4(gx, gx->gx_reg.r_rx_length,
1091             GX_RX_RING_CNT * sizeof(struct gx_rx_desc));
1092         CSR_WRITE_4(gx, gx->gx_reg.r_rx_head, 0);
1093         CSR_WRITE_4(gx, gx->gx_reg.r_rx_tail, GX_RX_RING_CNT - 1);
1094         gx->gx_rx_tail_idx = 0;
1095
1096         return (0);
1097 }
1098
1099 static void
1100 gx_free_rx_ring(struct gx_softc *gx)
1101 {
1102         struct mbuf **mp;
1103         int i;
1104
1105         mp = gx->gx_cdata.gx_rx_chain;
1106         for (i = 0; i < GX_RX_RING_CNT; i++, mp++) {
1107                 if (*mp != NULL) {
1108                         m_freem(*mp);
1109                         *mp = NULL;
1110                 }
1111         }
1112         bzero((void *)gx->gx_rdata->gx_rx_ring,
1113             GX_RX_RING_CNT * sizeof(struct gx_rx_desc));
1114
1115         /* release any partially-received packet chain */
1116         if (gx->gx_pkthdr != NULL) {
1117                 m_freem(gx->gx_pkthdr);
1118                 gx->gx_pkthdr = NULL;
1119         }
1120 }
1121
1122 static int
1123 gx_init_tx_ring(struct gx_softc *gx)
1124 {
1125
1126         /* bring transmitter out of reset state, leave disabled */
1127         CSR_WRITE_4(gx, GX_TX_CONTROL, 0);
1128
1129         /* set up ring registers */
1130         CSR_WRITE_8(gx, gx->gx_reg.r_tx_base,
1131             (u_quad_t)vtophys(gx->gx_rdata->gx_tx_ring));
1132         CSR_WRITE_4(gx, gx->gx_reg.r_tx_length,
1133             GX_TX_RING_CNT * sizeof(struct gx_tx_desc));
1134         CSR_WRITE_4(gx, gx->gx_reg.r_tx_head, 0);
1135         CSR_WRITE_4(gx, gx->gx_reg.r_tx_tail, 0);
1136         gx->gx_tx_head_idx = 0;
1137         gx->gx_tx_tail_idx = 0;
1138         gx->gx_txcnt = 0;
1139
1140         /* set up initial TX context */
1141         gx->gx_txcontext = GX_TXCONTEXT_NONE;
1142
1143         return (0);
1144 }
1145
1146 static void
1147 gx_free_tx_ring(struct gx_softc *gx)
1148 {
1149         struct mbuf **mp;
1150         int i;
1151
1152         mp = gx->gx_cdata.gx_tx_chain;
1153         for (i = 0; i < GX_TX_RING_CNT; i++, mp++) {
1154                 if (*mp != NULL) {
1155                         m_freem(*mp);
1156                         *mp = NULL;
1157                 }
1158         }
1159         bzero((void *)&gx->gx_rdata->gx_tx_ring,
1160             GX_TX_RING_CNT * sizeof(struct gx_tx_desc));
1161 }
1162
1163 static void
1164 gx_setmulti(struct gx_softc *gx)
1165 {
1166         int i;
1167
1168         /* wipe out the multicast table */
1169         for (i = 1; i < 128; i++)
1170                 CSR_WRITE_4(gx, GX_MULTICAST_BASE + i * 4, 0);
1171 }
1172
1173 static void
1174 gx_rxeof(struct gx_softc *gx)
1175 {
1176         struct gx_rx_desc *rx;
1177         struct ifnet *ifp;
1178         int idx, staterr, len;
1179         struct mbuf *m;
1180
1181         gx->gx_rx_interrupts++;
1182
1183         ifp = &gx->arpcom.ac_if;
1184         idx = gx->gx_rx_tail_idx;
1185
1186         while (gx->gx_rdata->gx_rx_ring[idx].rx_staterr & GX_RXSTAT_COMPLETED) {
1187
1188                 rx = &gx->gx_rdata->gx_rx_ring[idx];
1189                 m = gx->gx_cdata.gx_rx_chain[idx];
1190                 /*
1191                  * gx_newbuf overwrites status and length bits, so we
1192                  * make a copy of them here.
1193                  */
1194                 len = rx->rx_len;
1195                 staterr = rx->rx_staterr;
1196
1197                 if (staterr & GX_INPUT_ERROR)
1198                         goto ierror;
1199
1200                 if (gx_newbuf(gx, idx, NULL) == ENOBUFS)
1201                         goto ierror;
1202
1203                 GX_INC(idx, GX_RX_RING_CNT);
1204
1205                 if (staterr & GX_RXSTAT_INEXACT_MATCH) {
1206                         /*
1207                          * multicast packet, must verify against
1208                          * multicast address.
1209                          */
1210                 }
1211
1212                 if ((staterr & GX_RXSTAT_END_OF_PACKET) == 0) {
1213                         if (gx->gx_pkthdr == NULL) {
1214                                 m->m_len = len;
1215                                 m->m_pkthdr.len = len;
1216                                 gx->gx_pkthdr = m;
1217                                 gx->gx_pktnextp = &m->m_next;
1218                         } else {
1219                                 m->m_len = len;
1220                                 gx->gx_pkthdr->m_pkthdr.len += len;
1221                                 *(gx->gx_pktnextp) = m;
1222                                 gx->gx_pktnextp = &m->m_next;
1223                         }
1224                         continue;
1225                 }
1226
1227                 if (gx->gx_pkthdr == NULL) {
1228                         m->m_len = len;
1229                         m->m_pkthdr.len = len;
1230                 } else {
1231                         m->m_len = len;
1232                         gx->gx_pkthdr->m_pkthdr.len += len;
1233                         *(gx->gx_pktnextp) = m;
1234                         m = gx->gx_pkthdr;
1235                         gx->gx_pkthdr = NULL;
1236                 }
1237
1238                 ifp->if_ipackets++;
1239                 m->m_pkthdr.rcvif = ifp;
1240
1241 #define IP_CSMASK       (GX_RXSTAT_IGNORE_CSUM | GX_RXSTAT_HAS_IP_CSUM)
1242 #define TCP_CSMASK \
1243     (GX_RXSTAT_IGNORE_CSUM | GX_RXSTAT_HAS_TCP_CSUM | GX_RXERR_TCP_CSUM)
1244                 if (ifp->if_capenable & IFCAP_RXCSUM) {
1245 #if 0
1246                         /*
1247                          * Intel Erratum #23 indicates that the Receive IP
1248                          * Checksum offload feature has been completely
1249                          * disabled.
1250                          */
1251                         if ((staterr & IP_CSUM_MASK) == GX_RXSTAT_HAS_IP_CSUM) {
1252                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1253                                 if ((staterr & GX_RXERR_IP_CSUM) == 0)
1254                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1255                         }
1256 #endif
1257                         if ((staterr & TCP_CSMASK) == GX_RXSTAT_HAS_TCP_CSUM) {
1258                                 m->m_pkthdr.csum_flags |=
1259                                     CSUM_DATA_VALID | CSUM_PSEUDO_HDR |
1260                                     CSUM_FRAG_NOT_CHECKED;
1261                                 m->m_pkthdr.csum_data = 0xffff;
1262                         }
1263                 }
1264                 /*
1265                  * If we received a packet with a vlan tag, pass it
1266                  * to vlan_input() instead of ether_input().
1267                  */
1268                 if (staterr & GX_RXSTAT_VLAN_PKT)
1269                         VLAN_INPUT_TAG(m, rx->rx_special);
1270                 else
1271                         ifp->if_input(ifp, m);
1272                 continue;
1273
1274   ierror:
1275                 ifp->if_ierrors++;
1276                 gx_newbuf(gx, idx, m);
1277
1278                 /*
1279                  * XXX
1280                  * this isn't quite right.  Suppose we have a packet that
1281                  * spans 5 descriptors (9K split into 2K buffers).  If
1282                  * the 3rd descriptor sets an error, we need to ignore
1283                  * the last two.  The way things stand now, the last two
1284                  * will be accepted as a single packet.
1285                  *
1286                  * we don't worry about this -- the chip may not set an
1287                  * error in this case, and the checksum of the upper layers
1288                  * will catch the error.
1289                  */
1290                 if (gx->gx_pkthdr != NULL) {
1291                         m_freem(gx->gx_pkthdr);
1292                         gx->gx_pkthdr = NULL;
1293                 }
1294                 GX_INC(idx, GX_RX_RING_CNT);
1295         }
1296
1297         gx->gx_rx_tail_idx = idx;
1298         if (--idx < 0)
1299                 idx = GX_RX_RING_CNT - 1;
1300         CSR_WRITE_4(gx, gx->gx_reg.r_rx_tail, idx);
1301 }
1302
1303 static void
1304 gx_txeof(struct gx_softc *gx)
1305 {
1306         struct ifnet *ifp;
1307         int idx, cnt;
1308
1309         gx->gx_tx_interrupts++;
1310
1311         ifp = &gx->arpcom.ac_if;
1312         idx = gx->gx_tx_head_idx;
1313         cnt = gx->gx_txcnt;
1314
1315         /*
1316          * If the system chipset performs I/O write buffering, it is
1317          * possible for the PIO read of the head descriptor to bypass the
1318          * memory write of the descriptor, resulting in reading a descriptor
1319          * which has not been updated yet.
1320          */
1321         while (cnt) {
1322                 struct gx_tx_desc_old *tx;
1323
1324                 tx = (struct gx_tx_desc_old *)&gx->gx_rdata->gx_tx_ring[idx];
1325                 cnt--;
1326
1327                 if ((tx->tx_command & GX_TXOLD_END_OF_PKT) == 0) {
1328                         GX_INC(idx, GX_TX_RING_CNT);
1329                         continue;
1330                 }
1331
1332                 if ((tx->tx_status & GX_TXSTAT_DONE) == 0)
1333                         break;
1334
1335                 ifp->if_opackets++;
1336
1337                 m_freem(gx->gx_cdata.gx_tx_chain[idx]);
1338                 gx->gx_cdata.gx_tx_chain[idx] = NULL;
1339                 gx->gx_txcnt = cnt;
1340                 ifp->if_timer = 0;
1341
1342                 GX_INC(idx, GX_TX_RING_CNT);
1343                 gx->gx_tx_head_idx = idx;
1344         }
1345
1346         if (gx->gx_txcnt == 0)
1347                 ifp->if_flags &= ~IFF_OACTIVE;
1348 }
1349
1350 static void
1351 gx_intr(void *xsc)
1352 {
1353         struct gx_softc *gx = xsc;
1354         struct ifnet *ifp = &gx->arpcom.ac_if;
1355         u_int32_t intr;
1356
1357         gx->gx_interrupts++;
1358
1359         /* Disable host interrupts. */
1360         CSR_WRITE_4(gx, GX_INT_MASK_CLR, GX_INT_ALL);
1361
1362         /*
1363          * find out why we're being bothered.
1364          * reading this register automatically clears all bits.
1365          */
1366         intr = CSR_READ_4(gx, GX_INT_READ);
1367
1368         /* Check RX return ring producer/consumer */
1369         if (intr & (GX_INT_RCV_TIMER | GX_INT_RCV_THOLD | GX_INT_RCV_OVERRUN))
1370                 gx_rxeof(gx);
1371
1372         /* Check TX ring producer/consumer */
1373         if (intr & (GX_INT_XMIT_DONE | GX_INT_XMIT_EMPTY))
1374                 gx_txeof(gx);
1375
1376         /*
1377          * handle other interrupts here.
1378          */
1379
1380         /*
1381          * Link change interrupts are not reliable; the interrupt may
1382          * not be generated if the link is lost.  However, the register
1383          * read is reliable, so check that.  Use SEQ errors to possibly
1384          * indicate that the link has changed.
1385          */
1386         if (intr & GX_INT_LINK_CHANGE) {
1387                 if ((CSR_READ_4(gx, GX_STATUS) & GX_STAT_LINKUP) == 0) {
1388                         device_printf(gx->gx_dev, "link down\n");
1389                 } else {
1390                         device_printf(gx->gx_dev, "link up\n");
1391                 }
1392         }
1393
1394         /* Turn interrupts on. */
1395         CSR_WRITE_4(gx, GX_INT_MASK_SET, GX_INT_WANTED);
1396
1397         if (ifp->if_flags & IFF_RUNNING && !ifq_is_empty(&ifp->if_snd))
1398                 gx_start(ifp);
1399 }
1400
1401 /*
1402  * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
1403  * pointers to descriptors.
1404  */
1405 static int
1406 gx_encap(struct gx_softc *gx, struct mbuf *m_head)
1407 {
1408         struct gx_tx_desc_data *tx = NULL;
1409         struct gx_tx_desc_ctx *tctx;
1410         struct mbuf *m;
1411         int idx, cnt, csumopts, txcontext;
1412         struct ifvlan *ifv = NULL;
1413
1414         if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1415             m_head->m_pkthdr.rcvif != NULL &&
1416             m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
1417                 ifv = m_head->m_pkthdr.rcvif->if_softc;
1418
1419         cnt = gx->gx_txcnt;
1420         idx = gx->gx_tx_tail_idx;
1421         txcontext = gx->gx_txcontext;
1422
1423         /*
1424          * Insure we have at least 4 descriptors pre-allocated.
1425          */
1426         if (cnt >= GX_TX_RING_CNT - 4)
1427                 return (ENOBUFS);
1428
1429         /*
1430          * Set up the appropriate offload context if necessary.
1431          */
1432         csumopts = 0;
1433         if (m_head->m_pkthdr.csum_flags) {
1434                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1435                         csumopts |= GX_TXTCP_OPT_IP_CSUM;
1436                 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) {
1437                         csumopts |= GX_TXTCP_OPT_TCP_CSUM;
1438                         txcontext = GX_TXCONTEXT_TCPIP;
1439                 } else if (m_head->m_pkthdr.csum_flags & CSUM_UDP) {
1440                         csumopts |= GX_TXTCP_OPT_TCP_CSUM;
1441                         txcontext = GX_TXCONTEXT_UDPIP;
1442                 } else if (txcontext == GX_TXCONTEXT_NONE)
1443                         txcontext = GX_TXCONTEXT_TCPIP;
1444                 if (txcontext == gx->gx_txcontext)
1445                         goto context_done;
1446
1447                 tctx = (struct gx_tx_desc_ctx *)&gx->gx_rdata->gx_tx_ring[idx];
1448                 tctx->tx_ip_csum_start = ETHER_HDR_LEN;
1449                 tctx->tx_ip_csum_end = ETHER_HDR_LEN + sizeof(struct ip) - 1;
1450                 tctx->tx_ip_csum_offset =
1451                     ETHER_HDR_LEN + offsetof(struct ip, ip_sum);
1452                 tctx->tx_tcp_csum_start = ETHER_HDR_LEN + sizeof(struct ip);
1453                 tctx->tx_tcp_csum_end = 0;
1454                 if (txcontext == GX_TXCONTEXT_TCPIP)
1455                         tctx->tx_tcp_csum_offset = ETHER_HDR_LEN +
1456                             sizeof(struct ip) + offsetof(struct tcphdr, th_sum);
1457                 else
1458                         tctx->tx_tcp_csum_offset = ETHER_HDR_LEN +
1459                             sizeof(struct ip) + offsetof(struct udphdr, uh_sum);
1460                 tctx->tx_command = GX_TXCTX_EXTENSION | GX_TXCTX_INT_DELAY;
1461                 tctx->tx_type = 0;
1462                 tctx->tx_status = 0;
1463                 GX_INC(idx, GX_TX_RING_CNT);
1464                 cnt++;
1465         }
1466 context_done:
1467
1468         /*
1469          * Start packing the mbufs in this chain into the transmit
1470          * descriptors.  Stop when we run out of descriptors or hit
1471          * the end of the mbuf chain.
1472          */
1473         for (m = m_head; m != NULL; m = m->m_next) {
1474                 if (m->m_len == 0)
1475                         continue;
1476
1477                 if (cnt == GX_TX_RING_CNT) {
1478 kprintf("overflow(2): %d, %d\n", cnt, GX_TX_RING_CNT);
1479                         return (ENOBUFS);
1480 }
1481
1482                 tx = (struct gx_tx_desc_data *)&gx->gx_rdata->gx_tx_ring[idx];
1483                 tx->tx_addr = vtophys(mtod(m, vm_offset_t));
1484                 tx->tx_status = 0;
1485                 tx->tx_len = m->m_len;
1486                 if (gx->arpcom.ac_if.if_hwassist) {
1487                         tx->tx_type = 1;
1488                         tx->tx_command = GX_TXTCP_EXTENSION;
1489                         tx->tx_options = csumopts;
1490                 } else {
1491                         /*
1492                          * This is really a struct gx_tx_desc_old.
1493                          */
1494                         tx->tx_command = 0;
1495                 }
1496                 GX_INC(idx, GX_TX_RING_CNT);
1497                 cnt++;
1498         }
1499
1500         if (tx != NULL) {
1501                 tx->tx_command |= GX_TXTCP_REPORT_STATUS | GX_TXTCP_INT_DELAY |
1502                     GX_TXTCP_ETHER_CRC | GX_TXTCP_END_OF_PKT;
1503                 if (ifv != NULL) {
1504                         tx->tx_command |= GX_TXTCP_VLAN_ENABLE;
1505                         tx->tx_vlan = ifv->ifv_tag;
1506                 }
1507                 gx->gx_txcnt = cnt;
1508                 gx->gx_tx_tail_idx = idx;
1509                 gx->gx_txcontext = txcontext;
1510                 idx = GX_PREV(idx, GX_TX_RING_CNT);
1511                 gx->gx_cdata.gx_tx_chain[idx] = m_head;
1512
1513                 CSR_WRITE_4(gx, gx->gx_reg.r_tx_tail, gx->gx_tx_tail_idx);
1514         }
1515
1516         return (0);
1517 }
1518
1519 /*
1520  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1521  * to the mbuf data regions directly in the transmit descriptors.
1522  */
1523 static void
1524 gx_start(struct ifnet *ifp)
1525 {
1526         struct gx_softc *gx = ifp->if_softc;
1527         struct mbuf *m_head;
1528
1529         for (;;) {
1530                 m_head = ifq_poll(&ifp->if_snd);
1531                 if (m_head == NULL)
1532                         break;
1533
1534                 /*
1535                  * Pack the data into the transmit ring. If we
1536                  * don't have room, set the OACTIVE flag and wait
1537                  * for the NIC to drain the ring.
1538                  */
1539                 if (gx_encap(gx, m_head) != 0) {
1540                         ifp->if_flags |= IFF_OACTIVE;
1541                         break;
1542                 }
1543                 ifq_dequeue(&ifp->if_snd, m_head);
1544
1545                 BPF_MTAP(ifp, m_head);
1546
1547                 /*
1548                  * Set a timeout in case the chip goes out to lunch.
1549                  */
1550                 ifp->if_timer = 5;
1551         }
1552 }