1 Verilog-mode.el is a Verilog mode for Emacs which provides context-sensitive
2 highlighting, auto indenting, and provides macro expansion capabilities to
3 greatly reduce Verilog coding time.
5 Recent versions allow you to insert AUTOS in non-AUTO designs, so IP
6 interconnect can be easily modified. You can also expand Verilog-2001 ".*"
7 instantiations, to see what ports will be connected by simulators.
9 WWW: https://www.veripool.org/wiki/verilog-mode