kernel/bwi: Fix a wrong conversion to the automatic sysctx ctx/tree setup.
[dragonfly.git] / sys / dev / netif / bwi / if_bwi.c
CommitLineData
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1/*
2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
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33 */
34
35#include <sys/param.h>
b5b6e4f4 36#include <sys/bitops.h>
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37#include <sys/endian.h>
38#include <sys/kernel.h>
39#include <sys/bus.h>
9db4b353 40#include <sys/interrupt.h>
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41#include <sys/malloc.h>
42#include <sys/proc.h>
43#include <sys/rman.h>
44#include <sys/serialize.h>
45#include <sys/socket.h>
46#include <sys/sockio.h>
47#include <sys/sysctl.h>
48
49#include <net/ethernet.h>
50#include <net/if.h>
51#include <net/bpf.h>
52#include <net/if_arp.h>
53#include <net/if_dl.h>
54#include <net/if_media.h>
55#include <net/ifq_var.h>
56
ab411d47 57#include <netproto/802_11/ieee80211_radiotap.h>
5f9672cd 58#include <netproto/802_11/ieee80211_var.h>
21028056 59#include <netproto/802_11/wlan_ratectl/onoe/ieee80211_onoe_param.h>
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60
61#include <bus/pci/pcireg.h>
62#include <bus/pci/pcivar.h>
dcb4b80d 63#include "pcidevs.h"
5f9672cd 64
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65#include <dev/netif/bwi/if_bwireg.h>
66#include <dev/netif/bwi/if_bwivar.h>
67#include <dev/netif/bwi/bwimac.h>
68#include <dev/netif/bwi/bwirf.h>
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69
70struct bwi_clock_freq {
71 u_int clkfreq_min;
72 u_int clkfreq_max;
73};
74
75struct bwi_myaddr_bssid {
76 uint8_t myaddr[IEEE80211_ADDR_LEN];
77 uint8_t bssid[IEEE80211_ADDR_LEN];
78} __packed;
79
80static int bwi_probe(device_t);
81static int bwi_attach(device_t);
82static int bwi_detach(device_t);
83static int bwi_shutdown(device_t);
84
85static void bwi_init(void *);
86static int bwi_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
f0a26983 87static void bwi_start(struct ifnet *, struct ifaltq_subque *);
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88static void bwi_watchdog(struct ifnet *);
89static int bwi_newstate(struct ieee80211com *, enum ieee80211_state, int);
90static void bwi_updateslot(struct ifnet *);
91static int bwi_media_change(struct ifnet *);
21028056 92static void *bwi_ratectl_attach(struct ieee80211com *, u_int);
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93
94static void bwi_next_scan(void *);
95static void bwi_calibrate(void *);
96
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97static void bwi_newstate_begin(struct bwi_softc *, enum ieee80211_state);
98static void bwi_init_statechg(struct bwi_softc *, int);
99static int bwi_stop(struct bwi_softc *, int);
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100static int bwi_newbuf(struct bwi_softc *, int, int);
101static int bwi_encap(struct bwi_softc *, int, struct mbuf *,
cf414c9b 102 struct ieee80211_node **, int);
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103
104static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t,
105 bus_addr_t, int, int);
106static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t);
107
108static int bwi_init_tx_ring32(struct bwi_softc *, int);
109static int bwi_init_rx_ring32(struct bwi_softc *);
110static int bwi_init_txstats32(struct bwi_softc *);
111static void bwi_free_tx_ring32(struct bwi_softc *, int);
112static void bwi_free_rx_ring32(struct bwi_softc *);
113static void bwi_free_txstats32(struct bwi_softc *);
114static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int);
115static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *,
116 int, bus_addr_t, int);
da367f92 117static int bwi_rxeof32(struct bwi_softc *);
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118static void bwi_start_tx32(struct bwi_softc *, uint32_t, int);
119static void bwi_txeof_status32(struct bwi_softc *);
120
121static int bwi_init_tx_ring64(struct bwi_softc *, int);
122static int bwi_init_rx_ring64(struct bwi_softc *);
123static int bwi_init_txstats64(struct bwi_softc *);
124static void bwi_free_tx_ring64(struct bwi_softc *, int);
125static void bwi_free_rx_ring64(struct bwi_softc *);
126static void bwi_free_txstats64(struct bwi_softc *);
127static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int);
128static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *,
129 int, bus_addr_t, int);
da367f92 130static int bwi_rxeof64(struct bwi_softc *);
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131static void bwi_start_tx64(struct bwi_softc *, uint32_t, int);
132static void bwi_txeof_status64(struct bwi_softc *);
133
134static void bwi_intr(void *);
da367f92 135static int bwi_rxeof(struct bwi_softc *, int);
05277c82 136static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int);
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137static void bwi_txeof(struct bwi_softc *);
138static void bwi_txeof_status(struct bwi_softc *, int);
139static void bwi_enable_intrs(struct bwi_softc *, uint32_t);
140static void bwi_disable_intrs(struct bwi_softc *, uint32_t);
641ea785 141static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *);
ab411d47 142static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *,
da367f92 143 struct bwi_rxbuf_hdr *, const void *, int, int);
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144
145static int bwi_dma_alloc(struct bwi_softc *);
146static void bwi_dma_free(struct bwi_softc *);
147static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t,
148 struct bwi_ring_data *, bus_size_t,
149 uint32_t);
150static int bwi_dma_mbuf_create(struct bwi_softc *);
151static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int);
152static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t);
153static void bwi_dma_txstats_free(struct bwi_softc *);
154static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
155static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int,
156 bus_size_t, int);
157
158static void bwi_power_on(struct bwi_softc *, int);
159static int bwi_power_off(struct bwi_softc *, int);
160static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode);
161static int bwi_set_clock_delay(struct bwi_softc *);
162static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *);
163static int bwi_get_pwron_delay(struct bwi_softc *sc);
164static void bwi_set_addr_filter(struct bwi_softc *, uint16_t,
165 const uint8_t *);
166static void bwi_set_bssid(struct bwi_softc *, const uint8_t *);
167static int bwi_set_chan(struct bwi_softc *, struct ieee80211_channel *);
168
169static void bwi_get_card_flags(struct bwi_softc *);
170static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *);
171
172static int bwi_bus_attach(struct bwi_softc *);
173static int bwi_bbp_attach(struct bwi_softc *);
174static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode);
175static void bwi_bbp_power_off(struct bwi_softc *);
176
177static const char *bwi_regwin_name(const struct bwi_regwin *);
178static uint32_t bwi_regwin_disable_bits(struct bwi_softc *);
179static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *);
180static int bwi_regwin_select(struct bwi_softc *, int);
181
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182static void bwi_led_attach(struct bwi_softc *);
183static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state);
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184static void bwi_led_event(struct bwi_softc *, int);
185static void bwi_led_blink_start(struct bwi_softc *, int, int);
186static void bwi_led_blink_next(void *);
187static void bwi_led_blink_end(void *);
777ee4a9 188
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189static const struct bwi_dev {
190 uint16_t vid;
191 uint16_t did;
192 const char *desc;
193} bwi_devices[] = {
194 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4301,
195 "Broadcom BCM4301 802.11 Wireless Lan" },
196
197 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4307,
198 "Broadcom BCM4307 802.11 Wireless Lan" },
199
200 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4311,
201 "Broadcom BCM4311 802.11 Wireless Lan" },
202
203 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4312,
204 "Broadcom BCM4312 802.11 Wireless Lan" },
205
206 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_1,
207 "Broadcom BCM4306 802.11 Wireless Lan" },
208
209 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_2,
210 "Broadcom BCM4306 802.11 Wireless Lan" },
211
212 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_3,
213 "Broadcom BCM4306 802.11 Wireless Lan" },
214
215 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4309,
216 "Broadcom BCM4309 802.11 Wireless Lan" },
217
218 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4318,
219 "Broadcom BCM4318 802.11 Wireless Lan" },
220
221 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4319,
222 "Broadcom BCM4319 802.11 Wireless Lan" }
223};
224
225static device_method_t bwi_methods[] = {
226 DEVMETHOD(device_probe, bwi_probe),
227 DEVMETHOD(device_attach, bwi_attach),
228 DEVMETHOD(device_detach, bwi_detach),
229 DEVMETHOD(device_shutdown, bwi_shutdown),
230#if 0
231 DEVMETHOD(device_suspend, bwi_suspend),
232 DEVMETHOD(device_resume, bwi_resume),
233#endif
d3c9c58e 234 DEVMETHOD_END
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235};
236
237static driver_t bwi_driver = {
238 "bwi",
239 bwi_methods,
240 sizeof(struct bwi_softc)
241};
242
243static devclass_t bwi_devclass;
244
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245DRIVER_MODULE(bwi, pci, bwi_driver, bwi_devclass, NULL, NULL);
246DRIVER_MODULE(bwi, cardbus, bwi_driver, bwi_devclass, NULL, NULL);
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247
248MODULE_DEPEND(bwi, wlan, 1, 1, 1);
5f9672cd 249MODULE_DEPEND(bwi, wlan_ratectl_onoe, 1, 1, 1);
92285ca6 250#if 0
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251MODULE_DEPEND(bwi, wlan_ratectl_amrr, 1, 1, 1);
252#endif
253MODULE_DEPEND(bwi, pci, 1, 1, 1);
254MODULE_DEPEND(bwi, cardbus, 1, 1, 1);
255
256static const struct {
257 uint16_t did_min;
258 uint16_t did_max;
259 uint16_t bbp_id;
260} bwi_bbpid_map[] = {
261 { 0x4301, 0x4301, 0x4301 },
262 { 0x4305, 0x4307, 0x4307 },
263 { 0x4403, 0x4403, 0x4402 },
264 { 0x4610, 0x4615, 0x4610 },
265 { 0x4710, 0x4715, 0x4710 },
266 { 0x4720, 0x4725, 0x4309 }
267};
268
269static const struct {
270 uint16_t bbp_id;
271 int nregwin;
272} bwi_regwin_count[] = {
273 { 0x4301, 5 },
274 { 0x4306, 6 },
275 { 0x4307, 5 },
276 { 0x4310, 8 },
277 { 0x4401, 3 },
278 { 0x4402, 3 },
279 { 0x4610, 9 },
280 { 0x4704, 9 },
281 { 0x4710, 9 },
282 { 0x5365, 7 }
283};
284
285#define CLKSRC(src) \
286[BWI_CLKSRC_ ## src] = { \
287 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \
288 .freq_max = BWI_CLKSRC_ ##src## _FMAX \
289}
290
291static const struct {
292 u_int freq_min;
293 u_int freq_max;
294} bwi_clkfreq[BWI_CLKSRC_MAX] = {
295 CLKSRC(LP_OSC),
296 CLKSRC(CS_OSC),
297 CLKSRC(PCI)
298};
299
300#undef CLKSRC
301
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302#define VENDOR_LED_ACT(vendor) \
303{ \
304 .vid = PCI_VENDOR_##vendor, \
305 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \
306}
307
308static const struct {
309 uint16_t vid;
310 uint8_t led_act[BWI_LED_MAX];
311} bwi_vendor_led_act[] = {
312 VENDOR_LED_ACT(COMPAQ),
313 VENDOR_LED_ACT(LINKSYS)
314};
315
316static const uint8_t bwi_default_led_act[BWI_LED_MAX] =
317 { BWI_VENDOR_LED_ACT_DEFAULT };
318
319#undef VENDOR_LED_ACT
320
321static const struct {
322 int on_dur;
323 int off_dur;
324} bwi_led_duration[109] = {
325 [0] = { 400, 100 },
326 [2] = { 150, 75 },
327 [4] = { 90, 45 },
328 [11] = { 66, 34 },
329 [12] = { 53, 26 },
330 [18] = { 42, 21 },
331 [22] = { 35, 17 },
332 [24] = { 32, 16 },
333 [36] = { 21, 10 },
334 [48] = { 16, 8 },
335 [72] = { 11, 5 },
336 [96] = { 9, 4 },
337 [108] = { 7, 3 }
338};
339
9607893d 340#ifdef BWI_DEBUG
7fd94267 341#ifdef BWI_DEBUG_VERBOSE
9607893d 342static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER;
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343#else
344static uint32_t bwi_debug;
9607893d 345#endif
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346TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug);
347#endif /* BWI_DEBUG */
9607893d 348
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349static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN];
350
351static const struct ieee80211_rateset bwi_rateset_11b =
352 { 4, { 2, 4, 11, 22 } };
353static const struct ieee80211_rateset bwi_rateset_11g =
354 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
355
356uint16_t
357bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs)
358{
359 return CSR_READ_2(sc, ofs + BWI_SPROM_START);
360}
361
362static __inline void
363bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array,
364 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len,
365 int tx)
366{
367 struct bwi_desc32 *desc = &desc_array[desc_idx];
368 uint32_t ctrl, addr, addr_hi, addr_lo;
369
370 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK);
371 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK);
372
373 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) |
374 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK);
375
376 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |
377 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK);
378 if (desc_idx == ndesc - 1)
379 ctrl |= BWI_DESC32_C_EOR;
380 if (tx) {
381 /* XXX */
382 ctrl |= BWI_DESC32_C_FRAME_START |
383 BWI_DESC32_C_FRAME_END |
384 BWI_DESC32_C_INTR;
385 }
386
387 desc->addr = htole32(addr);
388 desc->ctrl = htole32(ctrl);
389}
390
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391/* XXX does not belong here */
392uint8_t
393bwi_rate2plcp(uint8_t rate)
394{
395 rate &= IEEE80211_RATE_VAL;
396
397 switch (rate) {
398 case 2: return 0xa;
399 case 4: return 0x14;
400 case 11: return 0x37;
401 case 22: return 0x6e;
402 case 44: return 0xdc;
403
404 case 12: return 0xb;
405 case 18: return 0xf;
406 case 24: return 0xa;
407 case 36: return 0xe;
408 case 48: return 0x9;
409 case 72: return 0xd;
410 case 96: return 0x8;
411 case 108: return 0xc;
412
413 default:
ed20d0e3 414 panic("unsupported rate %u", rate);
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415 }
416}
417
418/* XXX does not belong here */
419#define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0)
420#define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5)
421
422static __inline void
423bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate)
424{
425 uint32_t plcp;
426
427 plcp = __SHIFTIN(bwi_rate2plcp(rate), IEEE80211_OFDM_PLCP_RATE_MASK) |
428 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);
429 *plcp0 = htole32(plcp);
430}
431
432/* XXX does not belong here */
433struct ieee80211_ds_plcp_hdr {
434 uint8_t i_signal;
435 uint8_t i_service;
436 uint16_t i_length;
437 uint16_t i_crc;
438} __packed;
439
440#define IEEE80211_DS_PLCP_SERVICE_LOCKED 0x04
441#define IEEE80211_DS_PLCL_SERVICE_PBCC 0x08
442#define IEEE80211_DS_PLCP_SERVICE_LENEXT5 0x20
443#define IEEE80211_DS_PLCP_SERVICE_LENEXT6 0x40
444#define IEEE80211_DS_PLCP_SERVICE_LENEXT7 0x80
445
446static __inline void
447bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len,
448 uint8_t rate)
449{
450 int len, service, pkt_bitlen;
451
452 pkt_bitlen = pkt_len * NBBY;
453 len = howmany(pkt_bitlen * 2, rate);
454
455 service = IEEE80211_DS_PLCP_SERVICE_LOCKED;
456 if (rate == (11 * 2)) {
457 int pkt_bitlen1;
458
459 /*
460 * PLCP service field needs to be adjusted,
461 * if TX rate is 11Mbytes/s
462 */
463 pkt_bitlen1 = len * 11;
464 if (pkt_bitlen1 - pkt_bitlen >= NBBY)
465 service |= IEEE80211_DS_PLCP_SERVICE_LENEXT7;
466 }
467
468 plcp->i_signal = bwi_rate2plcp(rate);
469 plcp->i_service = service;
470 plcp->i_length = htole16(len);
471 /* NOTE: do NOT touch i_crc */
472}
473
474static __inline void
475bwi_plcp_header(void *plcp, int pkt_len, uint8_t rate)
476{
477 enum ieee80211_modtype modtype;
478
479 /*
480 * Assume caller has zeroed 'plcp'
481 */
482
483 modtype = ieee80211_rate2modtype(rate);
484 if (modtype == IEEE80211_MODTYPE_OFDM)
485 bwi_ofdm_plcp_header(plcp, pkt_len, rate);
486 else if (modtype == IEEE80211_MODTYPE_DS)
487 bwi_ds_plcp_header(plcp, pkt_len, rate);
488 else
ed20d0e3 489 panic("unsupport modulation type %u", modtype);
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490}
491
492static __inline uint8_t
493bwi_ofdm_plcp2rate(const uint32_t *plcp0)
494{
495 uint32_t plcp;
496 uint8_t plcp_rate;
497
498 plcp = le32toh(*plcp0);
499 plcp_rate = __SHIFTOUT(plcp, IEEE80211_OFDM_PLCP_RATE_MASK);
500 return ieee80211_plcp2rate(plcp_rate, 1);
501}
502
503static __inline uint8_t
504bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *hdr)
505{
506 return ieee80211_plcp2rate(hdr->i_signal, 0);
507}
508
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509static int
510bwi_probe(device_t dev)
511{
512 const struct bwi_dev *b;
513 uint16_t did, vid;
514
515 did = pci_get_device(dev);
516 vid = pci_get_vendor(dev);
517
518 for (b = bwi_devices; b->desc != NULL; ++b) {
519 if (b->did == did && b->vid == vid) {
520 device_set_desc(dev, b->desc);
521 return 0;
522 }
523 }
524 return ENXIO;
525}
526
527static int
528bwi_attach(device_t dev)
529{
530 struct bwi_softc *sc = device_get_softc(dev);
531 struct ieee80211com *ic = &sc->sc_ic;
532 struct ifnet *ifp = &ic->ic_if;
533 struct bwi_mac *mac;
534 struct bwi_phy *phy;
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535 struct sysctl_ctx_list *ctx;
536 struct sysctl_oid_list *tree;
1e290df3 537 char ethstr[ETHER_ADDRSTRLEN + 1];
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538 int i, error;
539
540 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
541 sc->sc_dev = dev;
542
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543 /*
544 * Initialize sysctl variables
545 */
546 sc->sc_fw_version = BWI_FW_VERSION3;
547 sc->sc_dwell_time = 200;
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548 sc->sc_led_idle = (2350 * hz) / 1000;
549 sc->sc_led_blink = 1;
0897f156 550 sc->sc_txpwr_calib = 1;
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551#ifdef BWI_DEBUG
552 sc->sc_debug = bwi_debug;
553#endif
554
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555 callout_init(&sc->sc_scan_ch);
556 callout_init(&sc->sc_calib_ch);
557
558#ifndef BURN_BRIDGES
559 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
560 uint32_t irq, mem;
561
562 /* XXX Save more PCIR */
563 irq = pci_read_config(dev, PCIR_INTLINE, 4);
564 mem = pci_read_config(dev, BWI_PCIR_BAR, 4);
565
566 device_printf(dev, "chip is in D%d power mode "
567 "-- setting to D0\n", pci_get_powerstate(dev));
568
569 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
570
571 pci_write_config(dev, PCIR_INTLINE, irq, 4);
c11da4be 572 pci_write_config(dev, BWI_PCIR_BAR, mem, 4);
5f9672cd
SZ
573 }
574#endif /* !BURN_BRIDGE */
575
576 pci_enable_busmaster(dev);
577
578 /* Get more PCI information */
579 sc->sc_pci_revid = pci_get_revid(dev);
580 sc->sc_pci_subvid = pci_get_subvendor(dev);
581 sc->sc_pci_subdid = pci_get_subdevice(dev);
582
583 /*
584 * Allocate IO memory
585 */
586 sc->sc_mem_rid = BWI_PCIR_BAR;
587 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
588 &sc->sc_mem_rid, RF_ACTIVE);
589 if (sc->sc_mem_res == NULL) {
590 device_printf(dev, "can't allocate IO memory\n");
591 return ENXIO;
592 }
593 sc->sc_mem_bt = rman_get_bustag(sc->sc_mem_res);
594 sc->sc_mem_bh = rman_get_bushandle(sc->sc_mem_res);
595
596 /*
597 * Allocate IRQ
598 */
599 sc->sc_irq_rid = 0;
600 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
601 &sc->sc_irq_rid,
602 RF_SHAREABLE | RF_ACTIVE);
603 if (sc->sc_irq_res == NULL) {
604 device_printf(dev, "can't allocate irq\n");
605 error = ENXIO;
606 goto fail;
607 }
608
516cc61f
SZ
609 /*
610 * Create sysctl tree
611 */
26595b18 612 ctx = device_get_sysctl_ctx(sc->bge_dev);
1b74c588 613 tree = device_get_sysctl_tree(sc->bge_dev);
516cc61f 614
26595b18 615 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
516cc61f
SZ
616 "dwell_time", CTLFLAG_RW, &sc->sc_dwell_time, 0,
617 "Channel dwell time during scan (msec)");
26595b18 618 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
516cc61f
SZ
619 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0,
620 "Firmware version");
26595b18 621 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
da367f92
SZ
622 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0,
623 "# ticks before LED enters idle state");
26595b18 624 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
da367f92
SZ
625 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0,
626 "Allow LED to blink");
26595b18 627 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
0897f156
SZ
628 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0,
629 "Enable software TX power calibration");
9607893d 630#ifdef BWI_DEBUG
26595b18 631 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
516cc61f 632 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags");
9607893d 633#endif
516cc61f 634
5f9672cd
SZ
635 bwi_power_on(sc, 1);
636
637 error = bwi_bbp_attach(sc);
638 if (error)
639 goto fail;
640
641 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
642 if (error)
643 goto fail;
644
645 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) {
646 error = bwi_set_clock_delay(sc);
647 if (error)
648 goto fail;
649
650 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST);
651 if (error)
652 goto fail;
653
654 error = bwi_get_pwron_delay(sc);
655 if (error)
656 goto fail;
657 }
658
659 error = bwi_bus_attach(sc);
660 if (error)
661 goto fail;
662
663 bwi_get_card_flags(sc);
664
777ee4a9 665 bwi_led_attach(sc);
5f9672cd
SZ
666
667 for (i = 0; i < sc->sc_nmac; ++i) {
668 struct bwi_regwin *old;
669
670 mac = &sc->sc_mac[i];
671 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old);
672 if (error)
673 goto fail;
674
675 error = bwi_mac_lateattach(mac);
676 if (error)
677 goto fail;
678
679 error = bwi_regwin_switch(sc, old, NULL);
680 if (error)
681 goto fail;
682 }
683
684 /*
685 * XXX First MAC is known to exist
686 * TODO2
687 */
688 mac = &sc->sc_mac[0];
689 phy = &mac->mac_phy;
690
691 bwi_bbp_power_off(sc);
692
693 error = bwi_dma_alloc(sc);
694 if (error)
695 goto fail;
696
697 ifp->if_softc = sc;
698 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
699 ifp->if_init = bwi_init;
700 ifp->if_ioctl = bwi_ioctl;
701 ifp->if_start = bwi_start;
702 ifp->if_watchdog = bwi_watchdog;
703 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
c3d41318 704#ifdef notyet
5f9672cd 705 ifq_set_ready(&ifp->if_snd);
c3d41318 706#endif
5f9672cd
SZ
707
708 /* Get locale */
709 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO),
710 BWI_SPROM_CARD_INFO_LOCALE);
9607893d 711 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale);
5f9672cd
SZ
712
713 /*
714 * Setup ratesets, phytype, channels and get MAC address
715 */
716 if (phy->phy_mode == IEEE80211_MODE_11B ||
717 phy->phy_mode == IEEE80211_MODE_11G) {
718 uint16_t chan_flags;
719
720 ic->ic_sup_rates[IEEE80211_MODE_11B] = bwi_rateset_11b;
721
722 if (phy->phy_mode == IEEE80211_MODE_11B) {
723 chan_flags = IEEE80211_CHAN_B;
724 ic->ic_phytype = IEEE80211_T_DS;
725 } else {
726 chan_flags = IEEE80211_CHAN_CCK |
727 IEEE80211_CHAN_OFDM |
728 IEEE80211_CHAN_DYN |
729 IEEE80211_CHAN_2GHZ;
730 ic->ic_phytype = IEEE80211_T_OFDM;
731 ic->ic_sup_rates[IEEE80211_MODE_11G] =
732 bwi_rateset_11g;
733 }
734
735 /* XXX depend on locale */
736 for (i = 1; i <= 14; ++i) {
737 ic->ic_channels[i].ic_freq =
738 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
739 ic->ic_channels[i].ic_flags = chan_flags;
740 }
741
742 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_myaddr);
743 if (IEEE80211_IS_MULTICAST(ic->ic_myaddr)) {
744 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_myaddr);
745 if (IEEE80211_IS_MULTICAST(ic->ic_myaddr)) {
746 device_printf(dev, "invalid MAC address: "
1e290df3 747 "%s\n", kether_ntoa(ic->ic_myaddr, ethstr));
5f9672cd
SZ
748 }
749 }
750 } else if (phy->phy_mode == IEEE80211_MODE_11A) {
751 /* TODO:11A */
752 error = ENXIO;
753 goto fail;
754 } else {
ed20d0e3 755 panic("unknown phymode %d", phy->phy_mode);
5f9672cd
SZ
756 }
757
5f9672cd
SZ
758 ic->ic_caps = IEEE80211_C_SHSLOT |
759 IEEE80211_C_SHPREAMBLE |
760 IEEE80211_C_WPA |
761 IEEE80211_C_MONITOR;
762 ic->ic_state = IEEE80211_S_INIT;
763 ic->ic_opmode = IEEE80211_M_STA;
764
21028056 765 IEEE80211_ONOE_PARAM_SETUP(&sc->sc_onoe_param);
92285ca6
SZ
766 ic->ic_ratectl.rc_st_ratectl_cap = IEEE80211_RATECTL_CAP_ONOE;
767 ic->ic_ratectl.rc_st_ratectl = IEEE80211_RATECTL_ONOE;
21028056 768 ic->ic_ratectl.rc_st_attach = bwi_ratectl_attach;
92285ca6 769
5f9672cd
SZ
770 ic->ic_updateslot = bwi_updateslot;
771
772 ieee80211_ifattach(ic);
773
774 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr);
775 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS;
776
777 sc->sc_newstate = ic->ic_newstate;
778 ic->ic_newstate = bwi_newstate;
779
780 ieee80211_media_init(ic, bwi_media_change, ieee80211_media_status);
781
ab411d47
SZ
782 /*
783 * Attach radio tap
784 */
785 bpfattach_dlt(ifp, DLT_IEEE802_11_RADIO,
786 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th),
787 &sc->sc_drvbpf);
788
789 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(uint32_t));
790 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len);
791 sc->sc_tx_th.wt_ihdr.it_present = htole32(BWI_TX_RADIOTAP_PRESENT);
792
793 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(uint32_t));
794 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len);
795 sc->sc_rx_th.wr_ihdr.it_present = htole32(BWI_RX_RADIOTAP_PRESENT);
796
4c77af2d
SZ
797 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sc_irq_res));
798
5f9672cd
SZ
799 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, bwi_intr, sc,
800 &sc->sc_irq_handle, ifp->if_serializer);
801 if (error) {
ab411d47
SZ
802 device_printf(dev, "can't setup intr\n");
803 bpfdetach(ifp);
5f9672cd
SZ
804 ieee80211_ifdetach(ic);
805 goto fail;
806 }
807
808 if (bootverbose)
809 ieee80211_announce(ic);
810
811 return 0;
812fail:
813 bwi_detach(dev);
814 return error;
815}
816
817static int
818bwi_detach(device_t dev)
819{
820 struct bwi_softc *sc = device_get_softc(dev);
821
822 if (device_is_attached(dev)) {
823 struct ifnet *ifp = &sc->sc_ic.ic_if;
824 int i;
825
826 lwkt_serialize_enter(ifp->if_serializer);
ba620a94 827 bwi_stop(sc, 1);
5f9672cd
SZ
828 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle);
829 lwkt_serialize_exit(ifp->if_serializer);
830
ab411d47 831 bpfdetach(ifp);
5f9672cd
SZ
832 ieee80211_ifdetach(&sc->sc_ic);
833
834 for (i = 0; i < sc->sc_nmac; ++i)
835 bwi_mac_detach(&sc->sc_mac[i]);
836 }
837
838 if (sc->sc_irq_res != NULL) {
839 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
840 sc->sc_irq_res);
841 }
842
843 if (sc->sc_mem_res != NULL) {
844 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
845 sc->sc_mem_res);
846 }
847
848 bwi_dma_free(sc);
849
850 return 0;
851}
852
853static int
854bwi_shutdown(device_t dev)
855{
856 struct bwi_softc *sc = device_get_softc(dev);
857 struct ifnet *ifp = &sc->sc_ic.ic_if;
858
859 lwkt_serialize_enter(ifp->if_serializer);
ba620a94 860 bwi_stop(sc, 1);
5f9672cd
SZ
861 lwkt_serialize_exit(ifp->if_serializer);
862 return 0;
863}
864
865static void
866bwi_power_on(struct bwi_softc *sc, int with_pll)
867{
868 uint32_t gpio_in, gpio_out, gpio_en;
869 uint16_t status;
870
871 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4);
872 if (gpio_in & BWI_PCIM_GPIO_PWR_ON)
873 goto back;
874
875 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
876 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
877
878 gpio_out |= BWI_PCIM_GPIO_PWR_ON;
879 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
880 if (with_pll) {
881 /* Turn off PLL first */
882 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
883 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
884 }
885
886 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
887 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
888 DELAY(1000);
889
890 if (with_pll) {
891 /* Turn on PLL */
892 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF;
893 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
894 DELAY(5000);
895 }
896
897back:
898 /* Clear "Signaled Target Abort" */
899 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
900 status &= ~PCIM_STATUS_STABORT;
901 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
902}
903
904static int
905bwi_power_off(struct bwi_softc *sc, int with_pll)
906{
907 uint32_t gpio_out, gpio_en;
908
909 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */
910 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
911 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
912
913 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON;
914 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
915 if (with_pll) {
916 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
917 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
918 }
919
920 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
921 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
922 return 0;
923}
924
925int
926bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw,
927 struct bwi_regwin **old_rw)
928{
929 int error;
930
931 if (old_rw != NULL)
932 *old_rw = NULL;
933
934 if (!BWI_REGWIN_EXIST(rw))
935 return EINVAL;
936
937 if (sc->sc_cur_regwin != rw) {
938 error = bwi_regwin_select(sc, rw->rw_id);
939 if (error) {
940 if_printf(&sc->sc_ic.ic_if, "can't select regwin %d\n",
941 rw->rw_id);
942 return error;
943 }
944 }
945
946 if (old_rw != NULL)
947 *old_rw = sc->sc_cur_regwin;
948 sc->sc_cur_regwin = rw;
949 return 0;
950}
951
952static int
953bwi_regwin_select(struct bwi_softc *sc, int id)
954{
955 uint32_t win = BWI_PCIM_REGWIN(id);
956 int i;
957
958#define RETRY_MAX 50
959 for (i = 0; i < RETRY_MAX; ++i) {
960 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4);
961 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win)
962 return 0;
963 DELAY(10);
964 }
965#undef RETRY_MAX
966
967 return ENXIO;
968}
969
970static void
971bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev)
972{
973 uint32_t val;
974
975 val = CSR_READ_4(sc, BWI_ID_HI);
976 *type = BWI_ID_HI_REGWIN_TYPE(val);
977 *rev = BWI_ID_HI_REGWIN_REV(val);
978
9607893d
SZ
979 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, "
980 "vendor 0x%04x\n", *type, *rev,
981 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));
5f9672cd
SZ
982}
983
984static int
985bwi_bbp_attach(struct bwi_softc *sc)
986{
5f9672cd
SZ
987 uint16_t bbp_id, rw_type;
988 uint8_t rw_rev;
989 uint32_t info;
990 int error, nregwin, i;
991
992 /*
993 * Get 0th regwin information
994 * NOTE: 0th regwin should exist
995 */
996 error = bwi_regwin_select(sc, 0);
997 if (error) {
998 device_printf(sc->sc_dev, "can't select regwin 0\n");
999 return error;
1000 }
1001 bwi_regwin_info(sc, &rw_type, &rw_rev);
1002
1003 /*
1004 * Find out BBP id
1005 */
1006 bbp_id = 0;
1007 info = 0;
1008 if (rw_type == BWI_REGWIN_T_COM) {
1009 info = CSR_READ_4(sc, BWI_INFO);
1010 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK);
1011
1012 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev);
1013
1014 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
1015 } else {
1016 uint16_t did = pci_get_device(sc->sc_dev);
1017 uint8_t revid = pci_get_revid(sc->sc_dev);
1018
c157ff7a 1019 for (i = 0; i < NELEM(bwi_bbpid_map); ++i) {
5f9672cd
SZ
1020 if (did >= bwi_bbpid_map[i].did_min &&
1021 did <= bwi_bbpid_map[i].did_max) {
1022 bbp_id = bwi_bbpid_map[i].bbp_id;
1023 break;
1024 }
1025 }
1026 if (bbp_id == 0) {
1027 device_printf(sc->sc_dev, "no BBP id for device id "
1028 "0x%04x\n", did);
1029 return ENXIO;
1030 }
1031
1032 info = __SHIFTIN(revid, BWI_INFO_BBPREV_MASK) |
1033 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK);
1034 }
1035
1036 /*
1037 * Find out number of regwins
1038 */
1039 nregwin = 0;
1040 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) {
1041 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK);
1042 } else {
c157ff7a 1043 for (i = 0; i < NELEM(bwi_regwin_count); ++i) {
5f9672cd
SZ
1044 if (bwi_regwin_count[i].bbp_id == bbp_id) {
1045 nregwin = bwi_regwin_count[i].nregwin;
1046 break;
1047 }
1048 }
1049 if (nregwin == 0) {
1050 device_printf(sc->sc_dev, "no number of win for "
1051 "BBP id 0x%04x\n", bbp_id);
1052 return ENXIO;
1053 }
1054 }
1055
1056 /* Record BBP id/rev for later using */
1057 sc->sc_bbp_id = bbp_id;
1058 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK);
1059 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK);
46af50ab 1060 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n",
5f9672cd
SZ
1061 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg);
1062
9607893d
SZ
1063 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n",
1064 nregwin, sc->sc_cap);
5f9672cd
SZ
1065
1066 /*
1067 * Create rest of the regwins
1068 */
1069
1070 /* Don't re-create common regwin, if it is already created */
1071 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0;
1072
1073 for (; i < nregwin; ++i) {
1074 /*
1075 * Get regwin information
1076 */
1077 error = bwi_regwin_select(sc, i);
1078 if (error) {
1079 device_printf(sc->sc_dev,
1080 "can't select regwin %d\n", i);
1081 return error;
1082 }
1083 bwi_regwin_info(sc, &rw_type, &rw_rev);
1084
1085 /*
1086 * Try attach:
1087 * 1) Bus (PCI/PCIE) regwin
1088 * 2) MAC regwin
1089 * Ignore rest types of regwin
1090 */
1091 if (rw_type == BWI_REGWIN_T_BUSPCI ||
1092 rw_type == BWI_REGWIN_T_BUSPCIE) {
1093 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
1094 device_printf(sc->sc_dev,
1095 "bus regwin already exists\n");
1096 } else {
1097 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i,
1098 rw_type, rw_rev);
1099 }
1100 } else if (rw_type == BWI_REGWIN_T_MAC) {
1101 /* XXX ignore return value */
1102 bwi_mac_attach(sc, i, rw_rev);
1103 }
1104 }
1105
1106 /* At least one MAC shold exist */
1107 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) {
1108 device_printf(sc->sc_dev, "no MAC was found\n");
1109 return ENXIO;
1110 }
1111 KKASSERT(sc->sc_nmac > 0);
1112
1113 /* Bus regwin must exist */
1114 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
1115 device_printf(sc->sc_dev, "no bus regwin was found\n");
1116 return ENXIO;
1117 }
1118
1119 /* Start with first MAC */
1120 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL);
1121 if (error)
1122 return error;
1123
1124 return 0;
5f9672cd
SZ
1125}
1126
1127int
1128bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac)
1129{
1130 struct bwi_regwin *old, *bus;
1131 uint32_t val;
1132 int error;
1133
1134 bus = &sc->sc_bus_regwin;
1135 KKASSERT(sc->sc_cur_regwin == &mac->mac_regwin);
1136
1137 /*
1138 * Tell bus to generate requested interrupts
1139 */
1140 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) {
1141 /*
1142 * NOTE: Read BWI_FLAGS from MAC regwin
1143 */
1144 val = CSR_READ_4(sc, BWI_FLAGS);
1145
1146 error = bwi_regwin_switch(sc, bus, &old);
1147 if (error)
1148 return error;
1149
1150 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK));
1151 } else {
1152 uint32_t mac_mask;
1153
1154 mac_mask = 1 << mac->mac_id;
1155
1156 error = bwi_regwin_switch(sc, bus, &old);
1157 if (error)
1158 return error;
1159
1160 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4);
1161 val |= mac_mask << 8;
1162 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4);
1163 }
1164
1165 if (sc->sc_flags & BWI_F_BUS_INITED)
1166 goto back;
1167
1168 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) {
1169 /*
1170 * Enable prefetch and burst
1171 */
1172 CSR_SETBITS_4(sc, BWI_BUS_CONFIG,
1173 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST);
1174
1175 if (bus->rw_rev < 5) {
1176 struct bwi_regwin *com = &sc->sc_com_regwin;
1177
1178 /*
1179 * Configure timeouts for bus operation
1180 */
1181
1182 /*
1183 * Set service timeout and request timeout
1184 */
1185 CSR_SETBITS_4(sc, BWI_CONF_LO,
1186 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |
1187 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));
1188
1189 /*
1190 * If there is common regwin, we switch to that regwin
1191 * and switch back to bus regwin once we have done.
1192 */
1193 if (BWI_REGWIN_EXIST(com)) {
1194 error = bwi_regwin_switch(sc, com, NULL);
1195 if (error)
1196 return error;
1197 }
1198
1199 /* Let bus know what we have changed */
1200 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC);
1201 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
1202 CSR_WRITE_4(sc, BWI_BUS_DATA, 0);
1203 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
1204
1205 if (BWI_REGWIN_EXIST(com)) {
1206 error = bwi_regwin_switch(sc, bus, NULL);
1207 if (error)
1208 return error;
1209 }
1210 } else if (bus->rw_rev >= 11) {
1211 /*
1212 * Enable memory read multiple
1213 */
1214 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM);
1215 }
1216 } else {
1217 /* TODO:PCIE */
1218 }
1219
1220 sc->sc_flags |= BWI_F_BUS_INITED;
1221back:
1222 return bwi_regwin_switch(sc, old, NULL);
1223}
1224
1225static void
1226bwi_get_card_flags(struct bwi_softc *sc)
1227{
1228 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS);
1229 if (sc->sc_card_flags == 0xffff)
1230 sc->sc_card_flags = 0;
1231
1232 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE &&
1233 sc->sc_pci_subdid == 0x4e && /* XXX */
1234 sc->sc_pci_revid > 0x40)
1235 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9;
1236
9607893d 1237 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags);
5f9672cd
SZ
1238}
1239
1240static void
1241bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr)
1242{
1243 int i;
1244
1245 for (i = 0; i < 3; ++i) {
1246 *((uint16_t *)eaddr + i) =
1247 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i));
1248 }
1249}
1250
1251static void
1252bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq)
1253{
1254 struct bwi_regwin *com;
1255 uint32_t val;
1256 u_int div;
1257 int src;
1258
1259 bzero(freq, sizeof(*freq));
1260 com = &sc->sc_com_regwin;
1261
1262 KKASSERT(BWI_REGWIN_EXIST(com));
1263 KKASSERT(sc->sc_cur_regwin == com);
1264 KKASSERT(sc->sc_cap & BWI_CAP_CLKMODE);
1265
1266 /*
1267 * Calculate clock frequency
1268 */
1269 src = -1;
1270 div = 0;
1271 if (com->rw_rev < 6) {
1272 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
1273 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) {
1274 src = BWI_CLKSRC_PCI;
1275 div = 64;
1276 } else {
1277 src = BWI_CLKSRC_CS_OSC;
1278 div = 32;
1279 }
1280 } else if (com->rw_rev < 10) {
1281 val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1282
1283 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);
1284 if (src == BWI_CLKSRC_LP_OSC) {
1285 div = 1;
1286 } else {
1287 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
1288
1289 /* Unknown source */
1290 if (src >= BWI_CLKSRC_MAX)
1291 src = BWI_CLKSRC_CS_OSC;
1292 }
1293 } else {
1294 val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1295
1296 src = BWI_CLKSRC_CS_OSC;
1297 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
1298 }
1299
1300 KKASSERT(src >= 0 && src < BWI_CLKSRC_MAX);
1301 KKASSERT(div != 0);
1302
9607893d 1303 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n",
5f9672cd
SZ
1304 src == BWI_CLKSRC_PCI ? "PCI" :
1305 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC"));
1306
1307 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;
1308 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;
1309
9607893d 1310 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n",
5f9672cd
SZ
1311 freq->clkfreq_min, freq->clkfreq_max);
1312}
1313
1314static int
1315bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
1316{
1317 struct bwi_regwin *old, *com;
1318 uint32_t clk_ctrl, clk_src;
1319 int error, pwr_off = 0;
1320
1321 com = &sc->sc_com_regwin;
1322 if (!BWI_REGWIN_EXIST(com))
1323 return 0;
1324
1325 if (com->rw_rev >= 10 || com->rw_rev < 6)
1326 return 0;
1327
1328 /*
1329 * For common regwin whose rev is [6, 10), the chip
1330 * must be capable to change clock mode.
1331 */
1332 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
1333 return 0;
1334
1335 error = bwi_regwin_switch(sc, com, &old);
1336 if (error)
1337 return error;
1338
1339 if (clk_mode == BWI_CLOCK_MODE_FAST)
1340 bwi_power_on(sc, 0); /* Don't turn on PLL */
1341
1342 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1343 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC);
1344
1345 switch (clk_mode) {
1346 case BWI_CLOCK_MODE_FAST:
1347 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW;
1348 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL;
1349 break;
1350 case BWI_CLOCK_MODE_SLOW:
1351 clk_ctrl |= BWI_CLOCK_CTRL_SLOW;
1352 break;
1353 case BWI_CLOCK_MODE_DYN:
1354 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW |
1355 BWI_CLOCK_CTRL_IGNPLL |
1356 BWI_CLOCK_CTRL_NODYN);
1357 if (clk_src != BWI_CLKSRC_CS_OSC) {
1358 clk_ctrl |= BWI_CLOCK_CTRL_NODYN;
1359 pwr_off = 1;
1360 }
1361 break;
1362 }
1363 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl);
1364
1365 if (pwr_off)
1366 bwi_power_off(sc, 0); /* Leave PLL as it is */
1367
1368 return bwi_regwin_switch(sc, old, NULL);
1369}
1370
1371static int
1372bwi_set_clock_delay(struct bwi_softc *sc)
1373{
1374 struct bwi_regwin *old, *com;
1375 int error;
1376
1377 com = &sc->sc_com_regwin;
1378 if (!BWI_REGWIN_EXIST(com))
1379 return 0;
1380
1381 error = bwi_regwin_switch(sc, com, &old);
1382 if (error)
1383 return error;
1384
1385 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) {
1386 if (sc->sc_bbp_rev == 0)
1387 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0);
1388 else if (sc->sc_bbp_rev == 1)
1389 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1);
1390 }
1391
1392 if (sc->sc_cap & BWI_CAP_CLKMODE) {
1393 if (com->rw_rev >= 10) {
1394 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000);
1395 } else {
1396 struct bwi_clock_freq freq;
1397
1398 bwi_get_clock_freq(sc, &freq);
1399 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY,
1400 howmany(freq.clkfreq_max * 150, 1000000));
1401 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY,
1402 howmany(freq.clkfreq_max * 15, 1000000));
1403 }
1404 }
1405
1406 return bwi_regwin_switch(sc, old, NULL);
1407}
1408
1409static void
1410bwi_init(void *xsc)
1411{
ba620a94
SZ
1412 bwi_init_statechg(xsc, 1);
1413}
1414
1415static void
1416bwi_init_statechg(struct bwi_softc *sc, int statechg)
1417{
5f9672cd
SZ
1418 struct ieee80211com *ic = &sc->sc_ic;
1419 struct ifnet *ifp = &ic->ic_if;
1420 struct bwi_mac *mac;
1421 int error;
1422
1423 ASSERT_SERIALIZED(ifp->if_serializer);
1424
ba620a94 1425 error = bwi_stop(sc, statechg);
5f9672cd
SZ
1426 if (error) {
1427 if_printf(ifp, "can't stop\n");
1428 return;
1429 }
1430
1431 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
1432
1433 /* TODO: 2 MAC */
1434
1435 mac = &sc->sc_mac[0];
1436 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL);
1437 if (error)
1438 goto back;
1439
1440 error = bwi_mac_init(mac);
1441 if (error)
1442 goto back;
1443
1444 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN);
1445
1446 bcopy(IF_LLADDR(ifp), ic->ic_myaddr, sizeof(ic->ic_myaddr));
1447
1448 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */
1449 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, ic->ic_myaddr);
1450
1451 bwi_mac_reset_hwkeys(mac);
1452
1453 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) {
1454 int i;
1455
1456#define NRETRY 1000
1457 /*
1458 * Drain any possible pending TX status
1459 */
1460 for (i = 0; i < NRETRY; ++i) {
5cfb4d2e
SZ
1461 if ((CSR_READ_4(sc, BWI_TXSTATUS0) &
1462 BWI_TXSTATUS0_VALID) == 0)
5f9672cd 1463 break;
5cfb4d2e 1464 CSR_READ_4(sc, BWI_TXSTATUS1);
5f9672cd
SZ
1465 }
1466 if (i == NRETRY)
1467 if_printf(ifp, "can't drain TX status\n");
1468#undef NRETRY
1469 }
1470
1471 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G)
1472 bwi_mac_updateslot(mac, 1);
1473
1474 /* Start MAC */
1475 error = bwi_mac_start(mac);
1476 if (error)
1477 goto back;
1478
1479 /* Enable intrs */
1480 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1481
1482 ifp->if_flags |= IFF_RUNNING;
9ed293e0 1483 ifq_clr_oactive(&ifp->if_snd);
5f9672cd 1484
ba620a94
SZ
1485 if (statechg) {
1486 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1487 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
1488 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
1489 } else {
1490 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
1491 }
5f9672cd 1492 } else {
ba620a94 1493 ieee80211_new_state(ic, ic->ic_state, -1);
5f9672cd
SZ
1494 }
1495back:
1496 if (error)
ba620a94
SZ
1497 bwi_stop(sc, 1);
1498 else
9db4b353 1499 ifp->if_start(ifp);
5f9672cd
SZ
1500}
1501
1502static int
1503bwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t req, struct ucred *cr)
1504{
1505 struct bwi_softc *sc = ifp->if_softc;
1506 int error = 0;
1507
1508 ASSERT_SERIALIZED(ifp->if_serializer);
1509
1510 switch (cmd) {
1511 case SIOCSIFFLAGS:
1512 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1513 (IFF_UP | IFF_RUNNING)) {
1514 struct bwi_mac *mac;
1515 int promisc = -1;
1516
1517 KKASSERT(sc->sc_cur_regwin->rw_type ==
1518 BWI_REGWIN_T_MAC);
1519 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1520
1521 if ((ifp->if_flags & IFF_PROMISC) &&
1522 (sc->sc_flags & BWI_F_PROMISC) == 0) {
1523 promisc = 1;
1524 sc->sc_flags |= BWI_F_PROMISC;
1525 } else if ((ifp->if_flags & IFF_PROMISC) == 0 &&
1526 (sc->sc_flags & BWI_F_PROMISC)) {
1527 promisc = 0;
1528 sc->sc_flags &= ~BWI_F_PROMISC;
1529 }
1530
1531 if (promisc >= 0)
1532 bwi_mac_set_promisc(mac, promisc);
1533 }
1534
1535 if (ifp->if_flags & IFF_UP) {
1536 if ((ifp->if_flags & IFF_RUNNING) == 0)
1537 bwi_init(sc);
1538 } else {
1539 if (ifp->if_flags & IFF_RUNNING)
ba620a94 1540 bwi_stop(sc, 1);
5f9672cd
SZ
1541 }
1542 break;
1543 default:
1544 error = ieee80211_ioctl(&sc->sc_ic, cmd, req, cr);
1545 break;
1546 }
1547
1548 if (error == ENETRESET) {
1549 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1550 (IFF_UP | IFF_RUNNING))
1551 bwi_init(sc);
1552 error = 0;
1553 }
1554 return error;
1555}
1556
1557static void
f0a26983 1558bwi_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
5f9672cd
SZ
1559{
1560 struct bwi_softc *sc = ifp->if_softc;
1561 struct ieee80211com *ic = &sc->sc_ic;
1562 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1563 int trans, idx;
1564
f0a26983 1565 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
5f9672cd
SZ
1566 ASSERT_SERIALIZED(ifp->if_serializer);
1567
9ed293e0 1568 if (ifq_is_oactive(&ifp->if_snd) || (ifp->if_flags & IFF_RUNNING) == 0)
5f9672cd
SZ
1569 return;
1570
1571 trans = 0;
1572 idx = tbd->tbd_idx;
1573
1574 while (tbd->tbd_buf[idx].tb_mbuf == NULL) {
1575 struct ieee80211_frame *wh;
1576 struct ieee80211_node *ni;
1577 struct mbuf *m;
1578 int mgt_pkt = 0;
1579
1580 if (!IF_QEMPTY(&ic->ic_mgtq)) {
1581 IF_DEQUEUE(&ic->ic_mgtq, m);
1582
1583 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1584 m->m_pkthdr.rcvif = NULL;
1585
1586 mgt_pkt = 1;
1587 } else if (!ifq_is_empty(&ifp->if_snd)) {
1588 struct ether_header *eh;
1589
9db4b353
SZ
1590 if (ic->ic_state != IEEE80211_S_RUN) {
1591 ifq_purge(&ifp->if_snd);
5f9672cd 1592 break;
9db4b353 1593 }
5f9672cd 1594
ac9843a1 1595 m = ifq_dequeue(&ifp->if_snd);
5f9672cd
SZ
1596 if (m == NULL)
1597 break;
1598
1599 if (m->m_len < sizeof(*eh)) {
1600 m = m_pullup(m, sizeof(*eh));
1601 if (m == NULL) {
d40991ef 1602 IFNET_STAT_INC(ifp, oerrors, 1);
5f9672cd
SZ
1603 continue;
1604 }
1605 }
1606 eh = mtod(m, struct ether_header *);
1607
1608 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
1609 if (ni == NULL) {
1610 m_freem(m);
d40991ef 1611 IFNET_STAT_INC(ifp, oerrors, 1);
5f9672cd
SZ
1612 continue;
1613 }
1614
1615 /* TODO: PS */
1616
1617 BPF_MTAP(ifp, m);
1618
1619 m = ieee80211_encap(ic, m, ni);
1620 if (m == NULL) {
1621 ieee80211_free_node(ni);
d40991ef 1622 IFNET_STAT_INC(ifp, oerrors, 1);
5f9672cd
SZ
1623 continue;
1624 }
1625 } else {
1626 break;
1627 }
1628
1629 if (ic->ic_rawbpf != NULL)
1630 bpf_mtap(ic->ic_rawbpf, m);
1631
1632 wh = mtod(m, struct ieee80211_frame *);
1633 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1634 if (ieee80211_crypto_encap(ic, ni, m) == NULL) {
1635 ieee80211_free_node(ni);
1636 m_freem(m);
d40991ef 1637 IFNET_STAT_INC(ifp, oerrors, 1);
5f9672cd
SZ
1638 continue;
1639 }
1640 }
1641 wh = NULL; /* Catch any invalid use */
1642
cf414c9b 1643 if (bwi_encap(sc, idx, m, &ni, mgt_pkt) != 0) {
5f9672cd
SZ
1644 /* 'm' is freed in bwi_encap() if we reach here */
1645 if (ni != NULL)
1646 ieee80211_free_node(ni);
d40991ef 1647 IFNET_STAT_INC(ifp, oerrors, 1);
5f9672cd
SZ
1648 continue;
1649 }
1650
1651 trans = 1;
1652 tbd->tbd_used++;
1653 idx = (idx + 1) % BWI_TX_NDESC;
1654
1655 if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) {
9ed293e0 1656 ifq_set_oactive(&ifp->if_snd);
5f9672cd
SZ
1657 break;
1658 }
1659 }
1660 tbd->tbd_idx = idx;
1661
1662 if (trans)
1663 sc->sc_tx_timer = 5;
1664 ifp->if_timer = 1;
1665}
1666
1667static void
1668bwi_watchdog(struct ifnet *ifp)
1669{
1670 struct bwi_softc *sc = ifp->if_softc;
1671
1672 ASSERT_SERIALIZED(ifp->if_serializer);
1673
1674 ifp->if_timer = 0;
1675
1676 if ((ifp->if_flags & IFF_RUNNING) == 0)
1677 return;
1678
1679 if (sc->sc_tx_timer) {
1680 if (--sc->sc_tx_timer == 0) {
1681 if_printf(ifp, "watchdog timeout\n");
d40991ef 1682 IFNET_STAT_INC(ifp, oerrors, 1);
5f9672cd
SZ
1683 /* TODO */
1684 } else {
1685 ifp->if_timer = 1;
1686 }
1687 }
1688 ieee80211_watchdog(&sc->sc_ic);
1689}
1690
1691static int
ba620a94 1692bwi_stop(struct bwi_softc *sc, int state_chg)
5f9672cd
SZ
1693{
1694 struct ieee80211com *ic = &sc->sc_ic;
1695 struct ifnet *ifp = &ic->ic_if;
1696 struct bwi_mac *mac;
1697 int i, error, pwr_off = 0;
1698
1699 ASSERT_SERIALIZED(ifp->if_serializer);
1700
ba620a94
SZ
1701 if (state_chg)
1702 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1703 else
1704 bwi_newstate_begin(sc, IEEE80211_S_INIT);
5f9672cd
SZ
1705
1706 if (ifp->if_flags & IFF_RUNNING) {
1707 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1708 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1709
1710 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1711 CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1712 bwi_mac_stop(mac);
1713 }
1714
1715 for (i = 0; i < sc->sc_nmac; ++i) {
1716 struct bwi_regwin *old_rw;
1717
1718 mac = &sc->sc_mac[i];
1719 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0)
1720 continue;
1721
1722 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw);
1723 if (error)
1724 continue;
1725
1726 bwi_mac_shutdown(mac);
1727 pwr_off = 1;
1728
1729 bwi_regwin_switch(sc, old_rw, NULL);
1730 }
1731
1732 if (pwr_off)
1733 bwi_bbp_power_off(sc);
1734
1735 sc->sc_tx_timer = 0;
1736 ifp->if_timer = 0;
9ed293e0
SZ
1737 ifp->if_flags &= ~IFF_RUNNING;
1738 ifq_clr_oactive(&ifp->if_snd);
5f9672cd
SZ
1739 return 0;
1740}
1741
1742static void
1743bwi_intr(void *xsc)
1744{
1745 struct bwi_softc *sc = xsc;
ba620a94 1746 struct bwi_mac *mac;
5f9672cd
SZ
1747 struct ifnet *ifp = &sc->sc_ic.ic_if;
1748 uint32_t intr_status;
1749 uint32_t txrx_intr_status[BWI_TXRX_NRING];
da367f92 1750 int i, txrx_error, tx = 0, rx_data = -1;
5f9672cd
SZ
1751
1752 ASSERT_SERIALIZED(ifp->if_serializer);
1753
1754 if ((ifp->if_flags & IFF_RUNNING) == 0)
1755 return;
1756
1757 /*
1758 * Get interrupt status
1759 */
1760 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
1761 if (intr_status == 0xffffffff) /* Not for us */
1762 return;
1763
9607893d 1764 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status);
5f9672cd
SZ
1765
1766 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1767 if (intr_status == 0) /* Nothing is interesting */
1768 return;
1769
ba620a94
SZ
1770 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1771 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1772
5f9672cd 1773 txrx_error = 0;
9607893d 1774 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr");
5f9672cd
SZ
1775 for (i = 0; i < BWI_TXRX_NRING; ++i) {
1776 uint32_t mask;
1777
1778 if (BWI_TXRX_IS_RX(i))
1779 mask = BWI_TXRX_RX_INTRS;
1780 else
1781 mask = BWI_TXRX_TX_INTRS;
1782
1783 txrx_intr_status[i] =
1784 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
1785
9607893d
SZ
1786 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x",
1787 i, txrx_intr_status[i]);
5f9672cd
SZ
1788
1789 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) {
1790 if_printf(ifp, "intr fatal TX/RX (%d) error 0x%08x\n",
1791 i, txrx_intr_status[i]);
1792 txrx_error = 1;
1793 }
1794 }
9607893d 1795 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", "");
5f9672cd
SZ
1796
1797 /*
1798 * Acknowledge interrupt
1799 */
1800 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status);
1801
1802 for (i = 0; i < BWI_TXRX_NRING; ++i)
1803 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]);
1804
1805 /* Disable all interrupts */
1806 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1807
ba620a94
SZ
1808 if (intr_status & BWI_INTR_PHY_TXERR) {
1809 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) {
1810 if_printf(ifp, "intr PHY TX error\n");
1811 /* XXX to netisr0? */
1812 bwi_init_statechg(sc, 0);
1813 return;
1814 }
1815 }
5f9672cd
SZ
1816
1817 if (txrx_error) {
1818 /* TODO: reset device */
1819 }
1820
ba620a94
SZ
1821 if (intr_status & BWI_INTR_TBTT)
1822 bwi_mac_config_ps(mac);
5f9672cd
SZ
1823
1824 if (intr_status & BWI_INTR_EO_ATIM)
1825 if_printf(ifp, "EO_ATIM\n");
1826
1827 if (intr_status & BWI_INTR_PMQ) {
1828 for (;;) {
1829 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)
1830 break;
1831 }
1832 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1833 }
1834
1835 if (intr_status & BWI_INTR_NOISE)
1836 if_printf(ifp, "intr noise\n");
1837
1838 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX)
da367f92 1839 rx_data = sc->sc_rxeof(sc);
5f9672cd 1840
da367f92 1841 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) {
5f9672cd 1842 sc->sc_txeof_status(sc);
da367f92
SZ
1843 tx = 1;
1844 }
5f9672cd 1845
da367f92 1846 if (intr_status & BWI_INTR_TX_DONE) {
5f9672cd 1847 bwi_txeof(sc);
da367f92
SZ
1848 tx = 1;
1849 }
5f9672cd
SZ
1850
1851 /* Re-enable interrupts */
1852 bwi_enable_intrs(sc, BWI_INIT_INTRS);
da367f92
SZ
1853
1854 if (sc->sc_blink_led != NULL && sc->sc_led_blink) {
1855 int evt = BWI_LED_EVENT_NONE;
1856
1857 if (tx && rx_data > 0) {
1858 if (sc->sc_rx_rate > sc->sc_tx_rate)
1859 evt = BWI_LED_EVENT_RX;
1860 else
1861 evt = BWI_LED_EVENT_TX;
1862 } else if (tx) {
1863 evt = BWI_LED_EVENT_TX;
1864 } else if (rx_data > 0) {
1865 evt = BWI_LED_EVENT_RX;
1866 } else if (rx_data == 0) {
1867 evt = BWI_LED_EVENT_POLL;
1868 }
1869
1870 if (evt != BWI_LED_EVENT_NONE)
1871 bwi_led_event(sc, evt);
1872 }
5f9672cd
SZ
1873}
1874
ba620a94
SZ
1875static void
1876bwi_newstate_begin(struct bwi_softc *sc, enum ieee80211_state nstate)
1877{
1878 callout_stop(&sc->sc_scan_ch);
1879 callout_stop(&sc->sc_calib_ch);
1880
1881 ieee80211_ratectl_newstate(&sc->sc_ic, nstate);
1882 bwi_led_newstate(sc, nstate);
1883
1884 if (nstate == IEEE80211_S_INIT)
1885 sc->sc_txpwrcb_type = BWI_TXPWR_INIT;
1886}
1887
5f9672cd
SZ
1888static int
1889bwi_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
1890{
1891 struct bwi_softc *sc = ic->ic_if.if_softc;
1892 struct ifnet *ifp = &ic->ic_if;
1893 int error;
1894
1895 ASSERT_SERIALIZED(ifp->if_serializer);
1896
ba620a94 1897 bwi_newstate_begin(sc, nstate);
92285ca6 1898
5f9672cd
SZ
1899 if (nstate == IEEE80211_S_INIT)
1900 goto back;
1901
1902 error = bwi_set_chan(sc, ic->ic_curchan);
1903 if (error) {
1904 if_printf(ifp, "can't set channel to %u\n",
1905 ieee80211_chan2ieee(ic, ic->ic_curchan));
1906 return error;
1907 }
1908
1909 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
1910 /* Nothing to do */
1911 } else if (nstate == IEEE80211_S_RUN) {
1912 struct bwi_mac *mac;
1913
1914 bwi_set_bssid(sc, ic->ic_bss->ni_bssid);
1915
1916 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1917 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1918
1919 /* Initial TX power calibration */
ba620a94
SZ
1920 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT);
1921#ifdef notyet
1922 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE;
1923#else
1924 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
1925#endif
5f9672cd
SZ
1926 } else {
1927 bwi_set_bssid(sc, bwi_zero_addr);
1928 }
1929
1930back:
1931 error = sc->sc_newstate(ic, nstate, arg);
1932
1933 if (nstate == IEEE80211_S_SCAN) {
1934 callout_reset(&sc->sc_scan_ch,
1935 (sc->sc_dwell_time * hz) / 1000,
1936 bwi_next_scan, sc);
1937 } else if (nstate == IEEE80211_S_RUN) {
ba620a94 1938 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc);
5f9672cd
SZ
1939 }
1940 return error;
1941}
1942
1943static int
1944bwi_media_change(struct ifnet *ifp)
1945{
1946 int error;
1947
1948 ASSERT_SERIALIZED(ifp->if_serializer);
1949
1950 error = ieee80211_media_change(ifp);
1951 if (error != ENETRESET)
1952 return error;
1953
1954 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING))
1955 bwi_init(ifp->if_softc);
1956 return 0;
1957}
1958
1959static int
1960bwi_dma_alloc(struct bwi_softc *sc)
1961{
1962 int error, i, has_txstats;
1963 bus_addr_t lowaddr = 0;
1964 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0;
1965 uint32_t txrx_ctrl_step = 0;
1966
1967 has_txstats = 0;
1968 for (i = 0; i < sc->sc_nmac; ++i) {
1969 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) {
1970 has_txstats = 1;
1971 break;
1972 }
1973 }
1974
1975 switch (sc->sc_bus_space) {
1976 case BWI_BUS_SPACE_30BIT:
1977 case BWI_BUS_SPACE_32BIT:
1978 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT)
1979 lowaddr = BWI_BUS_SPACE_MAXADDR;
1980 else
1981 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1982 desc_sz = sizeof(struct bwi_desc32);
1983 txrx_ctrl_step = 0x20;
1984
1985 sc->sc_init_tx_ring = bwi_init_tx_ring32;
1986 sc->sc_free_tx_ring = bwi_free_tx_ring32;
1987 sc->sc_init_rx_ring = bwi_init_rx_ring32;
1988 sc->sc_free_rx_ring = bwi_free_rx_ring32;
1989 sc->sc_setup_rxdesc = bwi_setup_rx_desc32;
1990 sc->sc_setup_txdesc = bwi_setup_tx_desc32;
1991 sc->sc_rxeof = bwi_rxeof32;
1992 sc->sc_start_tx = bwi_start_tx32;
1993 if (has_txstats) {
1994 sc->sc_init_txstats = bwi_init_txstats32;
1995 sc->sc_free_txstats = bwi_free_txstats32;
1996 sc->sc_txeof_status = bwi_txeof_status32;
1997 }
1998 break;
1999
2000 case BWI_BUS_SPACE_64BIT:
2001 lowaddr = BUS_SPACE_MAXADDR; /* XXX */
2002 desc_sz = sizeof(struct bwi_desc64);
2003 txrx_ctrl_step = 0x40;
2004
2005 sc->sc_init_tx_ring = bwi_init_tx_ring64;
2006 sc->sc_free_tx_ring = bwi_free_tx_ring64;
2007 sc->sc_init_rx_ring = bwi_init_rx_ring64;
2008 sc->sc_free_rx_ring = bwi_free_rx_ring64;
2009 sc->sc_setup_rxdesc = bwi_setup_rx_desc64;
2010 sc->sc_setup_txdesc = bwi_setup_tx_desc64;
2011 sc->sc_rxeof = bwi_rxeof64;
2012 sc->sc_start_tx = bwi_start_tx64;
2013 if (has_txstats) {
2014 sc->sc_init_txstats = bwi_init_txstats64;
2015 sc->sc_free_txstats = bwi_free_txstats64;
2016 sc->sc_txeof_status = bwi_txeof_status64;
2017 }
2018 break;
2019 }
2020
2021 KKASSERT(lowaddr != 0);
2022 KKASSERT(desc_sz != 0);
2023 KKASSERT(txrx_ctrl_step != 0);
2024
2025 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN);
2026 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN);
2027
2028 /*
2029 * Create top level DMA tag
2030 */
2031 error = bus_dma_tag_create(NULL, BWI_ALIGN, 0,
2032 lowaddr, BUS_SPACE_MAXADDR,
2033 NULL, NULL,
2034 MAXBSIZE,
2035 BUS_SPACE_UNRESTRICTED,
2036 BUS_SPACE_MAXSIZE_32BIT,
2037 0, &sc->sc_parent_dtag);
2038 if (error) {
2039 device_printf(sc->sc_dev, "can't create parent DMA tag\n");
2040 return error;
2041 }
2042
2043#define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step)
2044
2045 /*
2046 * Create TX ring DMA stuffs
2047 */
2048 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2049 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2050 NULL, NULL,
2051 tx_ring_sz, 1, BUS_SPACE_MAXSIZE_32BIT,
2052 0, &sc->sc_txring_dtag);
2053 if (error) {
2054 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n");
2055 return error;
2056 }
2057
2058 for (i = 0; i < BWI_TX_NRING; ++i) {
2059 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag,
2060 &sc->sc_tx_rdata[i], tx_ring_sz,
2061 TXRX_CTRL(i));
2062 if (error) {
2063 device_printf(sc->sc_dev, "%dth TX ring "
2064 "DMA alloc failed\n", i);
2065 return error;
2066 }
2067 }
2068
2069 /*
2070 * Create RX ring DMA stuffs
2071 */
2072 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2073 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2074 NULL, NULL,
2075 rx_ring_sz, 1, BUS_SPACE_MAXSIZE_32BIT,
2076 0, &sc->sc_rxring_dtag);
2077 if (error) {
2078 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n");
2079 return error;
2080 }
2081
2082 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata,
2083 rx_ring_sz, TXRX_CTRL(0));
2084 if (error) {
2085 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n");
2086 return error;
2087 }
2088
2089 if (has_txstats) {
2090 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz);
2091 if (error) {
2092 device_printf(sc->sc_dev,
2093 "TX stats DMA alloc failed\n");
2094 return error;
2095 }
2096 }
2097
2098#undef TXRX_CTRL
2099
2100 return bwi_dma_mbuf_create(sc);
2101}
2102
2103static void
2104bwi_dma_free(struct bwi_softc *sc)
2105{
2106 if (sc->sc_txring_dtag != NULL) {
2107 int i;
2108
2109 for (i = 0; i < BWI_TX_NRING; ++i) {
2110 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i];
2111
2112 if (rd->rdata_desc != NULL) {
2113 bus_dmamap_unload(sc->sc_txring_dtag,
2114 rd->rdata_dmap);
2115 bus_dmamem_free(sc->sc_txring_dtag,
2116 rd->rdata_desc,
2117 rd->rdata_dmap);
2118 }
2119 }
2120 bus_dma_tag_destroy(sc->sc_txring_dtag);
2121 }
2122
2123 if (sc->sc_rxring_dtag != NULL) {
2124 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2125
2126 if (rd->rdata_desc != NULL) {
2127 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap);
2128 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc,
2129 rd->rdata_dmap);
2130 }
2131 bus_dma_tag_destroy(sc->sc_rxring_dtag);
2132 }
2133
2134 bwi_dma_txstats_free(sc);
2135 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1);
2136
2137 if (sc->sc_parent_dtag != NULL)
2138 bus_dma_tag_destroy(sc->sc_parent_dtag);
2139}
2140
2141static int
2142bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag,
2143 struct bwi_ring_data *rd, bus_size_t size,
2144 uint32_t txrx_ctrl)
2145{
2146 int error;
2147
2148 error = bus_dmamem_alloc(dtag, &rd->rdata_desc,
2149 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2150 &rd->rdata_dmap);
2151 if (error) {
2152 device_printf(sc->sc_dev, "can't allocate DMA mem\n");
2153 return error;
2154 }
2155
2156 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size,
2157 bwi_dma_ring_addr, &rd->rdata_paddr,
2158 BUS_DMA_WAITOK);
2159 if (error) {
2160 device_printf(sc->sc_dev, "can't load DMA mem\n");
2161 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap);
2162 rd->rdata_desc = NULL;
2163 return error;
2164 }
2165
2166 rd->rdata_txrx_ctrl = txrx_ctrl;
2167 return 0;
2168}
2169
2170static int
2171bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base,
2172 bus_size_t desc_sz)
2173{
2174 struct bwi_txstats_data *st;
2175 bus_size_t dma_size;
2176 int error;
2177
2178 st = kmalloc(sizeof(*st), M_DEVBUF, M_WAITOK | M_ZERO);
2179 sc->sc_txstats = st;
2180
2181 /*
2182 * Create TX stats descriptor DMA stuffs
2183 */
2184 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN);
2185
2186 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2187 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2188 NULL, NULL,
2189 dma_size, 1, BUS_SPACE_MAXSIZE_32BIT,
2190 0, &st->stats_ring_dtag);
2191 if (error) {
2192 device_printf(sc->sc_dev, "can't create txstats ring "
2193 "DMA tag\n");
2194 return error;
2195 }
2196
2197 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring,
2198 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2199 &st->stats_ring_dmap);
2200 if (error) {
2201 device_printf(sc->sc_dev, "can't allocate txstats ring "
2202 "DMA mem\n");
2203 bus_dma_tag_destroy(st->stats_ring_dtag);
2204 st->stats_ring_dtag = NULL;
2205 return error;
2206 }
2207
2208 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap,
2209 st->stats_ring, dma_size,
2210 bwi_dma_ring_addr, &st->stats_ring_paddr,
2211 BUS_DMA_WAITOK);
2212 if (error) {
2213 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n");
2214 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2215 st->stats_ring_dmap);
2216 bus_dma_tag_destroy(st->stats_ring_dtag);
2217 st->stats_ring_dtag = NULL;
2218 return error;
2219 }
2220
2221 /*
2222 * Create TX stats DMA stuffs
2223 */
2224 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC,
2225 BWI_ALIGN);
2226
2227 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_ALIGN, 0,
2228 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2229 NULL, NULL,
2230 dma_size, 1, BUS_SPACE_MAXSIZE_32BIT,
2231 0, &st->stats_dtag);
2232 if (error) {
2233 device_printf(sc->sc_dev, "can't create txstats DMA tag\n");
2234 return error;
2235 }
2236
2237 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats,
2238 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2239 &st->stats_dmap);
2240 if (error) {
2241 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n");
2242 bus_dma_tag_destroy(st->stats_dtag);
2243 st->stats_dtag = NULL;
2244 return error;
2245 }
2246
2247 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats,
2248 dma_size, bwi_dma_ring_addr, &st->stats_paddr,
2249 BUS_DMA_WAITOK);
2250 if (error) {
2251 device_printf(sc->sc_dev, "can't load txstats DMA mem\n");
2252 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2253 bus_dma_tag_destroy(st->stats_dtag);
2254 st->stats_dtag = NULL;
2255 return error;
2256 }
2257
2258 st->stats_ctrl_base = ctrl_base;
2259 return 0;
2260}
2261
2262static void
2263bwi_dma_txstats_free(struct bwi_softc *sc)
2264{
2265 struct bwi_txstats_data *st;
2266
2267 if (sc->sc_txstats == NULL)
2268 return;
2269 st = sc->sc_txstats;
2270
2271 if (st->stats_ring_dtag != NULL) {
2272 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap);
2273 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2274 st->stats_ring_dmap);
2275 bus_dma_tag_destroy(st->stats_ring_dtag);
2276 }
2277
2278 if (st->stats_dtag != NULL) {
2279 bus_dmamap_unload(st->stats_dtag, st->stats_dmap);
2280 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2281 bus_dma_tag_destroy(st->stats_dtag);
2282 }
2283
2284 kfree(st, M_DEVBUF);
2285}
2286
2287static void
2288bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2289{
ed20d0e3 2290 KASSERT(nseg == 1, ("too many segments"));
5f9672cd
SZ
2291 *((bus_addr_t *)arg) = seg->ds_addr;
2292}
2293
2294static int
2295bwi_dma_mbuf_create(struct bwi_softc *sc)
2296{
2297 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2298 int i, j, k, ntx, error;
2299
2300 /*
2301 * Create TX/RX mbuf DMA tag
2302 */
2303 error = bus_dma_tag_create(sc->sc_parent_dtag, 1, 0,
2304 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2305 NULL, NULL, MCLBYTES, 1,
2306 BUS_SPACE_MAXSIZE_32BIT,
2307 0, &sc->sc_buf_dtag);
2308 if (error) {
2309 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
2310 return error;
2311 }
2312
2313 ntx = 0;
2314
2315 /*
2316 * Create TX mbuf DMA map
2317 */
2318 for (i = 0; i < BWI_TX_NRING; ++i) {
2319 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2320
2321 for (j = 0; j < BWI_TX_NDESC; ++j) {
2322 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2323 &tbd->tbd_buf[j].tb_dmap);
2324 if (error) {
2325 device_printf(sc->sc_dev, "can't create "
2326 "%dth tbd, %dth DMA map\n", i, j);
2327
2328 ntx = i;
2329 for (k = 0; k < j; ++k) {
2330 bus_dmamap_destroy(sc->sc_buf_dtag,
2331 tbd->tbd_buf[k].tb_dmap);
2332 }
2333 goto fail;
2334 }
2335 }
2336 }
2337 ntx = BWI_TX_NRING;
2338
2339 /*
2340 * Create RX mbuf DMA map and a spare DMA map
2341 */
2342 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2343 &rbd->rbd_tmp_dmap);
2344 if (error) {
2345 device_printf(sc->sc_dev,
2346 "can't create spare RX buf DMA map\n");
2347 goto fail;
2348 }
2349
2350 for (j = 0; j < BWI_RX_NDESC; ++j) {
2351 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2352 &rbd->rbd_buf[j].rb_dmap);
2353 if (error) {
2354 device_printf(sc->sc_dev, "can't create %dth "
2355 "RX buf DMA map\n", j);
2356
2357 for (k = 0; k < j; ++k) {
2358 bus_dmamap_destroy(sc->sc_buf_dtag,
2359 rbd->rbd_buf[j].rb_dmap);
2360 }
2361 bus_dmamap_destroy(sc->sc_buf_dtag,
2362 rbd->rbd_tmp_dmap);
2363 goto fail;
2364 }
2365 }
2366
2367 return 0;
2368fail:
2369 bwi_dma_mbuf_destroy(sc, ntx, 0);
2370 return error;
2371}
2372
2373static void
2374bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx)
2375{
2376 int i, j;
2377
2378 if (sc->sc_buf_dtag == NULL)
2379 return;
2380
2381 for (i = 0; i < ntx; ++i) {
2382 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2383
2384 for (j = 0; j < BWI_TX_NDESC; ++j) {
2385 struct bwi_txbuf *tb = &tbd->tbd_buf[j];
2386
2387 if (tb->tb_mbuf != NULL) {
2388 bus_dmamap_unload(sc->sc_buf_dtag,
2389 tb->tb_dmap);
2390 m_freem(tb->tb_mbuf);
2391 }
2392 if (tb->tb_ni != NULL)
2393 ieee80211_free_node(tb->tb_ni);
2394 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap);
2395 }
2396 }
2397
2398 if (nrx) {
2399 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2400
2401 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap);
2402 for (j = 0; j < BWI_RX_NDESC; ++j) {
2403 struct bwi_rxbuf *rb = &rbd->rbd_buf[j];
2404
2405 if (rb->rb_mbuf != NULL) {
2406 bus_dmamap_unload(sc->sc_buf_dtag,
2407 rb->rb_dmap);
2408 m_freem(rb->rb_mbuf);
2409 }
2410 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap);
2411 }
2412 }
2413
2414 bus_dma_tag_destroy(sc->sc_buf_dtag);
2415 sc->sc_buf_dtag = NULL;
2416}
2417
2418static void
2419bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs)
2420{
2421 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs);
2422}
2423
2424static void
2425bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs)
2426{
2427 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs);
2428}
2429
2430static int
2431bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx)
2432{
2433 struct bwi_ring_data *rd;
2434 struct bwi_txbuf_data *tbd;
2435 uint32_t val, addr_hi, addr_lo;
2436
2437 KKASSERT(ring_idx < BWI_TX_NRING);
2438 rd = &sc->sc_tx_rdata[ring_idx];
2439 tbd = &sc->sc_tx_bdata[ring_idx];
2440
2441 tbd->tbd_idx = 0;
2442 tbd->tbd_used = 0;
2443
2444 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC);
2445 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
2446 BUS_DMASYNC_PREWRITE);
2447
2448 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2449 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2450
2451 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2452 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2453 BWI_TXRX32_RINGINFO_FUNC_MASK);
2454 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val);
2455
2456 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2457 BWI_TXRX32_CTRL_ENABLE;
2458 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val);
2459
2460 return 0;
2461}
2462
2463static void
2464bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base,
2465 bus_addr_t paddr, int hdr_size, int ndesc)
2466{
2467 uint32_t val, addr_hi, addr_lo;
2468
2469 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2470 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2471
2472 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2473 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2474 BWI_TXRX32_RINGINFO_FUNC_MASK);
2475 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val);
2476
2477 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
2478 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2479 BWI_TXRX32_CTRL_ENABLE;
2480 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val);
2481
2482 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
2483 (ndesc - 1) * sizeof(struct bwi_desc32));
2484}
2485
2486static int
2487bwi_init_rx_ring32(struct bwi_softc *sc)
2488{
2489 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2490 int i, error;
2491
2492 sc->sc_rx_bdata.rbd_idx = 0;
2493
2494 for (i = 0; i < BWI_RX_NDESC; ++i) {
2495 error = bwi_newbuf(sc, i, 1);
2496 if (error) {
2497 if_printf(&sc->sc_ic.ic_if,
2498 "can't allocate %dth RX buffer\n", i);
2499 return error;
2500 }
2501 }
2502 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2503 BUS_DMASYNC_PREWRITE);
2504
2505 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr,
2506 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC);
2507 return 0;
2508}
2509
2510static int
2511bwi_init_txstats32(struct bwi_softc *sc)
2512{
2513 struct bwi_txstats_data *st = sc->sc_txstats;
2514 bus_addr_t stats_paddr;
2515 int i;
2516
2517 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats));
2518 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE);
2519
2520 st->stats_idx = 0;
2521
2522 stats_paddr = st->stats_paddr;
2523 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) {
2524 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i,
2525 stats_paddr, sizeof(struct bwi_txstats), 0);
2526 stats_paddr += sizeof(struct bwi_txstats);
2527 }
2528 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap,
2529 BUS_DMASYNC_PREWRITE);
2530
2531 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base,
2532 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC);
2533 return 0;
2534}
2535
2536static void
2537bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2538 int buf_len)
2539{
2540 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2541
2542 KKASSERT(buf_idx < BWI_RX_NDESC);
2543 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx,
2544 paddr, buf_len, 0);
2545}
2546
2547static void
2548bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd,
2549 int buf_idx, bus_addr_t paddr, int buf_len)
2550{
2551 KKASSERT(buf_idx < BWI_TX_NDESC);
2552 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx,
2553 paddr, buf_len, 1);
2554}
2555
2556static int
2557bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx)
2558{
2559 /* TODO:64 */
2560 return EOPNOTSUPP;
2561}
2562
2563static int
2564bwi_init_rx_ring64(struct bwi_softc *sc)
2565{
2566 /* TODO:64 */
2567 return EOPNOTSUPP;
2568}
2569
2570static int
2571bwi_init_txstats64(struct bwi_softc *sc)
2572{
2573 /* TODO:64 */
2574 return EOPNOTSUPP;
2575}
2576
2577static void
2578bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2579 int buf_len)
2580{
2581 /* TODO:64 */
2582}
2583
2584static void
2585bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd,
2586 int buf_idx, bus_addr_t paddr, int buf_len)
2587{
2588 /* TODO:64 */
2589}
2590
2591static void
2592bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
2593 bus_size_t mapsz __unused, int error)
2594{
2595 if (!error) {
ed20d0e3 2596 KASSERT(nseg == 1, ("too many segments(%d)", nseg));
5f9672cd
SZ
2597 *((bus_addr_t *)arg) = seg->ds_addr;
2598 }
2599}
2600
2601static int
2602bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init)
2603{
2604 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2605 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx];
2606 struct bwi_rxbuf_hdr *hdr;
2607 bus_dmamap_t map;
2608 bus_addr_t paddr;
2609 struct mbuf *m;
2610 int error;
2611
2612 KKASSERT(buf_idx < BWI_RX_NDESC);
2613
2614 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2615 if (m == NULL) {
2616 error = ENOBUFS;
2617
2618 /*
2619 * If the NIC is up and running, we need to:
2620 * - Clear RX buffer's header.
2621 * - Restore RX descriptor settings.
2622 */
2623 if (init)
2624 return error;
2625 else
2626 goto back;
2627 }
2628 m->m_len = m->m_pkthdr.len = MCLBYTES;
2629
2630 /*
2631 * Try to load RX buf into temporary DMA map
2632 */
2633 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m,
2634 bwi_dma_buf_addr, &paddr,
2635 init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2636 if (error) {
2637 m_freem(m);
2638
2639 /*
2640 * See the comment above
2641 */
2642 if (init)
2643 return error;
2644 else
2645 goto back;
2646 }
2647
2648 if (!init)
2649 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap);
2650 rxbuf->rb_mbuf = m;
2651 rxbuf->rb_paddr = paddr;
2652
2653 /*
2654 * Swap RX buf's DMA map with the loaded temporary one
2655 */
2656 map = rxbuf->rb_dmap;
2657 rxbuf->rb_dmap = rbd->rbd_tmp_dmap;
2658 rbd->rbd_tmp_dmap = map;
2659
2660back:
2661 /*
2662 * Clear RX buf header
2663 */
2664 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *);
2665 bzero(hdr, sizeof(*hdr));
2666 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE);
2667
2668 /*
2669 * Setup RX buf descriptor
2670 */
2671 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr,
2672 rxbuf->rb_mbuf->m_len - sizeof(*hdr));
2673 return error;
2674}
2675
2676static void
2677bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs,
2678 const uint8_t *addr)
2679{
2680 int i;
2681
2682 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
2683 BWI_ADDR_FILTER_CTRL_SET | addr_ofs);
2684
2685 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) {
2686 uint16_t addr_val;
2687
2688 addr_val = (uint16_t)addr[i * 2] |
2689 (((uint16_t)addr[(i * 2) + 1]) << 8);
2690 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
2691 }
2692}
2693
2694static int
2695bwi_set_chan(struct bwi_softc *sc, struct ieee80211_channel *c)
2696{
2697 struct ieee80211com *ic = &sc->sc_ic;
9db4b353 2698#ifdef INVARIANTS
5f9672cd 2699 struct ifnet *ifp = &ic->ic_if;
9db4b353 2700#endif
5f9672cd 2701 struct bwi_mac *mac;
ab411d47 2702 uint16_t flags;
5f9672cd
SZ
2703 u_int chan;
2704
2705 ASSERT_SERIALIZED(ifp->if_serializer);
2706
2707 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
2708 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2709
2710 chan = ieee80211_chan2ieee(ic, c);
2711
2712 bwi_rf_set_chan(mac, chan, 0);
2713
ab411d47
SZ
2714 /*
2715 * Setup radio tap channel freq and flags
2716 */
2717 if (IEEE80211_IS_CHAN_G(c))
2718 flags = IEEE80211_CHAN_G;
2719 else
2720 flags = IEEE80211_CHAN_B;
2721
2722 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
2723 htole16(c->ic_freq);
2724 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
2725 htole16(flags);
5f9672cd
SZ
2726
2727 return 0;
2728}
2729
2730static void
2731bwi_next_scan(void *xsc)
2732{
2733 struct bwi_softc *sc = xsc;
2734 struct ieee80211com *ic = &sc->sc_ic;
2735 struct ifnet *ifp = &ic->ic_if;
2736
2737 lwkt_serialize_enter(ifp->if_serializer);
2738
2739 if (ic->ic_state == IEEE80211_S_SCAN)
2740 ieee80211_next_scan(ic);
2741
2742 lwkt_serialize_exit(ifp->if_serializer);
2743}
2744
da367f92 2745static int
5f9672cd
SZ
2746bwi_rxeof(struct bwi_softc *sc, int end_idx)
2747{
2748 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2749 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2750 struct ieee80211com *ic = &sc->sc_ic;
2751 struct ifnet *ifp = &ic->ic_if;
da367f92 2752 int idx, rx_data = 0;
5f9672cd
SZ
2753
2754 idx = rbd->rbd_idx;
2755 while (idx != end_idx) {
2756 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx];
2757 struct bwi_rxbuf_hdr *hdr;
2758 struct ieee80211_frame_min *wh;
2759 struct ieee80211_node *ni;
2760 struct mbuf *m;
da367f92 2761 const void *plcp;
5f9672cd 2762 uint16_t flags2;
da367f92 2763 int buflen, wh_ofs, hdr_extra, rssi, type, rate;
5f9672cd
SZ
2764
2765 m = rb->rb_mbuf;
2766 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap,
2767 BUS_DMASYNC_POSTREAD);
2768
2769 if (bwi_newbuf(sc, idx, 0)) {
d40991ef 2770 IFNET_STAT_INC(ifp, ierrors, 1);
5f9672cd
SZ
2771 goto next;
2772 }
2773
2774 hdr = mtod(m, struct bwi_rxbuf_hdr *);
2775 flags2 = le16toh(hdr->rxh_flags2);
2776
2777 hdr_extra = 0;
2778 if (flags2 & BWI_RXH_F2_TYPE2FRAME)
2779 hdr_extra = 2;
ab411d47 2780 wh_ofs = hdr_extra + 6; /* XXX magic number */
5f9672cd
SZ
2781
2782 buflen = le16toh(hdr->rxh_buflen);
1296bc53
SZ
2783 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) {
2784 if_printf(ifp, "short frame %d, hdr_extra %d\n",
2785 buflen, hdr_extra);
d40991ef 2786 IFNET_STAT_INC(ifp, ierrors, 1);
5f9672cd
SZ
2787 m_freem(m);
2788 goto next;
2789 }
2790
ab411d47
SZ
2791 plcp = ((const uint8_t *)(hdr + 1) + hdr_extra);
2792 rssi = bwi_calc_rssi(sc, hdr);
5f9672cd
SZ
2793
2794 m->m_pkthdr.rcvif = ifp;
2795 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr);
2796 m_adj(m, sizeof(*hdr) + wh_ofs);
2797
da367f92
SZ
2798 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM)
2799 rate = bwi_ofdm_plcp2rate(plcp);
2800 else
2801 rate = bwi_ds_plcp2rate(plcp);
2802
ab411d47
SZ
2803 /* RX radio tap */
2804 if (sc->sc_drvbpf != NULL)
da367f92 2805 bwi_rx_radiotap(sc, m, hdr, plcp, rate, rssi);
5f9672cd
SZ
2806
2807 m_adj(m, -IEEE80211_CRC_LEN);
2808
2809 wh = mtod(m, struct ieee80211_frame_min *);
2810 ni = ieee80211_find_rxnode(ic, wh);
2811
da367f92
SZ
2812 type = ieee80211_input(ic, m, ni, rssi - BWI_NOISE_FLOOR,
2813 le16toh(hdr->rxh_tsf));
5f9672cd 2814 ieee80211_free_node(ni);
da367f92
SZ
2815
2816 if (type == IEEE80211_FC0_TYPE_DATA) {
2817 rx_data = 1;
2818 sc->sc_rx_rate = rate;
2819 }
5f9672cd
SZ
2820next:
2821 idx = (idx + 1) % BWI_RX_NDESC;
2822 }
2823
2824 rbd->rbd_idx = idx;
2825 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2826 BUS_DMASYNC_PREWRITE);
da367f92 2827 return rx_data;
5f9672cd
SZ
2828}
2829
da367f92 2830static int
5f9672cd
SZ
2831bwi_rxeof32(struct bwi_softc *sc)
2832{
2833 uint32_t val, rx_ctrl;
da367f92 2834 int end_idx, rx_data;
5f9672cd
SZ
2835
2836 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl;
2837
2838 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2839 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
2840 sizeof(struct bwi_desc32);
2841
da367f92 2842 rx_data = bwi_rxeof(sc, end_idx);
5f9672cd
SZ
2843
2844 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX,
2845 end_idx * sizeof(struct bwi_desc32));
da367f92
SZ
2846
2847 return rx_data;
5f9672cd
SZ
2848}
2849
da367f92 2850static int
5f9672cd
SZ
2851bwi_rxeof64(struct bwi_softc *sc)
2852{
2853 /* TODO:64 */
da367f92 2854 return 0;
5f9672cd
SZ
2855}
2856
2857static void
2858bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl)
2859{
2860 int i;
2861
2862 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0);
2863
2864#define NRETRY 10
2865
2866 for (i = 0; i < NRETRY; ++i) {
2867 uint32_t status;
2868
2869 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2870 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) ==
2871 BWI_RX32_STATUS_STATE_DISABLED)
2872 break;
2873
2874 DELAY(1000);
2875 }
2876 if (i == NRETRY)
2877 if_printf(&sc->sc_ic.ic_if, "reset rx ring timedout\n");
2878
2879#undef NRETRY
2880
2881 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0);
2882}
2883
2884static void
2885bwi_free_txstats32(struct bwi_softc *sc)
2886{
2887 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base);
2888}
2889
2890static void
2891bwi_free_rx_ring32(struct bwi_softc *sc)
2892{
2893 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2894 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2895 int i;
2896
2897 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl);
2898
2899 for (i = 0; i < BWI_RX_NDESC; ++i) {
2900 struct bwi_rxbuf *rb = &rbd->rbd_buf[i];
2901
2902 if (rb->rb_mbuf != NULL) {
2903 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap);
2904 m_freem(rb->rb_mbuf);
2905 rb->rb_mbuf = NULL;
2906 }
2907 }
2908}
2909
2910static void
2911bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx)
2912{
2913 struct bwi_ring_data *rd;
2914 struct bwi_txbuf_data *tbd;
2915 struct ifnet *ifp = &sc->sc_ic.ic_if;
2916 uint32_t state, val;
2917 int i;
2918
2919 KKASSERT(ring_idx < BWI_TX_NRING);
2920 rd = &sc->sc_tx_rdata[ring_idx];
2921 tbd = &sc->sc_tx_bdata[ring_idx];
2922
2923#define NRETRY 10
2924
2925 for (i = 0; i < NRETRY; ++i) {
2926 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2927 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2928 if (state == BWI_TX32_STATUS_STATE_DISABLED ||
2929 state == BWI_TX32_STATUS_STATE_IDLE ||
2930 state == BWI_TX32_STATUS_STATE_STOPPED)
2931 break;
2932
2933 DELAY(1000);
2934 }
2935 if (i == NRETRY) {
2936 if_printf(ifp, "wait for TX ring(%d) stable timed out\n",
2937 ring_idx);
2938 }
2939
2940 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0);
2941 for (i = 0; i < NRETRY; ++i) {
2942 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2943 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2944 if (state == BWI_TX32_STATUS_STATE_DISABLED)
2945 break;
2946
2947 DELAY(1000);
2948 }
2949 if (i == NRETRY)
2950 if_printf(ifp, "reset TX ring (%d) timed out\n", ring_idx);
2951
2952#undef NRETRY
2953
2954 DELAY(1000);
2955
2956 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0);
2957
2958 for (i = 0; i < BWI_TX_NDESC; ++i) {
2959 struct bwi_txbuf *tb = &tbd->tbd_buf[i];
2960
2961 if (tb->tb_mbuf != NULL) {
2962 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
2963 m_freem(tb->tb_mbuf);
2964 tb->tb_mbuf = NULL;
2965 }
2966 if (tb->tb_ni != NULL) {
2967 ieee80211_free_node(tb->tb_ni);
2968 tb->tb_ni = NULL;
2969 }
2970 }
2971}
2972
2973static void
2974bwi_free_txstats64(struct bwi_softc *sc)
2975{
2976 /* TODO:64 */
2977}
2978
2979static void
2980bwi_free_rx_ring64(struct bwi_softc *sc)
2981{
2982 /* TODO:64 */
2983}
2984
2985static void
2986bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx)
2987{
2988 /* TODO:64 */
2989}
2990
5f9672cd
SZ
2991static int
2992bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m,
cf414c9b 2993 struct ieee80211_node **ni0, int mgt_pkt)
5f9672cd
SZ
2994{
2995 struct ieee80211com *ic = &sc->sc_ic;
cf414c9b 2996 struct ieee80211_node *ni = *ni0;
5f9672cd
SZ
2997 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
2998 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
2999 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
3000 struct bwi_mac *mac;
3001 struct bwi_txbuf_hdr *hdr;
3002 struct ieee80211_frame *wh;
3003 uint8_t rate, rate_fb;
3004 uint32_t mac_ctrl;
3005 uint16_t phy_ctrl;
3006 bus_addr_t paddr;
cf414c9b 3007 int pkt_len, error, mcast_pkt = 0;
5f9672cd
SZ
3008#if 0
3009 const uint8_t *p;
3010 int i;
3011#endif
3012
cf414c9b 3013 KKASSERT(ni != NULL);
5f9672cd
SZ
3014 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3015 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3016
3017 wh = mtod(m, struct ieee80211_frame *);
3018
3019 /* Get 802.11 frame len before prepending TX header */
3020 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
3021
3022 /*
3023 * Find TX rate
3024 */
92285ca6 3025 bzero(tb->tb_rateidx, sizeof(tb->tb_rateidx));
cf414c9b 3026 if (!mgt_pkt) {
5f9672cd
SZ
3027 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) {
3028 int idx;
3029
3030 rate = IEEE80211_RS_RATE(&ni->ni_rates,
3031 ic->ic_fixed_rate);
3032
3033 if (ic->ic_fixed_rate >= 1)
3034 idx = ic->ic_fixed_rate - 1;
3035 else
3036 idx = 0;
3037 rate_fb = IEEE80211_RS_RATE(&ni->ni_rates, idx);
3038 } else {
92285ca6
SZ
3039 tb->tb_rateidx_cnt = ieee80211_ratectl_findrate(ni,
3040 m->m_pkthdr.len, tb->tb_rateidx, BWI_NTXRATE);
3041
3042 rate = IEEE80211_RS_RATE(&ni->ni_rates,
3043 tb->tb_rateidx[0]);
3044 if (tb->tb_rateidx_cnt == BWI_NTXRATE) {
3045 rate_fb = IEEE80211_RS_RATE(&ni->ni_rates,
3046 tb->tb_rateidx[1]);
3047 } else {
3048 rate_fb = rate;
3049 }
3050 tb->tb_buflen = m->m_pkthdr.len;
5f9672cd
SZ
3051 }
3052 } else {
ab411d47 3053 /* Fixed at 1Mbits/s for mgt frames */
5f9672cd
SZ
3054 rate = rate_fb = (1 * 2);
3055 }
3056
cf414c9b 3057 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
5f9672cd 3058 rate = rate_fb = ic->ic_mcast_rate;
cf414c9b
SZ
3059 mcast_pkt = 1;
3060 }
5f9672cd
SZ
3061
3062 if (rate == 0 || rate_fb == 0) {
cf414c9b 3063 /* XXX this should not happen */
5f9672cd
SZ
3064 if_printf(&ic->ic_if, "invalid rate %u or fallback rate %u",
3065 rate, rate_fb);
ab411d47 3066 rate = rate_fb = (1 * 2); /* Force 1Mbits/s */
5f9672cd 3067 }
da367f92 3068 sc->sc_tx_rate = rate;
5f9672cd 3069
ab411d47
SZ
3070 /*
3071 * TX radio tap
3072 */
3073 if (sc->sc_drvbpf != NULL) {
3074 sc->sc_tx_th.wt_flags = 0;
3075 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3076 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3077 if (ieee80211_rate2modtype(rate) == IEEE80211_MODTYPE_DS &&
3078 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
3079 rate != (1 * 2)) {
3080 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3081 }
3082 sc->sc_tx_th.wt_rate = rate;
3083
3084 bpf_ptap(sc->sc_drvbpf, m, &sc->sc_tx_th, sc->sc_tx_th_len);
3085 }
5f9672cd
SZ
3086
3087 /*
3088 * Setup the embedded TX header
3089 */
3090 M_PREPEND(m, sizeof(*hdr), MB_DONTWAIT);
3091 if (m == NULL) {
3092 if_printf(&ic->ic_if, "prepend TX header failed\n");
3093 return ENOBUFS;
3094 }
3095 hdr = mtod(m, struct bwi_txbuf_hdr *);
3096
3097 bzero(hdr, sizeof(*hdr));
3098
3099 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3100 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3101
cf414c9b 3102 if (!mcast_pkt) {
5f9672cd
SZ
3103 uint16_t dur;
3104 uint8_t ack_rate;
3105
3106 ack_rate = ieee80211_ack_rate(ni, rate_fb);
3107 dur = ieee80211_txtime(ni,
3108 sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN,
3f1eeae5 3109 ack_rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE);
5f9672cd
SZ
3110
3111 hdr->txh_fb_duration = htole16(dur);
3112 }
3113
3114 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3115 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3116
3117 bwi_plcp_header(hdr->txh_plcp, pkt_len, rate);
3118 bwi_plcp_header(hdr->txh_fb_plcp, pkt_len, rate_fb);
3119
3120 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3121 BWI_TXH_PHY_C_ANTMODE_MASK);
3122 if (ieee80211_rate2modtype(rate) == IEEE80211_MODTYPE_OFDM)
3123 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3124 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1))
3125 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3126
3127 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3128 if (!IEEE80211_IS_MULTICAST(wh->i_addr1))
3129 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3130 if (ieee80211_rate2modtype(rate_fb) == IEEE80211_MODTYPE_OFDM)
3131 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3132
3133 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3134 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3135
3136 /* Catch any further usage */
3137 hdr = NULL;
3138 wh = NULL;
3139
3140 /* DMA load */
3141 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3142 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3143 if (error && error != EFBIG) {
3144 if_printf(&ic->ic_if, "can't load TX buffer (1) %d\n", error);
3145 goto back;
3146 }
3147
3148 if (error) { /* error == EFBIG */
3149 struct mbuf *m_new;
3150
3151 m_new = m_defrag(m, MB_DONTWAIT);
3152 if (m_new == NULL) {
3153 if_printf(&ic->ic_if, "can't defrag TX buffer\n");
3154 error = ENOBUFS;
3155 goto back;
3156 } else {
3157 m = m_new;
3158 }
3159
3160 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3161 bwi_dma_buf_addr, &paddr,
3162 BUS_DMA_NOWAIT);
3163 if (error) {
3164 if_printf(&ic->ic_if, "can't load TX buffer (2) %d\n",
3165 error);
3166 goto back;
3167 }
3168 }
3169 error = 0;
3170
3171 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3172
cf414c9b
SZ
3173 if (mgt_pkt || mcast_pkt) {
3174 /* Don't involve mcast/mgt packets into TX rate control */
3175 ieee80211_free_node(ni);
3176 *ni0 = ni = NULL;
3177 }
5f9672cd
SZ
3178 tb->tb_mbuf = m;
3179 tb->tb_ni = ni;
3180
3181#if 0
3182 p = mtod(m, const uint8_t *);
3183 for (i = 0; i < m->m_pkthdr.len; ++i) {
3184 if (i != 0 && i % 8 == 0)
3185 kprintf("\n");
3186 kprintf("%02x ", p[i]);
3187 }
3188 kprintf("\n");
5f9672cd
SZ
3189#endif
3190
9607893d
SZ
3191 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3192 idx, pkt_len, m->m_pkthdr.len);
3193
5f9672cd
SZ
3194 /* Setup TX descriptor */
3195 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3196 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3197 BUS_DMASYNC_PREWRITE);
3198
3199 /* Kick start */
3200 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3201
3202back:
3203 if (error)
3204 m_freem(m);
3205 return error;
3206}
3207
3208static void
3209bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3210{
3211 idx = (idx + 1) % BWI_TX_NDESC;
3212 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX,
3213 idx * sizeof(struct bwi_desc32));
3214}
3215
3216static void
3217bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3218{
3219 /* TODO:64 */
3220}
3221
3222static void
3223bwi_txeof_status32(struct bwi_softc *sc)
3224{
3225 struct ifnet *ifp = &sc->sc_ic.ic_if;
3226 uint32_t val, ctrl_base;
3227 int end_idx;
3228
3229 ctrl_base = sc->sc_txstats->stats_ctrl_base;
3230
3231 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
3232 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
3233 sizeof(struct bwi_desc32);
3234
3235 bwi_txeof_status(sc, end_idx);
3236
3237 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
3238 end_idx * sizeof(struct bwi_desc32));
3239
9ed293e0 3240 if (!ifq_is_oactive(&ifp->if_snd))
5f9672cd
SZ
3241 ifp->if_start(ifp);
3242}
3243
3244static void
3245bwi_txeof_status64(struct bwi_softc *sc)
3246{
3247 /* TODO:64 */
3248}
3249
3250static void
05277c82 3251_bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt)
5f9672cd
SZ
3252{
3253 struct ifnet *ifp = &sc->sc_ic.ic_if;
3254 struct bwi_txbuf_data *tbd;
3255 struct bwi_txbuf *tb;
3256 int ring_idx, buf_idx;
3257
3258 if (tx_id == 0) {
3259 if_printf(ifp, "zero tx id\n");
3260 return;
3261 }
3262
3263 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK);
3264 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK);
3265
3266 KKASSERT(ring_idx == BWI_TX_DATA_RING);
3267 KKASSERT(buf_idx < BWI_TX_NDESC);
5f9672cd
SZ
3268
3269 tbd = &sc->sc_tx_bdata[ring_idx];
3270 KKASSERT(tbd->tbd_used > 0);
3271 tbd->tbd_used--;
3272
3273 tb = &tbd->tbd_buf[buf_idx];
3274
9607893d
SZ
3275 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, "
3276 "acked %d, data_txcnt %d, ni %p\n",
3277 buf_idx, acked, data_txcnt, tb->tb_ni);
3278
5f9672cd
SZ
3279 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
3280 m_freem(tb->tb_mbuf);
3281 tb->tb_mbuf = NULL;
3282
3283 if (tb->tb_ni != NULL) {
92285ca6
SZ
3284 struct ieee80211_ratectl_res res[BWI_NTXRATE];
3285 int res_len, retry;
3286
3287 if (data_txcnt <= BWI_SHRETRY_FB || tb->tb_rateidx_cnt == 1) {
3288 res_len = 1;
3289 res[0].rc_res_rateidx = tb->tb_rateidx[0];
3290 res[0].rc_res_tries = data_txcnt;
3291 } else {
3292 res_len = BWI_NTXRATE;
3293 res[0].rc_res_rateidx = tb->tb_rateidx[0];
3294 res[0].rc_res_tries = BWI_SHRETRY_FB;
3295 res[1].rc_res_rateidx = tb->tb_rateidx[1];
3296 res[1].rc_res_tries = data_txcnt - BWI_SHRETRY_FB;
3297 }
3298
ed08f5bc 3299 if (acked) {
d40991ef 3300 IFNET_STAT_INC(ifp, opackets, 1);
92285ca6 3301 retry = data_txcnt > 0 ? data_txcnt - 1 : 0;
ed08f5bc 3302 } else {
d40991ef 3303 IFNET_STAT_INC(ifp, oerrors, 1);
92285ca6 3304 retry = data_txcnt;
ed08f5bc 3305 }
92285ca6
SZ
3306
3307 ieee80211_ratectl_tx_complete(tb->tb_ni, tb->tb_buflen,
3308 res, res_len, retry, 0, !acked);
3309
5f9672cd
SZ
3310 ieee80211_free_node(tb->tb_ni);
3311 tb->tb_ni = NULL;
ed08f5bc
SZ
3312 } else {
3313 /* XXX mgt packet error */
d40991ef 3314 IFNET_STAT_INC(ifp, opackets, 1);
5f9672cd
SZ
3315 }
3316
3317 if (tbd->tbd_used == 0)
3318 sc->sc_tx_timer = 0;
3319
9ed293e0 3320 ifq_clr_oactive(&ifp->if_snd);
5f9672cd
SZ
3321}
3322
3323static void
3324bwi_txeof_status(struct bwi_softc *sc, int end_idx)
3325{
3326 struct bwi_txstats_data *st = sc->sc_txstats;
3327 int idx;
3328
3329 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD);
3330
3331 idx = st->stats_idx;
3332 while (idx != end_idx) {
05277c82
SZ
3333 const struct bwi_txstats *stats = &st->stats[idx];
3334
3335 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) {
3336 int data_txcnt;
3337
3338 data_txcnt = __SHIFTOUT(stats->txs_txcnt,
3339 BWI_TXS_TXCNT_DATA);
3340 _bwi_txeof(sc, le16toh(stats->txs_id),
3341 stats->txs_flags & BWI_TXS_F_ACKED,
3342 data_txcnt);
3343 }
5f9672cd
SZ
3344 idx = (idx + 1) % BWI_TXSTATS_NDESC;
3345 }
3346 st->stats_idx = idx;
3347}
3348
3349static void
3350bwi_txeof(struct bwi_softc *sc)
3351{
3352 struct ifnet *ifp = &sc->sc_ic.ic_if;
3353
3354 for (;;) {
3355 uint32_t tx_status0, tx_status1;
5cfb4d2e
SZ
3356 uint16_t tx_id;
3357 int data_txcnt;
5f9672cd 3358
5cfb4d2e
SZ
3359 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0);
3360 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0)
5f9672cd 3361 break;
5cfb4d2e 3362 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1);
5f9672cd 3363
5cfb4d2e
SZ
3364 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK);
3365 data_txcnt = __SHIFTOUT(tx_status0,
3366 BWI_TXSTATUS0_DATA_TXCNT_MASK);
5f9672cd 3367
5cfb4d2e 3368 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING))
5f9672cd
SZ
3369 continue;
3370
5cfb4d2e
SZ
3371 _bwi_txeof(sc, tx_id, tx_status0 & BWI_TXSTATUS0_ACKED,
3372 data_txcnt);
5f9672cd
SZ
3373 }
3374
9ed293e0 3375 if (!ifq_is_oactive(&ifp->if_snd))
5f9672cd
SZ
3376 ifp->if_start(ifp);
3377}
3378
3379static int
3380bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
3381{
3382 bwi_power_on(sc, 1);
3383 return bwi_set_clock_mode(sc, clk_mode);
3384}
3385
3386static void
3387bwi_bbp_power_off(struct bwi_softc *sc)
3388{
3389 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW);
3390 bwi_power_off(sc, 1);
3391}
3392
3393static int
3394bwi_get_pwron_delay(struct bwi_softc *sc)
3395{
3396 struct bwi_regwin *com, *old;
3397 struct bwi_clock_freq freq;
3398 uint32_t val;
3399 int error;
3400
3401 com = &sc->sc_com_regwin;
3402 KKASSERT(BWI_REGWIN_EXIST(com));
3403
3404 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
3405 return 0;
3406
3407 error = bwi_regwin_switch(sc, com, &old);
3408 if (error)
3409 return error;
3410
3411 bwi_get_clock_freq(sc, &freq);
3412
3413 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
3414 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min);
9607893d 3415 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay);
5f9672cd
SZ
3416
3417 return bwi_regwin_switch(sc, old, NULL);
3418}
3419
3420static int
3421bwi_bus_attach(struct bwi_softc *sc)
3422{
3423 struct bwi_regwin *bus, *old;
3424 int error;
3425
3426 bus = &sc->sc_bus_regwin;
3427
3428 error = bwi_regwin_switch(sc, bus, &old);
3429 if (error)
3430 return error;
3431
3432 if (!bwi_regwin_is_enabled(sc, bus))
3433 bwi_regwin_enable(sc, bus, 0);
3434
3435 /* Disable interripts */
3436 CSR_WRITE_4(sc, BWI_INTRVEC, 0);
3437
3438 return bwi_regwin_switch(sc, old, NULL);
3439}
3440
3441static const char *
3442bwi_regwin_name(const struct bwi_regwin *rw)
3443{
3444 switch (rw->rw_type) {
3445 case BWI_REGWIN_T_COM:
3446 return "COM";
3447 case BWI_REGWIN_T_BUSPCI:
3448 return "PCI";
3449 case BWI_REGWIN_T_MAC:
3450 return "MAC";
3451 case BWI_REGWIN_T_BUSPCIE:
3452 return "PCIE";
3453 }
ed20d0e3 3454 panic("unknown regwin type 0x%04x", rw->rw_type);
5f9672cd
SZ
3455 return NULL;
3456}
3457
3458static uint32_t
3459bwi_regwin_disable_bits(struct bwi_softc *sc)
3460{
3461 uint32_t busrev;
3462
3463 /* XXX cache this */
3464 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
9607893d
SZ
3465 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC,
3466 "bus rev %u\n", busrev);
5f9672cd
SZ
3467
3468 if (busrev == BWI_BUSREV_0)
3469 return BWI_STATE_LO_DISABLE1;
3470 else if (busrev == BWI_BUSREV_1)
3471 return BWI_STATE_LO_DISABLE2;
3472 else
3473 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2);
3474}
3475
3476int
3477bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw)
3478{
3479 uint32_t val, disable_bits;
3480
3481 disable_bits = bwi_regwin_disable_bits(sc);
3482 val = CSR_READ_4(sc, BWI_STATE_LO);
3483
3484 if ((val & (BWI_STATE_LO_CLOCK |
3485 BWI_STATE_LO_RESET |
3486 disable_bits)) == BWI_STATE_LO_CLOCK) {
9607893d
SZ
3487 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n",
3488 bwi_regwin_name(rw));
5f9672cd
SZ
3489 return 1;
3490 } else {
9607893d
SZ
3491 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n",
3492 bwi_regwin_name(rw));
5f9672cd
SZ
3493 return 0;
3494 }
3495}
3496
3497void
3498bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3499{
3500 uint32_t state_lo, disable_bits;
3501 int i;
3502
3503 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3504
3505 /*
3506 * If current regwin is in 'reset' state, it was already disabled.
3507 */
3508 if (state_lo & BWI_STATE_LO_RESET) {
9607893d
SZ
3509 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT,
3510 "%s was already disabled\n", bwi_regwin_name(rw));
5f9672cd
SZ
3511 return;
3512 }
3513
3514 disable_bits = bwi_regwin_disable_bits(sc);
3515
3516 /*
3517 * Disable normal clock
3518 */
3519 state_lo = BWI_STATE_LO_CLOCK | disable_bits;
3520 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3521
3522 /*
3523 * Wait until normal clock is disabled
3524 */
3525#define NRETRY 1000
3526 for (i = 0; i < NRETRY; ++i) {
3527 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3528 if (state_lo & disable_bits)
3529 break;
3530 DELAY(10);
3531 }
3532 if (i == NRETRY) {
3533 device_printf(sc->sc_dev, "%s disable clock timeout\n",
3534 bwi_regwin_name(rw));
3535 }
3536
3537 for (i = 0; i < NRETRY; ++i) {
3538 uint32_t state_hi;
3539
3540 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3541 if ((state_hi & BWI_STATE_HI_BUSY) == 0)
3542 break;
3543 DELAY(10);
3544 }
3545 if (i == NRETRY) {
3546 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n",
3547 bwi_regwin_name(rw));
3548 }
3549#undef NRETRY
3550
3551 /*
3552 * Reset and disable regwin with gated clock
3553 */
3554 state_lo = BWI_STATE_LO_RESET | disable_bits |
3555 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK |
3556 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3557 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3558
3559 /* Flush pending bus write */
3560 CSR_READ_4(sc, BWI_STATE_LO);
3561 DELAY(1);
3562
3563 /* Reset and disable regwin */
3564 state_lo = BWI_STATE_LO_RESET | disable_bits |
3565 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3566 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3567
3568 /* Flush pending bus write */
3569 CSR_READ_4(sc, BWI_STATE_LO);
3570 DELAY(1);
3571}
3572
3573void
3574bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3575{
3576 uint32_t state_lo, state_hi, imstate;
3577
3578 bwi_regwin_disable(sc, rw, flags);
3579
3580 /* Reset regwin with gated clock */
3581 state_lo = BWI_STATE_LO_RESET |
3582 BWI_STATE_LO_CLOCK |
3583 BWI_STATE_LO_GATED_CLOCK |
3584 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3585 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3586
3587 /* Flush pending bus write */
3588 CSR_READ_4(sc, BWI_STATE_LO);
3589 DELAY(1);
3590
3591 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3592 if (state_hi & BWI_STATE_HI_SERROR)
3593 CSR_WRITE_4(sc, BWI_STATE_HI, 0);
3594
3595 imstate = CSR_READ_4(sc, BWI_IMSTATE);
3596 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) {
3597 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT);
3598 CSR_WRITE_4(sc, BWI_IMSTATE, imstate);
3599 }
3600
3601 /* Enable regwin with gated clock */
3602 state_lo = BWI_STATE_LO_CLOCK |
3603 BWI_STATE_LO_GATED_CLOCK |
3604 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3605 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3606
3607 /* Flush pending bus write */
3608 CSR_READ_4(sc, BWI_STATE_LO);
3609 DELAY(1);
3610
3611 /* Enable regwin with normal clock */
3612 state_lo = BWI_STATE_LO_CLOCK |
3613 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3614 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3615
3616 /* Flush pending bus write */
3617 CSR_READ_4(sc, BWI_STATE_LO);
3618 DELAY(1);
3619}
3620
3621static void
3622bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid)
3623{
3624 struct ieee80211com *ic = &sc->sc_ic;
3625 struct bwi_mac *mac;
3626 struct bwi_myaddr_bssid buf;
3627 const uint8_t *p;
3628 uint32_t val;
3629 int n, i;
3630
3631 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3632 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3633
3634 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid);
3635
3636 bcopy(ic->ic_myaddr, buf.myaddr, sizeof(buf.myaddr));
3637 bcopy(bssid, buf.bssid, sizeof(buf.bssid));
3638
3639 n = sizeof(buf) / sizeof(val);
3640 p = (const uint8_t *)&buf;
3641 for (i = 0; i < n; ++i) {
3642 int j;
3643
3644 val = 0;
3645 for (j = 0; j < sizeof(val); ++j)
3646 val |= ((uint32_t)(*p++)) << (j * 8);
3647
3648 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val);
3649 }
3650}
3651
3652static void
3653bwi_updateslot(struct ifnet *ifp)
3654{
3655 struct bwi_softc *sc = ifp->if_softc;
3656 struct ieee80211com *ic = &sc->sc_ic;
3657 struct bwi_mac *mac;
3658
3659 if ((ifp->if_flags & IFF_RUNNING) == 0)
3660 return;
3661
3662 ASSERT_SERIALIZED(ifp->if_serializer);
3663
9607893d 3664 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__);
5f9672cd
SZ
3665
3666 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3667 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3668
3669 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT));
3670}
3671
3672static void
3673bwi_calibrate(void *xsc)
3674{
3675 struct bwi_softc *sc = xsc;
3676 struct ieee80211com *ic = &sc->sc_ic;
3677 struct ifnet *ifp = &ic->ic_if;
3678
3679 lwkt_serialize_enter(ifp->if_serializer);
3680
3681 if (ic->ic_state == IEEE80211_S_RUN) {
3682 struct bwi_mac *mac;
3683
3684 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3685 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3686
ba620a94
SZ
3687 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
3688 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type);
3689 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
3690 }
5f9672cd
SZ
3691
3692 /* XXX 15 seconds */
3693 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
3694 }
3695
3696 lwkt_serialize_exit(ifp->if_serializer);
3697}
641ea785
SZ
3698
3699static int
3700bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr)
3701{
3702 struct bwi_mac *mac;
3703
3704 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3705 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3706
3707 return bwi_rf_calc_rssi(mac, hdr);
3708}
ab411d47 3709
ab411d47
SZ
3710static void
3711bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m,
da367f92
SZ
3712 struct bwi_rxbuf_hdr *hdr, const void *plcp,
3713 int rate, int rssi)
ab411d47
SZ
3714{
3715 const struct ieee80211_frame_min *wh;
ab411d47
SZ
3716
3717 KKASSERT(sc->sc_drvbpf != NULL);
3718
ab411d47 3719 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS;
da367f92 3720 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE)
ab411d47
SZ
3721 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3722
3723 wh = mtod(m, const struct ieee80211_frame_min *);
3724 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3725 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP;
3726
3727 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */
3728 sc->sc_rx_th.wr_rate = rate;
3729 sc->sc_rx_th.wr_antsignal = rssi;
3730 sc->sc_rx_th.wr_antnoise = BWI_NOISE_FLOOR;
3731
3732 bpf_ptap(sc->sc_drvbpf, m, &sc->sc_rx_th, sc->sc_rx_th_len);
3733}
777ee4a9
SZ
3734
3735static void
3736bwi_led_attach(struct bwi_softc *sc)
3737{
da367f92 3738 const uint8_t *led_act = NULL;
777ee4a9
SZ
3739 uint16_t gpio, val[BWI_LED_MAX];
3740 int i;
3741
c157ff7a 3742 for (i = 0; i < NELEM(bwi_vendor_led_act); ++i) {
da367f92
SZ
3743 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) {
3744 led_act = bwi_vendor_led_act[i].led_act;
3745 break;
3746 }
3747 }
3748 if (led_act == NULL)
3749 led_act = bwi_default_led_act;
3750
777ee4a9
SZ
3751 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01);
3752 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0);
3753 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1);
3754
3755 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23);
3756 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2);
3757 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3);
3758
3759 for (i = 0; i < BWI_LED_MAX; ++i) {
3760 struct bwi_led *led = &sc->sc_leds[i];
3761
3762 if (val[i] == 0xff) {
da367f92 3763 led->l_act = led_act[i];
777ee4a9
SZ
3764 } else {
3765 if (val[i] & BWI_LED_ACT_LOW)
3766 led->l_flags |= BWI_LED_F_ACTLOW;
3767 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK);
3768 }
da367f92
SZ
3769 led->l_mask = (1 << i);
3770
3771 if (led->l_act == BWI_LED_ACT_BLINK_SLOW ||
3772 led->l_act == BWI_LED_ACT_BLINK_POLL ||
3773 led->l_act == BWI_LED_ACT_BLINK) {
3774 led->l_flags |= BWI_LED_F_BLINK;
3775 if (led->l_act == BWI_LED_ACT_BLINK_POLL)
3776 led->l_flags |= BWI_LED_F_POLLABLE;
3777 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW)
3778 led->l_flags |= BWI_LED_F_SLOW;
3779
3780 if (sc->sc_blink_led == NULL) {
3781 sc->sc_blink_led = led;
3782 if (led->l_flags & BWI_LED_F_SLOW)
3783 BWI_LED_SLOWDOWN(sc->sc_led_idle);
3784 }
3785 }
777ee4a9
SZ
3786
3787 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH,
3788 "%dth led, act %d, lowact %d\n", i,
3789 led->l_act, led->l_flags & BWI_LED_F_ACTLOW);
3790 }
da367f92
SZ
3791 callout_init(&sc->sc_led_blink_ch);
3792}
3793
3794static __inline uint16_t
3795bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on)
3796{
3797 if (led->l_flags & BWI_LED_F_ACTLOW)
3798 on = !on;
3799 if (on)
3800 val |= led->l_mask;
3801 else
3802 val &= ~led->l_mask;
3803 return val;
777ee4a9
SZ
3804}
3805
3806static void
3807bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate)
3808{
3809 struct ieee80211com *ic = &sc->sc_ic;
3810 uint16_t val;
3811 int i;
3812
da367f92
SZ
3813 if (nstate == IEEE80211_S_INIT) {
3814 callout_stop(&sc->sc_led_blink_ch);
3815 sc->sc_led_blinking = 0;
3816 }
3817
777ee4a9
SZ
3818 if ((ic->ic_if.if_flags & IFF_RUNNING) == 0)
3819 return;
3820
3821 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3822 for (i = 0; i < BWI_LED_MAX; ++i) {
3823 struct bwi_led *led = &sc->sc_leds[i];
3824 int on;
3825
3826 if (led->l_act == BWI_LED_ACT_UNKN ||
da367f92
SZ
3827 led->l_act == BWI_LED_ACT_NULL)
3828 continue;
3829
3830 if ((led->l_flags & BWI_LED_F_BLINK) &&
3831 nstate != IEEE80211_S_INIT)
777ee4a9 3832 continue;
777ee4a9
SZ
3833
3834 switch (led->l_act) {
da367f92 3835 case BWI_LED_ACT_ON: /* Always on */
777ee4a9
SZ
3836 on = 1;
3837 break;
da367f92
SZ
3838 case BWI_LED_ACT_OFF: /* Always off */
3839 case BWI_LED_ACT_5GHZ: /* TODO: 11A */
777ee4a9
SZ
3840 on = 0;
3841 break;
3842 default:
3843 on = 1;
3844 switch (nstate) {
3845 case IEEE80211_S_INIT:
3846 on = 0;
3847 break;
3848 case IEEE80211_S_RUN:
3849 if (led->l_act == BWI_LED_ACT_11G &&
3850 ic->ic_curmode != IEEE80211_MODE_11G)
3851 on = 0;
3852 break;
3853 default:
da367f92 3854 if (led->l_act == BWI_LED_ACT_ASSOC)
777ee4a9
SZ
3855 on = 0;
3856 break;
3857 }
3858 break;
3859 }
3860
da367f92
SZ
3861 val = bwi_led_onoff(led, val, on);
3862 }
3863 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3864}
3865
3866static void
3867bwi_led_event(struct bwi_softc *sc, int event)
3868{
3869 struct bwi_led *led = sc->sc_blink_led;
3870 int rate;
777ee4a9 3871
da367f92
SZ
3872 if (event == BWI_LED_EVENT_POLL) {
3873 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0)
3874 return;
3875 if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
3876 return;
3877 }
3878
3879 sc->sc_led_ticks = ticks;
3880 if (sc->sc_led_blinking)
3881 return;
3882
3883 switch (event) {
3884 case BWI_LED_EVENT_RX:
3885 rate = sc->sc_rx_rate;
3886 break;
3887 case BWI_LED_EVENT_TX:
3888 rate = sc->sc_tx_rate;
3889 break;
3890 case BWI_LED_EVENT_POLL:
3891 rate = 0;
3892 break;
3893 default:
ed20d0e3 3894 panic("unknown LED event %d", event);
da367f92
SZ
3895 break;
3896 }
3897 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur,
3898 bwi_led_duration[rate].off_dur);
3899}
3900
3901static void
3902bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur)
3903{
3904 struct bwi_led *led = sc->sc_blink_led;
3905 uint16_t val;
3906
3907 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3908 val = bwi_led_onoff(led, val, 1);
3909 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3910
3911 if (led->l_flags & BWI_LED_F_SLOW) {
3912 BWI_LED_SLOWDOWN(on_dur);
3913 BWI_LED_SLOWDOWN(off_dur);
777ee4a9 3914 }
da367f92
SZ
3915
3916 sc->sc_led_blinking = 1;
3917 sc->sc_led_blink_offdur = off_dur;
3918
3919 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc);
3920}
3921
3922static void
3923bwi_led_blink_next(void *xsc)
3924{
3925 struct bwi_softc *sc = xsc;
3926 uint16_t val;
3927
3928 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3929 val = bwi_led_onoff(sc->sc_blink_led, val, 0);
777ee4a9 3930 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
da367f92
SZ
3931
3932 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
3933 bwi_led_blink_end, sc);
3934}
3935
3936static void
3937bwi_led_blink_end(void *xsc)
3938{
3939 struct bwi_softc *sc = xsc;
3940
3941 sc->sc_led_blinking = 0;
777ee4a9