kernel tree reorganization stage 1: Major cvs repository work (not logged as
[dragonfly.git] / sys / i386 / i386 / identcpu.c
CommitLineData
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1/*
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * Copyright (c) 2001 Tamotsu Hattori.
6 * Copyright (c) 2001 Mitsuru IWASAKI.
7 * All rights reserved.
8 *
9 * This code is derived from software contributed to Berkeley by
10 * William Jolitz.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the University of
23 * California, Berkeley and its contributors.
24 * 4. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 *
40 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41 * $FreeBSD: src/sys/i386/i386/identcpu.c,v 1.80.2.15 2003/04/11 17:06:41 jhb Exp $
11e9db57 42 * $DragonFly: src/sys/i386/i386/Attic/identcpu.c,v 1.4 2003/07/13 05:51:17 dillon Exp $
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43 */
44
45#include "opt_cpu.h"
46
47#include <sys/param.h>
48#include <sys/systm.h>
49#include <sys/kernel.h>
50#include <sys/sysctl.h>
11e9db57 51#include <sys/lock.h>
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52
53#include <machine/asmacros.h>
54#include <machine/clock.h>
55#include <machine/cputypes.h>
56#include <machine/segments.h>
57#include <machine/specialreg.h>
58#include <machine/md_var.h>
59
60#include <i386/isa/intr_machdep.h>
61
62#define IDENTBLUE_CYRIX486 0
63#define IDENTBLUE_IBMCPU 1
64#define IDENTBLUE_CYRIXM2 2
65
66/* XXX - should be in header file: */
67void printcpuinfo(void);
68void finishidentcpu(void);
69#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
70void enable_K5_wt_alloc(void);
71void enable_K6_wt_alloc(void);
72void enable_K6_2_wt_alloc(void);
73#endif
74void panicifcpuunsupported(void);
75
76static void identifycyrix(void);
77#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
78static void print_AMD_features(void);
79#endif
80static void print_AMD_info(void);
81static void print_AMD_assoc(int i);
82static void print_transmeta_info(void);
83static void setup_tmx86_longrun(void);
84
85int cpu_class = CPUCLASS_386;
86u_int cpu_exthigh; /* Highest arg to extended CPUID */
87u_int cyrix_did; /* Device ID of Cyrix CPU */
88char machine[] = "i386";
89SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
90 machine, 0, "Machine class");
91
92static char cpu_model[128];
93SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
94 cpu_model, 0, "Machine model");
95
96static char cpu_brand[48];
97
98#define MAX_BRAND_INDEX 8
99
100static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
101 NULL, /* No brand */
102 "Intel Celeron",
103 "Intel Pentium III",
104 "Intel Pentium III Xeon",
105 NULL,
106 NULL,
107 NULL,
108 NULL,
109 "Intel Pentium 4"
110};
111
112static struct cpu_nameclass i386_cpus[] = {
113 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
114 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
115 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
116 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
117 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
118 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
119 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
120 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
121 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
122 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
123 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
124 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
125 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
126 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
127 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
128 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
129 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
130};
131
132#if defined(I586_CPU) && !defined(NO_F00F_HACK)
133int has_f00f_bug = 0; /* Initialized so that it can be patched. */
134#endif
135
136void
137printcpuinfo(void)
138{
139#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
140 u_int regs[4], i;
141#endif
142 char *brand;
143
144 cpu_class = i386_cpus[cpu].cpu_class;
145 printf("CPU: ");
146 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
147
148#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
149 /* Check for extended CPUID information and a processor name. */
150 if (cpu_high > 0 &&
151 (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
152 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
153 strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
154 strcmp(cpu_vendor, "TransmetaCPU") == 0)) {
155 do_cpuid(0x80000000, regs);
156 if (regs[0] >= 0x80000000) {
157 cpu_exthigh = regs[0];
158 if (cpu_exthigh >= 0x80000004) {
159 brand = cpu_brand;
160 for (i = 0x80000002; i < 0x80000005; i++) {
161 do_cpuid(i, regs);
162 memcpy(brand, regs, sizeof(regs));
163 brand += sizeof(regs);
164 }
165 }
166 }
167 }
168
169 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
170 if ((cpu_id & 0xf00) > 0x300) {
171 u_int brand_index;
172
173 cpu_model[0] = '\0';
174
175 switch (cpu_id & 0x3000) {
176 case 0x1000:
177 strcpy(cpu_model, "Overdrive ");
178 break;
179 case 0x2000:
180 strcpy(cpu_model, "Dual ");
181 break;
182 }
183
184 switch (cpu_id & 0xf00) {
185 case 0x400:
186 strcat(cpu_model, "i486 ");
187 /* Check the particular flavor of 486 */
188 switch (cpu_id & 0xf0) {
189 case 0x00:
190 case 0x10:
191 strcat(cpu_model, "DX");
192 break;
193 case 0x20:
194 strcat(cpu_model, "SX");
195 break;
196 case 0x30:
197 strcat(cpu_model, "DX2");
198 break;
199 case 0x40:
200 strcat(cpu_model, "SL");
201 break;
202 case 0x50:
203 strcat(cpu_model, "SX2");
204 break;
205 case 0x70:
206 strcat(cpu_model,
207 "DX2 Write-Back Enhanced");
208 break;
209 case 0x80:
210 strcat(cpu_model, "DX4");
211 break;
212 }
213 break;
214 case 0x500:
215 /* Check the particular flavor of 586 */
216 strcat(cpu_model, "Pentium");
217 switch (cpu_id & 0xf0) {
218 case 0x00:
219 strcat(cpu_model, " A-step");
220 break;
221 case 0x10:
222 strcat(cpu_model, "/P5");
223 break;
224 case 0x20:
225 strcat(cpu_model, "/P54C");
226 break;
227 case 0x30:
228 strcat(cpu_model, "/P54T Overdrive");
229 break;
230 case 0x40:
231 strcat(cpu_model, "/P55C");
232 break;
233 case 0x70:
234 strcat(cpu_model, "/P54C");
235 break;
236 case 0x80:
237 strcat(cpu_model, "/P55C (quarter-micron)");
238 break;
239 default:
240 /* nothing */
241 break;
242 }
243#if defined(I586_CPU) && !defined(NO_F00F_HACK)
244 /*
245 * XXX - If/when Intel fixes the bug, this
246 * should also check the version of the
247 * CPU, not just that it's a Pentium.
248 */
249 has_f00f_bug = 1;
250#endif
251 break;
252 case 0x600:
253 /* Check the particular flavor of 686 */
254 switch (cpu_id & 0xf0) {
255 case 0x00:
256 strcat(cpu_model, "Pentium Pro A-step");
257 break;
258 case 0x10:
259 strcat(cpu_model, "Pentium Pro");
260 break;
261 case 0x30:
262 case 0x50:
263 case 0x60:
264 strcat(cpu_model,
265 "Pentium II/Pentium II Xeon/Celeron");
266 cpu = CPU_PII;
267 break;
268 case 0x70:
269 case 0x80:
270 case 0xa0:
271 case 0xb0:
272 strcat(cpu_model,
273 "Pentium III/Pentium III Xeon/Celeron");
274 cpu = CPU_PIII;
275 break;
276 default:
277 strcat(cpu_model, "Unknown 80686");
278 break;
279 }
280 break;
281 case 0xf00:
282 strcat(cpu_model, "Pentium 4");
283 cpu = CPU_P4;
284 break;
285 default:
286 strcat(cpu_model, "unknown");
287 break;
288 }
289
290 /*
291 * If we didn't get a brand name from the extended
292 * CPUID, try to look it up in the brand table.
293 */
294 if (cpu_high > 0 && *cpu_brand == '\0') {
295 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
296 if (brand_index <= MAX_BRAND_INDEX &&
297 cpu_brandtable[brand_index] != NULL)
298 strcpy(cpu_brand,
299 cpu_brandtable[brand_index]);
300 }
301 }
302 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
303 /*
304 * Values taken from AMD Processor Recognition
305 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
306 * (also describes ``Features'' encodings.
307 */
308 strcpy(cpu_model, "AMD ");
309 switch (cpu_id & 0xFF0) {
310 case 0x410:
311 strcat(cpu_model, "Standard Am486DX");
312 break;
313 case 0x430:
314 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
315 break;
316 case 0x470:
317 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
318 break;
319 case 0x480:
320 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
321 break;
322 case 0x490:
323 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
324 break;
325 case 0x4E0:
326 strcat(cpu_model, "Am5x86 Write-Through");
327 break;
328 case 0x4F0:
329 strcat(cpu_model, "Am5x86 Write-Back");
330 break;
331 case 0x500:
332 strcat(cpu_model, "K5 model 0");
333 tsc_is_broken = 1;
334 break;
335 case 0x510:
336 strcat(cpu_model, "K5 model 1");
337 break;
338 case 0x520:
339 strcat(cpu_model, "K5 PR166 (model 2)");
340 break;
341 case 0x530:
342 strcat(cpu_model, "K5 PR200 (model 3)");
343 break;
344 case 0x560:
345 strcat(cpu_model, "K6");
346 break;
347 case 0x570:
348 strcat(cpu_model, "K6 266 (model 1)");
349 break;
350 case 0x580:
351 strcat(cpu_model, "K6-2");
352 break;
353 case 0x590:
354 strcat(cpu_model, "K6-III");
355 break;
356 default:
357 strcat(cpu_model, "Unknown");
358 break;
359 }
360#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
361 if ((cpu_id & 0xf00) == 0x500) {
362 if (((cpu_id & 0x0f0) > 0)
363 && ((cpu_id & 0x0f0) < 0x60)
364 && ((cpu_id & 0x00f) > 3))
365 enable_K5_wt_alloc();
366 else if (((cpu_id & 0x0f0) > 0x80)
367 || (((cpu_id & 0x0f0) == 0x80)
368 && (cpu_id & 0x00f) > 0x07))
369 enable_K6_2_wt_alloc();
370 else if ((cpu_id & 0x0f0) > 0x50)
371 enable_K6_wt_alloc();
372 }
373#endif
374 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
375 strcpy(cpu_model, "Cyrix ");
376 switch (cpu_id & 0xff0) {
377 case 0x440:
378 strcat(cpu_model, "MediaGX");
379 break;
380 case 0x520:
381 strcat(cpu_model, "6x86");
382 break;
383 case 0x540:
384 cpu_class = CPUCLASS_586;
385 strcat(cpu_model, "GXm");
386 break;
387 case 0x600:
388 strcat(cpu_model, "6x86MX");
389 break;
390 default:
391 /*
392 * Even though CPU supports the cpuid
393 * instruction, it can be disabled.
394 * Therefore, this routine supports all Cyrix
395 * CPUs.
396 */
397 switch (cyrix_did & 0xf0) {
398 case 0x00:
399 switch (cyrix_did & 0x0f) {
400 case 0x00:
401 strcat(cpu_model, "486SLC");
402 break;
403 case 0x01:
404 strcat(cpu_model, "486DLC");
405 break;
406 case 0x02:
407 strcat(cpu_model, "486SLC2");
408 break;
409 case 0x03:
410 strcat(cpu_model, "486DLC2");
411 break;
412 case 0x04:
413 strcat(cpu_model, "486SRx");
414 break;
415 case 0x05:
416 strcat(cpu_model, "486DRx");
417 break;
418 case 0x06:
419 strcat(cpu_model, "486SRx2");
420 break;
421 case 0x07:
422 strcat(cpu_model, "486DRx2");
423 break;
424 case 0x08:
425 strcat(cpu_model, "486SRu");
426 break;
427 case 0x09:
428 strcat(cpu_model, "486DRu");
429 break;
430 case 0x0a:
431 strcat(cpu_model, "486SRu2");
432 break;
433 case 0x0b:
434 strcat(cpu_model, "486DRu2");
435 break;
436 default:
437 strcat(cpu_model, "Unknown");
438 break;
439 }
440 break;
441 case 0x10:
442 switch (cyrix_did & 0x0f) {
443 case 0x00:
444 strcat(cpu_model, "486S");
445 break;
446 case 0x01:
447 strcat(cpu_model, "486S2");
448 break;
449 case 0x02:
450 strcat(cpu_model, "486Se");
451 break;
452 case 0x03:
453 strcat(cpu_model, "486S2e");
454 break;
455 case 0x0a:
456 strcat(cpu_model, "486DX");
457 break;
458 case 0x0b:
459 strcat(cpu_model, "486DX2");
460 break;
461 case 0x0f:
462 strcat(cpu_model, "486DX4");
463 break;
464 default:
465 strcat(cpu_model, "Unknown");
466 break;
467 }
468 break;
469 case 0x20:
470 if ((cyrix_did & 0x0f) < 8)
471 strcat(cpu_model, "6x86"); /* Where did you get it? */
472 else
473 strcat(cpu_model, "5x86");
474 break;
475 case 0x30:
476 strcat(cpu_model, "6x86");
477 break;
478 case 0x40:
479 if ((cyrix_did & 0xf000) == 0x3000) {
480 cpu_class = CPUCLASS_586;
481 strcat(cpu_model, "GXm");
482 } else
483 strcat(cpu_model, "MediaGX");
484 break;
485 case 0x50:
486 strcat(cpu_model, "6x86MX");
487 break;
488 case 0xf0:
489 switch (cyrix_did & 0x0f) {
490 case 0x0d:
491 strcat(cpu_model, "Overdrive CPU");
492 case 0x0e:
493 strcpy(cpu_model, "Texas Instruments 486SXL");
494 break;
495 case 0x0f:
496 strcat(cpu_model, "486SLC/DLC");
497 break;
498 default:
499 strcat(cpu_model, "Unknown");
500 break;
501 }
502 break;
503 default:
504 strcat(cpu_model, "Unknown");
505 break;
506 }
507 break;
508 }
509 } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
510 strcpy(cpu_model, "Rise ");
511 switch (cpu_id & 0xff0) {
512 case 0x500:
513 strcat(cpu_model, "mP6");
514 break;
515 default:
516 strcat(cpu_model, "Unknown");
517 }
518 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
519 switch (cpu_id & 0xff0) {
520 case 0x540:
521 strcpy(cpu_model, "IDT WinChip C6");
522 tsc_is_broken = 1;
523 break;
524 case 0x580:
525 strcpy(cpu_model, "IDT WinChip 2");
526 break;
527 case 0x670:
528 strcpy(cpu_model, "VIA C3 Samuel 2");
529 break;
530 default:
531 strcpy(cpu_model, "VIA/IDT Unknown");
532 }
533 } else if (strcmp(cpu_vendor, "IBM") == 0) {
534 strcpy(cpu_model, "Blue Lightning CPU");
535 }
536
537 /*
538 * Replace cpu_model with cpu_brand minus leading spaces if
539 * we have one.
540 */
541 brand = cpu_brand;
542 while (*brand == ' ')
543 ++brand;
544 if (*brand != '\0')
545 strcpy(cpu_model, brand);
546
547#endif
548
549 printf("%s (", cpu_model);
550 switch(cpu_class) {
551 case CPUCLASS_286:
552 printf("286");
553 break;
554#if defined(I386_CPU)
555 case CPUCLASS_386:
556 printf("386");
557 break;
558#endif
559#if defined(I486_CPU)
560 case CPUCLASS_486:
561 printf("486");
562 bzero = i486_bzero;
563 break;
564#endif
565#if defined(I586_CPU)
566 case CPUCLASS_586:
567 printf("%d.%02d-MHz ",
568 (tsc_freq + 4999) / 1000000,
569 ((tsc_freq + 4999) / 10000) % 100);
570 printf("586");
571 break;
572#endif
573#if defined(I686_CPU)
574 case CPUCLASS_686:
575 printf("%d.%02d-MHz ",
576 (tsc_freq + 4999) / 1000000,
577 ((tsc_freq + 4999) / 10000) % 100);
578 printf("686");
579 break;
580#endif
581 default:
582 printf("Unknown"); /* will panic below... */
583 }
584 printf("-class CPU)\n");
585#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
586 if(*cpu_vendor)
587 printf(" Origin = \"%s\"",cpu_vendor);
588 if(cpu_id)
589 printf(" Id = 0x%x", cpu_id);
590
591 if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
592 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
593 strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
594 strcmp(cpu_vendor, "CentaurHauls") == 0 ||
595 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
596 ((cpu_id & 0xf00) > 0x500))) {
597 printf(" Stepping = %u", cpu_id & 0xf);
598 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
599 printf(" DIR=0x%04x", cyrix_did);
600 if (cpu_high > 0) {
601 /*
602 * Here we should probably set up flags indicating
603 * whether or not various features are available.
604 * The interesting ones are probably VME, PSE, PAE,
605 * and PGE. The code already assumes without bothering
606 * to check that all CPUs >= Pentium have a TSC and
607 * MSRs.
608 */
609 printf("\n Features=0x%b", cpu_feature,
610 "\020"
611 "\001FPU" /* Integral FPU */
612 "\002VME" /* Extended VM86 mode support */
613 "\003DE" /* Debugging Extensions (CR4.DE) */
614 "\004PSE" /* 4MByte page tables */
615 "\005TSC" /* Timestamp counter */
616 "\006MSR" /* Machine specific registers */
617 "\007PAE" /* Physical address extension */
618 "\010MCE" /* Machine Check support */
619 "\011CX8" /* CMPEXCH8 instruction */
620 "\012APIC" /* SMP local APIC */
621 "\013oldMTRR" /* Previous implementation of MTRR */
622 "\014SEP" /* Fast System Call */
623 "\015MTRR" /* Memory Type Range Registers */
624 "\016PGE" /* PG_G (global bit) support */
625 "\017MCA" /* Machine Check Architecture */
626 "\020CMOV" /* CMOV instruction */
627 "\021PAT" /* Page attributes table */
628 "\022PSE36" /* 36 bit address space support */
629 "\023PN" /* Processor Serial number */
630 "\024CLFLUSH" /* Has the CLFLUSH instruction */
631 "\025<b20>"
632 "\026DTS" /* Debug Trace Store */
633 "\027ACPI" /* ACPI support */
634 "\030MMX" /* MMX instructions */
635 "\031FXSR" /* FXSAVE/FXRSTOR */
636 "\032SSE" /* Streaming SIMD Extensions */
637 "\033SSE2" /* Streaming SIMD Extensions #2 */
638 "\034SS" /* Self snoop */
639 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
640 "\036TM" /* Thermal Monitor clock slowdown */
641 "\037IA64" /* CPU can execute IA64 instructions */
642 "\040PBE" /* Pending Break Enable */
643 );
644
645 /*
646 * If this CPU supports hyperthreading then mention
647 * the number of logical CPU's it contains.
648 */
649 if (cpu_feature & CPUID_HTT &&
650 (cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1)
651 printf("\n Hyperthreading: %d logical CPUs",
652 (cpu_procinfo & CPUID_HTT_CORES) >> 16);
653 }
654 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
655 cpu_exthigh >= 0x80000001)
656 print_AMD_features();
657 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
658 printf(" DIR=0x%04x", cyrix_did);
659 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
660 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
661#ifndef CYRIX_CACHE_REALLY_WORKS
662 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
663 printf("\n CPU cache: write-through mode");
664#endif
665 }
666 /* Avoid ugly blank lines: only print newline when we have to. */
667 if (*cpu_vendor || cpu_id)
668 printf("\n");
669
670#endif
671 if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
672 strcmp(cpu_vendor, "TransmetaCPU") == 0) {
673 setup_tmx86_longrun();
674 }
675
676 if (!bootverbose)
677 return;
678
679 if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
680 print_AMD_info();
681 else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
682 strcmp(cpu_vendor, "TransmetaCPU") == 0)
683 print_transmeta_info();
684
685#ifdef I686_CPU
686 /*
687 * XXX - Do PPro CPUID level=2 stuff here?
688 *
689 * No, but maybe in a print_Intel_info() function called from here.
690 */
691#endif
692}
693
694void
695panicifcpuunsupported(void)
696{
697
698#if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
699#error This kernel is not configured for one of the supported CPUs
700#endif
701 /*
702 * Now that we have told the user what they have,
703 * let them know if that machine type isn't configured.
704 */
705 switch (cpu_class) {
706 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
707#if !defined(I386_CPU)
708 case CPUCLASS_386:
709#endif
710#if !defined(I486_CPU)
711 case CPUCLASS_486:
712#endif
713#if !defined(I586_CPU)
714 case CPUCLASS_586:
715#endif
716#if !defined(I686_CPU)
717 case CPUCLASS_686:
718#endif
719 panic("CPU class not configured");
720 default:
721 break;
722 }
723}
724
725
726static volatile u_int trap_by_rdmsr;
727
728/*
729 * Special exception 6 handler.
730 * The rdmsr instruction generates invalid opcodes fault on 486-class
731 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
732 * function identblue() when this handler is called. Stacked eip should
733 * be advanced.
734 */
735inthand_t bluetrap6;
736__asm
737("
738 .text
739 .p2align 2,0x90
740 .type " __XSTRING(CNAME(bluetrap6)) ",@function
741" __XSTRING(CNAME(bluetrap6)) ":
742 ss
743 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "
744 addl $2, (%esp) # I know rdmsr is a 2-bytes instruction.
745 iret
746");
747
748/*
749 * Special exception 13 handler.
750 * Accessing non-existent MSR generates general protection fault.
751 */
752inthand_t bluetrap13;
753__asm
754("
755 .text
756 .p2align 2,0x90
757 .type " __XSTRING(CNAME(bluetrap13)) ",@function
758" __XSTRING(CNAME(bluetrap13)) ":
759 ss
760 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "
761 popl %eax # discard errorcode.
762 addl $2, (%esp) # I know rdmsr is a 2-bytes instruction.
763 iret
764");
765
766/*
767 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
768 * support cpuid instruction. This function should be called after
769 * loading interrupt descriptor table register.
770 *
771 * I don't like this method that handles fault, but I couldn't get
772 * information for any other methods. Does blue giant know?
773 */
774static int
775identblue(void)
776{
777
778 trap_by_rdmsr = 0;
779
780 /*
781 * Cyrix 486-class CPU does not support rdmsr instruction.
782 * The rdmsr instruction generates invalid opcode fault, and exception
783 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
784 * bluetrap6() set the magic number to trap_by_rdmsr.
785 */
786 setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
787
788 /*
789 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
790 * In this case, rdmsr generates general protection fault, and
791 * exception will be trapped by bluetrap13().
792 */
793 setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
794
795 rdmsr(0x1002); /* Cyrix CPU generates fault. */
796
797 if (trap_by_rdmsr == 0xa8c1d)
798 return IDENTBLUE_CYRIX486;
799 else if (trap_by_rdmsr == 0xa89c4)
800 return IDENTBLUE_CYRIXM2;
801 return IDENTBLUE_IBMCPU;
802}
803
804
805/*
806 * identifycyrix() set lower 16 bits of cyrix_did as follows:
807 *
808 * F E D C B A 9 8 7 6 5 4 3 2 1 0
809 * +-------+-------+---------------+
810 * | SID | RID | Device ID |
811 * | (DIR 1) | (DIR 0) |
812 * +-------+-------+---------------+
813 */
814static void
815identifycyrix(void)
816{
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817 int ccr2_test = 0, dir_test = 0;
818 u_char ccr2, ccr3;
819
8a8d5d85 820 mpintr_lock();
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821
822 ccr2 = read_cyrix_reg(CCR2);
823 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
824 read_cyrix_reg(CCR2);
825 if (read_cyrix_reg(CCR2) != ccr2)
826 ccr2_test = 1;
827 write_cyrix_reg(CCR2, ccr2);
828
829 ccr3 = read_cyrix_reg(CCR3);
830 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
831 read_cyrix_reg(CCR3);
832 if (read_cyrix_reg(CCR3) != ccr3)
833 dir_test = 1; /* CPU supports DIRs. */
834 write_cyrix_reg(CCR3, ccr3);
835
836 if (dir_test) {
837 /* Device ID registers are available. */
838 cyrix_did = read_cyrix_reg(DIR1) << 8;
839 cyrix_did += read_cyrix_reg(DIR0);
840 } else if (ccr2_test)
841 cyrix_did = 0x0010; /* 486S A-step */
842 else
843 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
844
8a8d5d85 845 mpintr_unlock();
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846}
847
848/*
849 * Final stage of CPU identification. -- Should I check TI?
850 */
851void
852finishidentcpu(void)
853{
854 int isblue = 0;
855 u_char ccr3;
856 u_int regs[4];
857
858 if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
859 if (cpu == CPU_486) {
860 /*
861 * These conditions are equivalent to:
862 * - CPU does not support cpuid instruction.
863 * - Cyrix/IBM CPU is detected.
864 */
865 isblue = identblue();
866 if (isblue == IDENTBLUE_IBMCPU) {
867 strcpy(cpu_vendor, "IBM");
868 cpu = CPU_BLUE;
869 return;
870 }
871 }
872 switch (cpu_id & 0xf00) {
873 case 0x600:
874 /*
875 * Cyrix's datasheet does not describe DIRs.
876 * Therefor, I assume it does not have them
877 * and use the result of the cpuid instruction.
878 * XXX they seem to have it for now at least. -Peter
879 */
880 identifycyrix();
881 cpu = CPU_M2;
882 break;
883 default:
884 identifycyrix();
885 /*
886 * This routine contains a trick.
887 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
888 */
889 switch (cyrix_did & 0x00f0) {
890 case 0x00:
891 case 0xf0:
892 cpu = CPU_486DLC;
893 break;
894 case 0x10:
895 cpu = CPU_CY486DX;
896 break;
897 case 0x20:
898 if ((cyrix_did & 0x000f) < 8)
899 cpu = CPU_M1;
900 else
901 cpu = CPU_M1SC;
902 break;
903 case 0x30:
904 cpu = CPU_M1;
905 break;
906 case 0x40:
907 /* MediaGX CPU */
908 cpu = CPU_M1SC;
909 break;
910 default:
911 /* M2 and later CPUs are treated as M2. */
912 cpu = CPU_M2;
913
914 /*
915 * enable cpuid instruction.
916 */
917 ccr3 = read_cyrix_reg(CCR3);
918 write_cyrix_reg(CCR3, CCR3_MAPEN0);
919 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
920 write_cyrix_reg(CCR3, ccr3);
921
922 do_cpuid(0, regs);
923 cpu_high = regs[0]; /* eax */
924 do_cpuid(1, regs);
925 cpu_id = regs[0]; /* eax */
926 cpu_feature = regs[3]; /* edx */
927 break;
928 }
929 }
930 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
931 /*
932 * There are BlueLightning CPUs that do not change
933 * undefined flags by dividing 5 by 2. In this case,
934 * the CPU identification routine in locore.s leaves
935 * cpu_vendor null string and puts CPU_486 into the
936 * cpu.
937 */
938 isblue = identblue();
939 if (isblue == IDENTBLUE_IBMCPU) {
940 strcpy(cpu_vendor, "IBM");
941 cpu = CPU_BLUE;
942 return;
943 }
944 }
945}
946
947static void
948print_AMD_assoc(int i)
949{
950 if (i == 255)
951 printf(", fully associative\n");
952 else
953 printf(", %d-way associative\n", i);
954}
955
956static void
957print_AMD_info(void)
958{
959 quad_t amd_whcr;
960
961 if (cpu_exthigh >= 0x80000005) {
962 u_int regs[4];
963
964 do_cpuid(0x80000005, regs);
965 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
966 print_AMD_assoc(regs[1] >> 24);
967 printf("Instruction TLB: %d entries", regs[1] & 0xff);
968 print_AMD_assoc((regs[1] >> 8) & 0xff);
969 printf("L1 data cache: %d kbytes", regs[2] >> 24);
970 printf(", %d bytes/line", regs[2] & 0xff);
971 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
972 print_AMD_assoc((regs[2] >> 16) & 0xff);
973 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
974 printf(", %d bytes/line", regs[3] & 0xff);
975 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
976 print_AMD_assoc((regs[3] >> 16) & 0xff);
977 if (cpu_exthigh >= 0x80000006) { /* K6-III only */
978 do_cpuid(0x80000006, regs);
979 printf("L2 internal cache: %d kbytes", regs[2] >> 16);
980 printf(", %d bytes/line", regs[2] & 0xff);
981 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
982 print_AMD_assoc((regs[2] >> 12) & 0x0f);
983 }
984 }
985 if (((cpu_id & 0xf00) == 0x500)
986 && (((cpu_id & 0x0f0) > 0x80)
987 || (((cpu_id & 0x0f0) == 0x80)
988 && (cpu_id & 0x00f) > 0x07))) {
989 /* K6-2(new core [Stepping 8-F]), K6-III or later */
990 amd_whcr = rdmsr(0xc0000082);
991 if (!(amd_whcr & (0x3ff << 22))) {
992 printf("Write Allocate Disable\n");
993 } else {
994 printf("Write Allocate Enable Limit: %dM bytes\n",
995 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
996 printf("Write Allocate 15-16M bytes: %s\n",
997 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
998 }
999 } else if (((cpu_id & 0xf00) == 0x500)
1000 && ((cpu_id & 0x0f0) > 0x50)) {
1001 /* K6, K6-2(old core) */
1002 amd_whcr = rdmsr(0xc0000082);
1003 if (!(amd_whcr & (0x7f << 1))) {
1004 printf("Write Allocate Disable\n");
1005 } else {
1006 printf("Write Allocate Enable Limit: %dM bytes\n",
1007 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1008 printf("Write Allocate 15-16M bytes: %s\n",
1009 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1010 printf("Hardware Write Allocate Control: %s\n",
1011 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1012 }
1013 }
1014}
1015
1016#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
1017static void
1018print_AMD_features(void)
1019{
1020 u_int regs[4];
1021
1022 /*
1023 * Values taken from AMD Processor Recognition
1024 * http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
1025 */
1026 do_cpuid(0x80000001, regs);
1027 printf("\n AMD Features=0x%b", regs[3] &~ cpu_feature,
1028 "\020" /* in hex */
1029 "\001FPU" /* Integral FPU */
1030 "\002VME" /* Extended VM86 mode support */
1031 "\003DE" /* Debug extensions */
1032 "\004PSE" /* 4MByte page tables */
1033 "\005TSC" /* Timestamp counter */
1034 "\006MSR" /* Machine specific registers */
1035 "\007PAE" /* Physical address extension */
1036 "\010MCE" /* Machine Check support */
1037 "\011CX8" /* CMPEXCH8 instruction */
1038 "\012APIC" /* SMP local APIC */
1039 "\013<b10>"
1040 "\014SYSCALL" /* SYSENTER/SYSEXIT instructions */
1041 "\015MTRR" /* Memory Type Range Registers */
1042 "\016PGE" /* PG_G (global bit) support */
1043 "\017MCA" /* Machine Check Architecture */
1044 "\020ICMOV" /* CMOV instruction */
1045 "\021PAT" /* Page attributes table */
1046 "\022PGE36" /* 36 bit address space support */
1047 "\023RSVD" /* Reserved, unknown */
1048 "\024MP" /* Multiprocessor Capable */
1049 "\025<b20>"
1050 "\026<b21>"
1051 "\027AMIE" /* AMD MMX Instruction Extensions */
1052 "\030MMX"
1053 "\031FXSAVE" /* FXSAVE/FXRSTOR */
1054 "\032<b25>"
1055 "\033<b26>"
1056 "\034<b27>"
1057 "\035<b28>"
1058 "\036<b29>"
1059 "\037DSP" /* AMD 3DNow! Instruction Extensions */
1060 "\0403DNow!"
1061 );
1062}
1063#endif
1064
1065/*
1066 * Transmeta Crusoe LongRun Support by Tamotsu Hattori.
1067 */
1068
1069#define MSR_TMx86_LONGRUN 0x80868010
1070#define MSR_TMx86_LONGRUN_FLAGS 0x80868011
1071
1072#define LONGRUN_MODE_MASK(x) ((x) & 0x000000007f)
1073#define LONGRUN_MODE_RESERVED(x) ((x) & 0xffffff80)
1074#define LONGRUN_MODE_WRITE(x, y) (LONGRUN_MODE_RESERVED(x) | LONGRUN_MODE_MASK(y))
1075
1076#define LONGRUN_MODE_MINFREQUENCY 0x00
1077#define LONGRUN_MODE_ECONOMY 0x01
1078#define LONGRUN_MODE_PERFORMANCE 0x02
1079#define LONGRUN_MODE_MAXFREQUENCY 0x03
1080#define LONGRUN_MODE_UNKNOWN 0x04
1081#define LONGRUN_MODE_MAX 0x04
1082
1083union msrinfo {
1084 u_int64_t msr;
1085 u_int32_t regs[2];
1086};
1087
1088u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
1089 /* MSR low, MSR high, flags bit0 */
1090 { 0, 0, 0}, /* LONGRUN_MODE_MINFREQUENCY */
1091 { 0, 100, 0}, /* LONGRUN_MODE_ECONOMY */
1092 { 0, 100, 1}, /* LONGRUN_MODE_PERFORMANCE */
1093 { 100, 100, 1}, /* LONGRUN_MODE_MAXFREQUENCY */
1094};
1095
1096static u_int
1097tmx86_get_longrun_mode(void)
1098{
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1099 union msrinfo msrinfo;
1100 u_int low, high, flags, mode;
1101
8a8d5d85 1102 mpintr_lock();
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1103
1104 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1105 low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
1106 high = LONGRUN_MODE_MASK(msrinfo.regs[1]);
1107 flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01;
1108
1109 for (mode = 0; mode < LONGRUN_MODE_MAX; mode++) {
1110 if (low == longrun_modes[mode][0] &&
1111 high == longrun_modes[mode][1] &&
1112 flags == longrun_modes[mode][2]) {
1113 goto out;
1114 }
1115 }
1116 mode = LONGRUN_MODE_UNKNOWN;
1117out:
8a8d5d85 1118 mpintr_unlock();
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MD
1119 return (mode);
1120}
1121
1122static u_int
1123tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage)
1124{
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1125 u_int regs[4];
1126
8a8d5d85 1127 mpintr_lock();
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1128
1129 do_cpuid(0x80860007, regs);
1130 *frequency = regs[0];
1131 *voltage = regs[1];
1132 *percentage = regs[2];
1133
8a8d5d85 1134 mpintr_unlock();
984263bc
MD
1135 return (1);
1136}
1137
1138static u_int
1139tmx86_set_longrun_mode(u_int mode)
1140{
984263bc
MD
1141 union msrinfo msrinfo;
1142
1143 if (mode >= LONGRUN_MODE_UNKNOWN) {
1144 return (0);
1145 }
1146
8a8d5d85 1147 mpintr_lock();
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1148
1149 /* Write LongRun mode values to Model Specific Register. */
1150 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1151 msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0],
1152 longrun_modes[mode][0]);
1153 msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1],
1154 longrun_modes[mode][1]);
1155 wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr);
1156
1157 /* Write LongRun mode flags to Model Specific Register. */
1158 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);
1159 msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
1160 wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
1161
8a8d5d85 1162 mpintr_unlock();
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1163 return (1);
1164}
1165
1166static u_int crusoe_longrun;
1167static u_int crusoe_frequency;
1168static u_int crusoe_voltage;
1169static u_int crusoe_percentage;
1170static struct sysctl_ctx_list crusoe_sysctl_ctx;
1171static struct sysctl_oid *crusoe_sysctl_tree;
1172
1173static int
1174tmx86_longrun_sysctl(SYSCTL_HANDLER_ARGS)
1175{
1176 u_int mode;
1177 int error;
1178
1179 crusoe_longrun = tmx86_get_longrun_mode();
1180 mode = crusoe_longrun;
1181 error = sysctl_handle_int(oidp, &mode, 0, req);
1182 if (error || !req->newptr) {
1183 return (error);
1184 }
1185 if (mode >= LONGRUN_MODE_UNKNOWN) {
1186 error = EINVAL;
1187 return (error);
1188 }
1189 if (crusoe_longrun != mode) {
1190 crusoe_longrun = mode;
1191 tmx86_set_longrun_mode(crusoe_longrun);
1192 }
1193
1194 return (error);
1195}
1196
1197static int
1198tmx86_status_sysctl(SYSCTL_HANDLER_ARGS)
1199{
1200 u_int val;
1201 int error;
1202
1203 tmx86_get_longrun_status(&crusoe_frequency,
1204 &crusoe_voltage, &crusoe_percentage);
1205 val = *(u_int *)oidp->oid_arg1;
1206 error = sysctl_handle_int(oidp, &val, 0, req);
1207 return (error);
1208}
1209
1210static void
1211setup_tmx86_longrun(void)
1212{
1213 static int done = 0;
1214
1215 if (done)
1216 return;
1217 done++;
1218
1219 sysctl_ctx_init(&crusoe_sysctl_ctx);
1220 crusoe_sysctl_tree = SYSCTL_ADD_NODE(&crusoe_sysctl_ctx,
1221 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1222 "crusoe", CTLFLAG_RD, 0,
1223 "Transmeta Crusoe LongRun support");
1224 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1225 OID_AUTO, "longrun", CTLTYPE_INT | CTLFLAG_RW,
1226 &crusoe_longrun, 0, tmx86_longrun_sysctl, "I",
1227 "LongRun mode [0-3]");
1228 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1229 OID_AUTO, "frequency", CTLTYPE_INT | CTLFLAG_RD,
1230 &crusoe_frequency, 0, tmx86_status_sysctl, "I",
1231 "Current frequency (MHz)");
1232 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1233 OID_AUTO, "voltage", CTLTYPE_INT | CTLFLAG_RD,
1234 &crusoe_voltage, 0, tmx86_status_sysctl, "I",
1235 "Current voltage (mV)");
1236 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1237 OID_AUTO, "percentage", CTLTYPE_INT | CTLFLAG_RD,
1238 &crusoe_percentage, 0, tmx86_status_sysctl, "I",
1239 "Processing performance (%)");
1240}
1241
1242static void
1243print_transmeta_info()
1244{
1245 u_int regs[4], nreg = 0;
1246
1247 do_cpuid(0x80860000, regs);
1248 nreg = regs[0];
1249 if (nreg >= 0x80860001) {
1250 do_cpuid(0x80860001, regs);
1251 printf(" Processor revision %u.%u.%u.%u\n",
1252 (regs[1] >> 24) & 0xff,
1253 (regs[1] >> 16) & 0xff,
1254 (regs[1] >> 8) & 0xff,
1255 regs[1] & 0xff);
1256 }
1257 if (nreg >= 0x80860002) {
1258 do_cpuid(0x80860002, regs);
1259 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
1260 (regs[1] >> 24) & 0xff,
1261 (regs[1] >> 16) & 0xff,
1262 (regs[1] >> 8) & 0xff,
1263 regs[1] & 0xff,
1264 regs[2]);
1265 }
1266 if (nreg >= 0x80860006) {
1267 char info[65];
1268 do_cpuid(0x80860003, (u_int*) &info[0]);
1269 do_cpuid(0x80860004, (u_int*) &info[16]);
1270 do_cpuid(0x80860005, (u_int*) &info[32]);
1271 do_cpuid(0x80860006, (u_int*) &info[48]);
1272 info[64] = 0;
1273 printf(" %s\n", info);
1274 }
1275
1276 crusoe_longrun = tmx86_get_longrun_mode();
1277 tmx86_get_longrun_status(&crusoe_frequency,
1278 &crusoe_voltage, &crusoe_percentage);
1279 printf(" LongRun mode: %d <%dMHz %dmV %d%%>\n", crusoe_longrun,
1280 crusoe_frequency, crusoe_voltage, crusoe_percentage);
1281}
1282