Use clr instead of an explicit mov from ALLZEROS
[dragonfly.git] / sys / dev / disk / aic7xxx / aic79xx.seq
CommitLineData
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1/*
2 * Adaptec U320 device driver firmware for Linux and FreeBSD.
3 *
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
317c1a53
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40 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.seq,v 1.13 2003/06/28 04:44:10 gibbs Exp $
41 * $DragonFly: src/sys/dev/disk/aic7xxx/aic79xx.seq,v 1.4 2007/07/05 01:21:56 pavalos Exp $
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42 */
43
317c1a53 44VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#96 $"
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45PATCH_ARG_LIST = "struct ahd_softc *ahd"
46PREFIX = "ahd_"
47
48#include "aic79xx.reg"
49#include "scsi_message.h"
50
51restart:
52if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
53 test SEQINTCODE, 0xFF jz idle_loop;
54 SET_SEQINTCODE(NO_SEQINT)
55}
56
57idle_loop:
58
59 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
60 /*
61 * Convert ERROR status into a sequencer
62 * interrupt to handle the case of an
63 * interrupt collision on the hardware
64 * setting of HWERR.
65 */
66 test ERROR, 0xFF jz no_error_set;
67 SET_SEQINTCODE(SAW_HWERR)
68no_error_set:
69 }
70 SET_MODE(M_SCSI, M_SCSI)
71 test SCSISEQ0, ENSELO|ENARBO jnz idle_loop_checkbus;
72 test SEQ_FLAGS2, SELECTOUT_QFROZEN jnz idle_loop_checkbus;
73 cmp WAITING_TID_HEAD[1], SCB_LIST_NULL je idle_loop_checkbus;
74 /*
75 * ENSELO is cleared by a SELDO, so we must test for SELDO
76 * one last time.
77 */
78BEGIN_CRITICAL;
79 test SSTAT0, SELDO jnz select_out;
80END_CRITICAL;
81 call start_selection;
82idle_loop_checkbus:
83BEGIN_CRITICAL;
84 test SSTAT0, SELDO jnz select_out;
85END_CRITICAL;
86 test SSTAT0, SELDI jnz select_in;
87 test SCSIPHASE, ~DATA_PHASE_MASK jz idle_loop_check_nonpackreq;
88 test SCSISIGO, ATNO jz idle_loop_check_nonpackreq;
89 call unexpected_nonpkt_phase_find_ctxt;
90idle_loop_check_nonpackreq:
91 test SSTAT2, NONPACKREQ jz . + 2;
92 call unexpected_nonpkt_phase_find_ctxt;
93 if ((ahd->bugs & AHD_FAINT_LED_BUG) != 0) {
94 and A, FIFO0FREE|FIFO1FREE, DFFSTAT;
95 cmp A, FIFO0FREE|FIFO1FREE jne . + 3;
96 and SBLKCTL, ~DIAGLEDEN|DIAGLEDON;
97 jmp . + 2;
98 or SBLKCTL, DIAGLEDEN|DIAGLEDON;
99 }
100 call idle_loop_gsfifo_in_scsi_mode;
101 call idle_loop_service_fifos;
102 call idle_loop_cchan;
103 jmp idle_loop;
104
105BEGIN_CRITICAL;
106idle_loop_gsfifo:
107 SET_MODE(M_SCSI, M_SCSI)
108idle_loop_gsfifo_in_scsi_mode:
109 test LQISTAT2, LQIGSAVAIL jz return;
110 /*
111 * We have received good status for this transaction. There may
112 * still be data in our FIFOs draining to the host. Complete
113 * the SCB only if all data has transferred to the host.
114 */
115good_status_IU_done:
116 bmov SCBPTR, GSFIFO, 2;
117 clr SCB_SCSI_STATUS;
118 /*
119 * If a command completed before an attempted task management
120 * function completed, notify the host after disabling any
121 * pending select-outs.
122 */
123 test SCB_TASK_MANAGEMENT, 0xFF jz gsfifo_complete_normally;
124 test SSTAT0, SELDO|SELINGO jnz . + 2;
125 and SCSISEQ0, ~ENSELO;
126 SET_SEQINTCODE(TASKMGMT_CMD_CMPLT_OKAY)
127gsfifo_complete_normally:
128 or SCB_CONTROL, STATUS_RCVD;
129
130 /*
131 * Since this status did not consume a FIFO, we have to
132 * be a bit more dilligent in how we check for FIFOs pertaining
133 * to this transaction. There are two states that a FIFO still
134 * transferring data may be in.
135 *
136 * 1) Configured and draining to the host, with a FIFO handler.
137 * 2) Pending cfg4data, fifo not empty.
138 *
139 * Case 1 can be detected by noticing a non-zero FIFO active
140 * count in the SCB. In this case, we allow the routine servicing
141 * the FIFO to complete the SCB.
142 *
143 * Case 2 implies either a pending or yet to occur save data
144 * pointers for this same context in the other FIFO. So, if
145 * we detect case 1, we will properly defer the post of the SCB
146 * and achieve the desired result. The pending cfg4data will
147 * notice that status has been received and complete the SCB.
148 */
149 test SCB_FIFO_USE_COUNT, 0xFF jnz idle_loop_gsfifo_in_scsi_mode;
150 call complete;
151END_CRITICAL;
152 jmp idle_loop_gsfifo_in_scsi_mode;
153
154idle_loop_service_fifos:
155 SET_MODE(M_DFF0, M_DFF0)
156 test LONGJMP_ADDR[1], INVALID_ADDR jnz idle_loop_next_fifo;
157 call longjmp;
158idle_loop_next_fifo:
159 SET_MODE(M_DFF1, M_DFF1)
160 test LONGJMP_ADDR[1], INVALID_ADDR jz longjmp;
161return:
162 ret;
163
164idle_loop_cchan:
165 SET_MODE(M_CCHAN, M_CCHAN)
166 test QOFF_CTLSTA, HS_MAILBOX_ACT jz hs_mailbox_empty;
167 mov LOCAL_HS_MAILBOX, HS_MAILBOX;
168 or QOFF_CTLSTA, HS_MAILBOX_ACT;
169hs_mailbox_empty:
170BEGIN_CRITICAL;
171 test CCSCBCTL, CCARREN|CCSCBEN jz scbdma_idle;
172 test CCSCBCTL, CCSCBDIR jnz fetch_new_scb_inprog;
173 test CCSCBCTL, CCSCBDONE jz return;
174END_CRITICAL;
175 /* FALLTHROUGH */
176scbdma_tohost_done:
177 test CCSCBCTL, CCARREN jz fill_qoutfifo_dmadone;
178 /*
179 * An SCB has been succesfully uploaded to the host.
180 * If the SCB was uploaded for some reason other than
181 * bad SCSI status (currently only for underruns), we
182 * queue the SCB for normal completion. Otherwise, we
183 * wait until any select-out activity has halted, and
184 * then notify the host so that the transaction can be
185 * dealt with.
186 */
187 test SCB_SCSI_STATUS, 0xff jnz scbdma_notify_host;
188 and CCSCBCTL, ~(CCARREN|CCSCBEN);
189 bmov COMPLETE_DMA_SCB_HEAD, SCB_NEXT_COMPLETE, 2;
190 bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
191 bmov COMPLETE_SCB_HEAD, SCBPTR, 2 ret;
192scbdma_notify_host:
193 SET_MODE(M_SCSI, M_SCSI)
194 test SCSISEQ0, ENSELO jnz return;
195 test SSTAT0, (SELDO|SELINGO) jnz return;
196 SET_MODE(M_CCHAN, M_CCHAN)
197 /*
198 * Remove SCB and notify host.
199 */
200 and CCSCBCTL, ~(CCARREN|CCSCBEN);
201 bmov COMPLETE_DMA_SCB_HEAD, SCB_NEXT_COMPLETE, 2;
202 SET_SEQINTCODE(BAD_SCB_STATUS)
203 ret;
204fill_qoutfifo_dmadone:
205 and CCSCBCTL, ~(CCARREN|CCSCBEN);
206 call qoutfifo_updated;
207 mvi COMPLETE_SCB_DMAINPROG_HEAD[1], SCB_LIST_NULL;
208 bmov QOUTFIFO_NEXT_ADDR, SCBHADDR, 4;
209 test QOFF_CTLSTA, SDSCB_ROLLOVR jz return;
210 bmov QOUTFIFO_NEXT_ADDR, SHARED_DATA_ADDR, 4;
211 xor QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID_TOGGLE ret;
212
213qoutfifo_updated:
214 /*
215 * If there are more commands waiting to be dma'ed
216 * to the host, always coalesce. Otherwise honor the
217 * host's wishes.
218 */
219 cmp COMPLETE_DMA_SCB_HEAD[1], SCB_LIST_NULL jne coalesce_by_count;
220 cmp COMPLETE_SCB_HEAD[1], SCB_LIST_NULL jne coalesce_by_count;
221 test LOCAL_HS_MAILBOX, ENINT_COALESCE jz issue_cmdcmplt;
222
223 /*
224 * If we have relatively few commands outstanding, don't
225 * bother waiting for another command to complete.
226 */
227 test CMDS_PENDING[1], 0xFF jnz coalesce_by_count;
228 /* Add -1 so that jnc means <= not just < */
229 add A, -1, INT_COALESCING_MINCMDS;
230 add NONE, A, CMDS_PENDING;
231 jnc issue_cmdcmplt;
232
233 /*
234 * If coalescing, only coalesce up to the limit
235 * provided by the host driver.
236 */
237coalesce_by_count:
238 mov A, INT_COALESCING_MAXCMDS;
239 add NONE, A, INT_COALESCING_CMDCOUNT;
240 jc issue_cmdcmplt;
241 /*
242 * If the timer is not currently active,
243 * fire it up.
244 */
245 test INTCTL, SWTMINTMASK jz return;
246 bmov SWTIMER, INT_COALESCING_TIMER, 2;
247 mvi CLRSEQINTSTAT, CLRSEQ_SWTMRTO;
248 or INTCTL, SWTMINTEN|SWTIMER_START;
249 and INTCTL, ~SWTMINTMASK ret;
250
251issue_cmdcmplt:
252 mvi INTSTAT, CMDCMPLT;
253 clr INT_COALESCING_CMDCOUNT;
254 or INTCTL, SWTMINTMASK ret;
255
256BEGIN_CRITICAL;
257fetch_new_scb_inprog:
258 test CCSCBCTL, ARRDONE jz return;
259fetch_new_scb_done:
260 and CCSCBCTL, ~(CCARREN|CCSCBEN);
261 bmov REG0, SCBPTR, 2;
262 clr A;
263 add CMDS_PENDING, 1;
264 adc CMDS_PENDING[1], A;
265 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
266 /*
267 * "Short Luns" are not placed into outgoing LQ
268 * packets in the correct byte order. Use a full
269 * sized lun field instead and fill it with the
270 * one byte of lun information we support.
271 */
272 mov SCB_PKT_LUN[6], SCB_LUN;
273 }
274 /*
275 * The FIFO use count field is shared with the
276 * tag set by the host so that our SCB dma engine
277 * knows the correct location to store the SCB.
278 * Set it to zero before processing the SCB.
279 */
317c1a53 280 clr SCB_FIFO_USE_COUNT;
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281 /* Update the next SCB address to download. */
282 bmov NEXT_QUEUED_SCB_ADDR, SCB_NEXT_SCB_BUSADDR, 4;
283 mvi SCB_NEXT[1], SCB_LIST_NULL;
284 mvi SCB_NEXT2[1], SCB_LIST_NULL;
285 /* Increment our position in the QINFIFO. */
286 mov NONE, SNSCB_QOFF;
287 /*
288 * SCBs that want to send messages are always
289 * queued independently. This ensures that they
290 * are at the head of the SCB list to select out
291 * to a target and we will see the MK_MESSAGE flag.
292 */
293 test SCB_CONTROL, MK_MESSAGE jnz first_new_target_scb;
294 shr SINDEX, 3, SCB_SCSIID;
295 and SINDEX, ~0x1;
296 mvi SINDEX[1], (WAITING_SCB_TAILS >> 8);
297 bmov DINDEX, SINDEX, 2;
298 bmov SCBPTR, SINDIR, 2;
299 bmov DINDIR, REG0, 2;
300 cmp SCBPTR[1], SCB_LIST_NULL je first_new_target_scb;
301 bmov SCB_NEXT, REG0, 2 ret;
302first_new_target_scb:
303 cmp WAITING_TID_HEAD[1], SCB_LIST_NULL je first_new_scb;
304 bmov SCBPTR, WAITING_TID_TAIL, 2;
305 bmov SCB_NEXT2, REG0, 2;
306 bmov WAITING_TID_TAIL, REG0, 2 ret;
307first_new_scb:
308 bmov WAITING_TID_HEAD, REG0, 2;
309 bmov WAITING_TID_TAIL, REG0, 2 ret;
310END_CRITICAL;
311
312scbdma_idle:
313 /*
314 * Give precedence to downloading new SCBs to execute
315 * unless select-outs are currently frozen.
316 */
317 test SEQ_FLAGS2, SELECTOUT_QFROZEN jnz . + 2;
318BEGIN_CRITICAL;
319 test QOFF_CTLSTA, NEW_SCB_AVAIL jnz fetch_new_scb;
320 cmp COMPLETE_DMA_SCB_HEAD[1], SCB_LIST_NULL jne dma_complete_scb;
321 cmp COMPLETE_SCB_HEAD[1], SCB_LIST_NULL je return;
322 /* FALLTHROUGH */
323fill_qoutfifo:
324 /*
325 * Keep track of the SCBs we are dmaing just
326 * in case the DMA fails or is aborted.
327 */
328 mov A, QOUTFIFO_ENTRY_VALID_TAG;
329 bmov COMPLETE_SCB_DMAINPROG_HEAD, COMPLETE_SCB_HEAD, 2;
330 mvi CCSCBCTL, CCSCBRESET;
331 bmov SCBHADDR, QOUTFIFO_NEXT_ADDR, 4;
332 bmov SCBPTR, COMPLETE_SCB_HEAD, 2;
333fill_qoutfifo_loop:
334 mov CCSCBRAM, SCBPTR;
335 or CCSCBRAM, A, SCBPTR[1];
336 mov NONE, SDSCB_QOFF;
337 inc INT_COALESCING_CMDCOUNT;
338 add CMDS_PENDING, -1;
339 adc CMDS_PENDING[1], -1;
340 cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL je fill_qoutfifo_done;
341 cmp CCSCBADDR, CCSCBADDR_MAX je fill_qoutfifo_done;
342 test QOFF_CTLSTA, SDSCB_ROLLOVR jnz fill_qoutfifo_done;
343 bmov SCBPTR, SCB_NEXT_COMPLETE, 2;
344 jmp fill_qoutfifo_loop;
345fill_qoutfifo_done:
346 mov SCBHCNT, CCSCBADDR;
347 mvi CCSCBCTL, CCSCBEN|CCSCBRESET;
348 bmov COMPLETE_SCB_HEAD, SCB_NEXT_COMPLETE, 2;
349 mvi SCB_NEXT_COMPLETE[1], SCB_LIST_NULL ret;
350
351fetch_new_scb:
352 bmov SCBHADDR, NEXT_QUEUED_SCB_ADDR, 4;
353 mvi CCARREN|CCSCBEN|CCSCBDIR|CCSCBRESET jmp dma_scb;
354dma_complete_scb:
355 bmov SCBPTR, COMPLETE_DMA_SCB_HEAD, 2;
356 bmov SCBHADDR, SCB_BUSADDR, 4;
357 mvi CCARREN|CCSCBEN|CCSCBRESET jmp dma_scb;
358END_CRITICAL;
359
360/*
361 * Either post or fetch an SCB from host memory. The caller
362 * is responsible for polling for transfer completion.
363 *
364 * Prerequisits: Mode == M_CCHAN
365 * SINDEX contains CCSCBCTL flags
366 * SCBHADDR set to Host SCB address
367 * SCBPTR set to SCB src location on "push" operations
368 */
369SET_SRC_MODE M_CCHAN;
370SET_DST_MODE M_CCHAN;
371dma_scb:
372 mvi SCBHCNT, SCB_TRANSFER_SIZE;
373 mov CCSCBCTL, SINDEX ret;
374
375BEGIN_CRITICAL;
376setjmp:
377 bmov LONGJMP_ADDR, STACK, 2 ret;
378setjmp_inline:
379 bmov LONGJMP_ADDR, STACK, 2;
380longjmp:
381 bmov STACK, LONGJMP_ADDR, 2 ret;
382END_CRITICAL;
383
384/*************************** Chip Bug Work Arounds ****************************/
385/*
386 * Must disable interrupts when setting the mode pointer
387 * register as an interrupt occurring mid update will
388 * fail to store the new mode value for restoration on
389 * an iret.
390 */
391if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) {
392set_mode_work_around:
393 mvi SEQINTCTL, INTVEC1DSL;
394 mov MODE_PTR, SINDEX;
395 clr SEQINTCTL ret;
396
397toggle_dff_mode_work_around:
398 mvi SEQINTCTL, INTVEC1DSL;
399 xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
400 clr SEQINTCTL ret;
401}
402
403
404if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
405set_seqint_work_around:
406 mov SEQINTCODE, SINDEX;
407 mvi SEQINTCODE, NO_SEQINT ret;
408}
409
410/************************ Packetized LongJmp Routines *************************/
411SET_SRC_MODE M_SCSI;
412SET_DST_MODE M_SCSI;
413start_selection:
414BEGIN_CRITICAL;
415 if ((ahd->bugs & AHD_SENT_SCB_UPDATE_BUG) != 0) {
416 /*
417 * Razor #494
418 * Rev A hardware fails to update LAST/CURR/NEXTSCB
419 * correctly after a packetized selection in several
420 * situations:
421 *
422 * 1) If only one command existed in the queue, the
423 * LAST/CURR/NEXTSCB are unchanged.
424 *
425 * 2) In a non QAS, protocol allowed phase change,
426 * the queue is shifted 1 too far. LASTSCB is
427 * the last SCB that was correctly processed.
428 *
429 * 3) In the QAS case, if the full list of commands
430 * was successfully sent, NEXTSCB is NULL and neither
431 * CURRSCB nor LASTSCB can be trusted. We must
432 * manually walk the list counting MAXCMDCNT elements
433 * to find the last SCB that was sent correctly.
434 *
435 * To simplify the workaround for this bug in SELDO
436 * handling, we initialize LASTSCB prior to enabling
437 * selection so we can rely on it even for case #1 above.
438 */
439 bmov LASTSCB, WAITING_TID_HEAD, 2;
440 }
441 bmov CURRSCB, WAITING_TID_HEAD, 2;
442 bmov SCBPTR, WAITING_TID_HEAD, 2;
443 shr SELOID, 4, SCB_SCSIID;
444 /*
445 * If we want to send a message to the device, ensure
446 * we are selecting with atn irregardless of our packetized
447 * agreement. Since SPI4 only allows target reset or PPR
448 * messages if this is a packetized connection, the change
449 * to our negotiation table entry for this selection will
450 * be cleared when the message is acted on.
451 */
452 test SCB_CONTROL, MK_MESSAGE jz . + 3;
453 mov NEGOADDR, SELOID;
454 or NEGCONOPTS, ENAUTOATNO;
455 or SCSISEQ0, ENSELO ret;
456END_CRITICAL;
457
458/*
459 * Allocate a FIFO for a non-packetized transaction.
460 * In RevA hardware, both FIFOs must be free before we
461 * can allocate a FIFO for a non-packetized transaction.
462 */
463allocate_fifo_loop:
464 /*
465 * Do whatever work is required to free a FIFO.
466 */
467 call idle_loop_service_fifos;
468 SET_MODE(M_SCSI, M_SCSI)
469allocate_fifo:
470 if ((ahd->bugs & AHD_NONPACKFIFO_BUG) != 0) {
471 and A, FIFO0FREE|FIFO1FREE, DFFSTAT;
472 cmp A, FIFO0FREE|FIFO1FREE jne allocate_fifo_loop;
473 } else {
474 test DFFSTAT, FIFO1FREE jnz allocate_fifo1;
475 test DFFSTAT, FIFO0FREE jz allocate_fifo_loop;
476 mvi DFFSTAT, B_CURRFIFO_0;
477 SET_MODE(M_DFF0, M_DFF0)
478 bmov SCBPTR, ALLOCFIFO_SCBPTR, 2 ret;
479 }
480SET_SRC_MODE M_SCSI;
481SET_DST_MODE M_SCSI;
482allocate_fifo1:
483 mvi DFFSTAT, CURRFIFO_1;
484 SET_MODE(M_DFF1, M_DFF1)
485 bmov SCBPTR, ALLOCFIFO_SCBPTR, 2 ret;
486
487/*
488 * We have been reselected as an initiator
489 * or selected as a target.
490 */
491SET_SRC_MODE M_SCSI;
492SET_DST_MODE M_SCSI;
493select_in:
494 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
495 /*
496 * This exposes a window whereby a
497 * busfree just after a selection will
498 * be missed, but there is no other safe
499 * way to enable busfree detection if
500 * the busfreerev function is broken.
501 */
502 mvi CLRSINT1,CLRBUSFREE;
503 or SIMODE1, ENBUSFREE;
504 }
505 or SXFRCTL0, SPIOEN;
506 and SAVED_SCSIID, SELID_MASK, SELID;
507 and A, OID, IOWNID;
508 or SAVED_SCSIID, A;
509 mvi CLRSINT0, CLRSELDI;
510 jmp ITloop;
511
512/*
513 * We have successfully selected out.
514 *
515 * Clear SELDO.
516 * Dequeue all SCBs sent from the waiting queue
517 * Requeue all SCBs *not* sent to the tail of the waiting queue
518 * Take Razor #494 into account for above.
519 *
520 * In Packetized Mode:
521 * Return to the idle loop. Our interrupt handler will take
522 * care of any incoming L_Qs.
523 *
524 * In Non-Packetize Mode:
525 * Continue to our normal state machine.
526 */
527SET_SRC_MODE M_SCSI;
528SET_DST_MODE M_SCSI;
529select_out:
530BEGIN_CRITICAL;
531 /* Clear out all SCBs that have been successfully sent. */
532 if ((ahd->bugs & AHD_SENT_SCB_UPDATE_BUG) != 0) {
533 /*
534 * For packetized, the LQO manager clears ENSELO on
535 * the assertion of SELDO. If we are non-packetized,
536 * LASTSCB and CURRSCB are accurate.
537 */
538 test SCSISEQ0, ENSELO jnz use_lastscb;
539
540 /*
541 * The update is correct for LQOSTAT1 errors. All
542 * but LQOBUSFREE are handled by kernel interrupts.
543 * If we see LQOBUSFREE, return to the idle loop.
544 * Once we are out of the select_out critical section,
545 * the kernel will cleanup the LQOBUSFREE and we will
546 * eventually restart the selection if appropriate.
547 */
548 test LQOSTAT1, LQOBUSFREE jnz idle_loop;
549
550 /*
551 * On a phase change oustside of packet boundaries,
552 * LASTSCB points to the currently active SCB context
553 * on the bus.
554 */
555 test LQOSTAT2, LQOPHACHGOUTPKT jnz use_lastscb;
556
557 /*
558 * If the hardware has traversed the whole list, NEXTSCB
559 * will be NULL, CURRSCB and LASTSCB cannot be trusted,
560 * but MAXCMDCNT is accurate. If we stop part way through
561 * the list or only had one command to issue, NEXTSCB[1] is
562 * not NULL and LASTSCB is the last command to go out.
563 */
564 cmp NEXTSCB[1], SCB_LIST_NULL jne use_lastscb;
565
566 /*
567 * Brute force walk.
568 */
569 bmov SCBPTR, WAITING_TID_HEAD, 2;
570 mvi SEQINTCTL, INTVEC1DSL;
571 mvi MODE_PTR, MK_MODE(M_CFG, M_CFG);
572 mov A, MAXCMDCNT;
573 mvi MODE_PTR, MK_MODE(M_SCSI, M_SCSI);
574 clr SEQINTCTL;
575find_lastscb_loop:
576 dec A;
577 test A, 0xFF jz found_last_sent_scb;
578 bmov SCBPTR, SCB_NEXT, 2;
579 jmp find_lastscb_loop;
580use_lastscb:
581 bmov SCBPTR, LASTSCB, 2;
582found_last_sent_scb:
583 bmov CURRSCB, SCBPTR, 2;
584curscb_ww_done:
585 } else {
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586 bmov SCBPTR, CURRSCB, 2;
587 }
588
589 /*
590 * Requeue any SCBs not sent, to the tail of the waiting Q.
591 */
592 cmp SCB_NEXT[1], SCB_LIST_NULL je select_out_list_done;
593
594 /*
595 * We know that neither the per-TID list nor the list of
596 * TIDs is empty. Use this knowledge to our advantage.
597 */
598 bmov REG0, SCB_NEXT, 2;
599 bmov SCBPTR, WAITING_TID_TAIL, 2;
600 bmov SCB_NEXT2, REG0, 2;
601 bmov WAITING_TID_TAIL, REG0, 2;
602 jmp select_out_inc_tid_q;
603
604select_out_list_done:
605 /*
606 * The whole list made it. Just clear our TID's tail pointer
607 * unless we were queued independently due to our need to
608 * send a message.
609 */
610 test SCB_CONTROL, MK_MESSAGE jnz select_out_inc_tid_q;
611 shr DINDEX, 3, SCB_SCSIID;
612 or DINDEX, 1; /* Want only the second byte */
613 mvi DINDEX[1], ((WAITING_SCB_TAILS) >> 8);
614 mvi DINDIR, SCB_LIST_NULL;
615select_out_inc_tid_q:
616 bmov SCBPTR, WAITING_TID_HEAD, 2;
617 bmov WAITING_TID_HEAD, SCB_NEXT2, 2;
618 cmp WAITING_TID_HEAD[1], SCB_LIST_NULL jne . + 2;
619 mvi WAITING_TID_TAIL[1], SCB_LIST_NULL;
620 bmov SCBPTR, CURRSCB, 2;
621 mvi CLRSINT0, CLRSELDO;
622 test LQOSTAT2, LQOPHACHGOUTPKT jnz unexpected_nonpkt_phase;
623 test LQOSTAT1, LQOPHACHGINPKT jnz unexpected_nonpkt_phase;
624
625 /*
626 * If this is a packetized connection, return to our
627 * idle_loop and let our interrupt handler deal with
628 * any connection setup/teardown issues. The only
629 * exceptions are the case of MK_MESSAGE and task management
630 * SCBs.
631 */
632 if ((ahd->bugs & AHD_LQO_ATNO_BUG) != 0) {
633 /*
634 * In the A, the LQO manager transitions to LQOSTOP0 even if
635 * we have selected out with ATN asserted and the target
636 * REQs in a non-packet phase.
637 */
638 test SCB_CONTROL, MK_MESSAGE jz select_out_no_message;
639 test SCSISIGO, ATNO jnz select_out_non_packetized;
640select_out_no_message:
641 }
642 test LQOSTAT2, LQOSTOP0 jz select_out_non_packetized;
643 test SCB_TASK_MANAGEMENT, 0xFF jz idle_loop;
644 SET_SEQINTCODE(TASKMGMT_FUNC_COMPLETE)
645 jmp idle_loop;
646
647select_out_non_packetized:
648 /* Non packetized request. */
649 and SCSISEQ0, ~ENSELO;
650 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
651 /*
652 * This exposes a window whereby a
653 * busfree just after a selection will
654 * be missed, but there is no other safe
655 * way to enable busfree detection if
656 * the busfreerev function is broken.
657 */
658 mvi CLRSINT1,CLRBUSFREE;
659 or SIMODE1, ENBUSFREE;
660 }
661 mov SAVED_SCSIID, SCB_SCSIID;
662 mov SAVED_LUN, SCB_LUN;
663 mvi SEQ_FLAGS, NO_CDB_SENT;
664END_CRITICAL;
665 or SXFRCTL0, SPIOEN;
666
667 /*
668 * As soon as we get a successful selection, the target
669 * should go into the message out phase since we have ATN
670 * asserted.
671 */
672 mvi MSG_OUT, MSG_IDENTIFYFLAG;
673
674 /*
675 * Main loop for information transfer phases. Wait for the
676 * target to assert REQ before checking MSG, C/D and I/O for
677 * the bus phase.
678 */
679mesgin_phasemis:
680ITloop:
681 call phase_lock;
682
683 mov A, LASTPHASE;
684
685 test A, ~P_DATAIN_DT jz p_data;
686 cmp A,P_COMMAND je p_command;
687 cmp A,P_MESGOUT je p_mesgout;
688 cmp A,P_STATUS je p_status;
689 cmp A,P_MESGIN je p_mesgin;
690
691 SET_SEQINTCODE(BAD_PHASE)
692 jmp ITloop; /* Try reading the bus again. */
693
694/*
695 * Command phase. Set up the DMA registers and let 'er rip.
696 */
697p_command:
698 test SEQ_FLAGS, NOT_IDENTIFIED jz p_command_okay;
699 SET_SEQINTCODE(PROTO_VIOLATION)
700p_command_okay:
701 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
702 jnz p_command_allocate_fifo;
703 /*
704 * Command retry. Free our current FIFO and
705 * re-allocate a FIFO so transfer state is
706 * reset.
707 */
708SET_SRC_MODE M_DFF1;
709SET_DST_MODE M_DFF1;
710 mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
711 SET_MODE(M_SCSI, M_SCSI)
712p_command_allocate_fifo:
713 bmov ALLOCFIFO_SCBPTR, SCBPTR, 2;
714 call allocate_fifo;
715SET_SRC_MODE M_DFF1;
716SET_DST_MODE M_DFF1;
717 add NONE, -17, SCB_CDB_LEN;
718 jnc p_command_embedded;
719p_command_from_host:
720 bmov HADDR[0], SCB_HOST_CDB_PTR, 9;
721 mvi SG_CACHE_PRE, LAST_SEG;
722 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
723 jmp p_command_xfer;
724p_command_embedded:
725 bmov SHCNT[0], SCB_CDB_LEN, 1;
726 bmov DFDAT, SCB_CDB_STORE, 16;
727 mvi DFCNTRL, SCSIEN;
728p_command_xfer:
729 and SEQ_FLAGS, ~NO_CDB_SENT;
730 test DFCNTRL, SCSIEN jnz .;
731 /*
732 * DMA Channel automatically disabled.
733 * Don't allow a data phase if the command
734 * was not fully transferred.
735 */
736 test SSTAT2, SDONE jnz ITloop;
737 or SEQ_FLAGS, NO_CDB_SENT;
738 jmp ITloop;
739
740
741/*
742 * Status phase. Wait for the data byte to appear, then read it
743 * and store it into the SCB.
744 */
745SET_SRC_MODE M_SCSI;
746SET_DST_MODE M_SCSI;
747p_status:
748 test SEQ_FLAGS,NOT_IDENTIFIED jnz mesgin_proto_violation;
749p_status_okay:
750 mov SCB_SCSI_STATUS, SCSIDAT;
751 or SCB_CONTROL, STATUS_RCVD;
752 jmp ITloop;
753
754/*
755 * Message out phase. If MSG_OUT is MSG_IDENTIFYFLAG, build a full
756 * indentify message sequence and send it to the target. The host may
757 * override this behavior by setting the MK_MESSAGE bit in the SCB
758 * control byte. This will cause us to interrupt the host and allow
759 * it to handle the message phase completely on its own. If the bit
760 * associated with this target is set, we will also interrupt the host,
761 * thereby allowing it to send a message on the next selection regardless
762 * of the transaction being sent.
763 *
764 * If MSG_OUT is == HOST_MSG, also interrupt the host and take a message.
765 * This is done to allow the host to send messages outside of an identify
766 * sequence while protecting the seqencer from testing the MK_MESSAGE bit
767 * on an SCB that might not be for the current nexus. (For example, a
768 * BDR message in responce to a bad reselection would leave us pointed to
769 * an SCB that doesn't have anything to do with the current target).
770 *
771 * Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag,
772 * bus device reset).
773 *
774 * When there are no messages to send, MSG_OUT should be set to MSG_NOOP,
775 * in case the target decides to put us in this phase for some strange
776 * reason.
777 */
778p_mesgout_retry:
779 /* Turn on ATN for the retry */
780 mvi SCSISIGO, ATNO;
781p_mesgout:
782 mov SINDEX, MSG_OUT;
783 cmp SINDEX, MSG_IDENTIFYFLAG jne p_mesgout_from_host;
784 test SCB_CONTROL,MK_MESSAGE jnz host_message_loop;
785p_mesgout_identify:
786 or SINDEX, MSG_IDENTIFYFLAG|DISCENB, SCB_LUN;
787 test SCB_CONTROL, DISCENB jnz . + 2;
788 and SINDEX, ~DISCENB;
789/*
790 * Send a tag message if TAG_ENB is set in the SCB control block.
791 * Use SCB_NONPACKET_TAG as the tag value.
792 */
793p_mesgout_tag:
794 test SCB_CONTROL,TAG_ENB jz p_mesgout_onebyte;
795 mov SCSIDAT, SINDEX; /* Send the identify message */
796 call phase_lock;
797 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
798 and SCSIDAT,TAG_ENB|SCB_TAG_TYPE,SCB_CONTROL;
799 call phase_lock;
800 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
801 mov SCBPTR jmp p_mesgout_onebyte;
802/*
803 * Interrupt the driver, and allow it to handle this message
804 * phase and any required retries.
805 */
806p_mesgout_from_host:
807 cmp SINDEX, HOST_MSG jne p_mesgout_onebyte;
808 jmp host_message_loop;
809
810p_mesgout_onebyte:
811 mvi CLRSINT1, CLRATNO;
812 mov SCSIDAT, SINDEX;
813
814/*
815 * If the next bus phase after ATN drops is message out, it means
816 * that the target is requesting that the last message(s) be resent.
817 */
818 call phase_lock;
819 cmp LASTPHASE, P_MESGOUT je p_mesgout_retry;
820
821p_mesgout_done:
822 mvi CLRSINT1,CLRATNO; /* Be sure to turn ATNO off */
823 mov LAST_MSG, MSG_OUT;
824 mvi MSG_OUT, MSG_NOOP; /* No message left */
825 jmp ITloop;
826
827/*
828 * Message in phase. Bytes are read using Automatic PIO mode.
829 */
830p_mesgin:
831 /* read the 1st message byte */
832 mvi ACCUM call inb_first;
833
834 test A,MSG_IDENTIFYFLAG jnz mesgin_identify;
835 cmp A,MSG_DISCONNECT je mesgin_disconnect;
836 cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs;
837 cmp ALLZEROS,A je mesgin_complete;
838 cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs;
839 cmp A,MSG_IGN_WIDE_RESIDUE je mesgin_ign_wide_residue;
840 cmp A,MSG_NOOP je mesgin_done;
841
842/*
843 * Pushed message loop to allow the kernel to
844 * run it's own message state engine. To avoid an
845 * extra nop instruction after signaling the kernel,
846 * we perform the phase_lock before checking to see
847 * if we should exit the loop and skip the phase_lock
848 * in the ITloop. Performing back to back phase_locks
849 * shouldn't hurt, but why do it twice...
850 */
851host_message_loop:
852 call phase_lock; /* Benign the first time through. */
853 SET_SEQINTCODE(HOST_MSG_LOOP)
854 cmp RETURN_1, EXIT_MSG_LOOP je ITloop;
855 cmp RETURN_1, CONT_MSG_LOOP_WRITE jne . + 3;
856 mov SCSIDAT, RETURN_2;
857 jmp host_message_loop;
858 /* Must be CONT_MSG_LOOP_READ */
859 mov NONE, SCSIDAT; /* ACK Byte */
860 jmp host_message_loop;
861
862mesgin_ign_wide_residue:
863 mov SAVED_MODE, MODE_PTR;
864 SET_MODE(M_SCSI, M_SCSI)
865 shr NEGOADDR, 4, SAVED_SCSIID;
866 mov A, NEGCONOPTS;
867 RESTORE_MODE(SAVED_MODE)
868 test A, WIDEXFER jz mesgin_reject;
869 /* Pull the residue byte */
870 mvi REG0 call inb_next;
871 cmp REG0, 0x01 jne mesgin_reject;
872 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 2;
873 test SCB_TASK_ATTRIBUTE, SCB_XFERLEN_ODD jnz mesgin_done;
874 SET_SEQINTCODE(IGN_WIDE_RES)
875 jmp mesgin_done;
876
877mesgin_proto_violation:
878 SET_SEQINTCODE(PROTO_VIOLATION)
879 jmp mesgin_done;
880mesgin_reject:
881 mvi MSG_MESSAGE_REJECT call mk_mesg;
882mesgin_done:
883 mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
884 jmp ITloop;
885
886#define INDEX_DISC_LIST(scsiid, lun) \
887 and A, 0xC0, scsiid; \
888 or SCBPTR, A, lun; \
889 clr SCBPTR[1]; \
890 and SINDEX, 0x30, scsiid; \
891 shr SINDEX, 3; /* Multiply by 2 */ \
892 add SINDEX, (SCB_DISCONNECTED_LISTS & 0xFF); \
893 mvi SINDEX[1], ((SCB_DISCONNECTED_LISTS >> 8) & 0xFF)
894
895mesgin_identify:
896 /*
897 * Determine whether a target is using tagged or non-tagged
898 * transactions by first looking at the transaction stored in
899 * the per-device, disconnected array. If there is no untagged
900 * transaction for this target, this must be a tagged transaction.
901 */
902 and SAVED_LUN, MSG_IDENTIFY_LUNMASK, A;
903 INDEX_DISC_LIST(SAVED_SCSIID, SAVED_LUN);
904 bmov DINDEX, SINDEX, 2;
905 bmov REG0, SINDIR, 2;
906 cmp REG0[1], SCB_LIST_NULL je snoop_tag;
907 /* Untagged. Clear the busy table entry and setup the SCB. */
908 bmov DINDIR, ALLONES, 2;
909 bmov SCBPTR, REG0, 2;
910 jmp setup_SCB;
911
912/*
913 * Here we "snoop" the bus looking for a SIMPLE QUEUE TAG message.
914 * If we get one, we use the tag returned to find the proper
915 * SCB. After receiving the tag, look for the SCB at SCB locations tag and
916 * tag + 256.
917 */
918snoop_tag:
919 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
920 or SEQ_FLAGS, 0x80;
921 }
922 mov NONE, SCSIDAT; /* ACK Identify MSG */
923 call phase_lock;
924 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
925 or SEQ_FLAGS, 0x1;
926 }
927 cmp LASTPHASE, P_MESGIN jne not_found_ITloop;
928 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
929 or SEQ_FLAGS, 0x2;
930 }
931 cmp SCSIBUS, MSG_SIMPLE_Q_TAG jne not_found;
932get_tag:
933 clr SCBPTR[1];
934 mvi SCBPTR call inb_next; /* tag value */
935verify_scb:
936 test SCB_CONTROL,DISCONNECTED jz verify_other_scb;
937 mov A, SAVED_SCSIID;
938 cmp SCB_SCSIID, A jne verify_other_scb;
939 mov A, SAVED_LUN;
940 cmp SCB_LUN, A je setup_SCB_disconnected;
941verify_other_scb:
942 xor SCBPTR[1], 1;
943 test SCBPTR[1], 0xFF jnz verify_scb;
944 jmp not_found;
945
946/*
947 * Ensure that the SCB the tag points to is for
948 * an SCB transaction to the reconnecting target.
949 */
950setup_SCB:
951 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
952 or SEQ_FLAGS, 0x10;
953 }
954 test SCB_CONTROL,DISCONNECTED jz not_found;
955setup_SCB_disconnected:
956 and SCB_CONTROL,~DISCONNECTED;
957 clr SEQ_FLAGS; /* make note of IDENTIFY */
958 test SCB_SGPTR, SG_LIST_NULL jnz . + 3;
959 bmov ALLOCFIFO_SCBPTR, SCBPTR, 2;
960 call allocate_fifo;
961 /* See if the host wants to send a message upon reconnection */
962 test SCB_CONTROL, MK_MESSAGE jz mesgin_done;
963 mvi HOST_MSG call mk_mesg;
964 jmp mesgin_done;
965
966not_found:
967 SET_SEQINTCODE(NO_MATCH)
968 jmp mesgin_done;
969
970not_found_ITloop:
971 SET_SEQINTCODE(NO_MATCH)
972 jmp ITloop;
973
974/*
975 * We received a "command complete" message. Put the SCB on the complete
976 * queue and trigger a completion interrupt via the idle loop. Before doing
977 * so, check to see if there
978 * is a residual or the status byte is something other than STATUS_GOOD (0).
979 * In either of these conditions, we upload the SCB back to the host so it can
980 * process this information. In the case of a non zero status byte, we
981 * additionally interrupt the kernel driver synchronously, allowing it to
982 * decide if sense should be retrieved. If the kernel driver wishes to request
983 * sense, it will fill the kernel SCB with a request sense command, requeue
984 * it to the QINFIFO and tell us not to post to the QOUTFIFO by setting
985 * RETURN_1 to SEND_SENSE.
986 */
987mesgin_complete:
988
989 /*
990 * If ATN is raised, we still want to give the target a message.
991 * Perhaps there was a parity error on this last message byte.
992 * Either way, the target should take us to message out phase
993 * and then attempt to complete the command again. We should use a
994 * critical section here to guard against a timeout triggering
995 * for this command and setting ATN while we are still processing
996 * the completion.
997 test SCSISIGI, ATNI jnz mesgin_done;
998 */
999
1000 /*
1001 * If we are identified and have successfully sent the CDB,
1002 * any status will do. Optimize this fast path.
1003 */
1004 test SCB_CONTROL, STATUS_RCVD jz mesgin_proto_violation;
1005 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz complete_accepted;
1006
1007 /*
1008 * If the target never sent an identify message but instead went
1009 * to mesgin to give an invalid message, let the host abort us.
1010 */
1011 test SEQ_FLAGS, NOT_IDENTIFIED jnz mesgin_proto_violation;
1012
1013 /*
1014 * If we recevied good status but never successfully sent the
1015 * cdb, abort the command.
1016 */
1017 test SCB_SCSI_STATUS,0xff jnz complete_accepted;
1018 test SEQ_FLAGS, NO_CDB_SENT jnz mesgin_proto_violation;
1019complete_accepted:
1020
1021 /*
1022 * See if we attempted to deliver a message but the target ingnored us.
1023 */
1024 test SCB_CONTROL, MK_MESSAGE jz complete_nomsg;
1025 SET_SEQINTCODE(MKMSG_FAILED)
1026complete_nomsg:
1027 call queue_scb_completion;
1028 jmp await_busfree;
1029
1030freeze_queue:
1031 /* Cancel any pending select-out. */
1032 test SSTAT0, SELDO|SELINGO jnz . + 2;
1033 and SCSISEQ0, ~ENSELO;
1034 mov ACCUM_SAVE, A;
1035 clr A;
1036 add QFREEZE_COUNT, 1;
1037 adc QFREEZE_COUNT[1], A;
1038 or SEQ_FLAGS2, SELECTOUT_QFROZEN;
1039 mov A, ACCUM_SAVE ret;
1040
1041/*
1042 * Complete the current FIFO's SCB if data for this same
1043 * SCB is not transferring in the other FIFO.
1044 */
1045SET_SRC_MODE M_DFF1;
1046SET_DST_MODE M_DFF1;
1047pkt_complete_scb_if_fifos_idle:
1048 bmov ARG_1, SCBPTR, 2;
1049 mvi DFFSXFRCTL, CLRCHN;
1050 SET_MODE(M_SCSI, M_SCSI)
1051 bmov SCBPTR, ARG_1, 2;
1052 test SCB_FIFO_USE_COUNT, 0xFF jnz return;
1053queue_scb_completion:
1054 test SCB_SCSI_STATUS,0xff jnz bad_status;
1055 /*
1056 * Check for residuals
1057 */
1058 test SCB_SGPTR, SG_LIST_NULL jnz complete; /* No xfer */
1059 test SCB_SGPTR, SG_FULL_RESID jnz upload_scb;/* Never xfered */
1060 test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jz upload_scb;
1061complete:
1062 bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
1063 bmov COMPLETE_SCB_HEAD, SCBPTR, 2 ret;
1064bad_status:
1065 cmp SCB_SCSI_STATUS, STATUS_PKT_SENSE je upload_scb;
1066 call freeze_queue;
1067upload_scb:
1068 /*
1069 * Restore SCB TAG since we reuse this field
1070 * in the sequencer. We don't want to corrupt
1071 * it on the host.
1072 */
1073 bmov SCB_TAG, SCBPTR, 2;
1074 bmov SCB_NEXT_COMPLETE, COMPLETE_DMA_SCB_HEAD, 2;
1075 bmov COMPLETE_DMA_SCB_HEAD, SCBPTR, 2;
1076 or SCB_SGPTR, SG_STATUS_VALID ret;
1077
1078/*
1079 * Is it a disconnect message? Set a flag in the SCB to remind us
1080 * and await the bus going free. If this is an untagged transaction
1081 * store the SCB id for it in our untagged target table for lookup on
1082 * a reselction.
1083 */
1084mesgin_disconnect:
1085 /*
1086 * If ATN is raised, we still want to give the target a message.
1087 * Perhaps there was a parity error on this last message byte
1088 * or we want to abort this command. Either way, the target
1089 * should take us to message out phase and then attempt to
1090 * disconnect again.
1091 * XXX - Wait for more testing.
1092 test SCSISIGI, ATNI jnz mesgin_done;
1093 */
1094 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT
1095 jnz mesgin_proto_violation;
1096 or SCB_CONTROL,DISCONNECTED;
1097 test SCB_CONTROL, TAG_ENB jnz await_busfree;
1098queue_disc_scb:
1099 bmov REG0, SCBPTR, 2;
1100 INDEX_DISC_LIST(SAVED_SCSIID, SAVED_LUN);
1101 bmov DINDEX, SINDEX, 2;
1102 bmov DINDIR, REG0, 2;
1103 bmov SCBPTR, REG0, 2;
1104 /* FALLTHROUGH */
1105await_busfree:
1106 and SIMODE1, ~ENBUSFREE;
1107 if ((ahd->bugs & AHD_BUSFREEREV_BUG) == 0) {
1108 /*
1109 * In the BUSFREEREV_BUG case, the
1110 * busfree status was cleared at the
1111 * beginning of the connection.
1112 */
1113 mvi CLRSINT1,CLRBUSFREE;
1114 }
1115 mov NONE, SCSIDAT; /* Ack the last byte */
1116 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
1117 jnz await_busfree_not_m_dff;
1118SET_SRC_MODE M_DFF1;
1119SET_DST_MODE M_DFF1;
1120await_busfree_clrchn:
1121 mvi DFFSXFRCTL, CLRCHN;
1122await_busfree_not_m_dff:
1123 call clear_target_state;
1124 test SSTAT1,REQINIT|BUSFREE jz .;
1125 test SSTAT1, BUSFREE jnz idle_loop;
1126 SET_SEQINTCODE(MISSED_BUSFREE)
1127
1128
1129/*
1130 * Save data pointers message:
1131 * Copying RAM values back to SCB, for Save Data Pointers message, but
1132 * only if we've actually been into a data phase to change them. This
1133 * protects against bogus data in scratch ram and the residual counts
1134 * since they are only initialized when we go into data_in or data_out.
1135 * Ack the message as soon as possible.
1136 */
1137SET_SRC_MODE M_DFF1;
1138SET_DST_MODE M_DFF1;
1139mesgin_sdptrs:
1140 mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
1141 test SEQ_FLAGS, DPHASE jz ITloop;
1142 call save_pointers;
1143 jmp ITloop;
1144
1145save_pointers:
1146 /*
1147 * If we are asked to save our position at the end of the
1148 * transfer, just mark us at the end rather than perform a
1149 * full save.
1150 */
1151 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz save_pointers_full;
1152 or SCB_SGPTR, SG_LIST_NULL ret;
1153
1154save_pointers_full:
1155 /*
1156 * The SCB_DATAPTR becomes the current SHADDR.
1157 * All other information comes directly from our residual
1158 * state.
1159 */
1160 bmov SCB_DATAPTR, SHADDR, 8;
1161 bmov SCB_DATACNT, SCB_RESIDUAL_DATACNT, 8 ret;
1162
1163/*
1164 * Restore pointers message? Data pointers are recopied from the
1165 * SCB anytime we enter a data phase for the first time, so all
1166 * we need to do is clear the DPHASE flag and let the data phase
1167 * code do the rest. We also reset/reallocate the FIFO to make
1168 * sure we have a clean start for the next data or command phase.
1169 */
1170mesgin_rdptrs:
1171 and SEQ_FLAGS, ~DPHASE;
1172 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1)) jnz msgin_rdptrs_get_fifo;
1173 mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
1174 SET_MODE(M_SCSI, M_SCSI)
1175msgin_rdptrs_get_fifo:
1176 call allocate_fifo;
1177 jmp mesgin_done;
1178
1179clear_target_state:
1180 mvi LASTPHASE, P_BUSFREE;
1181 /* clear target specific flags */
1182 mvi SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT ret;
1183
1184phase_lock:
1185 if ((ahd->bugs & AHD_EARLY_REQ_BUG) != 0) {
1186 /*
1187 * Don't ignore persistent REQ assertions just because
1188 * they were asserted within the bus settle delay window.
1189 * This allows us to tolerate devices like the GEM318
1190 * that violate the SCSI spec. We are careful not to
1191 * count REQ while we are waiting for it to fall during
1192 * an async phase due to our asserted ACK. Each
1193 * sequencer instruction takes ~25ns, so the REQ must
1194 * last at least 100ns in order to be counted as a true
1195 * REQ.
1196 */
1197 test SCSIPHASE, 0xFF jnz phase_locked;
1198 test SCSISIGI, ACKI jnz phase_lock;
1199 test SCSISIGI, REQI jz phase_lock;
1200 test SCSIPHASE, 0xFF jnz phase_locked;
1201 test SCSISIGI, ACKI jnz phase_lock;
1202 test SCSISIGI, REQI jz phase_lock;
1203phase_locked:
1204 } else {
1205 test SCSIPHASE, 0xFF jz .;
1206 }
1207 test SSTAT1, SCSIPERR jnz phase_lock;
1208phase_lock_latch_phase:
1209 and LASTPHASE, PHASE_MASK, SCSISIGI ret;
1210
1211/*
1212 * Functions to read data in Automatic PIO mode.
1213 *
1214 * An ACK is not sent on input from the target until SCSIDATL is read from.
1215 * So we wait until SCSIDATL is latched (the usual way), then read the data
1216 * byte directly off the bus using SCSIBUSL. When we have pulled the ATN
1217 * line, or we just want to acknowledge the byte, then we do a dummy read
1218 * from SCISDATL. The SCSI spec guarantees that the target will hold the
1219 * data byte on the bus until we send our ACK.
1220 *
1221 * The assumption here is that these are called in a particular sequence,
1222 * and that REQ is already set when inb_first is called. inb_{first,next}
1223 * use the same calling convention as inb.
1224 */
1225inb_next:
1226 mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
1227inb_next_wait:
1228 /*
1229 * If there is a parity error, wait for the kernel to
1230 * see the interrupt and prepare our message response
1231 * before continuing.
1232 */
1233 test SCSIPHASE, 0xFF jz .;
1234 test SSTAT1, SCSIPERR jnz inb_next_wait;
1235inb_next_check_phase:
1236 and LASTPHASE, PHASE_MASK, SCSISIGI;
1237 cmp LASTPHASE, P_MESGIN jne mesgin_phasemis;
1238inb_first:
1239 clr DINDEX[1];
1240 mov DINDEX,SINDEX;
1241 mov DINDIR,SCSIBUS ret; /*read byte directly from bus*/
1242inb_last:
1243 mov NONE,SCSIDAT ret; /*dummy read from latch to ACK*/
1244
1245mk_mesg:
1246 mvi SCSISIGO, ATNO;
1247 mov MSG_OUT,SINDEX ret;
1248
1249SET_SRC_MODE M_DFF1;
1250SET_DST_MODE M_DFF1;
1251disable_ccsgen:
1252 test SG_STATE, FETCH_INPROG jz disable_ccsgen_fetch_done;
1253 clr CCSGCTL;
1254disable_ccsgen_fetch_done:
1255 clr SG_STATE ret;
1256
1257service_fifo:
1258 /*
1259 * Do we have any prefetch left???
1260 */
1261 test SG_STATE, SEGS_AVAIL jnz idle_sg_avail;
1262
1263 /*
1264 * Can this FIFO have access to the S/G cache yet?
1265 */
1266 test CCSGCTL, SG_CACHE_AVAIL jz return;
1267
1268 /* Did we just finish fetching segs? */
1269 test CCSGCTL, CCSGDONE jnz idle_sgfetch_complete;
1270
1271 /* Are we actively fetching segments? */
1272 test CCSGCTL, CCSGENACK jnz return;
1273
1274 /*
1275 * We fetch a "cacheline aligned" and sized amount of data
1276 * so we don't end up referencing a non-existant page.
1277 * Cacheline aligned is in quotes because the kernel will
1278 * set the prefetch amount to a reasonable level if the
1279 * cacheline size is unknown.
1280 */
1281 bmov SGHADDR, SCB_RESIDUAL_SGPTR, 4;
1282 mvi SGHCNT, SG_PREFETCH_CNT;
1283 if ((ahd->bugs & AHD_REG_SLOW_SETTLE_BUG) != 0) {
1284 /*
1285 * Need two instruction between "touches" of SGHADDR.
1286 */
1287 nop;
1288 }
1289 and SGHADDR[0], SG_PREFETCH_ALIGN_MASK, SCB_RESIDUAL_SGPTR;
1290 mvi CCSGCTL, CCSGEN|CCSGRESET;
1291 or SG_STATE, FETCH_INPROG ret;
1292idle_sgfetch_complete:
1293 /*
1294 * Guard against SG_CACHE_AVAIL activating during sg fetch
1295 * request in the other FIFO.
1296 */
1297 test SG_STATE, FETCH_INPROG jz return;
1298 clr CCSGCTL;
1299 and CCSGADDR, SG_PREFETCH_ADDR_MASK, SCB_RESIDUAL_SGPTR;
1300 mvi SG_STATE, SEGS_AVAIL|LOADING_NEEDED;
1301idle_sg_avail:
1302 /* Does the hardware have space for another SG entry? */
1303 test DFSTATUS, PRELOAD_AVAIL jz return;
1304 /*
1305 * On the A, preloading a segment before HDMAENACK
1306 * comes true can clobber the shaddow address of the
1307 * first segment in the S/G FIFO. Wait until it is
1308 * safe to proceed.
1309 */
1310 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) == 0) {
1311 test DFCNTRL, HDMAENACK jz return;
1312 }
1313 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
1314 bmov HADDR, CCSGRAM, 8;
1315 } else {
1316 bmov HADDR, CCSGRAM, 4;
1317 }
1318 bmov HCNT, CCSGRAM, 3;
1319 bmov SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1;
1320 if ((ahd->flags & AHD_39BIT_ADDRESSING) != 0) {
1321 and HADDR[4], SG_HIGH_ADDR_BITS, SCB_RESIDUAL_DATACNT[3];
1322 }
1323 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
1324 /* Skip 4 bytes of pad. */
1325 add CCSGADDR, 4;
1326 }
1327sg_advance:
1328 clr A; /* add sizeof(struct scatter) */
1329 add SCB_RESIDUAL_SGPTR[0],SG_SIZEOF;
1330 adc SCB_RESIDUAL_SGPTR[1],A;
1331 adc SCB_RESIDUAL_SGPTR[2],A;
1332 adc SCB_RESIDUAL_SGPTR[3],A;
1333 mov SINDEX, SCB_RESIDUAL_SGPTR[0];
1334 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 3;
1335 or SINDEX, LAST_SEG;
1336 clr SG_STATE;
1337 mov SG_CACHE_PRE, SINDEX;
1338 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) != 0) {
1339 /*
1340 * Use SCSIENWRDIS so that SCSIEN is never
1341 * modified by this operation.
1342 */
1343 or DFCNTRL, PRELOADEN|HDMAEN|SCSIENWRDIS;
1344 } else {
1345 or DFCNTRL, PRELOADEN|HDMAEN;
1346 }
1347 /*
1348 * Do we have another segment in the cache?
1349 */
1350 add NONE, SG_PREFETCH_CNT_LIMIT, CCSGADDR;
1351 jnc return;
1352 and SG_STATE, ~SEGS_AVAIL ret;
1353
1354/*
1355 * Initialize the DMA address and counter from the SCB.
1356 */
1357load_first_seg:
1358 bmov HADDR, SCB_DATAPTR, 11;
1359 and REG_ISR, ~SG_FULL_RESID, SCB_SGPTR[0];
1360 test SCB_DATACNT[3], SG_LAST_SEG jz . + 2;
1361 or REG_ISR, LAST_SEG;
1362 mov SG_CACHE_PRE, REG_ISR;
1363 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
1364 /*
1365 * Since we've are entering a data phase, we will
1366 * rely on the SCB_RESID* fields. Initialize the
1367 * residual and clear the full residual flag.
1368 */
1369 and SCB_SGPTR[0], ~SG_FULL_RESID;
1370 bmov SCB_RESIDUAL_DATACNT[3], SCB_DATACNT[3], 5;
1371 /* If we need more S/G elements, tell the idle loop */
1372 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jnz . + 2;
1373 mvi SG_STATE, LOADING_NEEDED ret;
1374 clr SG_STATE ret;
1375
1376p_data_handle_xfer:
1377 call setjmp;
1378 test SG_STATE, LOADING_NEEDED jnz service_fifo;
1379p_data_clear_handler:
1380 or LONGJMP_ADDR[1], INVALID_ADDR ret;
1381
1382p_data:
1383 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz p_data_allowed;
1384 SET_SEQINTCODE(PROTO_VIOLATION)
1385p_data_allowed:
1386
1387 test SEQ_FLAGS, DPHASE jz data_phase_initialize;
1388
1389 /*
1390 * If we re-enter the data phase after going through another
1391 * phase, our transfer location has almost certainly been
1392 * corrupted by the interveining, non-data, transfers. Ask
1393 * the host driver to fix us up based on the transfer residual
1394 * unless we already know that we should be bitbucketing.
1395 */
1396 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jnz p_data_bitbucket;
1397 SET_SEQINTCODE(PDATA_REINIT)
1398 jmp data_phase_inbounds;
1399
1400p_data_bitbucket:
1401 /*
1402 * Turn on `Bit Bucket' mode, wait until the target takes
1403 * us to another phase, and then notify the host.
1404 */
1405 mov SAVED_MODE, MODE_PTR;
1406 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
1407 jnz bitbucket_not_m_dff;
1408 /*
1409 * Ensure that any FIFO contents are cleared out and the
1410 * FIFO free'd prior to starting the BITBUCKET. BITBUCKET
1411 * doesn't discard data already in the FIFO.
1412 */
1413 mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
1414 SET_MODE(M_SCSI, M_SCSI)
1415bitbucket_not_m_dff:
1416 or SXFRCTL1,BITBUCKET;
1417 /* Wait for non-data phase. */
1418 test SCSIPHASE, ~DATA_PHASE_MASK jz .;
1419 and SXFRCTL1, ~BITBUCKET;
1420 RESTORE_MODE(SAVED_MODE)
1421SET_SRC_MODE M_DFF1;
1422SET_DST_MODE M_DFF1;
1423 SET_SEQINTCODE(DATA_OVERRUN)
1424 jmp ITloop;
1425
1426data_phase_initialize:
1427 test SCB_SGPTR[0], SG_LIST_NULL jnz p_data_bitbucket;
1428 call load_first_seg;
1429data_phase_inbounds:
1430 /* We have seen a data phase at least once. */
1431 or SEQ_FLAGS, DPHASE;
1432 mov SAVED_MODE, MODE_PTR;
1433 test SG_STATE, LOADING_NEEDED jz data_group_dma_loop;
1434 call p_data_handle_xfer;
1435data_group_dma_loop:
1436 /*
1437 * The transfer is complete if either the last segment
1438 * completes or the target changes phase. Both conditions
1439 * will clear SCSIEN.
1440 */
1441 call idle_loop_service_fifos;
1442 call idle_loop_cchan;
1443 call idle_loop_gsfifo;
1444 RESTORE_MODE(SAVED_MODE)
1445 test DFCNTRL, SCSIEN jnz data_group_dma_loop;
1446
1447data_group_dmafinish:
1448 /*
1449 * The transfer has terminated either due to a phase
1450 * change, and/or the completion of the last segment.
1451 * We have two goals here. Do as much other work
1452 * as possible while the data fifo drains on a read
1453 * and respond as quickly as possible to the standard
1454 * messages (save data pointers/disconnect and command
1455 * complete) that usually follow a data phase.
1456 */
1457 call calc_residual;
1458
1459 /*
1460 * Go ahead and shut down the DMA engine now.
1461 */
1462 test DFCNTRL, DIRECTION jnz data_phase_finish;
1463data_group_fifoflush:
1464 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
1465 or DFCNTRL, FIFOFLUSH;
1466 }
1467 /*
1468 * We have enabled the auto-ack feature. This means
1469 * that the controller may have already transferred
1470 * some overrun bytes into the data FIFO and acked them
1471 * on the bus. The only way to detect this situation is
1472 * to wait for LAST_SEG_DONE to come true on a completed
1473 * transfer and then test to see if the data FIFO is
1474 * non-empty. We know there is more data yet to transfer
1475 * if SG_LIST_NULL is not yet set, thus there cannot be
1476 * an overrun.
1477 */
1478 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz data_phase_finish;
1479 test SG_CACHE_SHADOW, LAST_SEG_DONE jz .;
1480 test DFSTATUS, FIFOEMP jnz data_phase_finish;
1481 /* Overrun */
1482 jmp p_data;
1483data_phase_finish:
1484 /*
1485 * If the target has left us in data phase, loop through
1486 * the dma code again. We will only loop if there is a
1487 * data overrun.
1488 */
1489 if ((ahd->flags & AHD_TARGETROLE) != 0) {
1490 test SSTAT0, TARGET jnz data_phase_done;
1491 }
1492 if ((ahd->flags & AHD_INITIATORROLE) != 0) {
1493 test SSTAT1, REQINIT jz .;
1494 test SCSIPHASE, DATA_PHASE_MASK jnz p_data;
1495 }
1496
1497data_phase_done:
1498 /* Kill off any pending prefetch */
1499 call disable_ccsgen;
1500 or LONGJMP_ADDR[1], INVALID_ADDR;
1501
1502 if ((ahd->flags & AHD_TARGETROLE) != 0) {
1503 test SEQ_FLAGS, DPHASE_PENDING jz ITloop;
1504 /*
1505 and SEQ_FLAGS, ~DPHASE_PENDING;
1506 * For data-in phases, wait for any pending acks from the
1507 * initiator before changing phase. We only need to
1508 * send Ignore Wide Residue messages for data-in phases.
1509 test DFCNTRL, DIRECTION jz target_ITloop;
1510 test SSTAT1, REQINIT jnz .;
1511 test SCB_TASK_ATTRIBUTE, SCB_XFERLEN_ODD jz target_ITloop;
1512 SET_MODE(M_SCSI, M_SCSI)
1513 test NEGCONOPTS, WIDEXFER jz target_ITloop;
1514 */
1515 /*
1516 * Issue an Ignore Wide Residue Message.
1517 mvi P_MESGIN|BSYO call change_phase;
1518 mvi MSG_IGN_WIDE_RESIDUE call target_outb;
1519 mvi 1 call target_outb;
1520 jmp target_ITloop;
1521 */
1522 } else {
1523 jmp ITloop;
1524 }
1525
1526/*
1527 * We assume that, even though data may still be
1528 * transferring to the host, that the SCSI side of
1529 * the DMA engine is now in a static state. This
1530 * allows us to update our notion of where we are
1531 * in this transfer.
1532 *
1533 * If, by chance, we stopped before being able
1534 * to fetch additional segments for this transfer,
1535 * yet the last S/G was completely exhausted,
1536 * call our idle loop until it is able to load
1537 * another segment. This will allow us to immediately
1538 * pickup on the next segment on the next data phase.
1539 *
1540 * If we happened to stop on the last segment, then
1541 * our residual information is still correct from
1542 * the idle loop and there is no need to perform
1543 * any fixups.
1544 */
1545residual_before_last_seg:
1546 test MDFFSTAT, SHVALID jnz sgptr_fixup;
1547 /*
1548 * Can never happen from an interrupt as the packetized
1549 * hardware will only interrupt us once SHVALID or
1550 * LAST_SEG_DONE.
1551 */
1552 call idle_loop_service_fifos;
1553 RESTORE_MODE(SAVED_MODE)
1554 /* FALLTHROUGH */
1555calc_residual:
1556 test SG_CACHE_SHADOW, LAST_SEG jz residual_before_last_seg;
1557 /* Record if we've consumed all S/G entries */
1558 test MDFFSTAT, SHVALID jz . + 2;
1559 bmov SCB_RESIDUAL_DATACNT, SHCNT, 3 ret;
1560 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL ret;
1561
1562sgptr_fixup:
1563 /*
1564 * Fixup the residual next S/G pointer. The S/G preload
1565 * feature of the chip allows us to load two elements
1566 * in addition to the currently active element. We
1567 * store the bottom byte of the next S/G pointer in
1568 * the SG_CACHE_PTR register so we can restore the
1569 * correct value when the DMA completes. If the next
1570 * sg ptr value has advanced to the point where higher
1571 * bytes in the address have been affected, fix them
1572 * too.
1573 */
1574 test SG_CACHE_SHADOW, 0x80 jz sgptr_fixup_done;
1575 test SCB_RESIDUAL_SGPTR[0], 0x80 jnz sgptr_fixup_done;
1576 add SCB_RESIDUAL_SGPTR[1], -1;
1577 adc SCB_RESIDUAL_SGPTR[2], -1;
1578 adc SCB_RESIDUAL_SGPTR[3], -1;
1579sgptr_fixup_done:
1580 and SCB_RESIDUAL_SGPTR[0], SG_ADDR_MASK, SG_CACHE_SHADOW;
1581 clr SCB_RESIDUAL_DATACNT[3]; /* We are not the last seg */
1582 bmov SCB_RESIDUAL_DATACNT, SHCNT, 3 ret;
1583
1584export timer_isr:
1585 call issue_cmdcmplt;
1586 mvi CLRSEQINTSTAT, CLRSEQ_SWTMRTO;
1587 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) {
1588 /*
1589 * In H2A4, the mode pointer is not saved
1590 * for intvec2, but is restored on iret.
1591 * This can lead to the restoration of a
1592 * bogus mode ptr. Manually clear the
1593 * intmask bits and do a normal return
1594 * to compensate.
1595 */
1596 and SEQINTCTL, ~(INTMASK2|INTMASK1) ret;
1597 } else {
1598 or SEQINTCTL, IRET ret;
1599 }
1600
1601export seq_isr:
1602 if ((ahd->features & AHD_RTI) == 0) {
1603 /*
1604 * On RevA Silicon, if the target returns us to data-out
1605 * after we have already trained for data-out, it is
1606 * possible for us to transition the free running clock to
1607 * data-valid before the required 100ns P1 setup time (8 P1
1608 * assertions in fast-160 mode). This will only happen if
1609 * this L-Q is a continuation of a data transfer for which
1610 * we have already prefetched data into our FIFO (LQ/Data
1611 * followed by LQ/Data for the same write transaction).
1612 * This can cause some target implementations to miss the
1613 * first few data transfers on the bus. We detect this
1614 * situation by noticing that this is the first data transfer
1615 * after an LQ (LQIWORKONLQ true), that the data transfer is
1616 * a continuation of a transfer already setup in our FIFO
1617 * (SAVEPTRS interrupt), and that the transaction is a write
1618 * (DIRECTION set in DFCNTRL). The delay is performed by
1619 * disabling SCSIEN until we see the first REQ from the
1620 * target.
1621 *
1622 * First instruction in an ISR cannot be a branch on
1623 * Rev A. Snapshot LQISTAT2 so the status is not missed
1624 * and deffer the test by one instruction.
1625 */
1626 mov REG_ISR, LQISTAT2;
1627 test REG_ISR, LQIWORKONLQ jz main_isr;
1628 test SEQINTSRC, SAVEPTRS jz main_isr;
1629 test LONGJMP_ADDR[1], INVALID_ADDR jz saveptr_active_fifo;
1630 /*
1631 * Switch to the active FIFO after clearing the snapshot
1632 * savepointer in the current FIFO. We do this so that
1633 * a pending CTXTDONE or SAVEPTR is visible in the active
1634 * FIFO. This status is the only way we can detect if we
1635 * have lost the race (e.g. host paused us) and our attepts
1636 * to disable the channel occurred after all REQs were
1637 * already seen and acked (REQINIT never comes true).
1638 */
1639 mvi DFFSXFRCTL, CLRCHN;
1640 xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
1641 test DFCNTRL, DIRECTION jz interrupt_return;
1642 and DFCNTRL, ~SCSIEN;
1643snapshot_wait_data_valid:
1644 test SEQINTSRC, (CTXTDONE|SAVEPTRS) jnz snapshot_data_valid;
1645 test SSTAT1, REQINIT jz snapshot_wait_data_valid;
1646snapshot_data_valid:
1647 or DFCNTRL, SCSIEN;
1648 or SEQINTCTL, IRET ret;
1649snapshot_saveptr:
1650 mvi DFFSXFRCTL, CLRCHN;
1651 or SEQINTCTL, IRET ret;
1652main_isr:
1653 }
1654 test SEQINTSRC, CFG4DATA jnz cfg4data_intr;
1655 test SEQINTSRC, CFG4ISTAT jnz cfg4istat_intr;
1656 test SEQINTSRC, SAVEPTRS jnz saveptr_intr;
1657 test SEQINTSRC, CFG4ICMD jnz cfg4icmd_intr;
1658 SET_SEQINTCODE(INVALID_SEQINT)
1659
1660/*
1661 * There are two types of save pointers interrupts:
1662 * The first is a snapshot save pointers where the current FIFO is not
1663 * active and contains a snapshot of the current poniter information.
1664 * This happens between packets in a stream for a single L_Q. Since we
1665 * are not performing a pointer save, we can safely clear the channel
1666 * so it can be used for other transactions. On RTI capable controllers,
1667 * where snapshots can, and are, disabled, the code to handle this type
1668 * of snapshot is not active.
1669 *
1670 * The second case is a save pointers on an active FIFO which occurs
1671 * if the target changes to a new L_Q or busfrees/QASes and the transfer
1672 * has a residual. This should occur coincident with a ctxtdone. We
1673 * disable the interrupt and allow our active routine to handle the
1674 * save.
1675 */
1676saveptr_intr:
1677 if ((ahd->features & AHD_RTI) == 0) {
1678 test LONGJMP_ADDR[1], INVALID_ADDR jnz snapshot_saveptr;
1679 }
1680saveptr_active_fifo:
1681 and SEQIMODE, ~ENSAVEPTRS;
1682 or SEQINTCTL, IRET ret;
1683
1684cfg4data_intr:
1685 test SCB_SGPTR[0], SG_LIST_NULL jnz pkt_handle_overrun_inc_use_count;
1686 call load_first_seg;
1687 call pkt_handle_xfer;
1688 inc SCB_FIFO_USE_COUNT;
1689interrupt_return:
1690 or SEQINTCTL, IRET ret;
1691
1692cfg4istat_intr:
1693 call freeze_queue;
1694 add NONE, -13, SCB_CDB_LEN;
1695 jnc cfg4istat_have_sense_addr;
1696 test SCB_CDB_LEN, SCB_CDB_LEN_PTR jnz cfg4istat_have_sense_addr;
1697 /*
1698 * Host sets up address/count and enables transfer.
1699 */
1700 SET_SEQINTCODE(CFG4ISTAT_INTR)
1701 jmp cfg4istat_setup_handler;
1702cfg4istat_have_sense_addr:
1703 bmov HADDR, SCB_SENSE_BUSADDR, 4;
1704 mvi HCNT[1], (AHD_SENSE_BUFSIZE >> 8);
1705 mvi SG_CACHE_PRE, LAST_SEG;
1706 mvi DFCNTRL, PRELOADEN|SCSIEN|HDMAEN;
1707cfg4istat_setup_handler:
1708 /*
1709 * Status pkt is transferring to host.
1710 * Wait in idle loop for transfer to complete.
1711 * If a command completed before an attempted
1712 * task management function completed, notify the host.
1713 */
1714 test SCB_TASK_MANAGEMENT, 0xFF jz cfg4istat_no_taskmgmt_func;
1715 SET_SEQINTCODE(TASKMGMT_CMD_CMPLT_OKAY)
1716cfg4istat_no_taskmgmt_func:
1717 call pkt_handle_status;
1718 or SEQINTCTL, IRET ret;
1719
1720cfg4icmd_intr:
1721 /*
1722 * In the case of DMAing a CDB from the host, the normal
1723 * CDB buffer is formatted with an 8 byte address followed
1724 * by a 1 byte count.
1725 */
1726 bmov HADDR[0], SCB_HOST_CDB_PTR, 9;
1727 mvi SG_CACHE_PRE, LAST_SEG;
1728 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
1729 call pkt_handle_cdb;
1730 or SEQINTCTL, IRET ret;
1731
1732/*
1733 * See if the target has gone on in this context creating an
1734 * overrun condition. For the write case, the hardware cannot
1735 * ack bytes until data are provided. So, if the target begins
1736 * another packet without changing contexts, implying we are
1737 * not sitting on a packet boundary, we are in an overrun
1738 * situation. For the read case, the hardware will continue to
1739 * ack bytes into the FIFO, and may even ack the last overrun packet
1740 * into the FIFO. If the FIFO should become non-empty, we are in
1741 * a read overrun case.
1742 */
1743#define check_overrun \
1744 /* Not on a packet boundary. */ \
1745 test MDFFSTAT, DLZERO jz pkt_handle_overrun; \
1746 test DFSTATUS, FIFOEMP jz pkt_handle_overrun
1747
1748pkt_handle_xfer:
1749 test SG_STATE, LOADING_NEEDED jz pkt_last_seg;
1750 call setjmp;
1751 test SEQINTSRC, SAVEPTRS jnz pkt_saveptrs;
1752 test SCSIPHASE, ~DATA_PHASE_MASK jz . + 2;
1753 test SCSISIGO, ATNO jnz . + 2;
1754 test SSTAT2, NONPACKREQ jz pkt_service_fifo;
1755 /*
1756 * Defer handling of this NONPACKREQ until we
1757 * can be sure it pertains to this FIFO. SAVEPTRS
1758 * will not be asserted if the NONPACKREQ is for us,
1759 * so we must simulate it if shaddow is valid. If
1760 * shaddow is not valid, keep running this FIFO until we
1761 * have satisfied the transfer by loading segments and
1762 * waiting for either shaddow valid or last_seg_done.
1763 */
1764 test MDFFSTAT, SHVALID jnz pkt_saveptrs;
1765pkt_service_fifo:
1766 test SG_STATE, LOADING_NEEDED jnz service_fifo;
1767pkt_last_seg:
1768 call setjmp;
1769 test SEQINTSRC, SAVEPTRS jnz pkt_saveptrs;
1770 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz pkt_last_seg_done;
1771 test SCSIPHASE, ~DATA_PHASE_MASK jz . + 2;
1772 test SCSISIGO, ATNO jnz . + 2;
1773 test SSTAT2, NONPACKREQ jz return;
1774 test MDFFSTAT, SHVALID jz return;
1775 /* FALLTHROUGH */
1776
1777/*
1778 * Either a SAVEPTRS interrupt condition is pending for this FIFO
1779 * or we have a pending NONPACKREQ for this FIFO. We differentiate
1780 * between the two by capturing the state of the SAVEPTRS interrupt
1781 * prior to clearing this status and executing the common code for
1782 * these two cases.
1783 */
1784pkt_saveptrs:
1785BEGIN_CRITICAL;
1786 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
1787 or DFCNTRL, FIFOFLUSH;
1788 }
1789 mov REG0, SEQINTSRC;
1790 call calc_residual;
1791 call save_pointers;
1792 mvi CLRSEQINTSRC, CLRSAVEPTRS;
1793 call disable_ccsgen;
1794 or SEQIMODE, ENSAVEPTRS;
1795 test DFCNTRL, DIRECTION jnz pkt_saveptrs_check_status;
1796 test DFSTATUS, FIFOEMP jnz pkt_saveptrs_check_status;
1797 /*
1798 * Keep a handler around for this FIFO until it drains
1799 * to the host to guarantee that we don't complete the
1800 * command to the host before the data arrives.
1801 */
1802pkt_saveptrs_wait_fifoemp:
1803 call setjmp;
1804 test DFSTATUS, FIFOEMP jz return;
1805pkt_saveptrs_check_status:
1806 or LONGJMP_ADDR[1], INVALID_ADDR;
1807 test REG0, SAVEPTRS jz unexpected_nonpkt_phase;
1808 dec SCB_FIFO_USE_COUNT;
1809 test SCB_CONTROL, STATUS_RCVD jnz pkt_complete_scb_if_fifos_idle;
1810 mvi DFFSXFRCTL, CLRCHN ret;
1811END_CRITICAL;
1812
1813/*
1814 * LAST_SEG_DONE status has been seen in the current FIFO.
1815 * This indicates that all of the allowed data for this
1816 * command has transferred across the SCSI and host buses.
1817 * Check for overrun and see if we can complete this command.
1818 */
1819pkt_last_seg_done:
1820BEGIN_CRITICAL;
1821 /*
1822 * Mark transfer as completed.
1823 */
1824 or SCB_SGPTR, SG_LIST_NULL;
1825
1826 /*
1827 * Wait for the current context to finish to verify that
1828 * no overrun condition has occurred.
1829 */
1830 test SEQINTSRC, CTXTDONE jnz pkt_ctxt_done;
1831 call setjmp;
1832pkt_wait_ctxt_done_loop:
1833 test SEQINTSRC, CTXTDONE jnz pkt_ctxt_done;
1834 /*
1835 * A sufficiently large overrun or a NONPACKREQ may
1836 * prevent CTXTDONE from ever asserting, so we must
1837 * poll for these statuses too.
1838 */
1839 check_overrun;
1840 test SSTAT2, NONPACKREQ jz return;
1841 test SEQINTSRC, CTXTDONE jz unexpected_nonpkt_phase;
1842 /* FALLTHROUGH */
1843
1844pkt_ctxt_done:
1845 check_overrun;
1846 or LONGJMP_ADDR[1], INVALID_ADDR;
1847 /*
1848 * If status has been received, it is safe to skip
1849 * the check to see if another FIFO is active because
1850 * LAST_SEG_DONE has been observed. However, we check
1851 * the FIFO anyway since it costs us only one extra
1852 * instruction to leverage common code to perform the
1853 * SCB completion.
1854 */
1855 dec SCB_FIFO_USE_COUNT;
1856 test SCB_CONTROL, STATUS_RCVD jnz pkt_complete_scb_if_fifos_idle;
1857 mvi DFFSXFRCTL, CLRCHN ret;
1858END_CRITICAL;
1859
1860/*
1861 * Must wait until CDB xfer is over before issuing the
1862 * clear channel.
1863 */
1864pkt_handle_cdb:
1865 call setjmp;
1866 test SG_CACHE_SHADOW, LAST_SEG_DONE jz return;
1867 or LONGJMP_ADDR[1], INVALID_ADDR;
1868 mvi DFFSXFRCTL, CLRCHN ret;
1869
1870/*
1871 * Watch over the status transfer. Our host sense buffer is
1872 * large enough to take the maximum allowed status packet.
1873 * None-the-less, we must still catch and report overruns to
1874 * the host. Additionally, properly catch unexpected non-packet
1875 * phases that are typically caused by CRC errors in status packet
1876 * transmission.
1877 */
1878pkt_handle_status:
1879 call setjmp;
1880 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz pkt_status_check_overrun;
1881 test SEQINTSRC, CTXTDONE jz pkt_status_check_nonpackreq;
1882 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz pkt_status_check_overrun;
1883pkt_status_IU_done:
1884 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
1885 or DFCNTRL, FIFOFLUSH;
1886 }
1887 test DFSTATUS, FIFOEMP jz return;
1888BEGIN_CRITICAL;
1889 or LONGJMP_ADDR[1], INVALID_ADDR;
1890 mvi SCB_SCSI_STATUS, STATUS_PKT_SENSE;
1891 or SCB_CONTROL, STATUS_RCVD;
1892 jmp pkt_complete_scb_if_fifos_idle;
1893END_CRITICAL;
1894pkt_status_check_overrun:
1895 /*
1896 * Status PKT overruns are uncerimoniously recovered with a
1897 * bus reset. If we've overrun, let the host know so that
1898 * recovery can be performed.
1899 *
1900 * LAST_SEG_DONE has been observed. If either CTXTDONE or
1901 * a NONPACKREQ phase change have occurred and the FIFO is
1902 * empty, there is no overrun.
1903 */
1904 test DFSTATUS, FIFOEMP jz pkt_status_report_overrun;
1905 test SEQINTSRC, CTXTDONE jz . + 2;
1906 test DFSTATUS, FIFOEMP jnz pkt_status_IU_done;
1907 test SCSIPHASE, ~DATA_PHASE_MASK jz return;
1908 test DFSTATUS, FIFOEMP jnz pkt_status_check_nonpackreq;
1909pkt_status_report_overrun:
1910 SET_SEQINTCODE(STATUS_OVERRUN)
1911 /* SEQUENCER RESTARTED */
1912pkt_status_check_nonpackreq:
1913 /*
1914 * CTXTDONE may be held off if a NONPACKREQ is associated with
1915 * the current context. If a NONPACKREQ is observed, decide
1916 * if it is for the current context. If it is for the current
1917 * context, we must defer NONPACKREQ processing until all data
1918 * has transferred to the host.
1919 */
1920 test SCSIPHASE, ~DATA_PHASE_MASK jz return;
1921 test SCSISIGO, ATNO jnz . + 2;
1922 test SSTAT2, NONPACKREQ jz return;
1923 test SEQINTSRC, CTXTDONE jnz pkt_status_IU_done;
1924 test DFSTATUS, FIFOEMP jz return;
1925 /*
1926 * The unexpected nonpkt phase handler assumes that any
1927 * data channel use will have a FIFO reference count. It
1928 * turns out that the status handler doesn't need a refernce
1929 * count since the status received flag, and thus completion
1930 * processing, cannot be set until the handler is finished.
1931 * We increment the count here to make the nonpkt handler
1932 * happy.
1933 */
1934 inc SCB_FIFO_USE_COUNT;
1935 /* FALLTHROUGH */
1936
1937/*
1938 * Nonpackreq is a polled status. It can come true in three situations:
1939 * we have received an L_Q, we have sent one or more L_Qs, or there is no
1940 * L_Q context associated with this REQ (REQ occurs immediately after a
1941 * (re)selection). Routines that know that the context responsible for this
1942 * nonpackreq call directly into unexpected_nonpkt_phase. In the case of the
1943 * top level idle loop, we exhaust all active contexts prior to determining that
1944 * we simply do not have the full I_T_L_Q for this phase.
1945 */
1946unexpected_nonpkt_phase_find_ctxt:
1947 /*
1948 * This nonpackreq is most likely associated with one of the tags
1949 * in a FIFO or an outgoing LQ. Only treat it as an I_T only
1950 * nonpackreq if we've cleared out the FIFOs and handled any
1951 * pending SELDO.
1952 */
1953SET_SRC_MODE M_SCSI;
1954SET_DST_MODE M_SCSI;
1955 and A, FIFO1FREE|FIFO0FREE, DFFSTAT;
1956 cmp A, FIFO1FREE|FIFO0FREE jne return;
1957 test SSTAT0, SELDO jnz return;
1958 mvi SCBPTR[1], SCB_LIST_NULL;
1959unexpected_nonpkt_phase:
5288fd4c
PA
1960 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
1961 jnz unexpected_nonpkt_mode_cleared;
984263bc
MD
1962SET_SRC_MODE M_DFF0;
1963SET_DST_MODE M_DFF0;
1964 or LONGJMP_ADDR[1], INVALID_ADDR;
1965 dec SCB_FIFO_USE_COUNT;
1966 mvi DFFSXFRCTL, CLRCHN;
5288fd4c 1967unexpected_nonpkt_mode_cleared:
984263bc
MD
1968 mvi CLRSINT2, CLRNONPACKREQ;
1969 test SCSIPHASE, ~(MSG_IN_PHASE|MSG_OUT_PHASE) jnz illegal_phase;
1970 SET_SEQINTCODE(ENTERING_NONPACK)
1971 jmp ITloop;
1972
1973illegal_phase:
1974 SET_SEQINTCODE(ILLEGAL_PHASE)
1975 jmp ITloop;
1976
1977/*
1978 * We have entered an overrun situation. If we have working
1979 * BITBUCKET, flip that on and let the hardware eat any overrun
1980 * data. Otherwise use an overrun buffer in the host to simulate
1981 * BITBUCKET.
1982 */
1983pkt_handle_overrun_inc_use_count:
1984 inc SCB_FIFO_USE_COUNT;
1985pkt_handle_overrun:
1986 SET_SEQINTCODE(CFG4OVERRUN)
1987 call freeze_queue;
1988 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) == 0) {
1989 or DFFSXFRCTL, DFFBITBUCKET;
1990SET_SRC_MODE M_DFF1;
1991SET_DST_MODE M_DFF1;
1992 } else {
1993 call load_overrun_buf;
1994 mvi DFCNTRL, (HDMAEN|SCSIEN|PRELOADEN);
1995 }
1996 call setjmp;
1997 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
1998 test DFSTATUS, PRELOAD_AVAIL jz overrun_load_done;
1999 call load_overrun_buf;
2000 or DFCNTRL, PRELOADEN;
2001overrun_load_done:
2002 test SEQINTSRC, CTXTDONE jnz pkt_overrun_end;
2003 } else {
2004 test DFFSXFRCTL, DFFBITBUCKET jz pkt_overrun_end;
2005 }
2006 test SSTAT2, NONPACKREQ jz return;
2007pkt_overrun_end:
2008 or SCB_RESIDUAL_SGPTR, SG_OVERRUN_RESID;
2009 test SEQINTSRC, CTXTDONE jz unexpected_nonpkt_phase;
2010 dec SCB_FIFO_USE_COUNT;
2011 or LONGJMP_ADDR[1], INVALID_ADDR;
2012 test SCB_CONTROL, STATUS_RCVD jnz pkt_complete_scb_if_fifos_idle;
2013 mvi DFFSXFRCTL, CLRCHN ret;
2014
2015if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
2016load_overrun_buf:
2017 /*
2018 * Load a dummy segment if preload space is available.
2019 */
2020 mov HADDR[0], SHARED_DATA_ADDR;
2021 add HADDR[1], PKT_OVERRUN_BUFOFFSET, SHARED_DATA_ADDR[1];
2022 mov ACCUM_SAVE, A;
2023 clr A;
2024 adc HADDR[2], A, SHARED_DATA_ADDR[2];
2025 adc HADDR[3], A, SHARED_DATA_ADDR[3];
2026 mov A, ACCUM_SAVE;
2027 bmov HADDR[4], ALLZEROS, 4;
2028 /* PKT_OVERRUN_BUFSIZE is a multiple of 256 */
2029 clr HCNT[0];
2030 mvi HCNT[1], ((PKT_OVERRUN_BUFSIZE >> 8) & 0xFF);
2031 clr HCNT[2] ret;
2032}