Add the SiS "7007" OHCI IEEE 1394 controller.
[dragonfly.git] / sys / bus / firewire / fwohcireg.h
CommitLineData
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1/*
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the acknowledgement as bellow:
16 *
17 * This product includes software developed by K. Kobayashi and H. Shimokawa
18 *
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
78748771 34 * $FreeBSD: src/sys/dev/firewire/fwohcireg.h,v 1.15 2004/01/06 14:24:01 simokawa Exp $
3672879e 35 * $DragonFly: src/sys/bus/firewire/fwohcireg.h,v 1.11 2004/07/16 12:37:02 asmodai Exp $
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36 *
37 */
38#define PCI_CBMEM 0x10
39
88436e3a 40#define FW_VENDORID_NATSEMI 0x1000
984263bc 41#define FW_VENDORID_NEC 0x1033
3672879e 42#define FW_VENDORID_SIS 0x1039
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43#define FW_VENDORID_TI 0x104c
44#define FW_VENDORID_SONY 0x104d
45#define FW_VENDORID_VIA 0x1106
46#define FW_VENDORID_RICOH 0x1180
47#define FW_VENDORID_APPLE 0x106b
48#define FW_VENDORID_LUCENT 0x11c1
169a6807 49#define FW_VENDORID_INTEL 0x8086
6f4f7256 50#define FW_VENDORID_ADAPTEC 0x9004
984263bc 51
88436e3a 52#define FW_DEVICE_CS4210 (0x000f << 16)
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53#define FW_DEVICE_UPD861 (0x0063 << 16)
54#define FW_DEVICE_UPD871 (0x00ce << 16)
55#define FW_DEVICE_UPD72870 (0x00cd << 16)
63cc36d5 56#define FW_DEVICE_UPD72873 (0x00e7 << 16)
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57#define FW_DEVICE_UPD72874 (0x00f2 << 16)
58#define FW_DEVICE_TITSB22 (0x8009 << 16)
59#define FW_DEVICE_TITSB23 (0x8019 << 16)
60#define FW_DEVICE_TITSB26 (0x8020 << 16)
61#define FW_DEVICE_TITSB43 (0x8021 << 16)
62#define FW_DEVICE_TITSB43A (0x8023 << 16)
63#define FW_DEVICE_TITSB43AB23 (0x8024 << 16)
78748771 64#define FW_DEVICE_TITSB82AA2 (0x8025 << 16)
6256cfa5 65#define FW_DEVICE_TITSB43AB21 (0x8026 << 16)
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66#define FW_DEVICE_TIPCI4410A (0x8017 << 16)
67#define FW_DEVICE_TIPCI4450 (0x8011 << 16)
68#define FW_DEVICE_TIPCI4451 (0x8027 << 16)
69#define FW_DEVICE_CX3022 (0x8039 << 16)
70#define FW_DEVICE_VT6306 (0x3044 << 16)
71#define FW_DEVICE_R5C551 (0x0551 << 16)
72#define FW_DEVICE_R5C552 (0x0552 << 16)
73#define FW_DEVICE_PANGEA (0x0030 << 16)
74#define FW_DEVICE_UNINORTH (0x0031 << 16)
6f4f7256 75#define FW_DEVICE_AIC5800 (0x5800 << 16)
984263bc 76#define FW_DEVICE_FW322 (0x5811 << 16)
3672879e 77#define FW_DEVICE_7007 (0x7007 << 16)
169a6807 78#define FW_DEVICE_82372FB (0x7605 << 16)
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79
80#define PCI_INTERFACE_OHCI 0x10
81
82#define FW_OHCI_BASE_REG 0x10
83
84#define OHCI_DMA_ITCH 0x20
85#define OHCI_DMA_IRCH 0x20
86
87#define OHCI_MAX_DMA_CH (0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH)
88
89
78748771 90typedef u_int32_t fwohcireg_t;
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91
92/* for PCI */
93#if BYTE_ORDER == BIG_ENDIAN
94#define FWOHCI_DMA_WRITE(x, y) ((x) = htole32(y))
95#define FWOHCI_DMA_READ(x) le32toh(x)
96#define FWOHCI_DMA_SET(x, y) ((x) |= htole32(y))
97#define FWOHCI_DMA_CLEAR(x, y) ((x) &= htole32(~(y)))
98#else
99#define FWOHCI_DMA_WRITE(x, y) ((x) = (y))
100#define FWOHCI_DMA_READ(x) (x)
101#define FWOHCI_DMA_SET(x, y) ((x) |= (y))
102#define FWOHCI_DMA_CLEAR(x, y) ((x) &= ~(y))
103#endif
104
105struct fwohcidb {
106 union {
107 struct {
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108 u_int32_t cmd;
109 u_int32_t addr;
110 u_int32_t depend;
111 u_int32_t res;
984263bc 112 } desc;
78748771 113 u_int32_t immed[4];
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114 } db;
115#define OHCI_STATUS_SHIFT 16
116#define OHCI_COUNT_MASK 0xffff
117#define OHCI_OUTPUT_MORE (0 << 28)
118#define OHCI_OUTPUT_LAST (1 << 28)
119#define OHCI_INPUT_MORE (2 << 28)
120#define OHCI_INPUT_LAST (3 << 28)
121#define OHCI_STORE_QUAD (4 << 28)
122#define OHCI_LOAD_QUAD (5 << 28)
123#define OHCI_NOP (6 << 28)
124#define OHCI_STOP (7 << 28)
125#define OHCI_STORE (8 << 28)
126#define OHCI_CMD_MASK (0xf << 28)
127
128#define OHCI_UPDATE (1 << 27)
129
130#define OHCI_KEY_ST0 (0 << 24)
131#define OHCI_KEY_ST1 (1 << 24)
132#define OHCI_KEY_ST2 (2 << 24)
133#define OHCI_KEY_ST3 (3 << 24)
134#define OHCI_KEY_REGS (5 << 24)
135#define OHCI_KEY_SYS (6 << 24)
136#define OHCI_KEY_DEVICE (7 << 24)
137#define OHCI_KEY_MASK (7 << 24)
138
139#define OHCI_INTERRUPT_NEVER (0 << 20)
140#define OHCI_INTERRUPT_TRUE (1 << 20)
141#define OHCI_INTERRUPT_FALSE (2 << 20)
142#define OHCI_INTERRUPT_ALWAYS (3 << 20)
143
144#define OHCI_BRANCH_NEVER (0 << 18)
145#define OHCI_BRANCH_TRUE (1 << 18)
146#define OHCI_BRANCH_FALSE (2 << 18)
147#define OHCI_BRANCH_ALWAYS (3 << 18)
148#define OHCI_BRANCH_MASK (3 << 18)
149
150#define OHCI_WAIT_NEVER (0 << 16)
151#define OHCI_WAIT_TRUE (1 << 16)
152#define OHCI_WAIT_FALSE (2 << 16)
153#define OHCI_WAIT_ALWAYS (3 << 16)
154};
155
156#define OHCI_SPD_S100 0x4
157#define OHCI_SPD_S200 0x1
158#define OHCI_SPD_S400 0x2
159
160
161#define FWOHCIEV_NOSTAT 0
162#define FWOHCIEV_LONGP 2
163#define FWOHCIEV_MISSACK 3
164#define FWOHCIEV_UNDRRUN 4
165#define FWOHCIEV_OVRRUN 5
166#define FWOHCIEV_DESCERR 6
167#define FWOHCIEV_DTRDERR 7
168#define FWOHCIEV_DTWRERR 8
169#define FWOHCIEV_BUSRST 9
170#define FWOHCIEV_TIMEOUT 0xa
171#define FWOHCIEV_TCODERR 0xb
172#define FWOHCIEV_UNKNOWN 0xe
173#define FWOHCIEV_FLUSHED 0xf
174#define FWOHCIEV_ACKCOMPL 0x11
175#define FWOHCIEV_ACKPEND 0x12
176#define FWOHCIEV_ACKBSX 0x14
177#define FWOHCIEV_ACKBSA 0x15
178#define FWOHCIEV_ACKBSB 0x16
179#define FWOHCIEV_ACKTARD 0x1b
180#define FWOHCIEV_ACKDERR 0x1d
181#define FWOHCIEV_ACKTERR 0x1e
182
183#define FWOHCIEV_MASK 0x1f
184
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185struct ohci_dma{
186 fwohcireg_t cntl;
187
188#define OHCI_CNTL_CYCMATCH_S (0x1 << 31)
189
190#define OHCI_CNTL_BUFFIL (0x1 << 31)
191#define OHCI_CNTL_ISOHDR (0x1 << 30)
192#define OHCI_CNTL_CYCMATCH_R (0x1 << 29)
193#define OHCI_CNTL_MULTICH (0x1 << 28)
194
195#define OHCI_CNTL_DMA_RUN (0x1 << 15)
196#define OHCI_CNTL_DMA_WAKE (0x1 << 12)
197#define OHCI_CNTL_DMA_DEAD (0x1 << 11)
198#define OHCI_CNTL_DMA_ACTIVE (0x1 << 10)
199#define OHCI_CNTL_DMA_BT (0x1 << 8)
200#define OHCI_CNTL_DMA_BAD (0x1 << 7)
201#define OHCI_CNTL_DMA_STAT (0xff)
202
203 fwohcireg_t cntl_clr;
204 fwohcireg_t dummy0;
205 fwohcireg_t cmd;
206 fwohcireg_t match;
207 fwohcireg_t dummy1;
208 fwohcireg_t dummy2;
209 fwohcireg_t dummy3;
210};
211
212struct ohci_itdma{
213 fwohcireg_t cntl;
214 fwohcireg_t cntl_clr;
215 fwohcireg_t dummy0;
216 fwohcireg_t cmd;
217};
218
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219struct ohci_registers {
220 fwohcireg_t ver; /* Version No. 0x0 */
221 fwohcireg_t guid; /* GUID_ROM No. 0x4 */
222 fwohcireg_t retry; /* AT retries 0x8 */
223#define FWOHCI_RETRY 0x8
224 fwohcireg_t csr_data; /* CSR data 0xc */
225 fwohcireg_t csr_cmp; /* CSR compare 0x10 */
226 fwohcireg_t csr_cntl; /* CSR compare 0x14 */
227 fwohcireg_t rom_hdr; /* config ROM ptr. 0x18 */
228 fwohcireg_t bus_id; /* BUS_ID 0x1c */
229 fwohcireg_t bus_opt; /* BUS option 0x20 */
230#define FWOHCIGUID_H 0x24
231#define FWOHCIGUID_L 0x28
232 fwohcireg_t guid_hi; /* GUID hi 0x24 */
233 fwohcireg_t guid_lo; /* GUID lo 0x28 */
234 fwohcireg_t dummy0[2]; /* dummy 0x2c-0x30 */
235 fwohcireg_t config_rom; /* config ROM map 0x34 */
236 fwohcireg_t post_wr_lo; /* post write addr lo 0x38 */
237 fwohcireg_t post_wr_hi; /* post write addr hi 0x3c */
238 fwohcireg_t vender; /* vender ID 0x40 */
239 fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */
240 fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */
241 fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */
242#define OHCI_HCC_BIBIV (1 << 31) /* BIBimage Valid */
243#define OHCI_HCC_BIGEND (1 << 30) /* noByteSwapData */
244#define OHCI_HCC_PRPHY (1 << 23) /* programPhyEnable */
245#define OHCI_HCC_PHYEN (1 << 22) /* aPhyEnhanceEnable */
246#define OHCI_HCC_LPS (1 << 19) /* LPS */
247#define OHCI_HCC_POSTWR (1 << 18) /* postedWriteEnable */
248#define OHCI_HCC_LINKEN (1 << 17) /* linkEnable */
249#define OHCI_HCC_RESET (1 << 16) /* softReset */
250 fwohcireg_t dummy2[2]; /* dummy 0x58-0x5c */
251 fwohcireg_t dummy3[1]; /* dummy 0x60 */
252 fwohcireg_t sid_buf; /* self id buffer 0x64 */
253 fwohcireg_t sid_cnt; /* self id count 0x68 */
254 fwohcireg_t dummy4[1]; /* dummy 0x6c */
255 fwohcireg_t ir_mask_hi_set; /* ir mask hi set 0x70 */
256 fwohcireg_t ir_mask_hi_clr; /* ir mask hi set 0x74 */
257 fwohcireg_t ir_mask_lo_set; /* ir mask hi set 0x78 */
258 fwohcireg_t ir_mask_lo_clr; /* ir mask hi set 0x7c */
259#define FWOHCI_INTSTAT 0x80
260#define FWOHCI_INTSTATCLR 0x84
261#define FWOHCI_INTMASK 0x88
262#define FWOHCI_INTMASKCLR 0x8c
263 fwohcireg_t int_stat; /* 0x80 */
264 fwohcireg_t int_clear; /* 0x84 */
265 fwohcireg_t int_mask; /* 0x88 */
266 fwohcireg_t int_mask_clear; /* 0x8c */
267 fwohcireg_t it_int_stat; /* 0x90 */
268 fwohcireg_t it_int_clear; /* 0x94 */
269 fwohcireg_t it_int_mask; /* 0x98 */
270 fwohcireg_t it_mask_clear; /* 0x9c */
271 fwohcireg_t ir_int_stat; /* 0xa0 */
272 fwohcireg_t ir_int_clear; /* 0xa4 */
273 fwohcireg_t ir_int_mask; /* 0xa8 */
274 fwohcireg_t ir_mask_clear; /* 0xac */
275 fwohcireg_t dummy5[11]; /* dummy 0xb0-d8 */
276 fwohcireg_t fairness; /* fairness control 0xdc */
277 fwohcireg_t link_cntl; /* Chip control 0xe0*/
278 fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/
279#define FWOHCI_NODEID 0xe8
280 fwohcireg_t node; /* Node ID 0xe8 */
281#define OHCI_NODE_VALID (1 << 31)
282#define OHCI_NODE_ROOT (1 << 30)
283
284#define OHCI_ASYSRCBUS 1
285
286 fwohcireg_t phy_access; /* PHY cntl 0xec */
287#define PHYDEV_RDDONE (1<<31)
288#define PHYDEV_RDCMD (1<<15)
289#define PHYDEV_WRCMD (1<<14)
290#define PHYDEV_REGADDR 8
291#define PHYDEV_WRDATA 0
292#define PHYDEV_RDADDR 24
293#define PHYDEV_RDDATA 16
294
295 fwohcireg_t cycle_timer; /* Cycle Timer 0xf0 */
296 fwohcireg_t dummy6[3]; /* dummy 0xf4-fc */
297 fwohcireg_t areq_hi; /* Async req. filter hi 0x100 */
298 fwohcireg_t areq_hi_clr; /* Async req. filter hi 0x104 */
299 fwohcireg_t areq_lo; /* Async req. filter lo 0x108 */
300 fwohcireg_t areq_lo_clr; /* Async req. filter lo 0x10c */
301 fwohcireg_t preq_hi; /* Async req. filter hi 0x110 */
302 fwohcireg_t preq_hi_clr; /* Async req. filter hi 0x114 */
303 fwohcireg_t preq_lo; /* Async req. filter lo 0x118 */
304 fwohcireg_t preq_lo_clr; /* Async req. filter lo 0x11c */
305
306 fwohcireg_t pys_upper; /* Physical Upper bound 0x120 */
307
308 fwohcireg_t dummy7[23]; /* dummy 0x124-0x17c */
309
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310 /* 0x180, 0x184, 0x188, 0x18c */
311 /* 0x190, 0x194, 0x198, 0x19c */
312 /* 0x1a0, 0x1a4, 0x1a8, 0x1ac */
313 /* 0x1b0, 0x1b4, 0x1b8, 0x1bc */
314 /* 0x1c0, 0x1c4, 0x1c8, 0x1cc */
315 /* 0x1d0, 0x1d4, 0x1d8, 0x1dc */
316 /* 0x1e0, 0x1e4, 0x1e8, 0x1ec */
317 /* 0x1f0, 0x1f4, 0x1f8, 0x1fc */
318 struct ohci_dma dma_ch[0x4];
319
320 /* 0x200, 0x204, 0x208, 0x20c */
321 /* 0x210, 0x204, 0x208, 0x20c */
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322 struct ohci_itdma dma_itch[0x20];
323
324 /* 0x400, 0x404, 0x408, 0x40c */
325 /* 0x410, 0x404, 0x408, 0x40c */
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326 struct ohci_dma dma_irch[0x20];
327};
328
329struct fwohcidb_tr{
330 STAILQ_ENTRY(fwohcidb_tr) link;
331 struct fw_xfer *xfer;
78748771 332 struct fwohcidb *db;
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333 bus_dmamap_t dma_map;
334 caddr_t buf;
335 bus_addr_t bus_addr;
336 int dbcnt;
337};
338
339/*
340 * OHCI info structure.
341 */
342struct fwohci_txpkthdr{
343 union{
344 u_int32_t ld[4];
345 struct {
346#if BYTE_ORDER == BIG_ENDIAN
78748771 347 u_int32_t spd:16, /* XXX include reserved field */
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348 :8,
349 tcode:4,
350 :4;
351#else
352 u_int32_t :4,
353 tcode:4,
354 :8,
78748771 355 spd:16; /* XXX include reserved fields */
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356#endif
357 }common;
358 struct {
359#if BYTE_ORDER == BIG_ENDIAN
360 u_int32_t :8,
361 srcbus:1,
362 :4,
363 spd:3,
364 tlrt:8,
365 tcode:4,
366 :4;
367#else
368 u_int32_t :4,
369 tcode:4,
370 tlrt:8,
371 spd:3,
372 :4,
373 srcbus:1,
374 :8;
375#endif
376 BIT16x2(dst, );
377 }asycomm;
378 struct {
379#if BYTE_ORDER == BIG_ENDIAN
380 u_int32_t :13,
381 spd:3,
382 chtag:8,
383 tcode:4,
384 sy:4;
385#else
386 u_int32_t sy:4,
387 tcode:4,
388 chtag:8,
389 spd:3,
390 :13;
391#endif
392 BIT16x2(len, );
393 }stream;
394 }mode;
395};
396struct fwohci_trailer{
397 u_int32_t time:16,
398 stat:16;
399};
400
401#define OHCI_CNTL_CYCSRC (0x1 << 22)
402#define OHCI_CNTL_CYCMTR (0x1 << 21)
403#define OHCI_CNTL_CYCTIMER (0x1 << 20)
404#define OHCI_CNTL_PHYPKT (0x1 << 10)
405#define OHCI_CNTL_SID (0x1 << 9)
406
407#define OHCI_INT_DMA_ATRQ (0x1 << 0)
408#define OHCI_INT_DMA_ATRS (0x1 << 1)
409#define OHCI_INT_DMA_ARRQ (0x1 << 2)
410#define OHCI_INT_DMA_ARRS (0x1 << 3)
411#define OHCI_INT_DMA_PRRQ (0x1 << 4)
412#define OHCI_INT_DMA_PRRS (0x1 << 5)
413#define OHCI_INT_DMA_IT (0x1 << 6)
414#define OHCI_INT_DMA_IR (0x1 << 7)
415#define OHCI_INT_PW_ERR (0x1 << 8)
416#define OHCI_INT_LR_ERR (0x1 << 9)
417
418#define OHCI_INT_PHY_SID (0x1 << 16)
419#define OHCI_INT_PHY_BUS_R (0x1 << 17)
420
421#define OHCI_INT_REG_FAIL (0x1 << 18)
422
423#define OHCI_INT_PHY_INT (0x1 << 19)
424#define OHCI_INT_CYC_START (0x1 << 20)
425#define OHCI_INT_CYC_64SECOND (0x1 << 21)
426#define OHCI_INT_CYC_LOST (0x1 << 22)
427#define OHCI_INT_CYC_ERR (0x1 << 23)
428
429#define OHCI_INT_ERR (0x1 << 24)
430#define OHCI_INT_CYC_LONG (0x1 << 25)
431#define OHCI_INT_PHY_REG (0x1 << 26)
432
433#define OHCI_INT_EN (0x1 << 31)
434
435#define IP_CHANNELS 0x0234
436#define FWOHCI_MAXREC 2048
437
438#define OHCI_ISORA 0x02
439#define OHCI_ISORB 0x04
440
441#define FWOHCITCODE_PHY 0xe