if_iwm - Sync nvm parsing code with Linux iwlwifi.
[dragonfly.git] / sys / dev / netif / iwm / if_iwmreg.h
CommitLineData
ec7b6344 1/* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */
24a8d46a
MD
2/* $FreeBSD$ */
3
4/******************************************************************************
5 *
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
8 *
9 * GPL LICENSE SUMMARY
10 *
11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
25 * USA
26 *
27 * The full GNU General Public License is included in this distribution
28 * in the file called COPYING.
29 *
30 * Contact Information:
31 * Intel Linux Wireless <ilw@linux.intel.com>
32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 *
34 * BSD LICENSE
35 *
36 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
37 * All rights reserved.
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 *
43 * * Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * * Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
48 * distribution.
49 * * Neither the name Intel Corporation nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific prior written permission.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
56 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
57 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
58 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
59 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
64 *
65 *****************************************************************************/
66#ifndef __IF_IWM_REG_H__
67#define __IF_IWM_REG_H__
68
69#define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_)))
70#define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_)))
71
24a8d46a
MD
72/*
73 * CSR (control and status registers)
74 *
75 * CSR registers are mapped directly into PCI bus space, and are accessible
76 * whenever platform supplies power to device, even when device is in
77 * low power states due to driver-invoked device resets
78 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
79 *
80 * Use iwl_write32() and iwl_read32() family to access these registers;
81 * these provide simple PCI bus access, without waking up the MAC.
82 * Do not use iwl_write_direct32() family for these registers;
83 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
84 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
85 * the CSR registers.
86 *
87 * NOTE: Device does need to be awake in order to read this memory
88 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers
89 */
90#define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */
91#define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
92#define IWM_CSR_INT (0x008) /* host interrupt status/ack */
93#define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */
94#define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/
95#define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */
96#define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/
97#define IWM_CSR_GP_CNTRL (0x024)
98
99/* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */
100#define IWM_CSR_INT_PERIODIC_REG (0x005)
101
102/*
103 * Hardware revision info
104 * Bit fields:
105 * 31-16: Reserved
106 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions
107 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
108 * 1-0: "Dash" (-) value, as in A-1, etc.
109 */
110#define IWM_CSR_HW_REV (0x028)
111
112/*
113 * EEPROM and OTP (one-time-programmable) memory reads
114 *
115 * NOTE: Device must be awake, initialized via apm_ops.init(),
116 * in order to read.
117 */
118#define IWM_CSR_EEPROM_REG (0x02c)
119#define IWM_CSR_EEPROM_GP (0x030)
120#define IWM_CSR_OTP_GP_REG (0x034)
121
122#define IWM_CSR_GIO_REG (0x03C)
123#define IWM_CSR_GP_UCODE_REG (0x048)
124#define IWM_CSR_GP_DRIVER_REG (0x050)
125
126/*
127 * UCODE-DRIVER GP (general purpose) mailbox registers.
128 * SET/CLR registers set/clear bit(s) if "1" is written.
129 */
130#define IWM_CSR_UCODE_DRV_GP1 (0x054)
131#define IWM_CSR_UCODE_DRV_GP1_SET (0x058)
132#define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c)
133#define IWM_CSR_UCODE_DRV_GP2 (0x060)
134
edfc8a07
IV
135#define IWM_CSR_MBOX_SET_REG (0x088)
136#define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20
137
24a8d46a
MD
138#define IWM_CSR_LED_REG (0x094)
139#define IWM_CSR_DRAM_INT_TBL_REG (0x0A0)
140#define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */
141
142
143/* GIO Chicken Bits (PCI Express bus link power management) */
144#define IWM_CSR_GIO_CHICKEN_BITS (0x100)
145
146/* Analog phase-lock-loop configuration */
147#define IWM_CSR_ANA_PLL_CFG (0x20c)
148
149/*
150 * CSR Hardware Revision Workaround Register. Indicates hardware rev;
151 * "step" determines CCK backoff for txpower calculation. Used for 4965 only.
152 * See also IWM_CSR_HW_REV register.
153 * Bit fields:
154 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
155 * 1-0: "Dash" (-) value, as in C-1, etc.
156 */
157#define IWM_CSR_HW_REV_WA_REG (0x22C)
158
159#define IWM_CSR_DBG_HPET_MEM_REG (0x240)
160#define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250)
161
162/* Bits for IWM_CSR_HW_IF_CONFIG_REG */
163#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)
164#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)
165#define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
166#define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
167#define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
168#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
169#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
170#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
171
172#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
173#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
174#define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
175#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
176#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
177#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)
178
179#define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
180#define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
181#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
182#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
183#define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
edfc8a07
IV
184#define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)
185#define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */
24a8d46a
MD
186
187#define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
188#define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
189
190/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
191 * acknowledged (reset) by host writing "1" to flagged bits. */
192#define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
193#define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
194#define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
195#define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
196#define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
197#define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
198#define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
199#define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
200#define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
201#define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
202#define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
203
204#define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \
205 IWM_CSR_INT_BIT_HW_ERR | \
206 IWM_CSR_INT_BIT_FH_TX | \
207 IWM_CSR_INT_BIT_SW_ERR | \
208 IWM_CSR_INT_BIT_RF_KILL | \
209 IWM_CSR_INT_BIT_SW_RX | \
210 IWM_CSR_INT_BIT_WAKEUP | \
211 IWM_CSR_INT_BIT_ALIVE | \
212 IWM_CSR_INT_BIT_RX_PERIODIC)
213
214/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
215#define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
216#define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
217#define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
218#define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
219#define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
220#define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
221
222#define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \
223 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \
224 IWM_CSR_FH_INT_BIT_RX_CHNL0)
225
226#define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \
227 IWM_CSR_FH_INT_BIT_TX_CHNL0)
228
229/* GPIO */
230#define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
231#define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
232#define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
233
234/* RESET */
235#define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
236#define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
237#define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
238#define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
239#define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
240#define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
241
242/*
243 * GP (general purpose) CONTROL REGISTER
244 * Bit fields:
245 * 27: HW_RF_KILL_SW
246 * Indicates state of (platform's) hardware RF-Kill switch
247 * 26-24: POWER_SAVE_TYPE
248 * Indicates current power-saving mode:
249 * 000 -- No power saving
250 * 001 -- MAC power-down
251 * 010 -- PHY (radio) power-down
252 * 011 -- Error
253 * 9-6: SYS_CONFIG
254 * Indicates current system configuration, reflecting pins on chip
255 * as forced high/low by device circuit board.
256 * 4: GOING_TO_SLEEP
257 * Indicates MAC is entering a power-saving sleep power-down.
258 * Not a good time to access device-internal resources.
259 * 3: MAC_ACCESS_REQ
260 * Host sets this to request and maintain MAC wakeup, to allow host
261 * access to device-internal resources. Host must wait for
262 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
263 * device registers.
264 * 2: INIT_DONE
265 * Host sets this to put device into fully operational D0 power mode.
266 * Host resets this after SW_RESET to put device into low power mode.
267 * 0: MAC_CLOCK_READY
268 * Indicates MAC (ucode processor, etc.) is powered up and can run.
269 * Internal resources are accessible.
270 * NOTE: This does not indicate that the processor is actually running.
271 * NOTE: This does not indicate that device has completed
272 * init or post-power-down restore of internal SRAM memory.
273 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
274 * SRAM is restored and uCode is in normal operation mode.
275 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
276 * do not need to save/restore it.
277 * NOTE: After device reset, this bit remains "0" until host sets
278 * INIT_DONE
279 */
280#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
281#define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
282#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
283#define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
284
285#define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
286
287#define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
288#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
289#define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
290
291
292/* HW REV */
293#define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)
294#define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)
295
84292f0c
IV
296/**
297 * hw_rev values
298 */
299enum {
300 IWM_SILICON_A_STEP = 0,
301 IWM_SILICON_B_STEP,
302 IWM_SILICON_C_STEP,
303};
304
305
24a8d46a
MD
306#define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0)
307#define IWM_CSR_HW_REV_TYPE_5300 (0x0000020)
308#define IWM_CSR_HW_REV_TYPE_5350 (0x0000030)
309#define IWM_CSR_HW_REV_TYPE_5100 (0x0000050)
310#define IWM_CSR_HW_REV_TYPE_5150 (0x0000040)
311#define IWM_CSR_HW_REV_TYPE_1000 (0x0000060)
312#define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070)
313#define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080)
314#define IWM_CSR_HW_REV_TYPE_6150 (0x0000084)
315#define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0)
316#define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05
317#define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05
318#define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0)
319#define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100)
320#define IWM_CSR_HW_REV_TYPE_105 (0x0000110)
321#define IWM_CSR_HW_REV_TYPE_135 (0x0000120)
edfc8a07 322#define IWM_CSR_HW_REV_TYPE_7265D (0x0000210)
24a8d46a
MD
323#define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0)
324
325/* EEPROM REG */
326#define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
327#define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002)
328#define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
329#define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
330
331/* EEPROM GP */
332#define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
333#define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
334#define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
335#define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
336#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
337#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
338
339/* One-time-programmable memory general purpose reg */
340#define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
341#define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
342#define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
343#define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
344
345/* GP REG */
346#define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
347#define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000)
348#define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
349#define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
350#define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
351
352
353/* CSR GIO */
354#define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
355
356/*
357 * UCODE-DRIVER GP (general purpose) mailbox register 1
358 * Host driver and uCode write and/or read this register to communicate with
359 * each other.
360 * Bit fields:
361 * 4: UCODE_DISABLE
362 * Host sets this to request permanent halt of uCode, same as
363 * sending CARD_STATE command with "halt" bit set.
364 * 3: CT_KILL_EXIT
365 * Host sets this to request exit from CT_KILL state, i.e. host thinks
366 * device temperature is low enough to continue normal operation.
367 * 2: CMD_BLOCKED
368 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
369 * to release uCode to clear all Tx and command queues, enter
370 * unassociated mode, and power down.
371 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
372 * 1: SW_BIT_RFKILL
373 * Host sets this when issuing CARD_STATE command to request
374 * device sleep.
375 * 0: MAC_SLEEP
376 * uCode sets this when preparing a power-saving power-down.
377 * uCode resets this when power-up is complete and SRAM is sane.
378 * NOTE: device saves internal SRAM data to host when powering down,
379 * and must restore this data after powering back up.
380 * MAC_SLEEP is the best indication that restore is complete.
381 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
382 * do not need to save/restore it.
383 */
384#define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
385#define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002)
386#define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
387#define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
388#define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
389
390/* GP Driver */
391#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
392#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
393#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
394#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
395#define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)
396#define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)
397
398#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)
399
400/* GIO Chicken Bits (PCI Express bus link power management) */
401#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
402#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
403
404/* LED */
405#define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
406#define IWM_CSR_LED_REG_TURN_ON (0x60)
407#define IWM_CSR_LED_REG_TURN_OFF (0x20)
408
409/* ANA_PLL */
410#define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300)
411
412/* HPET MEM debug */
413#define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
414
415/* DRAM INT TABLE */
416#define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31)
edfc8a07 417#define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)
24a8d46a
MD
418#define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
419
420/* SECURE boot registers */
421#define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100)
422enum iwm_secure_boot_config_reg {
423 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001,
424 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002,
425};
426
427#define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100)
428#define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100)
429enum iwm_secure_boot_status_reg {
430 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003,
431 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002,
432 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004,
433 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008,
434 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010,
435};
436
edfc8a07
IV
437#define IWM_FH_UCODE_LOAD_STATUS 0x1af0
438#define IWM_CSR_UCODE_LOAD_STATUS_ADDR 0x1e70
24a8d46a 439enum iwm_secure_load_status_reg {
edfc8a07
IV
440 IWM_LMPM_CPU_UCODE_LOADING_STARTED = 0x00000001,
441 IWM_LMPM_CPU_HDRS_LOADING_COMPLETED = 0x00000003,
442 IWM_LMPM_CPU_UCODE_LOADING_COMPLETED = 0x00000007,
443 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8,
444 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00,
24a8d46a 445};
edfc8a07
IV
446#define IWM_FH_MEM_TB_MAX_LENGTH 0x20000
447
448#define IWM_LMPM_SECURE_INSPECTOR_CODE_ADDR 0x1e38
449#define IWM_LMPM_SECURE_INSPECTOR_DATA_ADDR 0x1e3c
450#define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78
451#define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c
24a8d46a 452
edfc8a07
IV
453#define IWM_LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE 0x400000
454#define IWM_LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE 0x402000
455#define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000
456#define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400
24a8d46a
MD
457
458#define IWM_CSR_SECURE_TIME_OUT (100)
459
edfc8a07
IV
460/* extended range in FW SRAM */
461#define IWM_FW_MEM_EXTENDED_START 0x40000
462#define IWM_FW_MEM_EXTENDED_END 0x57FFF
463
464/* FW chicken bits */
465#define IWM_LMPM_CHICK 0xa01ff8
466#define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01
467
24a8d46a
MD
468#define IWM_FH_TCSR_0_REG0 (0x1D00)
469
470/*
471 * HBUS (Host-side Bus)
472 *
473 * HBUS registers are mapped directly into PCI bus space, but are used
474 * to indirectly access device's internal memory or registers that
475 * may be powered-down.
476 *
477 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
478 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
479 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
480 * internal resources.
481 *
482 * Do not use iwl_write32()/iwl_read32() family to access these registers;
483 * these provide only simple PCI bus access, without waking up the MAC.
484 */
485#define IWM_HBUS_BASE (0x400)
486
487/*
488 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
489 * structures, error log, event log, verifying uCode load).
490 * First write to address register, then read from or write to data register
491 * to complete the job. Once the address register is set up, accesses to
492 * data registers auto-increment the address by one dword.
493 * Bit usage for address registers (read or write):
494 * 0-31: memory address within device
495 */
496#define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c)
497#define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010)
498#define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018)
499#define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c)
500
501/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
502#define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030)
503#define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
504
505/*
506 * Registers for accessing device's internal peripheral registers
507 * (e.g. SCD, BSM, etc.). First write to address register,
508 * then read from or write to data register to complete the job.
509 * Bit usage for address registers (read or write):
510 * 0-15: register address (offset) within device
511 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
512 */
513#define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044)
514#define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048)
515#define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c)
516#define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050)
517
edfc8a07
IV
518/* enable the ID buf for read */
519#define IWM_WFPM_PS_CTL_CLR 0xa0300c
520#define IWM_WFMP_MAC_ADDR_0 0xa03080
521#define IWM_WFMP_MAC_ADDR_1 0xa03084
522#define IWM_LMPM_PMG_EN 0xa01cec
523#define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078
524#define IWM_RFIC_REG_RD 0xad0470
525#define IWM_WFPM_CTRL_REG 0xa03030
526#define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000
527#define IWM_ENABLE_WFPM 0x80000000
528
529#define IWM_AUX_MISC_REG 0xa200b0
530#define IWM_HW_STEP_LOCATION_BITS 24
531
532#define IWM_AUX_MISC_MASTER1_EN 0xa20818
533#define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1
534#define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800
535#define IWM_RSA_ENABLE 0xa24b08
536#define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0
537#define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78
538#define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000
539#define IWM_SB_CFG_BASE_OVERRIDE 0xa20000
540#define IWM_SB_MODIFY_CFG_FLAG 0xa03088
541#define IWM_SB_CPU_1_STATUS 0xa01e30
542#define IWM_SB_CPU_2_STATUS 0Xa01e34
543
24a8d46a
MD
544/* Used to enable DBGM */
545#define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c)
546
547/*
548 * Per-Tx-queue write pointer (index, really!)
549 * Indicates index to next TFD that driver will fill (1 past latest filled).
550 * Bit usage:
551 * 0-7: queue write index
552 * 11-8: queue selector
553 */
554#define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060)
555
556/**********************************************************
557 * CSR values
558 **********************************************************/
559 /*
560 * host interrupt timeout value
561 * used with setting interrupt coalescing timer
562 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
563 *
564 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
565 */
566#define IWM_HOST_INT_TIMEOUT_MAX (0xFF)
567#define IWM_HOST_INT_TIMEOUT_DEF (0x40)
568#define IWM_HOST_INT_TIMEOUT_MIN (0x0)
569#define IWM_HOST_INT_OPER_MODE (1 << 31)
570
571/*****************************************************************************
572 * 7000/3000 series SHR DTS addresses *
573 *****************************************************************************/
574
575/* Diode Results Register Structure: */
576enum iwm_dtd_diode_reg {
577 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */
578 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */
579 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */
580 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */
581 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */
582 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */
583/* Those are the masks INSIDE the flags bit-field: */
584 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0,
585 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */
586 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7,
587 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */
588};
589
24a8d46a 590/**
29fcb331 591 * enum iwm_ucode_tlv_flag - ucode API flags
24a8d46a
MD
592 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
593 * was a separate TLV but moved here to save space.
594 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
595 * treats good CRC threshold as a boolean
596 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
597 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P.
598 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS
599 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD
600 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan
601 * offload profile config command.
602 * @IWM_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api
603 * @IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API.
604 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six
605 * (rather than two) IPv6 addresses
606 * @IWM_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API
607 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element
608 * from the probe request template.
609 * @IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping
610 * connection when going back to D0
611 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version)
612 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version)
613 * @IWM_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan.
614 * @IWM_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API
615 * @IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command
616 * containing CAM (Continuous Active Mode) indication.
617 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a
618 * single bound interface).
edfc8a07
IV
619 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD
620 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS.
24a8d46a 621 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save
edfc8a07
IV
622 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering.
623 * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients
624 *
24a8d46a
MD
625 */
626enum iwm_ucode_tlv_flag {
627 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0),
628 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1),
629 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2),
630 IWM_UCODE_TLV_FLAGS_P2P = (1 << 3),
631 IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4),
632 IWM_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5),
633 IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT = (1 << 6),
634 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7),
635 IWM_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8),
636 IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9),
637 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10),
638 IWM_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11),
639 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12),
640 IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14),
641 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15),
642 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16),
643 IWM_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17),
644 IWM_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19),
645 IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20),
646 IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21),
edfc8a07
IV
647 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM = (1 << 22),
648 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM = (1 << 23),
24a8d46a 649 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24),
edfc8a07 650 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25),
24a8d46a 651 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26),
edfc8a07
IV
652 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29),
653 IWM_UCODE_TLV_FLAGS_GO_UAPSD = (1 << 30),
654 IWM_UCODE_TLV_FLAGS_LTE_COEX = (1 << 31),
655};
656
657#define IWM_UCODE_TLV_FLAG_BITS \
658 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \
659Y\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \
660L_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \
661P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX"
662
663/**
664 * enum iwm_ucode_tlv_api - ucode api
665 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time
666 * longer than the passive one, which is essential for fragmented scan.
667 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source.
668 * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header
669 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params
670 * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority
671 * instead of 3.
672 * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size
673 * (command version 3) that supports per-chain limits
674 *
675 * @IWM_NUM_UCODE_TLV_API: number of bits used
676 */
677enum iwm_ucode_tlv_api {
678 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = (1 << 8),
679 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = (1 << 9),
680 IWM_UCODE_TLV_API_WIDE_CMD_HDR = (1 << 14),
681 IWM_UCODE_TLV_API_LQ_SS_PARAMS = (1 << 18),
682 IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY = (1 << 24),
683 IWM_UCODE_TLV_API_TX_POWER_CHAIN = (1 << 27),
684
685 IWM_NUM_UCODE_TLV_API = 32
686};
687
688#define IWM_UCODE_TLV_API_BITS \
689 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN"
690
691/**
692 * enum iwm_ucode_tlv_capa - ucode capabilities
693 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3
694 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory
695 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan.
696 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer
697 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM)
698 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality
699 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current
700 * tx power value into TPC Report action frame and Link Measurement Report
701 * action frame
702 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current
703 * channel in DS parameter set element in probe requests.
704 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in
705 * probe requests.
706 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests
707 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA),
708 * which also implies support for the scheduler configuration command
709 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching
710 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image
711 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command
712 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command
713 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command
714 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload
715 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics
716 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD
717 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running
718 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different
719 * sources for the MCC. This TLV bit is a future replacement to
720 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR
721 * is supported.
722 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC
723 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan
724 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN
725 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported,
726 * 0=no support)
727 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement
728 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts
729 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT
730 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what
731 * antenna the beacon should be transmitted
732 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon
733 * from AP and will send it upon d0i3 exit.
734 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2
735 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill
736 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature
737 * thresholds reporting
738 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command
739 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in
740 * regular image.
741 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared
742 * memory addresses from the firmware.
743 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement
744 * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported,
745 * 0=no support)
746 *
747 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used
748 */
749enum iwm_ucode_tlv_capa {
750 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0,
751 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1,
752 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2,
753 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3,
754 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5,
755 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6,
756 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8,
757 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9,
758 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10,
759 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11,
760 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12,
761 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13,
762 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17,
763 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18,
764 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19,
765 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20,
766 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21,
767 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22,
768 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26,
769 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28,
770 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29,
771 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30,
772 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31,
773 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34,
774 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35,
775 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64,
776 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65,
777 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67,
778 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68,
779 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71,
780 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72,
781 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73,
782 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74,
783 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75,
784 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76,
785 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77,
786 IWM_UCODE_TLV_CAPA_LMAC_UPLOAD = 79,
787 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80,
788 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81,
789
790 IWM_NUM_UCODE_TLV_CAPA = 128
24a8d46a
MD
791};
792
793/* The default calibrate table size if not specified by firmware file */
794#define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18
795#define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19
796#define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253
797
798/* The default max probe length if not specified by the firmware file */
799#define IWM_DEFAULT_MAX_PROBE_LENGTH 200
800
801/*
802 * enumeration of ucode section.
803 * This enumeration is used directly for older firmware (before 16.0).
804 * For new firmware, there can be up to 4 sections (see below) but the
805 * first one packaged into the firmware file is the DATA section and
806 * some debugging code accesses that.
807 */
808enum iwm_ucode_sec {
809 IWM_UCODE_SECTION_DATA,
810 IWM_UCODE_SECTION_INST,
811};
812/*
813 * For 16.0 uCode and above, there is no differentiation between sections,
814 * just an offset to the HW address.
815 */
edfc8a07
IV
816#define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC
817#define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB
24a8d46a
MD
818
819/* uCode version contains 4 values: Major/Minor/API/Serial */
820#define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)
821#define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16)
822#define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8)
823#define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF)
824
825/*
826 * Calibration control struct.
827 * Sent as part of the phy configuration command.
828 * @flow_trigger: bitmap for which calibrations to perform according to
829 * flow triggers.
830 * @event_trigger: bitmap for which calibrations to perform according to
831 * event triggers.
832 */
833struct iwm_tlv_calib_ctrl {
834 uint32_t flow_trigger;
835 uint32_t event_trigger;
836} __packed;
837
838enum iwm_fw_phy_cfg {
839 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0,
840 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS,
841 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2,
842 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS,
843 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4,
844 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS,
845 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16,
846 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS,
847 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20,
848 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS,
849};
850
851#define IWM_UCODE_MAX_CS 1
852
853/**
854 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW.
855 * @cipher: a cipher suite selector
856 * @flags: cipher scheme flags (currently reserved for a future use)
857 * @hdr_len: a size of MPDU security header
858 * @pn_len: a size of PN
859 * @pn_off: an offset of pn from the beginning of the security header
860 * @key_idx_off: an offset of key index byte in the security header
861 * @key_idx_mask: a bit mask of key_idx bits
862 * @key_idx_shift: bit shift needed to get key_idx
863 * @mic_len: mic length in bytes
864 * @hw_cipher: a HW cipher index used in host commands
865 */
866struct iwm_fw_cipher_scheme {
867 uint32_t cipher;
868 uint8_t flags;
869 uint8_t hdr_len;
870 uint8_t pn_len;
871 uint8_t pn_off;
872 uint8_t key_idx_off;
873 uint8_t key_idx_mask;
874 uint8_t key_idx_shift;
875 uint8_t mic_len;
876 uint8_t hw_cipher;
877} __packed;
878
879/**
880 * struct iwm_fw_cscheme_list - a cipher scheme list
881 * @size: a number of entries
882 * @cs: cipher scheme entries
883 */
884struct iwm_fw_cscheme_list {
885 uint8_t size;
886 struct iwm_fw_cipher_scheme cs[];
887} __packed;
888
24a8d46a
MD
889/* v1/v2 uCode file layout */
890struct iwm_ucode_header {
891 uint32_t ver; /* major/minor/API/serial */
892 union {
893 struct {
894 uint32_t inst_size; /* bytes of runtime code */
895 uint32_t data_size; /* bytes of runtime data */
896 uint32_t init_size; /* bytes of init code */
897 uint32_t init_data_size; /* bytes of init data */
898 uint32_t boot_size; /* bytes of bootstrap code */
899 uint8_t data[0]; /* in same order as sizes */
900 } v1;
901 struct {
902 uint32_t build; /* build number */
903 uint32_t inst_size; /* bytes of runtime code */
904 uint32_t data_size; /* bytes of runtime data */
905 uint32_t init_size; /* bytes of init code */
906 uint32_t init_data_size; /* bytes of init data */
907 uint32_t boot_size; /* bytes of bootstrap code */
908 uint8_t data[0]; /* in same order as sizes */
909 } v2;
910 } u;
911};
912
913/*
914 * new TLV uCode file layout
915 *
916 * The new TLV file format contains TLVs, that each specify
917 * some piece of data.
918 */
919
920enum iwm_ucode_tlv_type {
921 IWM_UCODE_TLV_INVALID = 0, /* unused */
922 IWM_UCODE_TLV_INST = 1,
923 IWM_UCODE_TLV_DATA = 2,
924 IWM_UCODE_TLV_INIT = 3,
925 IWM_UCODE_TLV_INIT_DATA = 4,
926 IWM_UCODE_TLV_BOOT = 5,
927 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */
928 IWM_UCODE_TLV_PAN = 7,
929 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
930 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
931 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
932 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11,
933 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
934 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13,
935 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14,
936 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
937 IWM_UCODE_TLV_WOWLAN_INST = 16,
938 IWM_UCODE_TLV_WOWLAN_DATA = 17,
939 IWM_UCODE_TLV_FLAGS = 18,
940 IWM_UCODE_TLV_SEC_RT = 19,
941 IWM_UCODE_TLV_SEC_INIT = 20,
942 IWM_UCODE_TLV_SEC_WOWLAN = 21,
943 IWM_UCODE_TLV_DEF_CALIB = 22,
944 IWM_UCODE_TLV_PHY_SKU = 23,
945 IWM_UCODE_TLV_SECURE_SEC_RT = 24,
946 IWM_UCODE_TLV_SECURE_SEC_INIT = 25,
947 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26,
948 IWM_UCODE_TLV_NUM_OF_CPU = 27,
949 IWM_UCODE_TLV_CSCHEME = 28,
950
951 /*
952 * Following two are not in our base tag, but allow
953 * handling ucode version 9.
954 */
955 IWM_UCODE_TLV_API_CHANGES_SET = 29,
edfc8a07
IV
956 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30,
957
958 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31,
959 IWM_UCODE_TLV_PAGING = 32,
960 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34,
961 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35,
962 IWM_UCODE_TLV_FW_VERSION = 36,
963 IWM_UCODE_TLV_FW_DBG_DEST = 38,
964 IWM_UCODE_TLV_FW_DBG_CONF = 39,
965 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40,
966 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50,
24a8d46a
MD
967};
968
969struct iwm_ucode_tlv {
970 uint32_t type; /* see above */
971 uint32_t length; /* not including type/length fields */
972 uint8_t data[0];
973};
974
edfc8a07
IV
975struct iwm_ucode_api {
976 uint32_t api_index;
977 uint32_t api_flags;
978} __packed;
979
980struct iwm_ucode_capa {
981 uint32_t api_index;
982 uint32_t api_capa;
983} __packed;
984
24a8d46a
MD
985#define IWM_TLV_UCODE_MAGIC 0x0a4c5749
986
987struct iwm_tlv_ucode_header {
988 /*
989 * The TLV style ucode header is distinguished from
990 * the v1/v2 style header by first four bytes being
991 * zero, as such is an invalid combination of
992 * major/minor/API/serial versions.
993 */
994 uint32_t zero;
995 uint32_t magic;
996 uint8_t human_readable[64];
997 uint32_t ver; /* major/minor/API/serial */
998 uint32_t build;
999 uint64_t ignore;
1000 /*
1001 * The data contained herein has a TLV layout,
1002 * see above for the TLV header and types.
1003 * Note that each TLV is padded to a length
1004 * that is a multiple of 4 for alignment.
1005 */
1006 uint8_t data[0];
1007};
1008
24a8d46a
MD
1009/*
1010 * Registers in this file are internal, not PCI bus memory mapped.
1011 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers.
1012 */
1013#define IWM_PRPH_BASE (0x00000)
1014#define IWM_PRPH_END (0xFFFFF)
1015
1016/* APMG (power management) constants */
1017#define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000)
1018#define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000)
1019#define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004)
1020#define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008)
1021#define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c)
1022#define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010)
1023#define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014)
1024#define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c)
1025#define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020)
1026#define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058)
1027#define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C)
1028
1029#define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)
1030#define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
1031#define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
1032
1033#define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
1034#define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
1035#define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
1036#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
1037#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
1038#define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
1039#define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
1040
1041#define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
1042
1043#define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000)
1044
1045/* Device system time */
1046#define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C
1047
1048/* Device NMI register */
edfc8a07
IV
1049#define IWM_DEVICE_SET_NMI_REG 0x00a01c30
1050#define IWM_DEVICE_SET_NMI_VAL_HW 0x01
1051#define IWM_DEVICE_SET_NMI_VAL_DRV 0x80
e8951a47
IV
1052#define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24
1053#define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000
1054
1055/*
1056 * Device reset for family 8000
1057 * write to bit 24 in order to reset the CPU
1058 */
1059#define IWM_RELEASE_CPU_RESET 0x300c
1060#define IWM_RELEASE_CPU_RESET_BIT 0x1000000
1061
24a8d46a
MD
1062
1063/*****************************************************************************
1064 * 7000/3000 series SHR DTS addresses *
1065 *****************************************************************************/
1066
1067#define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024)
1068#define IWM_DTSC_CFG_MODE (0x00a10604)
1069#define IWM_DTSC_VREF_AVG (0x00a10648)
1070#define IWM_DTSC_VREF5_AVG (0x00a1064c)
1071#define IWM_DTSC_CFG_MODE_PERIODIC (0x2)
1072#define IWM_DTSC_PTAT_AVG (0x00a10650)
1073
1074
1075/**
1076 * Tx Scheduler
1077 *
1078 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs
1079 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
1080 * host DRAM. It steers each frame's Tx command (which contains the frame
1081 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
1082 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
1083 * but one DMA channel may take input from several queues.
1084 *
1085 * Tx DMA FIFOs have dedicated purposes.
1086 *
1087 * For 5000 series and up, they are used differently
1088 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
1089 *
1090 * 0 -- EDCA BK (background) frames, lowest priority
1091 * 1 -- EDCA BE (best effort) frames, normal priority
1092 * 2 -- EDCA VI (video) frames, higher priority
1093 * 3 -- EDCA VO (voice) and management frames, highest priority
1094 * 4 -- unused
1095 * 5 -- unused
1096 * 6 -- unused
1097 * 7 -- Commands
1098 *
1099 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
1100 * In addition, driver can map the remaining queues to Tx DMA/FIFO
1101 * channels 0-3 to support 11n aggregation via EDCA DMA channels.
1102 *
1103 * The driver sets up each queue to work in one of two modes:
1104 *
1105 * 1) Scheduler-Ack, in which the scheduler automatically supports a
1106 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue
1107 * contains TFDs for a unique combination of Recipient Address (RA)
1108 * and Traffic Identifier (TID), that is, traffic of a given
1109 * Quality-Of-Service (QOS) priority, destined for a single station.
1110 *
1111 * In scheduler-ack mode, the scheduler keeps track of the Tx status of
1112 * each frame within the BA window, including whether it's been transmitted,
1113 * and whether it's been acknowledged by the receiving station. The device
1114 * automatically processes block-acks received from the receiving STA,
1115 * and reschedules un-acked frames to be retransmitted (successful
1116 * Tx completion may end up being out-of-order).
1117 *
1118 * The driver must maintain the queue's Byte Count table in host DRAM
1119 * for this mode.
1120 * This mode does not support fragmentation.
1121 *
1122 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
1123 * The device may automatically retry Tx, but will retry only one frame
1124 * at a time, until receiving ACK from receiving station, or reaching
1125 * retry limit and giving up.
1126 *
1127 * The command queue (#4/#9) must use this mode!
1128 * This mode does not require use of the Byte Count table in host DRAM.
1129 *
1130 * Driver controls scheduler operation via 3 means:
1131 * 1) Scheduler registers
1132 * 2) Shared scheduler data base in internal SRAM
1133 * 3) Shared data in host DRAM
1134 *
1135 * Initialization:
1136 *
1137 * When loading, driver should allocate memory for:
1138 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
1139 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
1140 * (1024 bytes for each queue).
1141 *
1142 * After receiving "Alive" response from uCode, driver must initialize
1143 * the scheduler (especially for queue #4/#9, the command queue, otherwise
1144 * the driver can't issue commands!):
1145 */
1146#define IWM_SCD_MEM_LOWER_BOUND (0x0000)
1147
1148/**
1149 * Max Tx window size is the max number of contiguous TFDs that the scheduler
1150 * can keep track of at one time when creating block-ack chains of frames.
1151 * Note that "64" matches the number of ack bits in a block-ack packet.
1152 */
1153#define IWM_SCD_WIN_SIZE 64
1154#define IWM_SCD_FRAME_LIMIT 64
1155
1156#define IWM_SCD_TXFIFO_POS_TID (0)
1157#define IWM_SCD_TXFIFO_POS_RA (4)
1158#define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
1159
1160/* agn SCD */
1161#define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0)
1162#define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3)
1163#define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4)
1164#define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
1165#define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000)
1166
1167#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8)
1168#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
1169#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
1170#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
1171#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0)
1172#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F)
1173#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
1174#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
edfc8a07
IV
1175#define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0)
1176#define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18)
24a8d46a
MD
1177
1178/* Context Data */
1179#define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600)
1180#define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
1181
1182/* Tx status */
1183#define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
1184#define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
1185
1186/* Translation Data */
1187#define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
1188#define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808)
1189
1190#define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\
1191 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))
1192
1193#define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\
1194 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16))
1195
1196#define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \
1197 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
1198
1199#define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00)
1200
1201#define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0)
1202#define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8)
1203#define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c)
1204#define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10)
1205#define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14)
1206#define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8)
1207#define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244)
1208#define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248)
1209#define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108)
edfc8a07
IV
1210#define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8)
1211#define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254)
24a8d46a
MD
1212
1213static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl)
1214{
1215 if (chnl < 20)
1216 return IWM_SCD_BASE + 0x18 + chnl * 4;
1217 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4;
1218}
1219
1220static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl)
1221{
1222 if (chnl < 20)
1223 return IWM_SCD_BASE + 0x68 + chnl * 4;
1224 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4;
1225}
1226
1227static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl)
1228{
1229 if (chnl < 20)
1230 return IWM_SCD_BASE + 0x10c + chnl * 4;
1231 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4;
1232}
1233
1234/*********************** END TX SCHEDULER *************************************/
1235
1236/* Oscillator clock */
1237#define IWM_OSC_CLK (0xa04068)
1238#define IWM_OSC_CLK_FORCE_CONTROL (0x8)
1239
24a8d46a
MD
1240/****************************/
1241/* Flow Handler Definitions */
1242/****************************/
1243
1244/**
1245 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
1246 * Addresses are offsets from device's PCI hardware base address.
1247 */
1248#define IWM_FH_MEM_LOWER_BOUND (0x1000)
1249#define IWM_FH_MEM_UPPER_BOUND (0x2000)
1250
1251/**
1252 * Keep-Warm (KW) buffer base address.
1253 *
1254 * Driver must allocate a 4KByte buffer that is for keeping the
1255 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
1256 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host
1257 * from going into a power-savings mode that would cause higher DRAM latency,
1258 * and possible data over/under-runs, before all Tx/Rx is complete.
1259 *
1260 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
1261 * of the buffer, which must be 4K aligned. Once this is set up, the device
1262 * automatically invokes keep-warm accesses when normal accesses might not
1263 * be sufficient to maintain fast DRAM response.
1264 *
1265 * Bit fields:
1266 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
1267 */
1268#define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C)
1269
1270
1271/**
1272 * TFD Circular Buffers Base (CBBC) addresses
1273 *
1274 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
1275 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
1276 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04
1277 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
1278 * aligned (address bits 0-7 must be 0).
1279 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers
1280 * for them are in different places.
1281 *
1282 * Bit fields in each pointer register:
1283 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
1284 */
1285#define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1286#define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10)
1287#define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0)
1288#define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1289#define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20)
1290#define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80)
1291
1292/* Find TFD CB base pointer for given queue */
1293static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl)
1294{
1295 if (chnl < 16)
1296 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl;
1297 if (chnl < 20)
1298 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16);
1299 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20);
1300}
1301
1302
1303/**
1304 * Rx SRAM Control and Status Registers (RSCSR)
1305 *
1306 * These registers provide handshake between driver and device for the Rx queue
1307 * (this queue handles *all* command responses, notifications, Rx data, etc.
1308 * sent from uCode to host driver). Unlike Tx, there is only one Rx
1309 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
1310 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
1311 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
1312 * mapping between RBDs and RBs.
1313 *
1314 * Driver must allocate host DRAM memory for the following, and set the
1315 * physical address of each into device registers:
1316 *
1317 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
1318 * entries (although any power of 2, up to 4096, is selectable by driver).
1319 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
1320 * (typically 4K, although 8K or 16K are also selectable by driver).
1321 * Driver sets up RB size and number of RBDs in the CB via Rx config
1322 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG.
1323 *
1324 * Bit fields within one RBD:
1325 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
1326 *
1327 * Driver sets physical address [35:8] of base of RBD circular buffer
1328 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
1329 *
1330 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers
1331 * (RBs) have been filled, via a "write pointer", actually the index of
1332 * the RB's corresponding RBD within the circular buffer. Driver sets
1333 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
1334 *
1335 * Bit fields in lower dword of Rx status buffer (upper dword not used
1336 * by driver:
1337 * 31-12: Not used by driver
1338 * 11- 0: Index of last filled Rx buffer descriptor
1339 * (device writes, driver reads this value)
1340 *
1341 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must
1342 * enter pointers to these RBs into contiguous RBD circular buffer entries,
1343 * and update the device's "write" index register,
1344 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
1345 *
1346 * This "write" index corresponds to the *next* RBD that the driver will make
1347 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
1348 * the circular buffer. This value should initially be 0 (before preparing any
1349 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
1350 * wrap back to 0 at the end of the circular buffer (but don't wrap before
1351 * "read" index has advanced past 1! See below).
1352 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
1353 *
1354 * As the device fills RBs (referenced from contiguous RBDs within the circular
1355 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
1356 * to tell the driver the index of the latest filled RBD. The driver must
1357 * read this "read" index from DRAM after receiving an Rx interrupt from device
1358 *
1359 * The driver must also internally keep track of a third index, which is the
1360 * next RBD to process. When receiving an Rx interrupt, driver should process
1361 * all filled but unprocessed RBs up to, but not including, the RB
1362 * corresponding to the "read" index. For example, if "read" index becomes "1",
1363 * driver may process the RB pointed to by RBD 0. Depending on volume of
1364 * traffic, there may be many RBs to process.
1365 *
1366 * If read index == write index, device thinks there is no room to put new data.
1367 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
1368 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
1369 * and "read" indexes; that is, make sure that there are no more than 254
1370 * buffers waiting to be filled.
1371 */
1372#define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0)
1373#define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1374#define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND)
1375
1376/**
1377 * Physical base address of 8-byte Rx Status buffer.
1378 * Bit fields:
1379 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
1380 */
1381#define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0)
1382
1383/**
1384 * Physical base address of Rx Buffer Descriptor Circular Buffer.
1385 * Bit fields:
1386 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
1387 */
1388#define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004)
1389
1390/**
1391 * Rx write pointer (index, really!).
1392 * Bit fields:
1393 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
1394 * NOTE: For 256-entry circular buffer, use only bits [7:0].
1395 */
1396#define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008)
1397#define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
1398
1399#define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c)
1400#define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG
1401
1402/**
1403 * Rx Config/Status Registers (RCSR)
1404 * Rx Config Reg for channel 0 (only channel used)
1405 *
1406 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
1407 * normal operation (see bit fields).
1408 *
1409 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
1410 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for
1411 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
1412 *
1413 * Bit fields:
1414 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1415 * '10' operate normally
1416 * 29-24: reserved
1417 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
1418 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
1419 * 19-18: reserved
1420 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
1421 * '10' 12K, '11' 16K.
1422 * 15-14: reserved
1423 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
1424 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
1425 * typical value 0x10 (about 1/2 msec)
1426 * 3- 0: reserved
1427 */
1428#define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1429#define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0)
1430#define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND)
1431
1432#define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0)
1433#define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8)
1434#define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10)
1435
1436#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
1437#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
1438#define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
1439#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
1440#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
1441#define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
1442
1443#define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
1444#define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
1445#define IWM_RX_RB_TIMEOUT (0x11)
1446
1447#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1448#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1449#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1450
1451#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1452#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
1453#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
1454#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
1455
1456#define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
1457#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1458#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1459
1460/**
1461 * Rx Shared Status Registers (RSSR)
1462 *
1463 * After stopping Rx DMA channel (writing 0 to
1464 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
1465 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
1466 *
1467 * Bit fields:
1468 * 24: 1 = Channel 0 is idle
1469 *
1470 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
1471 * contain default values that should not be altered by the driver.
1472 */
1473#define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40)
1474#define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1475
1476#define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND)
1477#define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004)
1478#define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
1479 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008)
1480
1481#define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1482
1483#define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
1484
1485/* TFDB Area - TFDs buffer table */
1486#define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
1487#define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900)
1488#define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958)
1489#define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1490#define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1491
1492/**
1493 * Transmit DMA Channel Control/Status Registers (TCSR)
1494 *
1495 * Device has one configuration register for each of 8 Tx DMA/FIFO channels
1496 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1497 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1498 *
1499 * To use a Tx DMA channel, driver must initialize its
1500 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1501 *
1502 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1503 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1504 *
1505 * All other bits should be 0.
1506 *
1507 * Bit fields:
1508 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1509 * '10' operate normally
1510 * 29- 4: Reserved, set to "0"
1511 * 3: Enable internal DMA requests (1, normal operation), disable (0)
1512 * 2- 0: Reserved, set to "0"
1513 */
1514#define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1515#define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60)
1516
1517/* Find Control/Status reg for given Tx DMA/FIFO channel */
1518#define IWM_FH_TCSR_CHNL_NUM (8)
1519
1520/* TCSR: tx_config register values */
1521#define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1522 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))
1523#define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
1524 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
1525#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
1526 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
1527
1528#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
1529#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
1530
1531#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
1532#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
1533
1534#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
1535#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
1536#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
1537
1538#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
1539#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
1540#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
1541
1542#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1543#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1544#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1545
1546#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
1547#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
1548#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
1549
1550#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
1551#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
1552
1553/**
1554 * Tx Shared Status Registers (TSSR)
1555 *
1556 * After stopping Tx DMA channel (writing 0 to
1557 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1558 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
1559 * (channel's buffers empty | no pending requests).
1560 *
1561 * Bit fields:
1562 * 31-24: 1 = Channel buffers empty (channel 7:0)
1563 * 23-16: 1 = No pending requests (channel 7:0)
1564 */
1565#define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0)
1566#define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0)
1567
1568#define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010)
1569
1570/**
1571 * Bit fields for TSSR(Tx Shared Status & Control) error status register:
1572 * 31: Indicates an address error when accessed to internal memory
1573 * uCode/driver must write "1" in order to clear this flag
1574 * 30: Indicates that Host did not send the expected number of dwords to FH
1575 * uCode/driver must write "1" in order to clear this flag
1576 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
1577 * command was received from the scheduler while the TRB was already full
1578 * with previous command
1579 * uCode/driver must write "1" in order to clear this flag
1580 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
1581 * bit is set, it indicates that the FH has received a full indication
1582 * from the RTC TxFIFO and the current value of the TxCredit counter was
1583 * not equal to zero. This mean that the credit mechanism was not
1584 * synchronized to the TxFIFO status
1585 * uCode/driver must write "1" in order to clear this flag
1586 */
1587#define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018)
1588#define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008)
1589
1590#define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
1591
1592/* Tx service channels */
1593#define IWM_FH_SRVC_CHNL (9)
1594#define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8)
1595#define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1596#define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
1597 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
1598
1599#define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98)
1600#define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \
1601 (_chan) * 4)
1602
1603/* Instruct FH to increment the retry count of a packet when
1604 * it is brought from the memory to TX-FIFO
1605 */
1606#define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
1607
1608#define IWM_RX_QUEUE_SIZE 256
1609#define IWM_RX_QUEUE_MASK 255
1610#define IWM_RX_QUEUE_SIZE_LOG 8
1611
1612/*
1613 * RX related structures and functions
1614 */
1615#define IWM_RX_FREE_BUFFERS 64
1616#define IWM_RX_LOW_WATERMARK 8
1617
1618/**
1619 * struct iwm_rb_status - reseve buffer status
1620 * host memory mapped FH registers
1621 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed
1622 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed
1623 * @finished_rb_num [0:11] - Indicates the index of the current RB
1624 * in which the last frame was written to
1625 * @finished_fr_num [0:11] - Indicates the index of the RX Frame
1626 * which was transferred
1627 */
1628struct iwm_rb_status {
1629 uint16_t closed_rb_num;
1630 uint16_t closed_fr_num;
1631 uint16_t finished_rb_num;
1632 uint16_t finished_fr_nam;
1633 uint32_t unused;
1634} __packed;
1635
1636
1637#define IWM_TFD_QUEUE_SIZE_MAX (256)
1638#define IWM_TFD_QUEUE_SIZE_BC_DUP (64)
1639#define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \
1640 IWM_TFD_QUEUE_SIZE_BC_DUP)
1641#define IWM_TX_DMA_MASK DMA_BIT_MASK(36)
1642#define IWM_NUM_OF_TBS 20
1643
1644static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr)
1645{
1646 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF;
1647}
1648/**
1649 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor
1650 *
1651 * This structure contains dma address and length of transmission address
1652 *
1653 * @lo: low [31:0] portion of the dma address of TX buffer
1654 * every even is unaligned on 16 bit boundary
1655 * @hi_n_len 0-3 [35:32] portion of dma
1656 * 4-15 length of the tx buffer
1657 */
1658struct iwm_tfd_tb {
1659 uint32_t lo;
1660 uint16_t hi_n_len;
1661} __packed;
1662
1663/**
1664 * struct iwm_tfd
1665 *
1666 * Transmit Frame Descriptor (TFD)
1667 *
1668 * @ __reserved1[3] reserved
1669 * @ num_tbs 0-4 number of active tbs
1670 * 5 reserved
1671 * 6-7 padding (not used)
1672 * @ tbs[20] transmit frame buffer descriptors
1673 * @ __pad padding
1674 *
1675 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
1676 * Both driver and device share these circular buffers, each of which must be
1677 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
1678 *
1679 * Driver must indicate the physical address of the base of each
1680 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers.
1681 *
1682 * Each TFD contains pointer/size information for up to 20 data buffers
1683 * in host DRAM. These buffers collectively contain the (one) frame described
1684 * by the TFD. Each buffer must be a single contiguous block of memory within
1685 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
1686 * of (4K - 4). The concatenates all of a TFD's buffers into a single
1687 * Tx frame, up to 8 KBytes in size.
1688 *
1689 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
1690 */
1691struct iwm_tfd {
1692 uint8_t __reserved1[3];
1693 uint8_t num_tbs;
1694 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS];
1695 uint32_t __pad;
1696} __packed;
1697
1698/* Keep Warm Size */
1699#define IWM_KW_SIZE 0x1000 /* 4k */
1700
1701/* Fixed (non-configurable) rx data from phy */
1702
1703/**
1704 * struct iwm_agn_schedq_bc_tbl scheduler byte count table
1705 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR
1706 * @tfd_offset 0-12 - tx command byte count
1707 * 12-16 - station index
1708 */
1709struct iwm_agn_scd_bc_tbl {
1710 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE];
1711} __packed;
1712
edfc8a07
IV
1713/* Maximum number of Tx queues. */
1714#define IWM_MVM_MAX_QUEUES 31
24a8d46a
MD
1715
1716/* Tx queue numbers */
1717enum {
1718 IWM_MVM_OFFCHANNEL_QUEUE = 8,
1719 IWM_MVM_CMD_QUEUE = 9,
edfc8a07 1720 IWM_MVM_AUX_QUEUE = 15,
24a8d46a
MD
1721};
1722
29fcb331
IV
1723enum iwm_mvm_tx_fifo {
1724 IWM_MVM_TX_FIFO_BK = 0,
1725 IWM_MVM_TX_FIFO_BE,
1726 IWM_MVM_TX_FIFO_VI,
1727 IWM_MVM_TX_FIFO_VO,
1728 IWM_MVM_TX_FIFO_MCAST = 5,
1729 IWM_MVM_TX_FIFO_CMD = 7,
1730};
24a8d46a
MD
1731
1732#define IWM_MVM_STATION_COUNT 16
1733
1734/* commands */
1735enum {
1736 IWM_MVM_ALIVE = 0x1,
1737 IWM_REPLY_ERROR = 0x2,
1738
1739 IWM_INIT_COMPLETE_NOTIF = 0x4,
1740
1741 /* PHY context commands */
1742 IWM_PHY_CONTEXT_CMD = 0x8,
1743 IWM_DBG_CFG = 0x9,
1744
e8951a47
IV
1745 /* UMAC scan commands */
1746 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5,
1747 IWM_SCAN_CFG_CMD = 0xc,
1748 IWM_SCAN_REQ_UMAC = 0xd,
1749 IWM_SCAN_ABORT_UMAC = 0xe,
1750 IWM_SCAN_COMPLETE_UMAC = 0xf,
1751
24a8d46a
MD
1752 /* station table */
1753 IWM_ADD_STA_KEY = 0x17,
1754 IWM_ADD_STA = 0x18,
1755 IWM_REMOVE_STA = 0x19,
1756
1757 /* TX */
1758 IWM_TX_CMD = 0x1c,
1759 IWM_TXPATH_FLUSH = 0x1e,
1760 IWM_MGMT_MCAST_KEY = 0x1f,
1761
edfc8a07
IV
1762 /* scheduler config */
1763 IWM_SCD_QUEUE_CFG = 0x1d,
1764
24a8d46a
MD
1765 /* global key */
1766 IWM_WEP_KEY = 0x20,
1767
1768 /* MAC and Binding commands */
1769 IWM_MAC_CONTEXT_CMD = 0x28,
1770 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */
1771 IWM_TIME_EVENT_NOTIFICATION = 0x2a,
1772 IWM_BINDING_CONTEXT_CMD = 0x2b,
1773 IWM_TIME_QUOTA_CMD = 0x2c,
1774 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d,
1775
1776 IWM_LQ_CMD = 0x4e,
1777
1778 /* Calibration */
1779 IWM_TEMPERATURE_NOTIFICATION = 0x62,
1780 IWM_CALIBRATION_CFG_CMD = 0x65,
1781 IWM_CALIBRATION_RES_NOTIFICATION = 0x66,
1782 IWM_CALIBRATION_COMPLETE_NOTIFICATION = 0x67,
1783 IWM_RADIO_VERSION_NOTIFICATION = 0x68,
1784
1785 /* Scan offload */
1786 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51,
1787 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52,
edfc8a07
IV
1788 IWM_HOT_SPOT_CMD = 0x53,
1789 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d,
1790 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e,
24a8d46a
MD
1791 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f,
1792 IWM_MATCH_FOUND_NOTIFICATION = 0xd9,
edfc8a07 1793 IWM_SCAN_ITERATION_COMPLETE = 0xe7,
24a8d46a
MD
1794
1795 /* Phy */
1796 IWM_PHY_CONFIGURATION_CMD = 0x6a,
1797 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b,
1798 /* IWM_PHY_DB_CMD = 0x6c, */
1799
1800 /* Power - legacy power table command */
1801 IWM_POWER_TABLE_CMD = 0x77,
1802 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78,
1803
1804 /* Thermal Throttling*/
1805 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e,
1806
1807 /* Scanning */
24a8d46a
MD
1808 IWM_SCAN_ABORT_CMD = 0x81,
1809 IWM_SCAN_START_NOTIFICATION = 0x82,
1810 IWM_SCAN_RESULTS_NOTIFICATION = 0x83,
24a8d46a
MD
1811
1812 /* NVM */
1813 IWM_NVM_ACCESS_CMD = 0x88,
1814
1815 IWM_SET_CALIB_DEFAULT_CMD = 0x8e,
1816
1817 IWM_BEACON_NOTIFICATION = 0x90,
1818 IWM_BEACON_TEMPLATE_CMD = 0x91,
1819 IWM_TX_ANT_CONFIGURATION_CMD = 0x98,
1820 IWM_BT_CONFIG = 0x9b,
1821 IWM_STATISTICS_NOTIFICATION = 0x9d,
1822 IWM_REDUCE_TX_POWER_CMD = 0x9f,
1823
1824 /* RF-KILL commands and notifications */
1825 IWM_CARD_STATE_CMD = 0xa0,
1826 IWM_CARD_STATE_NOTIFICATION = 0xa1,
1827
1828 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2,
1829
edfc8a07
IV
1830 IWM_MFUART_LOAD_NOTIFICATION = 0xb1,
1831
24a8d46a
MD
1832 /* Power - new power table command */
1833 IWM_MAC_PM_POWER_TABLE = 0xa9,
1834
1835 IWM_REPLY_RX_PHY_CMD = 0xc0,
1836 IWM_REPLY_RX_MPDU_CMD = 0xc1,
1837 IWM_BA_NOTIF = 0xc5,
1838
edfc8a07
IV
1839 /* Location Aware Regulatory */
1840 IWM_MCC_UPDATE_CMD = 0xc8,
1841 IWM_MCC_CHUB_UPDATE_CMD = 0xc9,
1842
24a8d46a
MD
1843 /* BT Coex */
1844 IWM_BT_COEX_PRIO_TABLE = 0xcc,
1845 IWM_BT_COEX_PROT_ENV = 0xcd,
1846 IWM_BT_PROFILE_NOTIFICATION = 0xce,
1847 IWM_BT_COEX_CI = 0x5d,
1848
1849 IWM_REPLY_SF_CFG_CMD = 0xd1,
1850 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2,
1851
edfc8a07
IV
1852 /* DTS measurements */
1853 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc,
1854 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd,
1855
24a8d46a
MD
1856 IWM_REPLY_DEBUG_CMD = 0xf0,
1857 IWM_DEBUG_LOG_MSG = 0xf7,
1858
1859 IWM_MCAST_FILTER_CMD = 0xd0,
1860
1861 /* D3 commands/notifications */
1862 IWM_D3_CONFIG_CMD = 0xd3,
1863 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4,
1864 IWM_OFFLOADS_QUERY_CMD = 0xd5,
1865 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6,
1866
1867 /* for WoWLAN in particular */
1868 IWM_WOWLAN_PATTERNS = 0xe0,
1869 IWM_WOWLAN_CONFIGURATION = 0xe1,
1870 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2,
1871 IWM_WOWLAN_TKIP_PARAM = 0xe3,
1872 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4,
1873 IWM_WOWLAN_GET_STATUSES = 0xe5,
1874 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6,
1875
1876 /* and for NetDetect */
1877 IWM_NET_DETECT_CONFIG_CMD = 0x54,
1878 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56,
1879 IWM_NET_DETECT_PROFILES_CMD = 0x57,
1880 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58,
1881 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59,
1882
1883 IWM_REPLY_MAX = 0xff,
1884};
1885
1886/**
1887 * struct iwm_cmd_response - generic response struct for most commands
1888 * @status: status of the command asked, changes for each one
1889 */
1890struct iwm_cmd_response {
1891 uint32_t status;
1892};
1893
1894/*
1895 * struct iwm_tx_ant_cfg_cmd
1896 * @valid: valid antenna configuration
1897 */
1898struct iwm_tx_ant_cfg_cmd {
1899 uint32_t valid;
1900} __packed;
1901
1902/**
1903 * struct iwm_reduce_tx_power_cmd - TX power reduction command
1904 * IWM_REDUCE_TX_POWER_CMD = 0x9f
1905 * @flags: (reserved for future implementation)
1906 * @mac_context_id: id of the mac ctx for which we are reducing TX power.
1907 * @pwr_restriction: TX power restriction in dBms.
1908 */
1909struct iwm_reduce_tx_power_cmd {
1910 uint8_t flags;
1911 uint8_t mac_context_id;
1912 uint16_t pwr_restriction;
1913} __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */
1914
1915/*
1916 * Calibration control struct.
1917 * Sent as part of the phy configuration command.
1918 * @flow_trigger: bitmap for which calibrations to perform according to
1919 * flow triggers.
1920 * @event_trigger: bitmap for which calibrations to perform according to
1921 * event triggers.
1922 */
1923struct iwm_calib_ctrl {
1924 uint32_t flow_trigger;
1925 uint32_t event_trigger;
1926} __packed;
1927
1928/* This enum defines the bitmap of various calibrations to enable in both
1929 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD.
1930 */
1931enum iwm_calib_cfg {
1932 IWM_CALIB_CFG_XTAL_IDX = (1 << 0),
1933 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1),
1934 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2),
1935 IWM_CALIB_CFG_PAPD_IDX = (1 << 3),
1936 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4),
1937 IWM_CALIB_CFG_DC_IDX = (1 << 5),
1938 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6),
1939 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7),
1940 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8),
1941 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9),
1942 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10),
1943 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11),
1944 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12),
1945 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13),
1946 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14),
1947 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15),
1948 IWM_CALIB_CFG_DAC_IDX = (1 << 16),
1949 IWM_CALIB_CFG_ABS_IDX = (1 << 17),
1950 IWM_CALIB_CFG_AGC_IDX = (1 << 18),
1951};
1952
1953/*
1954 * Phy configuration command.
1955 */
1956struct iwm_phy_cfg_cmd {
1957 uint32_t phy_cfg;
1958 struct iwm_calib_ctrl calib_control;
1959} __packed;
1960
1961#define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1))
1962#define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3))
1963#define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5))
1964#define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7))
1965#define IWM_PHY_CFG_TX_CHAIN_A (1 << 8)
1966#define IWM_PHY_CFG_TX_CHAIN_B (1 << 9)
1967#define IWM_PHY_CFG_TX_CHAIN_C (1 << 10)
1968#define IWM_PHY_CFG_RX_CHAIN_A (1 << 12)
1969#define IWM_PHY_CFG_RX_CHAIN_B (1 << 13)
1970#define IWM_PHY_CFG_RX_CHAIN_C (1 << 14)
1971
1972
1973/* Target of the IWM_NVM_ACCESS_CMD */
1974enum {
1975 IWM_NVM_ACCESS_TARGET_CACHE = 0,
1976 IWM_NVM_ACCESS_TARGET_OTP = 1,
1977 IWM_NVM_ACCESS_TARGET_EEPROM = 2,
1978};
1979
1980/* Section types for IWM_NVM_ACCESS_CMD */
1981enum {
39f8331b
IV
1982 IWM_NVM_SECTION_TYPE_SW = 1,
1983 IWM_NVM_SECTION_TYPE_REGULATORY = 3,
1984 IWM_NVM_SECTION_TYPE_CALIBRATION = 4,
1985 IWM_NVM_SECTION_TYPE_PRODUCTION = 5,
1986 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE = 11,
1987 IWM_NVM_SECTION_TYPE_PHY_SKU = 12,
1988 IWM_NVM_MAX_NUM_SECTIONS = 13,
24a8d46a
MD
1989};
1990
1991/**
1992 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section
1993 * @op_code: 0 - read, 1 - write
1994 * @target: IWM_NVM_ACCESS_TARGET_*
1995 * @type: IWM_NVM_SECTION_TYPE_*
1996 * @offset: offset in bytes into the section
1997 * @length: in bytes, to read/write
1998 * @data: if write operation, the data to write. On read its empty
1999 */
2000struct iwm_nvm_access_cmd {
2001 uint8_t op_code;
2002 uint8_t target;
2003 uint16_t type;
2004 uint16_t offset;
2005 uint16_t length;
2006 uint8_t data[];
2007} __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */
2008
2009/**
2010 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD
2011 * @offset: offset in bytes into the section
2012 * @length: in bytes, either how much was written or read
2013 * @type: IWM_NVM_SECTION_TYPE_*
2014 * @status: 0 for success, fail otherwise
2015 * @data: if read operation, the data returned. Empty on write.
2016 */
2017struct iwm_nvm_access_resp {
2018 uint16_t offset;
2019 uint16_t length;
2020 uint16_t type;
2021 uint16_t status;
2022 uint8_t data[];
2023} __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */
2024
2025/* IWM_MVM_ALIVE 0x1 */
2026
2027/* alive response is_valid values */
2028#define IWM_ALIVE_RESP_UCODE_OK (1 << 0)
2029#define IWM_ALIVE_RESP_RFKILL (1 << 1)
2030
2031/* alive response ver_type values */
2032enum {
2033 IWM_FW_TYPE_HW = 0,
2034 IWM_FW_TYPE_PROT = 1,
2035 IWM_FW_TYPE_AP = 2,
2036 IWM_FW_TYPE_WOWLAN = 3,
2037 IWM_FW_TYPE_TIMING = 4,
2038 IWM_FW_TYPE_WIPAN = 5
2039};
2040
2041/* alive response ver_subtype values */
2042enum {
2043 IWM_FW_SUBTYPE_FULL_FEATURE = 0,
2044 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */
2045 IWM_FW_SUBTYPE_REDUCED = 2,
2046 IWM_FW_SUBTYPE_ALIVE_ONLY = 3,
2047 IWM_FW_SUBTYPE_WOWLAN = 4,
2048 IWM_FW_SUBTYPE_AP_SUBTYPE = 5,
2049 IWM_FW_SUBTYPE_WIPAN = 6,
2050 IWM_FW_SUBTYPE_INITIALIZE = 9
2051};
2052
2053#define IWM_ALIVE_STATUS_ERR 0xDEAD
2054#define IWM_ALIVE_STATUS_OK 0xCAFE
2055
2056#define IWM_ALIVE_FLG_RFKILL (1 << 0)
2057
edfc8a07 2058struct iwm_mvm_alive_resp_v1 {
24a8d46a
MD
2059 uint16_t status;
2060 uint16_t flags;
2061 uint8_t ucode_minor;
2062 uint8_t ucode_major;
2063 uint16_t id;
2064 uint8_t api_minor;
2065 uint8_t api_major;
2066 uint8_t ver_subtype;
2067 uint8_t ver_type;
2068 uint8_t mac;
2069 uint8_t opt;
2070 uint16_t reserved2;
2071 uint32_t timestamp;
2072 uint32_t error_event_table_ptr; /* SRAM address for error log */
2073 uint32_t log_event_table_ptr; /* SRAM address for event log */
2074 uint32_t cpu_register_ptr;
2075 uint32_t dbgm_config_ptr;
2076 uint32_t alive_counter_ptr;
2077 uint32_t scd_base_ptr; /* SRAM address for SCD */
2078} __packed; /* IWM_ALIVE_RES_API_S_VER_1 */
2079
edfc8a07
IV
2080struct iwm_mvm_alive_resp_v2 {
2081 uint16_t status;
2082 uint16_t flags;
2083 uint8_t ucode_minor;
2084 uint8_t ucode_major;
2085 uint16_t id;
2086 uint8_t api_minor;
2087 uint8_t api_major;
2088 uint8_t ver_subtype;
2089 uint8_t ver_type;
2090 uint8_t mac;
2091 uint8_t opt;
2092 uint16_t reserved2;
2093 uint32_t timestamp;
2094 uint32_t error_event_table_ptr; /* SRAM address for error log */
2095 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */
2096 uint32_t cpu_register_ptr;
2097 uint32_t dbgm_config_ptr;
2098 uint32_t alive_counter_ptr;
2099 uint32_t scd_base_ptr; /* SRAM address for SCD */
2100 uint32_t st_fwrd_addr; /* pointer to Store and forward */
2101 uint32_t st_fwrd_size;
2102 uint8_t umac_minor; /* UMAC version: minor */
2103 uint8_t umac_major; /* UMAC version: major */
2104 uint16_t umac_id; /* UMAC version: id */
2105 uint32_t error_info_addr; /* SRAM address for UMAC error log */
2106 uint32_t dbg_print_buff_addr;
2107} __packed; /* ALIVE_RES_API_S_VER_2 */
2108
2109struct iwm_mvm_alive_resp_v3 {
2110 uint16_t status;
2111 uint16_t flags;
2112 uint32_t ucode_minor;
2113 uint32_t ucode_major;
2114 uint8_t ver_subtype;
2115 uint8_t ver_type;
2116 uint8_t mac;
2117 uint8_t opt;
2118 uint32_t timestamp;
2119 uint32_t error_event_table_ptr; /* SRAM address for error log */
2120 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */
2121 uint32_t cpu_register_ptr;
2122 uint32_t dbgm_config_ptr;
2123 uint32_t alive_counter_ptr;
2124 uint32_t scd_base_ptr; /* SRAM address for SCD */
2125 uint32_t st_fwrd_addr; /* pointer to Store and forward */
2126 uint32_t st_fwrd_size;
2127 uint32_t umac_minor; /* UMAC version: minor */
2128 uint32_t umac_major; /* UMAC version: major */
2129 uint32_t error_info_addr; /* SRAM address for UMAC error log */
2130 uint32_t dbg_print_buff_addr;
2131} __packed; /* ALIVE_RES_API_S_VER_3 */
2132
24a8d46a
MD
2133/* Error response/notification */
2134enum {
2135 IWM_FW_ERR_UNKNOWN_CMD = 0x0,
2136 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1,
2137 IWM_FW_ERR_SERVICE = 0x2,
2138 IWM_FW_ERR_ARC_MEMORY = 0x3,
2139 IWM_FW_ERR_ARC_CODE = 0x4,
2140 IWM_FW_ERR_WATCH_DOG = 0x5,
2141 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10,
2142 IWM_FW_ERR_WEP_KEY_SIZE = 0x11,
2143 IWM_FW_ERR_OBSOLETE_FUNC = 0x12,
2144 IWM_FW_ERR_UNEXPECTED = 0xFE,
2145 IWM_FW_ERR_FATAL = 0xFF
2146};
2147
2148/**
2149 * struct iwm_error_resp - FW error indication
2150 * ( IWM_REPLY_ERROR = 0x2 )
2151 * @error_type: one of IWM_FW_ERR_*
77de6c2d 2152 * @cmd_id: the command ID for which the error occurred
24a8d46a
MD
2153 * @bad_cmd_seq_num: sequence number of the erroneous command
2154 * @error_service: which service created the error, applicable only if
2155 * error_type = 2, otherwise 0
2156 * @timestamp: TSF in usecs.
2157 */
2158struct iwm_error_resp {
2159 uint32_t error_type;
2160 uint8_t cmd_id;
2161 uint8_t reserved1;
2162 uint16_t bad_cmd_seq_num;
2163 uint32_t error_service;
2164 uint64_t timestamp;
2165} __packed;
2166
2167
2168/* Common PHY, MAC and Bindings definitions */
2169
2170#define IWM_MAX_MACS_IN_BINDING (3)
2171#define IWM_MAX_BINDINGS (4)
2172#define IWM_AUX_BINDING_INDEX (3)
2173#define IWM_MAX_PHYS (4)
2174
2175/* Used to extract ID and color from the context dword */
2176#define IWM_FW_CTXT_ID_POS (0)
2177#define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS)
2178#define IWM_FW_CTXT_COLOR_POS (8)
2179#define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS)
2180#define IWM_FW_CTXT_INVALID (0xffffffff)
2181
2182#define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\
2183 (_color << IWM_FW_CTXT_COLOR_POS))
2184
2185/* Possible actions on PHYs, MACs and Bindings */
2186enum {
2187 IWM_FW_CTXT_ACTION_STUB = 0,
2188 IWM_FW_CTXT_ACTION_ADD,
2189 IWM_FW_CTXT_ACTION_MODIFY,
2190 IWM_FW_CTXT_ACTION_REMOVE,
2191 IWM_FW_CTXT_ACTION_NUM
2192}; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */
2193
2194/* Time Events */
2195
2196/* Time Event types, according to MAC type */
2197enum iwm_time_event_type {
2198 /* BSS Station Events */
2199 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC,
2200 IWM_TE_BSS_STA_ASSOC,
2201 IWM_TE_BSS_EAP_DHCP_PROT,
2202 IWM_TE_BSS_QUIET_PERIOD,
2203
2204 /* P2P Device Events */
2205 IWM_TE_P2P_DEVICE_DISCOVERABLE,
2206 IWM_TE_P2P_DEVICE_LISTEN,
2207 IWM_TE_P2P_DEVICE_ACTION_SCAN,
2208 IWM_TE_P2P_DEVICE_FULL_SCAN,
2209
2210 /* P2P Client Events */
2211 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC,
2212 IWM_TE_P2P_CLIENT_ASSOC,
2213 IWM_TE_P2P_CLIENT_QUIET_PERIOD,
2214
2215 /* P2P GO Events */
2216 IWM_TE_P2P_GO_ASSOC_PROT,
2217 IWM_TE_P2P_GO_REPETITIVE_NOA,
2218 IWM_TE_P2P_GO_CT_WINDOW,
2219
2220 /* WiDi Sync Events */
2221 IWM_TE_WIDI_TX_SYNC,
2222
2223 IWM_TE_MAX
2224}; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */
2225
2226
2227
2228/* Time event - defines for command API v1 */
2229
2230/*
2231 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed.
2232 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2233 * the first fragment is scheduled.
2234 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only
2235 * the first 2 fragments are scheduled.
2236 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2237 * number of fragments are valid.
2238 *
2239 * Other than the constant defined above, specifying a fragmentation value 'x'
2240 * means that the event can be fragmented but only the first 'x' will be
2241 * scheduled.
2242 */
2243enum {
2244 IWM_TE_V1_FRAG_NONE = 0,
2245 IWM_TE_V1_FRAG_SINGLE = 1,
2246 IWM_TE_V1_FRAG_DUAL = 2,
2247 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff
2248};
2249
2250/* If a Time Event can be fragmented, this is the max number of fragments */
2251#define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff
2252/* Repeat the time event endlessly (until removed) */
2253#define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff
2254/* If a Time Event has bounded repetitions, this is the maximal value */
2255#define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff
2256
2257/* Time Event dependencies: none, on another TE, or in a specific time */
2258enum {
2259 IWM_TE_V1_INDEPENDENT = 0,
2260 IWM_TE_V1_DEP_OTHER = (1 << 0),
2261 IWM_TE_V1_DEP_TSF = (1 << 1),
2262 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2),
2263}; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */
2264
2265/*
2266 * @IWM_TE_V1_NOTIF_NONE: no notifications
2267 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start
2268 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end
2269 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use
2270 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use.
2271 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2272 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2273 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use.
2274 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use.
2275 *
2276 * Supported Time event notifications configuration.
2277 * A notification (both event and fragment) includes a status indicating weather
2278 * the FW was able to schedule the event or not. For fragment start/end
2279 * notification the status is always success. There is no start/end fragment
2280 * notification for monolithic events.
2281 */
2282enum {
2283 IWM_TE_V1_NOTIF_NONE = 0,
2284 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0),
2285 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1),
2286 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2287 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2288 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4),
2289 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5),
2290 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2291 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7),
edfc8a07 2292 IWM_T2_V2_START_IMMEDIATELY = (1 << 11),
24a8d46a
MD
2293}; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */
2294
2295
2296/**
2297 * struct iwm_time_event_cmd_api_v1 - configuring Time Events
2298 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 (see also
2299 * with version 2. determined by IWM_UCODE_TLV_FLAGS)
2300 * ( IWM_TIME_EVENT_CMD = 0x29 )
2301 * @id_and_color: ID and color of the relevant MAC
2302 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2303 * @id: this field has two meanings, depending on the action:
2304 * If the action is ADD, then it means the type of event to add.
2305 * For all other actions it is the unique event ID assigned when the
2306 * event was added by the FW.
2307 * @apply_time: When to start the Time Event (in GP2)
2308 * @max_delay: maximum delay to event's start (apply time), in TU
2309 * @depends_on: the unique ID of the event we depend on (if any)
2310 * @interval: interval between repetitions, in TU
2311 * @interval_reciprocal: 2^32 / interval
2312 * @duration: duration of event in TU
2313 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS
2314 * @dep_policy: one of IWM_TE_V1_INDEPENDENT, IWM_TE_V1_DEP_OTHER, IWM_TE_V1_DEP_TSF
2315 * and IWM_TE_V1_EVENT_SOCIOPATHIC
2316 * @is_present: 0 or 1, are we present or absent during the Time Event
2317 * @max_frags: maximal number of fragments the Time Event can be divided to
2318 * @notify: notifications using IWM_TE_V1_NOTIF_* (whom to notify when)
2319 */
2320struct iwm_time_event_cmd_v1 {
2321 /* COMMON_INDEX_HDR_API_S_VER_1 */
2322 uint32_t id_and_color;
2323 uint32_t action;
2324 uint32_t id;
2325 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 */
2326 uint32_t apply_time;
2327 uint32_t max_delay;
2328 uint32_t dep_policy;
2329 uint32_t depends_on;
2330 uint32_t is_present;
2331 uint32_t max_frags;
2332 uint32_t interval;
2333 uint32_t interval_reciprocal;
2334 uint32_t duration;
2335 uint32_t repeat;
2336 uint32_t notify;
2337} __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_1 */
2338
2339
2340/* Time event - defines for command API v2 */
2341
2342/*
2343 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed.
2344 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2345 * the first fragment is scheduled.
2346 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only
2347 * the first 2 fragments are scheduled.
2348 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2349 * number of fragments are valid.
2350 *
2351 * Other than the constant defined above, specifying a fragmentation value 'x'
2352 * means that the event can be fragmented but only the first 'x' will be
2353 * scheduled.
2354 */
2355enum {
2356 IWM_TE_V2_FRAG_NONE = 0,
2357 IWM_TE_V2_FRAG_SINGLE = 1,
2358 IWM_TE_V2_FRAG_DUAL = 2,
2359 IWM_TE_V2_FRAG_MAX = 0xfe,
2360 IWM_TE_V2_FRAG_ENDLESS = 0xff
2361};
2362
2363/* Repeat the time event endlessly (until removed) */
2364#define IWM_TE_V2_REPEAT_ENDLESS 0xff
2365/* If a Time Event has bounded repetitions, this is the maximal value */
2366#define IWM_TE_V2_REPEAT_MAX 0xfe
2367
2368#define IWM_TE_V2_PLACEMENT_POS 12
2369#define IWM_TE_V2_ABSENCE_POS 15
2370
2371/* Time event policy values (for time event cmd api v2)
2372 * A notification (both event and fragment) includes a status indicating weather
2373 * the FW was able to schedule the event or not. For fragment start/end
2374 * notification the status is always success. There is no start/end fragment
2375 * notification for monolithic events.
2376 *
2377 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable
2378 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start
2379 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end
2380 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use
2381 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use.
2382 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2383 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2384 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use.
2385 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use.
2386 * @IWM_TE_V2_DEP_OTHER: depends on another time event
2387 * @IWM_TE_V2_DEP_TSF: depends on a specific time
2388 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC
2389 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event.
2390 */
2391enum {
2392 IWM_TE_V2_DEFAULT_POLICY = 0x0,
2393
2394 /* notifications (event start/stop, fragment start/stop) */
2395 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0),
2396 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1),
2397 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2398 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2399
2400 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4),
2401 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5),
2402 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2403 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7),
2404
2405 IWM_TE_V2_NOTIF_MSK = 0xff,
2406
2407 /* placement characteristics */
2408 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS),
2409 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)),
2410 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)),
2411
2412 /* are we present or absent during the Time Event. */
2413 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS),
2414};
2415
2416/**
2417 * struct iwm_time_event_cmd_api_v2 - configuring Time Events
2418 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also
2419 * with version 1. determined by IWM_UCODE_TLV_FLAGS)
2420 * ( IWM_TIME_EVENT_CMD = 0x29 )
2421 * @id_and_color: ID and color of the relevant MAC
2422 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2423 * @id: this field has two meanings, depending on the action:
2424 * If the action is ADD, then it means the type of event to add.
2425 * For all other actions it is the unique event ID assigned when the
2426 * event was added by the FW.
2427 * @apply_time: When to start the Time Event (in GP2)
2428 * @max_delay: maximum delay to event's start (apply time), in TU
2429 * @depends_on: the unique ID of the event we depend on (if any)
2430 * @interval: interval between repetitions, in TU
2431 * @duration: duration of event in TU
2432 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS
2433 * @max_frags: maximal number of fragments the Time Event can be divided to
2434 * @policy: defines whether uCode shall notify the host or other uCode modules
2435 * on event and/or fragment start and/or end
2436 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF
2437 * IWM_TE_EVENT_SOCIOPATHIC
2438 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_*
2439 */
2440struct iwm_time_event_cmd_v2 {
2441 /* COMMON_INDEX_HDR_API_S_VER_1 */
2442 uint32_t id_and_color;
2443 uint32_t action;
2444 uint32_t id;
2445 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */
2446 uint32_t apply_time;
2447 uint32_t max_delay;
2448 uint32_t depends_on;
2449 uint32_t interval;
2450 uint32_t duration;
2451 uint8_t repeat;
2452 uint8_t max_frags;
2453 uint16_t policy;
2454} __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */
2455
2456/**
2457 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd
2458 * @status: bit 0 indicates success, all others specify errors
2459 * @id: the Time Event type
2460 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE
2461 * @id_and_color: ID and color of the relevant MAC
2462 */
2463struct iwm_time_event_resp {
2464 uint32_t status;
2465 uint32_t id;
2466 uint32_t unique_id;
2467 uint32_t id_and_color;
2468} __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */
2469
2470/**
2471 * struct iwm_time_event_notif - notifications of time event start/stop
2472 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a )
2473 * @timestamp: action timestamp in GP2
2474 * @session_id: session's unique id
2475 * @unique_id: unique id of the Time Event itself
2476 * @id_and_color: ID and color of the relevant MAC
2477 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END
2478 * @status: true if scheduled, false otherwise (not executed)
2479 */
2480struct iwm_time_event_notif {
2481 uint32_t timestamp;
2482 uint32_t session_id;
2483 uint32_t unique_id;
2484 uint32_t id_and_color;
2485 uint32_t action;
2486 uint32_t status;
2487} __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */
2488
2489
2490/* Bindings and Time Quota */
2491
2492/**
2493 * struct iwm_binding_cmd - configuring bindings
2494 * ( IWM_BINDING_CONTEXT_CMD = 0x2b )
2495 * @id_and_color: ID and color of the relevant Binding
2496 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2497 * @macs: array of MAC id and colors which belong to the binding
2498 * @phy: PHY id and color which belongs to the binding
2499 */
2500struct iwm_binding_cmd {
2501 /* COMMON_INDEX_HDR_API_S_VER_1 */
2502 uint32_t id_and_color;
2503 uint32_t action;
2504 /* IWM_BINDING_DATA_API_S_VER_1 */
2505 uint32_t macs[IWM_MAX_MACS_IN_BINDING];
2506 uint32_t phy;
2507} __packed; /* IWM_BINDING_CMD_API_S_VER_1 */
2508
2509/* The maximal number of fragments in the FW's schedule session */
2510#define IWM_MVM_MAX_QUOTA 128
2511
2512/**
2513 * struct iwm_time_quota_data - configuration of time quota per binding
2514 * @id_and_color: ID and color of the relevant Binding
2515 * @quota: absolute time quota in TU. The scheduler will try to divide the
2516 * remainig quota (after Time Events) according to this quota.
2517 * @max_duration: max uninterrupted context duration in TU
2518 */
2519struct iwm_time_quota_data {
2520 uint32_t id_and_color;
2521 uint32_t quota;
2522 uint32_t max_duration;
2523} __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */
2524
2525/**
2526 * struct iwm_time_quota_cmd - configuration of time quota between bindings
2527 * ( IWM_TIME_QUOTA_CMD = 0x2c )
2528 * @quotas: allocations per binding
2529 */
2530struct iwm_time_quota_cmd {
2531 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS];
2532} __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */
2533
2534
2535/* PHY context */
2536
2537/* Supported bands */
2538#define IWM_PHY_BAND_5 (0)
2539#define IWM_PHY_BAND_24 (1)
2540
2541/* Supported channel width, vary if there is VHT support */
2542#define IWM_PHY_VHT_CHANNEL_MODE20 (0x0)
2543#define IWM_PHY_VHT_CHANNEL_MODE40 (0x1)
2544#define IWM_PHY_VHT_CHANNEL_MODE80 (0x2)
2545#define IWM_PHY_VHT_CHANNEL_MODE160 (0x3)
2546
2547/*
2548 * Control channel position:
2549 * For legacy set bit means upper channel, otherwise lower.
2550 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
2551 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
2552 * center_freq
2553 * |
2554 * 40Mhz |_______|_______|
2555 * 80Mhz |_______|_______|_______|_______|
2556 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______|
2557 * code 011 010 001 000 | 100 101 110 111
2558 */
2559#define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0)
2560#define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1)
2561#define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2)
2562#define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3)
2563#define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4)
2564#define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5)
2565#define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6)
2566#define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7)
2567
2568/*
2569 * @band: IWM_PHY_BAND_*
2570 * @channel: channel number
2571 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
2572 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
2573 */
2574struct iwm_fw_channel_info {
2575 uint8_t band;
2576 uint8_t channel;
2577 uint8_t width;
2578 uint8_t ctrl_pos;
2579} __packed;
2580
2581#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
2582#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \
2583 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS)
2584#define IWM_PHY_RX_CHAIN_VALID_POS (1)
2585#define IWM_PHY_RX_CHAIN_VALID_MSK \
2586 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS)
2587#define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4)
2588#define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \
2589 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS)
2590#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
2591#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
2592 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
2593#define IWM_PHY_RX_CHAIN_CNT_POS (10)
2594#define IWM_PHY_RX_CHAIN_CNT_MSK \
2595 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS)
2596#define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12)
2597#define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \
2598 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS)
2599#define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14)
2600#define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \
2601 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS)
2602
2603/* TODO: fix the value, make it depend on firmware at runtime? */
2604#define IWM_NUM_PHY_CTX 3
2605
2606/* TODO: complete missing documentation */
2607/**
2608 * struct iwm_phy_context_cmd - config of the PHY context
2609 * ( IWM_PHY_CONTEXT_CMD = 0x8 )
2610 * @id_and_color: ID and color of the relevant Binding
2611 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2612 * @apply_time: 0 means immediate apply and context switch.
2613 * other value means apply new params after X usecs
2614 * @tx_param_color: ???
2615 * @channel_info:
2616 * @txchain_info: ???
2617 * @rxchain_info: ???
2618 * @acquisition_data: ???
2619 * @dsp_cfg_flags: set to 0
2620 */
2621struct iwm_phy_context_cmd {
2622 /* COMMON_INDEX_HDR_API_S_VER_1 */
2623 uint32_t id_and_color;
2624 uint32_t action;
2625 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */
2626 uint32_t apply_time;
2627 uint32_t tx_param_color;
2628 struct iwm_fw_channel_info ci;
2629 uint32_t txchain_info;
2630 uint32_t rxchain_info;
2631 uint32_t acquisition_data;
2632 uint32_t dsp_cfg_flags;
2633} __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */
2634
2635#define IWM_RX_INFO_PHY_CNT 8
2636#define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1
2637#define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
2638#define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
2639#define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
2640#define IWM_RX_INFO_ENERGY_ANT_A_POS 0
2641#define IWM_RX_INFO_ENERGY_ANT_B_POS 8
2642#define IWM_RX_INFO_ENERGY_ANT_C_POS 16
2643
2644#define IWM_RX_INFO_AGC_IDX 1
2645#define IWM_RX_INFO_RSSI_AB_IDX 2
2646#define IWM_OFDM_AGC_A_MSK 0x0000007f
2647#define IWM_OFDM_AGC_A_POS 0
2648#define IWM_OFDM_AGC_B_MSK 0x00003f80
2649#define IWM_OFDM_AGC_B_POS 7
2650#define IWM_OFDM_AGC_CODE_MSK 0x3fe00000
2651#define IWM_OFDM_AGC_CODE_POS 20
2652#define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff
2653#define IWM_OFDM_RSSI_A_POS 0
2654#define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00
2655#define IWM_OFDM_RSSI_ALLBAND_A_POS 8
2656#define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000
2657#define IWM_OFDM_RSSI_B_POS 16
2658#define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000
2659#define IWM_OFDM_RSSI_ALLBAND_B_POS 24
2660
2661/**
2662 * struct iwm_rx_phy_info - phy info
2663 * (IWM_REPLY_RX_PHY_CMD = 0xc0)
2664 * @non_cfg_phy_cnt: non configurable DSP phy data byte count
2665 * @cfg_phy_cnt: configurable DSP phy data byte count
2666 * @stat_id: configurable DSP phy data set ID
2667 * @reserved1:
2668 * @system_timestamp: GP2 at on air rise
2669 * @timestamp: TSF at on air rise
2670 * @beacon_time_stamp: beacon at on-air rise
2671 * @phy_flags: general phy flags: band, modulation, ...
2672 * @channel: channel number
2673 * @non_cfg_phy_buf: for various implementations of non_cfg_phy
2674 * @rate_n_flags: IWM_RATE_MCS_*
2675 * @byte_count: frame's byte-count
2676 * @frame_time: frame's time on the air, based on byte count and frame rate
2677 * calculation
2678 * @mac_active_msk: what MACs were active when the frame was received
2679 *
2680 * Before each Rx, the device sends this data. It contains PHY information
2681 * about the reception of the packet.
2682 */
2683struct iwm_rx_phy_info {
2684 uint8_t non_cfg_phy_cnt;
2685 uint8_t cfg_phy_cnt;
2686 uint8_t stat_id;
2687 uint8_t reserved1;
2688 uint32_t system_timestamp;
2689 uint64_t timestamp;
2690 uint32_t beacon_time_stamp;
2691 uint16_t phy_flags;
2692#define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2)
2693 uint16_t channel;
2694 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT];
2695 uint8_t rate;
2696 uint8_t rflags;
2697 uint16_t xrflags;
2698 uint32_t byte_count;
2699 uint16_t mac_active_msk;
2700 uint16_t frame_time;
2701} __packed;
2702
2703struct iwm_rx_mpdu_res_start {
2704 uint16_t byte_count;
2705 uint16_t reserved;
2706} __packed;
2707
2708/**
2709 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags
2710 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
2711 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK:
2712 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
2713 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND:
2714 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
2715 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
2716 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
2717 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
2718 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
2719 */
2720enum iwm_rx_phy_flags {
2721 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0),
2722 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1),
2723 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2),
2724 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3),
2725 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
2726 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4,
2727 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7),
2728 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8),
2729 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9),
2730 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10),
2731};
2732
2733/**
2734 * enum iwm_mvm_rx_status - written by fw for each Rx packet
2735 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
2736 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
2737 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND:
2738 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID:
2739 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK:
2740 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
2741 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
2742 * in the driver.
2743 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
2744 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or
2745 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if
2746 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
2747 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
2748 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
2749 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
2750 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
2751 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
2752 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
2753 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
2754 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
2755 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP:
2756 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP:
2757 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT:
2758 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
2759 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK:
2760 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK:
2761 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL:
2762 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK:
2763 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK:
2764 */
2765enum iwm_mvm_rx_status {
2766 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0),
2767 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1),
2768 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2),
2769 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3),
2770 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4),
2771 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5),
2772 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6),
2773 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7),
2774 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7),
2775 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8),
2776 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8),
2777 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8),
2778 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8),
2779 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8),
2780 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8),
2781 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8),
2782 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8),
2783 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11),
2784 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12),
2785 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13),
2786 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14),
2787 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15),
2788 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000),
2789 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000),
2790 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29),
2791 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000),
2792 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000),
2793};
2794
2795/**
2796 * struct iwm_radio_version_notif - information on the radio version
2797 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 )
2798 * @radio_flavor:
2799 * @radio_step:
2800 * @radio_dash:
2801 */
2802struct iwm_radio_version_notif {
2803 uint32_t radio_flavor;
2804 uint32_t radio_step;
2805 uint32_t radio_dash;
2806} __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */
2807
2808enum iwm_card_state_flags {
2809 IWM_CARD_ENABLED = 0x00,
2810 IWM_HW_CARD_DISABLED = 0x01,
2811 IWM_SW_CARD_DISABLED = 0x02,
2812 IWM_CT_KILL_CARD_DISABLED = 0x04,
2813 IWM_HALT_CARD_DISABLED = 0x08,
2814 IWM_CARD_DISABLED_MSK = 0x0f,
2815 IWM_CARD_IS_RX_ON = 0x10,
2816};
2817
2818/**
2819 * struct iwm_radio_version_notif - information on the radio version
2820 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 )
2821 * @flags: %iwm_card_state_flags
2822 */
2823struct iwm_card_state_notif {
2824 uint32_t flags;
2825} __packed; /* CARD_STATE_NTFY_API_S_VER_1 */
2826
2827/**
2828 * struct iwm_missed_beacons_notif - information on missed beacons
2829 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 )
2830 * @mac_id: interface ID
2831 * @consec_missed_beacons_since_last_rx: number of consecutive missed
2832 * beacons since last RX.
2833 * @consec_missed_beacons: number of consecutive missed beacons
2834 * @num_expected_beacons:
2835 * @num_recvd_beacons:
2836 */
2837struct iwm_missed_beacons_notif {
2838 uint32_t mac_id;
2839 uint32_t consec_missed_beacons_since_last_rx;
2840 uint32_t consec_missed_beacons;
2841 uint32_t num_expected_beacons;
2842 uint32_t num_recvd_beacons;
2843} __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */
2844
edfc8a07
IV
2845/**
2846 * struct iwm_mfuart_load_notif - mfuart image version & status
2847 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 )
2848 * @installed_ver: installed image version
2849 * @external_ver: external image version
2850 * @status: MFUART loading status
2851 * @duration: MFUART loading time
2852*/
2853struct iwm_mfuart_load_notif {
2854 uint32_t installed_ver;
2855 uint32_t external_ver;
2856 uint32_t status;
2857 uint32_t duration;
2858} __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/
2859
24a8d46a
MD
2860/**
2861 * struct iwm_set_calib_default_cmd - set default value for calibration.
2862 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e )
2863 * @calib_index: the calibration to set value for
2864 * @length: of data
2865 * @data: the value to set for the calibration result
2866 */
2867struct iwm_set_calib_default_cmd {
2868 uint16_t calib_index;
2869 uint16_t length;
2870 uint8_t data[0];
2871} __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */
2872
2873#define IWM_MAX_PORT_ID_NUM 2
2874#define IWM_MAX_MCAST_FILTERING_ADDRESSES 256
2875
2876/**
2877 * struct iwm_mcast_filter_cmd - configure multicast filter.
2878 * @filter_own: Set 1 to filter out multicast packets sent by station itself
2879 * @port_id: Multicast MAC addresses array specifier. This is a strange way
2880 * to identify network interface adopted in host-device IF.
2881 * It is used by FW as index in array of addresses. This array has
2882 * IWM_MAX_PORT_ID_NUM members.
2883 * @count: Number of MAC addresses in the array
2884 * @pass_all: Set 1 to pass all multicast packets.
2885 * @bssid: current association BSSID.
2886 * @addr_list: Place holder for array of MAC addresses.
2887 * IMPORTANT: add padding if necessary to ensure DWORD alignment.
2888 */
2889struct iwm_mcast_filter_cmd {
2890 uint8_t filter_own;
2891 uint8_t port_id;
2892 uint8_t count;
2893 uint8_t pass_all;
2894 uint8_t bssid[6];
2895 uint8_t reserved[2];
2896 uint8_t addr_list[0];
2897} __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */
2898
2899struct iwm_mvm_statistics_dbg {
2900 uint32_t burst_check;
2901 uint32_t burst_count;
2902 uint32_t wait_for_silence_timeout_cnt;
2903 uint32_t reserved[3];
2904} __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */
2905
2906struct iwm_mvm_statistics_div {
2907 uint32_t tx_on_a;
2908 uint32_t tx_on_b;
2909 uint32_t exec_time;
2910 uint32_t probe_time;
2911 uint32_t rssi_ant;
2912 uint32_t reserved2;
2913} __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */
2914
2915struct iwm_mvm_statistics_general_common {
2916 uint32_t temperature; /* radio temperature */
2917 uint32_t temperature_m; /* radio voltage */
2918 struct iwm_mvm_statistics_dbg dbg;
2919 uint32_t sleep_time;
2920 uint32_t slots_out;
2921 uint32_t slots_idle;
2922 uint32_t ttl_timestamp;
2923 struct iwm_mvm_statistics_div div;
2924 uint32_t rx_enable_counter;
2925 /*
2926 * num_of_sos_states:
2927 * count the number of times we have to re-tune
2928 * in order to get out of bad PHY status
2929 */
2930 uint32_t num_of_sos_states;
2931} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
2932
2933struct iwm_mvm_statistics_rx_non_phy {
2934 uint32_t bogus_cts; /* CTS received when not expecting CTS */
2935 uint32_t bogus_ack; /* ACK received when not expecting ACK */
2936 uint32_t non_bssid_frames; /* number of frames with BSSID that
2937 * doesn't belong to the STA BSSID */
2938 uint32_t filtered_frames; /* count frames that were dumped in the
2939 * filtering process */
2940 uint32_t non_channel_beacons; /* beacons with our bss id but not on
2941 * our serving channel */
2942 uint32_t channel_beacons; /* beacons with our bss id and in our
2943 * serving channel */
2944 uint32_t num_missed_bcon; /* number of missed beacons */
2945 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the
2946 * ADC was in saturation */
2947 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched
2948 * for INA */
2949 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */
2950 uint32_t interference_data_flag; /* flag for interference data
2951 * availability. 1 when data is
2952 * available. */
2953 uint32_t channel_load; /* counts RX Enable time in uSec */
2954 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM
2955 * and CCK) counter */
2956 uint32_t beacon_rssi_a;
2957 uint32_t beacon_rssi_b;
2958 uint32_t beacon_rssi_c;
2959 uint32_t beacon_energy_a;
2960 uint32_t beacon_energy_b;
2961 uint32_t beacon_energy_c;
2962 uint32_t num_bt_kills;
2963 uint32_t mac_id;
2964 uint32_t directed_data_mpdu;
2965} __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */
2966
2967struct iwm_mvm_statistics_rx_phy {
2968 uint32_t ina_cnt;
2969 uint32_t fina_cnt;
2970 uint32_t plcp_err;
2971 uint32_t crc32_err;
2972 uint32_t overrun_err;
2973 uint32_t early_overrun_err;
2974 uint32_t crc32_good;
2975 uint32_t false_alarm_cnt;
2976 uint32_t fina_sync_err_cnt;
2977 uint32_t sfd_timeout;
2978 uint32_t fina_timeout;
2979 uint32_t unresponded_rts;
2980 uint32_t rxe_frame_limit_overrun;
2981 uint32_t sent_ack_cnt;
2982 uint32_t sent_cts_cnt;
2983 uint32_t sent_ba_rsp_cnt;
2984 uint32_t dsp_self_kill;
2985 uint32_t mh_format_err;
2986 uint32_t re_acq_main_rssi_sum;
2987 uint32_t reserved;
2988} __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */
2989
2990struct iwm_mvm_statistics_rx_ht_phy {
2991 uint32_t plcp_err;
2992 uint32_t overrun_err;
2993 uint32_t early_overrun_err;
2994 uint32_t crc32_good;
2995 uint32_t crc32_err;
2996 uint32_t mh_format_err;
2997 uint32_t agg_crc32_good;
2998 uint32_t agg_mpdu_cnt;
2999 uint32_t agg_cnt;
3000 uint32_t unsupport_mcs;
3001} __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */
3002
3003#define IWM_MAX_CHAINS 3
3004
3005struct iwm_mvm_statistics_tx_non_phy_agg {
3006 uint32_t ba_timeout;
3007 uint32_t ba_reschedule_frames;
3008 uint32_t scd_query_agg_frame_cnt;
3009 uint32_t scd_query_no_agg;
3010 uint32_t scd_query_agg;
3011 uint32_t scd_query_mismatch;
3012 uint32_t frame_not_ready;
3013 uint32_t underrun;
3014 uint32_t bt_prio_kill;
3015 uint32_t rx_ba_rsp_cnt;
3016 int8_t txpower[IWM_MAX_CHAINS];
3017 int8_t reserved;
3018 uint32_t reserved2;
3019} __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */
3020
3021struct iwm_mvm_statistics_tx_channel_width {
3022 uint32_t ext_cca_narrow_ch20[1];
3023 uint32_t ext_cca_narrow_ch40[2];
3024 uint32_t ext_cca_narrow_ch80[3];
3025 uint32_t ext_cca_narrow_ch160[4];
3026 uint32_t last_tx_ch_width_indx;
3027 uint32_t rx_detected_per_ch_width[4];
3028 uint32_t success_per_ch_width[4];
3029 uint32_t fail_per_ch_width[4];
3030}; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */
3031
3032struct iwm_mvm_statistics_tx {
3033 uint32_t preamble_cnt;
3034 uint32_t rx_detected_cnt;
3035 uint32_t bt_prio_defer_cnt;
3036 uint32_t bt_prio_kill_cnt;
3037 uint32_t few_bytes_cnt;
3038 uint32_t cts_timeout;
3039 uint32_t ack_timeout;
3040 uint32_t expected_ack_cnt;
3041 uint32_t actual_ack_cnt;
3042 uint32_t dump_msdu_cnt;
3043 uint32_t burst_abort_next_frame_mismatch_cnt;
3044 uint32_t burst_abort_missing_next_frame_cnt;
3045 uint32_t cts_timeout_collision;
3046 uint32_t ack_or_ba_timeout_collision;
3047 struct iwm_mvm_statistics_tx_non_phy_agg agg;
3048 struct iwm_mvm_statistics_tx_channel_width channel_width;
3049} __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */
3050
3051
3052struct iwm_mvm_statistics_bt_activity {
3053 uint32_t hi_priority_tx_req_cnt;
3054 uint32_t hi_priority_tx_denied_cnt;
3055 uint32_t lo_priority_tx_req_cnt;
3056 uint32_t lo_priority_tx_denied_cnt;
3057 uint32_t hi_priority_rx_req_cnt;
3058 uint32_t hi_priority_rx_denied_cnt;
3059 uint32_t lo_priority_rx_req_cnt;
3060 uint32_t lo_priority_rx_denied_cnt;
3061} __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */
3062
3063struct iwm_mvm_statistics_general {
3064 struct iwm_mvm_statistics_general_common common;
3065 uint32_t beacon_filtered;
3066 uint32_t missed_beacons;
3067 int8_t beacon_filter_average_energy;
3068 int8_t beacon_filter_reason;
3069 int8_t beacon_filter_current_energy;
3070 int8_t beacon_filter_reserved;
3071 uint32_t beacon_filter_delta_time;
3072 struct iwm_mvm_statistics_bt_activity bt_activity;
3073} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
3074
3075struct iwm_mvm_statistics_rx {
3076 struct iwm_mvm_statistics_rx_phy ofdm;
3077 struct iwm_mvm_statistics_rx_phy cck;
3078 struct iwm_mvm_statistics_rx_non_phy general;
3079 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht;
3080} __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */
3081
3082/*
3083 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command)
3084 *
3085 * By default, uCode issues this notification after receiving a beacon
3086 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the
3087 * IWM_REPLY_STATISTICS_CMD 0x9c, above.
3088 *
3089 * Statistics counters continue to increment beacon after beacon, but are
3090 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD
3091 * 0x9c with CLEAR_STATS bit set (see above).
3092 *
3093 * uCode also issues this notification during scans. uCode clears statistics
3094 * appropriately so that each notification contains statistics for only the
3095 * one channel that has just been scanned.
3096 */
3097
3098struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */
3099 uint32_t flag;
3100 struct iwm_mvm_statistics_rx rx;
3101 struct iwm_mvm_statistics_tx tx;
3102 struct iwm_mvm_statistics_general general;
3103} __packed;
3104
3105/***********************************
3106 * Smart Fifo API
3107 ***********************************/
3108/* Smart Fifo state */
3109enum iwm_sf_state {
3110 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */
3111 IWM_SF_FULL_ON,
3112 IWM_SF_UNINIT,
3113 IWM_SF_INIT_OFF,
3114 IWM_SF_HW_NUM_STATES
3115};
3116
3117/* Smart Fifo possible scenario */
3118enum iwm_sf_scenario {
3119 IWM_SF_SCENARIO_SINGLE_UNICAST,
3120 IWM_SF_SCENARIO_AGG_UNICAST,
3121 IWM_SF_SCENARIO_MULTICAST,
3122 IWM_SF_SCENARIO_BA_RESP,
3123 IWM_SF_SCENARIO_TX_RESP,
3124 IWM_SF_NUM_SCENARIO
3125};
3126
3127#define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */
3128#define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */
3129
3130/* smart FIFO default values */
3131#define IWM_SF_W_MARK_SISO 4096
3132#define IWM_SF_W_MARK_MIMO2 8192
3133#define IWM_SF_W_MARK_MIMO3 6144
3134#define IWM_SF_W_MARK_LEGACY 4096
3135#define IWM_SF_W_MARK_SCAN 4096
3136
edfc8a07
IV
3137/* SF Scenarios timers for default configuration (aligned to 32 uSec) */
3138#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3139#define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3140#define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3141#define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
288315ff 3142#define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 uSec */
edfc8a07
IV
3143#define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3144#define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */
3145#define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */
3146#define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */
3147#define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */
3148
24a8d46a
MD
3149/* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */
3150#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */
3151#define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */
3152#define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */
3153#define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */
3154#define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */
3155#define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */
3156#define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */
3157#define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */
3158#define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */
3159#define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */
3160
3161#define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */
3162
edfc8a07
IV
3163#define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16)
3164
24a8d46a
MD
3165/**
3166 * Smart Fifo configuration command.
288315ff 3167 * @state: smart fifo state, types listed in enum %iwm_sf_state.
77de6c2d 3168 * @watermark: Minimum allowed available free space in RXF for transient state.
24a8d46a
MD
3169 * @long_delay_timeouts: aging and idle timer values for each scenario
3170 * in long delay state.
3171 * @full_on_timeouts: timer values for each scenario in full on state.
3172 */
3173struct iwm_sf_cfg_cmd {
288315ff 3174 uint32_t state;
24a8d46a
MD
3175 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER];
3176 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
3177 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
3178} __packed; /* IWM_SF_CFG_API_S_VER_2 */
3179
24a8d46a
MD
3180/*
3181 * The first MAC indices (starting from 0)
3182 * are available to the driver, AUX follows
3183 */
3184#define IWM_MAC_INDEX_AUX 4
3185#define IWM_MAC_INDEX_MIN_DRIVER 0
3186#define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX
3187
3188enum iwm_ac {
3189 IWM_AC_BK,
3190 IWM_AC_BE,
3191 IWM_AC_VI,
3192 IWM_AC_VO,
3193 IWM_AC_NUM,
3194};
3195
3196/**
3197 * enum iwm_mac_protection_flags - MAC context flags
3198 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames,
3199 * this will require CCK RTS/CTS2self.
3200 * RTS/CTS will protect full burst time.
3201 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection
3202 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions
3203 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self
3204 */
3205enum iwm_mac_protection_flags {
3206 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3),
3207 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23),
3208 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24),
3209 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30),
3210};
3211
3212#define IWM_MAC_FLG_SHORT_SLOT (1 << 4)
3213#define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5)
3214
3215/**
3216 * enum iwm_mac_types - Supported MAC types
3217 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type
3218 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal)
3219 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?)
3220 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS
3221 * @IWM_FW_MAC_TYPE_IBSS: IBSS
3222 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station
3223 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device
3224 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client
3225 * @IWM_FW_MAC_TYPE_GO: P2P GO
3226 * @IWM_FW_MAC_TYPE_TEST: ?
3227 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type
3228 */
3229enum iwm_mac_types {
3230 IWM_FW_MAC_TYPE_FIRST = 1,
3231 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST,
3232 IWM_FW_MAC_TYPE_LISTENER,
3233 IWM_FW_MAC_TYPE_PIBSS,
3234 IWM_FW_MAC_TYPE_IBSS,
3235 IWM_FW_MAC_TYPE_BSS_STA,
3236 IWM_FW_MAC_TYPE_P2P_DEVICE,
3237 IWM_FW_MAC_TYPE_P2P_STA,
3238 IWM_FW_MAC_TYPE_GO,
3239 IWM_FW_MAC_TYPE_TEST,
3240 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST
3241}; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */
3242
3243/**
3244 * enum iwm_tsf_id - TSF hw timer ID
3245 * @IWM_TSF_ID_A: use TSF A
3246 * @IWM_TSF_ID_B: use TSF B
3247 * @IWM_TSF_ID_C: use TSF C
3248 * @IWM_TSF_ID_D: use TSF D
3249 * @IWM_NUM_TSF_IDS: number of TSF timers available
3250 */
3251enum iwm_tsf_id {
3252 IWM_TSF_ID_A = 0,
3253 IWM_TSF_ID_B = 1,
3254 IWM_TSF_ID_C = 2,
3255 IWM_TSF_ID_D = 3,
3256 IWM_NUM_TSF_IDS = 4,
3257}; /* IWM_TSF_ID_API_E_VER_1 */
3258
3259/**
3260 * struct iwm_mac_data_ap - configuration data for AP MAC context
3261 * @beacon_time: beacon transmit time in system time
3262 * @beacon_tsf: beacon transmit time in TSF
3263 * @bi: beacon interval in TU
3264 * @bi_reciprocal: 2^32 / bi
3265 * @dtim_interval: dtim transmit time in TU
3266 * @dtim_reciprocal: 2^32 / dtim_interval
3267 * @mcast_qid: queue ID for multicast traffic
3268 * @beacon_template: beacon template ID
3269 */
3270struct iwm_mac_data_ap {
3271 uint32_t beacon_time;
3272 uint64_t beacon_tsf;
3273 uint32_t bi;
3274 uint32_t bi_reciprocal;
3275 uint32_t dtim_interval;
3276 uint32_t dtim_reciprocal;
3277 uint32_t mcast_qid;
3278 uint32_t beacon_template;
3279} __packed; /* AP_MAC_DATA_API_S_VER_1 */
3280
3281/**
3282 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context
3283 * @beacon_time: beacon transmit time in system time
3284 * @beacon_tsf: beacon transmit time in TSF
3285 * @bi: beacon interval in TU
3286 * @bi_reciprocal: 2^32 / bi
3287 * @beacon_template: beacon template ID
3288 */
3289struct iwm_mac_data_ibss {
3290 uint32_t beacon_time;
3291 uint64_t beacon_tsf;
3292 uint32_t bi;
3293 uint32_t bi_reciprocal;
3294 uint32_t beacon_template;
3295} __packed; /* IBSS_MAC_DATA_API_S_VER_1 */
3296
3297/**
3298 * struct iwm_mac_data_sta - configuration data for station MAC context
3299 * @is_assoc: 1 for associated state, 0 otherwise
3300 * @dtim_time: DTIM arrival time in system time
3301 * @dtim_tsf: DTIM arrival time in TSF
3302 * @bi: beacon interval in TU, applicable only when associated
3303 * @bi_reciprocal: 2^32 / bi , applicable only when associated
3304 * @dtim_interval: DTIM interval in TU, applicable only when associated
3305 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated
3306 * @listen_interval: in beacon intervals, applicable only when associated
3307 * @assoc_id: unique ID assigned by the AP during association
3308 */
3309struct iwm_mac_data_sta {
3310 uint32_t is_assoc;
3311 uint32_t dtim_time;
3312 uint64_t dtim_tsf;
3313 uint32_t bi;
3314 uint32_t bi_reciprocal;
3315 uint32_t dtim_interval;
3316 uint32_t dtim_reciprocal;
3317 uint32_t listen_interval;
3318 uint32_t assoc_id;
3319 uint32_t assoc_beacon_arrive_time;
3320} __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */
3321
3322/**
3323 * struct iwm_mac_data_go - configuration data for P2P GO MAC context
3324 * @ap: iwm_mac_data_ap struct with most config data
3325 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
3326 * 0 indicates that there is no CT window.
3327 * @opp_ps_enabled: indicate that opportunistic PS allowed
3328 */
3329struct iwm_mac_data_go {
3330 struct iwm_mac_data_ap ap;
3331 uint32_t ctwin;
3332 uint32_t opp_ps_enabled;
3333} __packed; /* GO_MAC_DATA_API_S_VER_1 */
3334
3335/**
3336 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context
3337 * @sta: iwm_mac_data_sta struct with most config data
3338 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
3339 * 0 indicates that there is no CT window.
3340 */
3341struct iwm_mac_data_p2p_sta {
3342 struct iwm_mac_data_sta sta;
3343 uint32_t ctwin;
3344} __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */
3345
3346/**
3347 * struct iwm_mac_data_pibss - Pseudo IBSS config data
3348 * @stats_interval: interval in TU between statistics notifications to host.
3349 */
3350struct iwm_mac_data_pibss {
3351 uint32_t stats_interval;
3352} __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */
3353
3354/*
3355 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC
3356 * context.
3357 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on
3358 * other channels as well. This should be to true only in case that the
3359 * device is discoverable and there is an active GO. Note that setting this
3360 * field when not needed, will increase the number of interrupts and have
3361 * effect on the platform power, as this setting opens the Rx filters on
3362 * all macs.
3363 */
3364struct iwm_mac_data_p2p_dev {
3365 uint32_t is_disc_extended;
3366} __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */
3367
3368/**
3369 * enum iwm_mac_filter_flags - MAC context filter flags
3370 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames
3371 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and
3372 * control frames to the host
3373 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames
3374 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames
3375 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames
3376 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host
3377 * (in station mode when associated)
3378 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames
3379 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames
3380 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host
3381 */
3382enum iwm_mac_filter_flags {
3383 IWM_MAC_FILTER_IN_PROMISC = (1 << 0),
3384 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1),
3385 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2),
3386 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3),
3387 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4),
3388 IWM_MAC_FILTER_IN_BEACON = (1 << 6),
3389 IWM_MAC_FILTER_OUT_BCAST = (1 << 8),
3390 IWM_MAC_FILTER_IN_CRC32 = (1 << 11),
3391 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12),
3392};
3393
3394/**
3395 * enum iwm_mac_qos_flags - QoS flags
3396 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ?
3397 * @IWM_MAC_QOS_FLG_TGN: HT is enabled
3398 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ?
3399 *
3400 */
3401enum iwm_mac_qos_flags {
3402 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0),
3403 IWM_MAC_QOS_FLG_TGN = (1 << 1),
3404 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4),
3405};
3406
3407/**
3408 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD
3409 * @cw_min: Contention window, start value in numbers of slots.
3410 * Should be a power-of-2, minus 1. Device's default is 0x0f.
3411 * @cw_max: Contention window, max value in numbers of slots.
3412 * Should be a power-of-2, minus 1. Device's default is 0x3f.
3413 * @aifsn: Number of slots in Arbitration Interframe Space (before
3414 * performing random backoff timing prior to Tx). Device default 1.
3415 * @fifos_mask: FIFOs used by this MAC for this AC
3416 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0.
3417 *
3418 * One instance of this config struct for each of 4 EDCA access categories
3419 * in struct iwm_qosparam_cmd.
3420 *
3421 * Device will automatically increase contention window by (2*CW) + 1 for each
3422 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW
3423 * value, to cap the CW value.
3424 */
3425struct iwm_ac_qos {
3426 uint16_t cw_min;
3427 uint16_t cw_max;
3428 uint8_t aifsn;
3429 uint8_t fifos_mask;
3430 uint16_t edca_txop;
3431} __packed; /* IWM_AC_QOS_API_S_VER_2 */
3432
3433/**
3434 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts
3435 * ( IWM_MAC_CONTEXT_CMD = 0x28 )
3436 * @id_and_color: ID and color of the MAC
3437 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
3438 * @mac_type: one of IWM_FW_MAC_TYPE_*
3439 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_*
3440 * @node_addr: MAC address
3441 * @bssid_addr: BSSID
3442 * @cck_rates: basic rates available for CCK
3443 * @ofdm_rates: basic rates available for OFDM
3444 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_*
3445 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise
3446 * @short_slot: 0x10 for enabling short slots, 0 otherwise
3447 * @filter_flags: combination of IWM_MAC_FILTER_*
3448 * @qos_flags: from IWM_MAC_QOS_FLG_*
3449 * @ac: one iwm_mac_qos configuration for each AC
3450 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type
3451 */
3452struct iwm_mac_ctx_cmd {
3453 /* COMMON_INDEX_HDR_API_S_VER_1 */
3454 uint32_t id_and_color;
3455 uint32_t action;
3456 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */
3457 uint32_t mac_type;
3458 uint32_t tsf_id;
3459 uint8_t node_addr[6];
3460 uint16_t reserved_for_node_addr;
3461 uint8_t bssid_addr[6];
3462 uint16_t reserved_for_bssid_addr;
3463 uint32_t cck_rates;
3464 uint32_t ofdm_rates;
3465 uint32_t protection_flags;
3466 uint32_t cck_short_preamble;
3467 uint32_t short_slot;
3468 uint32_t filter_flags;
3469 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */
3470 uint32_t qos_flags;
3471 struct iwm_ac_qos ac[IWM_AC_NUM+1];
3472 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */
3473 union {
3474 struct iwm_mac_data_ap ap;
3475 struct iwm_mac_data_go go;
3476 struct iwm_mac_data_sta sta;
3477 struct iwm_mac_data_p2p_sta p2p_sta;
3478 struct iwm_mac_data_p2p_dev p2p_dev;
3479 struct iwm_mac_data_pibss pibss;
3480 struct iwm_mac_data_ibss ibss;
3481 };
3482} __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */
3483
3484static inline uint32_t iwm_mvm_reciprocal(uint32_t v)
3485{
3486 if (!v)
3487 return 0;
3488 return 0xFFFFFFFF / v;
3489}
3490
3491#define IWM_NONQOS_SEQ_GET 0x1
3492#define IWM_NONQOS_SEQ_SET 0x2
3493struct iwm_nonqos_seq_query_cmd {
3494 uint32_t get_set_flag;
3495 uint32_t mac_id_n_color;
3496 uint16_t value;
3497 uint16_t reserved;
3498} __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */
3499
24a8d46a
MD
3500/* Power Management Commands, Responses, Notifications */
3501
3502/* Radio LP RX Energy Threshold measured in dBm */
3503#define IWM_POWER_LPRX_RSSI_THRESHOLD 75
3504#define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94
3505#define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30
3506
3507/**
3508 * enum iwm_scan_flags - masks for power table command flags
3509 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3510 * receiver and transmitter. '0' - does not allow.
3511 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management,
3512 * '1' Driver enables PM (use rest of parameters)
3513 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM,
3514 * '1' PM could sleep over DTIM till listen Interval.
3515 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all
3516 * access categories are both delivery and trigger enabled.
3517 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and
3518 * PBW Snoozing enabled
3519 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask
3520 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable.
3521 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving
3522 * detection enablement
3523*/
3524enum iwm_power_flags {
3525 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3526 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1),
3527 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2),
3528 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5),
3529 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8),
3530 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9),
3531 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11),
3532 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12),
3533};
3534
3535#define IWM_POWER_VEC_SIZE 5
3536
3537/**
3538 * struct iwm_powertable_cmd - legacy power command. Beside old API support this
3539 * is used also with a new power API for device wide power settings.
3540 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response)
3541 *
3542 * @flags: Power table command flags from IWM_POWER_FLAGS_*
3543 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3544 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3545 * set regardless of power scheme or current power state.
3546 * FW use this value also when PM is disabled.
3547 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3548 * PSM transition - legacy PM
3549 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3550 * PSM transition - legacy PM
3551 * @sleep_interval: not in use
3552 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3553 * is set. For example, if it is required to skip over
3554 * one DTIM, this value need to be set to 2 (DTIM periods).
3555 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3556 * Default: 80dbm
3557 */
3558struct iwm_powertable_cmd {
3559 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3560 uint16_t flags;
3561 uint8_t keep_alive_seconds;
3562 uint8_t debug_flags;
3563 uint32_t rx_data_timeout;
3564 uint32_t tx_data_timeout;
3565 uint32_t sleep_interval[IWM_POWER_VEC_SIZE];
3566 uint32_t skip_dtim_periods;
3567 uint32_t lprx_rssi_threshold;
3568} __packed;
3569
3570/**
3571 * enum iwm_device_power_flags - masks for device power command flags
3572 * @DEVIC_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3573 * receiver and transmitter. '0' - does not allow. This flag should be
3574 * always set to '1' unless one need to disable actual power down for debug
3575 * purposes.
3576 * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: '1' CAM (Continuous Active Mode) is set, meaning
3577 * that power management is disabled. '0' Power management is enabled, one
3578 * of power schemes is applied.
3579*/
3580enum iwm_device_power_flags {
3581 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3582 IWM_DEVICE_POWER_FLAGS_CAM_MSK = (1 << 13),
3583};
3584
3585/**
3586 * struct iwm_device_power_cmd - device wide power command.
3587 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response)
3588 *
3589 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_*
3590 */
3591struct iwm_device_power_cmd {
3592 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3593 uint16_t flags;
3594 uint16_t reserved;
3595} __packed;
3596
3597/**
3598 * struct iwm_mac_power_cmd - New power command containing uAPSD support
3599 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response)
3600 * @id_and_color: MAC contex identifier
3601 * @flags: Power table command flags from POWER_FLAGS_*
3602 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3603 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3604 * set regardless of power scheme or current power state.
3605 * FW use this value also when PM is disabled.
3606 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3607 * PSM transition - legacy PM
3608 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3609 * PSM transition - legacy PM
3610 * @sleep_interval: not in use
3611 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3612 * is set. For example, if it is required to skip over
3613 * one DTIM, this value need to be set to 2 (DTIM periods).
3614 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to
3615 * PSM transition - uAPSD
3616 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to
3617 * PSM transition - uAPSD
3618 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3619 * Default: 80dbm
3620 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set
3621 * @snooze_interval: Maximum time between attempts to retrieve buffered data
3622 * from the AP [msec]
3623 * @snooze_window: A window of time in which PBW snoozing insures that all
3624 * packets received. It is also the minimum time from last
3625 * received unicast RX packet, before client stops snoozing
3626 * for data. [msec]
3627 * @snooze_step: TBD
3628 * @qndp_tid: TID client shall use for uAPSD QNDP triggers
3629 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for
3630 * each corresponding AC.
3631 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values.
3632 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct
3633 * values.
3634 * @heavy_tx_thld_packets: TX threshold measured in number of packets
3635 * @heavy_rx_thld_packets: RX threshold measured in number of packets
3636 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage
3637 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage
3638 * @limited_ps_threshold:
3639*/
3640struct iwm_mac_power_cmd {
3641 /* CONTEXT_DESC_API_T_VER_1 */
3642 uint32_t id_and_color;
3643
3644 /* CLIENT_PM_POWER_TABLE_S_VER_1 */
3645 uint16_t flags;
3646 uint16_t keep_alive_seconds;
3647 uint32_t rx_data_timeout;
3648 uint32_t tx_data_timeout;
3649 uint32_t rx_data_timeout_uapsd;
3650 uint32_t tx_data_timeout_uapsd;
3651 uint8_t lprx_rssi_threshold;
3652 uint8_t skip_dtim_periods;
3653 uint16_t snooze_interval;
3654 uint16_t snooze_window;
3655 uint8_t snooze_step;
3656 uint8_t qndp_tid;
3657 uint8_t uapsd_ac_flags;
3658 uint8_t uapsd_max_sp;
3659 uint8_t heavy_tx_thld_packets;
3660 uint8_t heavy_rx_thld_packets;
3661 uint8_t heavy_tx_thld_percentage;
3662 uint8_t heavy_rx_thld_percentage;
3663 uint8_t limited_ps_threshold;
3664 uint8_t reserved;
3665} __packed;
3666
3667/*
3668 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when
3669 * associated AP is identified as improperly implementing uAPSD protocol.
3670 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78
3671 * @sta_id: index of station in uCode's station table - associated AP ID in
3672 * this context.
3673 */
3674struct iwm_uapsd_misbehaving_ap_notif {
3675 uint32_t sta_id;
3676 uint8_t mac_id;
3677 uint8_t reserved[3];
3678} __packed;
3679
3680/**
3681 * struct iwm_beacon_filter_cmd
3682 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command)
3683 * @id_and_color: MAC contex identifier
3684 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon
3685 * to driver if delta in Energy values calculated for this and last
3686 * passed beacon is greater than this threshold. Zero value means that
3687 * the Energy change is ignored for beacon filtering, and beacon will
3688 * not be forced to be sent to driver regardless of this delta. Typical
3689 * energy delta 5dB.
3690 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state.
3691 * Send beacon to driver if delta in Energy values calculated for this
3692 * and last passed beacon is greater than this threshold. Zero value
3693 * means that the Energy change is ignored for beacon filtering while in
3694 * Roaming state, typical energy delta 1dB.
3695 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values
3696 * calculated for current beacon is less than the threshold, use
3697 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta
3698 * Threshold. Typical energy threshold is -72dBm.
3699 * @bf_temp_threshold: This threshold determines the type of temperature
3700 * filtering (Slow or Fast) that is selected (Units are in Celsuis):
3701 * If the current temperature is above this threshold - Fast filter
3702 * will be used, If the current temperature is below this threshold -
3703 * Slow filter will be used.
3704 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values
3705 * calculated for this and the last passed beacon is greater than this
3706 * threshold. Zero value means that the temperature change is ignored for
3707 * beacon filtering; beacons will not be forced to be sent to driver
77de6c2d 3708 * regardless of whether its temperature has been changed.
24a8d46a
MD
3709 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values
3710 * calculated for this and the last passed beacon is greater than this
3711 * threshold. Zero value means that the temperature change is ignored for
3712 * beacon filtering; beacons will not be forced to be sent to driver
77de6c2d 3713 * regardless of whether its temperature has been changed.
24a8d46a
MD
3714 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled.
3715 * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed
3716 * for a specific period of time. Units: Beacons.
3717 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed
3718 * for a longer period of time then this escape-timeout. Units: Beacons.
3719 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled.
3720 */
3721struct iwm_beacon_filter_cmd {
3722 uint32_t bf_energy_delta;
3723 uint32_t bf_roaming_energy_delta;
3724 uint32_t bf_roaming_state;
3725 uint32_t bf_temp_threshold;
3726 uint32_t bf_temp_fast_filter;
3727 uint32_t bf_temp_slow_filter;
3728 uint32_t bf_enable_beacon_filter;
3729 uint32_t bf_debug_flag;
3730 uint32_t bf_escape_timer;
3731 uint32_t ba_escape_timer;
3732 uint32_t ba_enable_beacon_abort;
3733} __packed;
3734
3735/* Beacon filtering and beacon abort */
3736#define IWM_BF_ENERGY_DELTA_DEFAULT 5
3737#define IWM_BF_ENERGY_DELTA_MAX 255
3738#define IWM_BF_ENERGY_DELTA_MIN 0
3739
3740#define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1
3741#define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255
3742#define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0
3743
3744#define IWM_BF_ROAMING_STATE_DEFAULT 72
3745#define IWM_BF_ROAMING_STATE_MAX 255
3746#define IWM_BF_ROAMING_STATE_MIN 0
3747
3748#define IWM_BF_TEMP_THRESHOLD_DEFAULT 112
3749#define IWM_BF_TEMP_THRESHOLD_MAX 255
3750#define IWM_BF_TEMP_THRESHOLD_MIN 0
3751
3752#define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1
3753#define IWM_BF_TEMP_FAST_FILTER_MAX 255
3754#define IWM_BF_TEMP_FAST_FILTER_MIN 0
3755
3756#define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5
3757#define IWM_BF_TEMP_SLOW_FILTER_MAX 255
3758#define IWM_BF_TEMP_SLOW_FILTER_MIN 0
3759
3760#define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1
3761
3762#define IWM_BF_DEBUG_FLAG_DEFAULT 0
3763
3764#define IWM_BF_ESCAPE_TIMER_DEFAULT 50
3765#define IWM_BF_ESCAPE_TIMER_MAX 1024
3766#define IWM_BF_ESCAPE_TIMER_MIN 0
3767
3768#define IWM_BA_ESCAPE_TIMER_DEFAULT 6
3769#define IWM_BA_ESCAPE_TIMER_D3 9
3770#define IWM_BA_ESCAPE_TIMER_MAX 1024
3771#define IWM_BA_ESCAPE_TIMER_MIN 0
3772
3773#define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1
3774
3775#define IWM_BF_CMD_CONFIG_DEFAULTS \
3776 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \
3777 .bf_roaming_energy_delta = \
3778 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \
3779 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \
3780 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \
3781 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \
3782 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \
3783 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \
3784 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \
3785 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT)
3786
24a8d46a
MD
3787/*
3788 * These serve as indexes into
3789 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT];
3790 * TODO: avoid overlap between legacy and HT rates
3791 */
3792enum {
3793 IWM_RATE_1M_INDEX = 0,
3794 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX,
3795 IWM_RATE_2M_INDEX,
3796 IWM_RATE_5M_INDEX,
3797 IWM_RATE_11M_INDEX,
3798 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX,
3799 IWM_RATE_6M_INDEX,
3800 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX,
3801 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX,
3802 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX,
3803 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX,
3804 IWM_RATE_9M_INDEX,
3805 IWM_RATE_12M_INDEX,
3806 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX,
3807 IWM_RATE_18M_INDEX,
3808 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX,
3809 IWM_RATE_24M_INDEX,
3810 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX,
3811 IWM_RATE_36M_INDEX,
3812 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX,
3813 IWM_RATE_48M_INDEX,
3814 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX,
3815 IWM_RATE_54M_INDEX,
3816 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX,
3817 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX,
3818 IWM_RATE_60M_INDEX,
3819 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX,
3820 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX,
3821 IWM_RATE_MCS_8_INDEX,
3822 IWM_RATE_MCS_9_INDEX,
3823 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX,
3824 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1,
3825 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1,
3826};
3827
3828#define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX))
3829
3830/* fw API values for legacy bit rates, both OFDM and CCK */
3831enum {
3832 IWM_RATE_6M_PLCP = 13,
3833 IWM_RATE_9M_PLCP = 15,
3834 IWM_RATE_12M_PLCP = 5,
3835 IWM_RATE_18M_PLCP = 7,
3836 IWM_RATE_24M_PLCP = 9,
3837 IWM_RATE_36M_PLCP = 11,
3838 IWM_RATE_48M_PLCP = 1,
3839 IWM_RATE_54M_PLCP = 3,
3840 IWM_RATE_1M_PLCP = 10,
3841 IWM_RATE_2M_PLCP = 20,
3842 IWM_RATE_5M_PLCP = 55,
3843 IWM_RATE_11M_PLCP = 110,
3844 IWM_RATE_INVM_PLCP = -1,
3845};
3846
3847/*
3848 * rate_n_flags bit fields
3849 *
3850 * The 32-bit value has different layouts in the low 8 bites depending on the
3851 * format. There are three formats, HT, VHT and legacy (11abg, with subformats
3852 * for CCK and OFDM).
3853 *
3854 * High-throughput (HT) rate format
3855 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM)
3856 * Very High-throughput (VHT) rate format
3857 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM)
3858 * Legacy OFDM rate format for bits 7:0
3859 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM)
3860 * Legacy CCK rate format for bits 7:0:
3861 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK)
3862 */
3863
3864/* Bit 8: (1) HT format, (0) legacy or VHT format */
3865#define IWM_RATE_MCS_HT_POS 8
3866#define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS)
3867
3868/* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */
3869#define IWM_RATE_MCS_CCK_POS 9
3870#define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS)
3871
3872/* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */
3873#define IWM_RATE_MCS_VHT_POS 26
3874#define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS)
3875
3876
3877/*
3878 * High-throughput (HT) rate format for bits 7:0
3879 *
3880 * 2-0: MCS rate base
3881 * 0) 6 Mbps
3882 * 1) 12 Mbps
3883 * 2) 18 Mbps
3884 * 3) 24 Mbps
3885 * 4) 36 Mbps
3886 * 5) 48 Mbps
3887 * 6) 54 Mbps
3888 * 7) 60 Mbps
3889 * 4-3: 0) Single stream (SISO)
3890 * 1) Dual stream (MIMO)
3891 * 2) Triple stream (MIMO)
3892 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
3893 * (bits 7-6 are zero)
3894 *
3895 * Together the low 5 bits work out to the MCS index because we don't
3896 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two
3897 * streams and 16-23 have three streams. We could also support MCS 32
3898 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.)
3899 */
3900#define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7
3901#define IWM_RATE_HT_MCS_NSS_POS 3
3902#define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS)
3903
3904/* Bit 10: (1) Use Green Field preamble */
3905#define IWM_RATE_HT_MCS_GF_POS 10
3906#define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS)
3907
3908#define IWM_RATE_HT_MCS_INDEX_MSK 0x3f
3909
3910/*
3911 * Very High-throughput (VHT) rate format for bits 7:0
3912 *
3913 * 3-0: VHT MCS (0-9)
3914 * 5-4: number of streams - 1:
3915 * 0) Single stream (SISO)
3916 * 1) Dual stream (MIMO)
3917 * 2) Triple stream (MIMO)
3918 */
3919
3920/* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */
3921#define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf
3922#define IWM_RATE_VHT_MCS_NSS_POS 4
3923#define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS)
3924
3925/*
3926 * Legacy OFDM rate format for bits 7:0
3927 *
3928 * 3-0: 0xD) 6 Mbps