Explicitly set error before jumping to fail.
[dragonfly.git] / sys / dev / netif / txp / if_txp.c
CommitLineData
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1/* $OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $ */
2/* $FreeBSD: src/sys/dev/txp/if_txp.c,v 1.4.2.4 2001/12/14 19:50:43 jlemon Exp $ */
402379ab 3/* $DragonFly: src/sys/dev/netif/txp/if_txp.c,v 1.27 2005/06/20 13:49:52 joerg Exp $ */
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4
5/*
6 * Copyright (c) 2001
7 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and
8 * Aaron Campbell <aaron@monkey.org>. All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Jason L. Wright,
21 * Theo de Raadt and Aaron Campbell.
22 * 4. Neither the name of the author nor the names of any co-contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
36 * THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39/*
40 * Driver for 3c990 (Typhoon) Ethernet ASIC
41 */
42
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/sockio.h>
46#include <sys/mbuf.h>
47#include <sys/malloc.h>
48#include <sys/kernel.h>
49#include <sys/socket.h>
9228feed 50#include <sys/thread2.h>
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51
52#include <net/if.h>
871d7209 53#include <net/ifq_var.h>
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54#include <net/if_arp.h>
55#include <net/ethernet.h>
56#include <net/if_dl.h>
57#include <net/if_types.h>
1f2de5d4 58#include <net/vlan/if_vlan_var.h>
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59
60#include <netinet/in.h>
61#include <netinet/in_systm.h>
62#include <netinet/in_var.h>
63#include <netinet/ip.h>
64#include <netinet/if_ether.h>
3f9db7f8 65#include <sys/in_cksum.h>
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66
67#include <net/if_media.h>
68
69#include <net/bpf.h>
70
71#include <vm/vm.h> /* for vtophys */
72#include <vm/pmap.h> /* for vtophys */
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73#include <machine/bus_pio.h>
74#include <machine/bus_memio.h>
75#include <machine/bus.h>
76#include <machine/resource.h>
77#include <sys/bus.h>
78#include <sys/rman.h>
79
1f2de5d4
MD
80#include "../mii_layer/mii.h"
81#include "../mii_layer/miivar.h"
82#include <bus/pci/pcireg.h>
83#include <bus/pci/pcivar.h>
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84
85#define TXP_USEIOSPACE
86#define __STRICT_ALIGNMENT
87
1f2de5d4
MD
88#include "if_txpreg.h"
89#include "3c990img.h"
984263bc 90
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91/*
92 * Various supported device vendors/types and their names.
93 */
94static struct txp_type txp_devs[] = {
95 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_95,
96 "3Com 3cR990-TX-95 Etherlink with 3XP Processor" },
97 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_97,
98 "3Com 3cR990-TX-97 Etherlink with 3XP Processor" },
99 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_TXM,
100 "3Com 3cR990B-TXM Etherlink with 3XP Processor" },
101 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_95,
102 "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" },
103 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_97,
104 "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" },
105 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_SRV,
106 "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" },
107 { 0, 0, NULL }
108};
109
b5101a88
RG
110static int txp_probe (device_t);
111static int txp_attach (device_t);
112static int txp_detach (device_t);
113static void txp_intr (void *);
114static void txp_tick (void *);
115static int txp_shutdown (device_t);
bd4539cc 116static int txp_ioctl (struct ifnet *, u_long, caddr_t, struct ucred *);
b5101a88
RG
117static void txp_start (struct ifnet *);
118static void txp_stop (struct txp_softc *);
119static void txp_init (void *);
120static void txp_watchdog (struct ifnet *);
121
fcb8c909 122static void txp_release_resources (device_t);
b5101a88
RG
123static int txp_chip_init (struct txp_softc *);
124static int txp_reset_adapter (struct txp_softc *);
125static int txp_download_fw (struct txp_softc *);
126static int txp_download_fw_wait (struct txp_softc *);
127static int txp_download_fw_section (struct txp_softc *,
128 struct txp_fw_section_header *, int);
129static int txp_alloc_rings (struct txp_softc *);
130static int txp_rxring_fill (struct txp_softc *);
131static void txp_rxring_empty (struct txp_softc *);
132static void txp_set_filter (struct txp_softc *);
133
134static int txp_cmd_desc_numfree (struct txp_softc *);
135static int txp_command (struct txp_softc *, u_int16_t, u_int16_t, u_int32_t,
136 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int);
137static int txp_command2 (struct txp_softc *, u_int16_t, u_int16_t,
984263bc 138 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t,
b5101a88
RG
139 struct txp_rsp_desc **, int);
140static int txp_response (struct txp_softc *, u_int32_t, u_int16_t, u_int16_t,
141 struct txp_rsp_desc **);
142static void txp_rsp_fixup (struct txp_softc *, struct txp_rsp_desc *,
143 struct txp_rsp_desc *);
144static void txp_capabilities (struct txp_softc *);
145
146static void txp_ifmedia_sts (struct ifnet *, struct ifmediareq *);
147static int txp_ifmedia_upd (struct ifnet *);
984263bc 148#ifdef TXP_DEBUG
b5101a88 149static void txp_show_descriptor (void *);
984263bc 150#endif
b5101a88
RG
151static void txp_tx_reclaim (struct txp_softc *, struct txp_tx_ring *);
152static void txp_rxbuf_reclaim (struct txp_softc *);
153static void txp_rx_reclaim (struct txp_softc *, struct txp_rx_ring *);
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154
155#ifdef TXP_USEIOSPACE
156#define TXP_RES SYS_RES_IOPORT
157#define TXP_RID TXP_PCI_LOIO
158#else
159#define TXP_RES SYS_RES_MEMORY
160#define TXP_RID TXP_PCI_LOMEM
161#endif
162
163static device_method_t txp_methods[] = {
164 /* Device interface */
165 DEVMETHOD(device_probe, txp_probe),
166 DEVMETHOD(device_attach, txp_attach),
167 DEVMETHOD(device_detach, txp_detach),
168 DEVMETHOD(device_shutdown, txp_shutdown),
169 { 0, 0 }
170};
171
172static driver_t txp_driver = {
173 "txp",
174 txp_methods,
175 sizeof(struct txp_softc)
176};
177
178static devclass_t txp_devclass;
179
32832096 180DECLARE_DUMMY_MODULE(if_txp);
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181DRIVER_MODULE(if_txp, pci, txp_driver, txp_devclass, 0, 0);
182
183static int
184txp_probe(dev)
185 device_t dev;
186{
187 struct txp_type *t;
188
189 t = txp_devs;
190
191 while(t->txp_name != NULL) {
192 if ((pci_get_vendor(dev) == t->txp_vid) &&
193 (pci_get_device(dev) == t->txp_did)) {
194 device_set_desc(dev, t->txp_name);
195 return(0);
196 }
197 t++;
198 }
199
200 return(ENXIO);
201}
202
203static int
204txp_attach(dev)
205 device_t dev;
206{
207 struct txp_softc *sc;
208 struct ifnet *ifp;
52bcf561
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209 uint16_t p1;
210 uint32_t p2;
211 uint8_t enaddr[ETHER_ADDR_LEN];
fcb8c909 212 int error = 0, rid;
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213
214 sc = device_get_softc(dev);
9e6fd080 215 callout_init(&sc->txp_stat_timer);
984263bc 216
fcb8c909
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217 ifp = &sc->sc_arpcom.ac_if;
218 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
219
6cc66259 220 pci_enable_busmaster(dev);
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221
222 rid = TXP_RID;
4e6d744d 223 sc->sc_res = bus_alloc_resource_any(dev, TXP_RES, &rid, RF_ACTIVE);
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224
225 if (sc->sc_res == NULL) {
226 device_printf(dev, "couldn't map ports/memory\n");
402379ab 227 return(ENXIO);
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228 }
229
230 sc->sc_bt = rman_get_bustag(sc->sc_res);
231 sc->sc_bh = rman_get_bushandle(sc->sc_res);
232
233 /* Allocate interrupt */
234 rid = 0;
4e6d744d 235 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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236 RF_SHAREABLE | RF_ACTIVE);
237
238 if (sc->sc_irq == NULL) {
239 device_printf(dev, "couldn't map interrupt\n");
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240 error = ENXIO;
241 goto fail;
242 }
243
244 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET,
e9cb6d99 245 txp_intr, sc, &sc->sc_intrhand, NULL);
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246
247 if (error) {
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248 device_printf(dev, "couldn't set up irq\n");
249 goto fail;
250 }
251
252 if (txp_chip_init(sc)) {
402379ab 253 error = ENXIO;
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254 goto fail;
255 }
256
257 sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF,
258 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
259 error = txp_download_fw(sc);
260 contigfree(sc->sc_fwbuf, 32768, M_DEVBUF);
261 sc->sc_fwbuf = NULL;
262
402379ab 263 if (error)
984263bc 264 goto fail;
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265
266 sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF,
267 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
268 bzero(sc->sc_ldata, sizeof(struct txp_ldata));
269
270 if (txp_alloc_rings(sc)) {
402379ab 271 error = ENXIO;
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272 goto fail;
273 }
274
275 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0,
276 NULL, NULL, NULL, 1)) {
402379ab 277 error = ENXIO;
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MD
278 goto fail;
279 }
280
281 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0,
282 &p1, &p2, NULL, 1)) {
402379ab 283 error = ENXIO;
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MD
284 goto fail;
285 }
286
287 txp_set_filter(sc);
288
52bcf561
JS
289 enaddr[0] = ((uint8_t *)&p1)[1];
290 enaddr[1] = ((uint8_t *)&p1)[0];
291 enaddr[2] = ((uint8_t *)&p2)[3];
292 enaddr[3] = ((uint8_t *)&p2)[2];
293 enaddr[4] = ((uint8_t *)&p2)[1];
294 enaddr[5] = ((uint8_t *)&p2)[0];
984263bc 295
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MD
296 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts);
297 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
298 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
299 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
300 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
301 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
302 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
303 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
304
305 sc->sc_xcvr = TXP_XCVR_AUTO;
306 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0,
307 NULL, NULL, NULL, 0);
308 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO);
309
984263bc 310 ifp->if_softc = sc;
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311 ifp->if_mtu = ETHERMTU;
312 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
313 ifp->if_ioctl = txp_ioctl;
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314 ifp->if_start = txp_start;
315 ifp->if_watchdog = txp_watchdog;
316 ifp->if_init = txp_init;
317 ifp->if_baudrate = 100000000;
871d7209
JS
318 ifq_set_maxlen(&ifp->if_snd, TX_ENTRIES);
319 ifq_set_ready(&ifp->if_snd);
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320 ifp->if_hwassist = 0;
321 txp_capabilities(sc);
322
323 /*
324 * Attach us everywhere
325 */
52bcf561 326 ether_ifattach(ifp, enaddr);
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327 return(0);
328
329fail:
fcb8c909 330 txp_release_resources(dev);
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331 return(error);
332}
333
334static int
335txp_detach(dev)
336 device_t dev;
337{
338 struct txp_softc *sc;
339 struct ifnet *ifp;
340 int i;
341
342 sc = device_get_softc(dev);
343 ifp = &sc->sc_arpcom.ac_if;
344
345 txp_stop(sc);
346 txp_shutdown(dev);
347
348 ifmedia_removeall(&sc->sc_ifmedia);
0a8b5977 349 ether_ifdetach(ifp);
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350
351 for (i = 0; i < RXBUF_ENTRIES; i++)
352 free(sc->sc_rxbufs[i].rb_sd, M_DEVBUF);
353
fcb8c909 354 txp_release_resources(dev);
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355
356 return(0);
357}
358
359static void
fcb8c909 360txp_release_resources(device_t dev)
984263bc 361{
fcb8c909 362 struct txp_softc *sc;
984263bc 363
fcb8c909 364 sc = device_get_softc(dev);
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MD
365
366 if (sc->sc_intrhand != NULL)
367 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
368
369 if (sc->sc_irq != NULL)
370 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
371
372 if (sc->sc_res != NULL)
373 bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res);
374
375 if (sc->sc_ldata != NULL)
376 contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF);
377
378 return;
379}
380
381static int
382txp_chip_init(sc)
383 struct txp_softc *sc;
384{
385 /* disable interrupts */
386 WRITE_REG(sc, TXP_IER, 0);
387 WRITE_REG(sc, TXP_IMR,
388 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
389 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
390 TXP_INT_LATCH);
391
392 /* ack all interrupts */
393 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
394 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
395 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
396 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
397 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0);
398
399 if (txp_reset_adapter(sc))
400 return (-1);
401
402 /* disable interrupts */
403 WRITE_REG(sc, TXP_IER, 0);
404 WRITE_REG(sc, TXP_IMR,
405 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
406 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
407 TXP_INT_LATCH);
408
409 /* ack all interrupts */
410 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
411 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
412 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
413 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
414 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0);
415
416 return (0);
417}
418
419static int
420txp_reset_adapter(sc)
421 struct txp_softc *sc;
422{
423 u_int32_t r;
424 int i;
425
426 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL);
427 DELAY(1000);
428 WRITE_REG(sc, TXP_SRR, 0);
429
430 /* Should wait max 6 seconds */
431 for (i = 0; i < 6000; i++) {
432 r = READ_REG(sc, TXP_A2H_0);
433 if (r == STAT_WAITING_FOR_HOST_REQUEST)
434 break;
435 DELAY(1000);
436 }
437
438 if (r != STAT_WAITING_FOR_HOST_REQUEST) {
fcb8c909 439 if_printf(&sc->sc_arpcom.ac_if, "reset hung\n");
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440 return (-1);
441 }
442
443 return (0);
444}
445
446static int
447txp_download_fw(sc)
448 struct txp_softc *sc;
449{
450 struct txp_fw_file_header *fileheader;
451 struct txp_fw_section_header *secthead;
452 int sect;
453 u_int32_t r, i, ier, imr;
454
455 ier = READ_REG(sc, TXP_IER);
456 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0);
457
458 imr = READ_REG(sc, TXP_IMR);
459 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0);
460
461 for (i = 0; i < 10000; i++) {
462 r = READ_REG(sc, TXP_A2H_0);
463 if (r == STAT_WAITING_FOR_HOST_REQUEST)
464 break;
465 DELAY(50);
466 }
467 if (r != STAT_WAITING_FOR_HOST_REQUEST) {
fcb8c909
JS
468 if_printf(&sc->sc_arpcom.ac_if,
469 "not waiting for host request\n");
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470 return (-1);
471 }
472
473 /* Ack the status */
474 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
475
476 fileheader = (struct txp_fw_file_header *)tc990image;
477 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) {
fcb8c909 478 if_printf(&sc->sc_arpcom.ac_if, "fw invalid magic\n");
984263bc
MD
479 return (-1);
480 }
481
482 /* Tell boot firmware to get ready for image */
483 WRITE_REG(sc, TXP_H2A_1, fileheader->addr);
484 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE);
485
486 if (txp_download_fw_wait(sc)) {
fcb8c909 487 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed, initial\n");
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MD
488 return (-1);
489 }
490
491 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) +
492 sizeof(struct txp_fw_file_header));
493
494 for (sect = 0; sect < fileheader->nsections; sect++) {
495 if (txp_download_fw_section(sc, secthead, sect))
496 return (-1);
497 secthead = (struct txp_fw_section_header *)
498 (((u_int8_t *)secthead) + secthead->nbytes +
499 sizeof(*secthead));
500 }
501
502 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE);
503
504 for (i = 0; i < 10000; i++) {
505 r = READ_REG(sc, TXP_A2H_0);
506 if (r == STAT_WAITING_FOR_BOOT)
507 break;
508 DELAY(50);
509 }
510 if (r != STAT_WAITING_FOR_BOOT) {
fcb8c909 511 if_printf(&sc->sc_arpcom.ac_if, "not waiting for boot\n");
984263bc
MD
512 return (-1);
513 }
514
515 WRITE_REG(sc, TXP_IER, ier);
516 WRITE_REG(sc, TXP_IMR, imr);
517
518 return (0);
519}
520
521static int
522txp_download_fw_wait(sc)
523 struct txp_softc *sc;
524{
525 u_int32_t i, r;
526
527 for (i = 0; i < 10000; i++) {
528 r = READ_REG(sc, TXP_ISR);
529 if (r & TXP_INT_A2H_0)
530 break;
531 DELAY(50);
532 }
533
534 if (!(r & TXP_INT_A2H_0)) {
fcb8c909 535 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed comm0\n");
984263bc
MD
536 return (-1);
537 }
538
539 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
540
541 r = READ_REG(sc, TXP_A2H_0);
542 if (r != STAT_WAITING_FOR_SEGMENT) {
fcb8c909 543 if_printf(&sc->sc_arpcom.ac_if, "fw not waiting for segment\n");
984263bc
MD
544 return (-1);
545 }
546 return (0);
547}
548
549static int
550txp_download_fw_section(sc, sect, sectnum)
551 struct txp_softc *sc;
552 struct txp_fw_section_header *sect;
553 int sectnum;
554{
555 vm_offset_t dma;
556 int rseg, err = 0;
557 struct mbuf m;
558 u_int16_t csum;
559
560 /* Skip zero length sections */
561 if (sect->nbytes == 0)
562 return (0);
563
564 /* Make sure we aren't past the end of the image */
565 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image);
566 if (rseg >= sizeof(tc990image)) {
fcb8c909 567 if_printf(&sc->sc_arpcom.ac_if, "fw invalid section address, "
984263bc
MD
568 "section %d\n", sectnum);
569 return (-1);
570 }
571
572 /* Make sure this section doesn't go past the end */
573 rseg += sect->nbytes;
574 if (rseg >= sizeof(tc990image)) {
fcb8c909 575 if_printf(&sc->sc_arpcom.ac_if, "fw truncated section %d\n",
984263bc
MD
576 sectnum);
577 return (-1);
578 }
579
580 bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes);
581 dma = vtophys(sc->sc_fwbuf);
582
583 /*
584 * dummy up mbuf and verify section checksum
585 */
586 m.m_type = MT_DATA;
587 m.m_next = m.m_nextpkt = NULL;
588 m.m_len = sect->nbytes;
589 m.m_data = sc->sc_fwbuf;
590 m.m_flags = 0;
591 csum = in_cksum(&m, sect->nbytes);
592 if (csum != sect->cksum) {
fcb8c909 593 if_printf(&sc->sc_arpcom.ac_if, "fw section %d, bad "
984263bc
MD
594 "cksum (expected 0x%x got 0x%x)\n",
595 sectnum, sect->cksum, csum);
596 err = -1;
597 goto bail;
598 }
599
600 WRITE_REG(sc, TXP_H2A_1, sect->nbytes);
601 WRITE_REG(sc, TXP_H2A_2, sect->cksum);
602 WRITE_REG(sc, TXP_H2A_3, sect->addr);
603 WRITE_REG(sc, TXP_H2A_4, 0);
604 WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff);
605 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE);
606
607 if (txp_download_fw_wait(sc)) {
fcb8c909 608 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed, "
984263bc
MD
609 "section %d\n", sectnum);
610 err = -1;
611 }
612
613bail:
614 return (err);
615}
616
617static void
618txp_intr(vsc)
619 void *vsc;
620{
621 struct txp_softc *sc = vsc;
622 struct txp_hostvar *hv = sc->sc_hostvar;
623 u_int32_t isr;
624
625 /* mask all interrupts */
626 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF |
627 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
628 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 |
629 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
630 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH);
631
632 isr = READ_REG(sc, TXP_ISR);
633 while (isr) {
634 WRITE_REG(sc, TXP_ISR, isr);
635
636 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff))
637 txp_rx_reclaim(sc, &sc->sc_rxhir);
638 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff))
639 txp_rx_reclaim(sc, &sc->sc_rxlor);
640
641 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx)
642 txp_rxbuf_reclaim(sc);
643
644 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons !=
645 TXP_OFFSET2IDX(*(sc->sc_txhir.r_off))))
646 txp_tx_reclaim(sc, &sc->sc_txhir);
647
648 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons !=
649 TXP_OFFSET2IDX(*(sc->sc_txlor.r_off))))
650 txp_tx_reclaim(sc, &sc->sc_txlor);
651
652 isr = READ_REG(sc, TXP_ISR);
653 }
654
655 /* unmask all interrupts */
656 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3);
657
658 txp_start(&sc->sc_arpcom.ac_if);
659
660 return;
661}
662
663static void
664txp_rx_reclaim(sc, r)
665 struct txp_softc *sc;
666 struct txp_rx_ring *r;
667{
668 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
669 struct txp_rx_desc *rxd;
670 struct mbuf *m;
671 struct txp_swdesc *sd = NULL;
672 u_int32_t roff, woff;
984263bc
MD
673
674 roff = *r->r_roff;
675 woff = *r->r_woff;
676 rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc));
677
678 while (roff != woff) {
679
680 if (rxd->rx_flags & RX_FLAGS_ERROR) {
fcb8c909 681 if_printf(ifp, "error 0x%x\n", rxd->rx_stat);
984263bc
MD
682 ifp->if_ierrors++;
683 goto next;
684 }
685
686 /* retrieve stashed pointer */
687 sd = rxd->rx_sd;
688
689 m = sd->sd_mbuf;
690 sd->sd_mbuf = NULL;
691
692 m->m_pkthdr.len = m->m_len = rxd->rx_len;
693
694#ifdef __STRICT_ALIGNMENT
695 {
696 /*
697 * XXX Nice chip, except it won't accept "off by 2"
698 * buffers, so we're force to copy. Supposedly
699 * this will be fixed in a newer firmware rev
700 * and this will be temporary.
701 */
702 struct mbuf *mnew;
703
74f1caca 704 MGETHDR(mnew, MB_DONTWAIT, MT_DATA);
984263bc
MD
705 if (mnew == NULL) {
706 m_freem(m);
707 goto next;
708 }
709 if (m->m_len > (MHLEN - 2)) {
74f1caca 710 MCLGET(mnew, MB_DONTWAIT);
984263bc
MD
711 if (!(mnew->m_flags & M_EXT)) {
712 m_freem(mnew);
713 m_freem(m);
714 goto next;
715 }
716 }
717 mnew->m_pkthdr.rcvif = ifp;
718 m_adj(mnew, 2);
719 mnew->m_pkthdr.len = mnew->m_len = m->m_len;
720 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t));
721 m_freem(m);
722 m = mnew;
723 }
724#endif
725
726 if (rxd->rx_stat & RX_STAT_IPCKSUMBAD)
727 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
728 else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD)
729 m->m_pkthdr.csum_flags |=
730 CSUM_IP_CHECKED|CSUM_IP_VALID;
731
732 if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) ||
733 (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) {
734 m->m_pkthdr.csum_flags |=
735 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
736 m->m_pkthdr.csum_data = 0xffff;
737 }
738
3013ac0e
JS
739 if (rxd->rx_stat & RX_STAT_VLAN)
740 VLAN_INPUT_TAG(m, htons(rxd->rx_vlan >> 16));
741 else
742 (*ifp->if_input)(ifp, m);
984263bc
MD
743
744next:
745
746 roff += sizeof(struct txp_rx_desc);
747 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) {
748 roff = 0;
749 rxd = r->r_desc;
750 } else
751 rxd++;
752 woff = *r->r_woff;
753 }
754
755 *r->r_roff = woff;
756
757 return;
758}
759
760static void
761txp_rxbuf_reclaim(sc)
762 struct txp_softc *sc;
763{
764 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
765 struct txp_hostvar *hv = sc->sc_hostvar;
766 struct txp_rxbuf_desc *rbd;
767 struct txp_swdesc *sd;
768 u_int32_t i;
769
770 if (!(ifp->if_flags & IFF_RUNNING))
771 return;
772
773 i = sc->sc_rxbufprod;
774 rbd = sc->sc_rxbufs + i;
775
776 while (1) {
777 sd = rbd->rb_sd;
778 if (sd->sd_mbuf != NULL)
779 break;
780
74f1caca 781 MGETHDR(sd->sd_mbuf, MB_DONTWAIT, MT_DATA);
984263bc
MD
782 if (sd->sd_mbuf == NULL)
783 goto err_sd;
784
74f1caca 785 MCLGET(sd->sd_mbuf, MB_DONTWAIT);
984263bc
MD
786 if ((sd->sd_mbuf->m_flags & M_EXT) == 0)
787 goto err_mbuf;
788 sd->sd_mbuf->m_pkthdr.rcvif = ifp;
789 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES;
790
791 rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t))
792 & 0xffffffff;
793 rbd->rb_paddrhi = 0;
794
795 hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i);
796
797 if (++i == RXBUF_ENTRIES) {
798 i = 0;
799 rbd = sc->sc_rxbufs;
800 } else
801 rbd++;
802 }
803
804 sc->sc_rxbufprod = i;
805
806 return;
807
808err_mbuf:
809 m_freem(sd->sd_mbuf);
810err_sd:
811 free(sd, M_DEVBUF);
812}
813
814/*
815 * Reclaim mbufs and entries from a transmit ring.
816 */
817static void
818txp_tx_reclaim(sc, r)
819 struct txp_softc *sc;
820 struct txp_tx_ring *r;
821{
822 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
823 u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off));
824 u_int32_t cons = r->r_cons, cnt = r->r_cnt;
825 struct txp_tx_desc *txd = r->r_desc + cons;
826 struct txp_swdesc *sd = sc->sc_txd + cons;
827 struct mbuf *m;
828
829 while (cons != idx) {
830 if (cnt == 0)
831 break;
832
833 if ((txd->tx_flags & TX_FLAGS_TYPE_M) ==
834 TX_FLAGS_TYPE_DATA) {
835 m = sd->sd_mbuf;
836 if (m != NULL) {
837 m_freem(m);
838 txd->tx_addrlo = 0;
839 txd->tx_addrhi = 0;
840 ifp->if_opackets++;
841 }
842 }
843 ifp->if_flags &= ~IFF_OACTIVE;
844
845 if (++cons == TX_ENTRIES) {
846 txd = r->r_desc;
847 cons = 0;
848 sd = sc->sc_txd;
849 } else {
850 txd++;
851 sd++;
852 }
853
854 cnt--;
855 }
856
857 r->r_cons = cons;
858 r->r_cnt = cnt;
859 if (cnt == 0)
860 ifp->if_timer = 0;
861}
862
863static int
864txp_shutdown(dev)
865 device_t dev;
866{
867 struct txp_softc *sc;
868
869 sc = device_get_softc(dev);
870
871 /* mask all interrupts */
872 WRITE_REG(sc, TXP_IMR,
873 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
874 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
875 TXP_INT_LATCH);
876
877 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0);
878 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0);
879 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0);
880
881 return(0);
882}
883
884static int
885txp_alloc_rings(sc)
886 struct txp_softc *sc;
887{
888 struct txp_boot_record *boot;
889 struct txp_ldata *ld;
890 u_int32_t r;
891 int i;
892
893 ld = sc->sc_ldata;
894 boot = &ld->txp_boot;
895
896 /* boot record */
897 sc->sc_boot = boot;
898
899 /* host variables */
900 bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar));
901 boot->br_hostvar_lo = vtophys(&ld->txp_hostvar);
902 boot->br_hostvar_hi = 0;
903 sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar;
904
905 /* hi priority tx ring */
906 boot->br_txhipri_lo = vtophys(&ld->txp_txhiring);;
907 boot->br_txhipri_hi = 0;
908 boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc);
909 sc->sc_txhir.r_reg = TXP_H2A_1;
910 sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring;
911 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0;
912 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx;
913
914 /* lo priority tx ring */
915 boot->br_txlopri_lo = vtophys(&ld->txp_txloring);
916 boot->br_txlopri_hi = 0;
917 boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc);
918 sc->sc_txlor.r_reg = TXP_H2A_3;
919 sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring;
920 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0;
921 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx;
922
923 /* high priority rx ring */
924 boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring);
925 boot->br_rxhipri_hi = 0;
926 boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc);
927 sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring;
928 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx;
929 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx;
930
931 /* low priority rx ring */
932 boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring);
933 boot->br_rxlopri_hi = 0;
934 boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc);
935 sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring;
936 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx;
937 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx;
938
939 /* command ring */
940 bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES);
941 boot->br_cmd_lo = vtophys(&ld->txp_cmdring);
942 boot->br_cmd_hi = 0;
943 boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc);
944 sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring;
945 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc);
946 sc->sc_cmdring.lastwrite = 0;
947
948 /* response ring */
949 bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES);
950 boot->br_resp_lo = vtophys(&ld->txp_rspring);
951 boot->br_resp_hi = 0;
952 boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc);
953 sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring;
954 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc);
955 sc->sc_rspring.lastwrite = 0;
956
957 /* receive buffer ring */
958 boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs);
959 boot->br_rxbuf_hi = 0;
960 boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc);
961 sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs;
962
963 for (i = 0; i < RXBUF_ENTRIES; i++) {
964 struct txp_swdesc *sd;
965 if (sc->sc_rxbufs[i].rb_sd != NULL)
966 continue;
967 sc->sc_rxbufs[i].rb_sd = malloc(sizeof(struct txp_swdesc),
c5541aee 968 M_DEVBUF, M_WAITOK);
984263bc
MD
969 if (sc->sc_rxbufs[i].rb_sd == NULL)
970 return(ENOBUFS);
971 sd = sc->sc_rxbufs[i].rb_sd;
972 sd->sd_mbuf = NULL;
973 }
974 sc->sc_rxbufprod = 0;
975
976 /* zero dma */
977 bzero(&ld->txp_zero, sizeof(u_int32_t));
978 boot->br_zero_lo = vtophys(&ld->txp_zero);
979 boot->br_zero_hi = 0;
980
981 /* See if it's waiting for boot, and try to boot it */
982 for (i = 0; i < 10000; i++) {
983 r = READ_REG(sc, TXP_A2H_0);
984 if (r == STAT_WAITING_FOR_BOOT)
985 break;
986 DELAY(50);
987 }
988
989 if (r != STAT_WAITING_FOR_BOOT) {
fcb8c909 990 if_printf(&sc->sc_arpcom.ac_if, "not waiting for boot\n");
984263bc
MD
991 return(ENXIO);
992 }
993
994 WRITE_REG(sc, TXP_H2A_2, 0);
995 WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot));
996 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD);
997
998 /* See if it booted */
999 for (i = 0; i < 10000; i++) {
1000 r = READ_REG(sc, TXP_A2H_0);
1001 if (r == STAT_RUNNING)
1002 break;
1003 DELAY(50);
1004 }
1005 if (r != STAT_RUNNING) {
fcb8c909 1006 if_printf(&sc->sc_arpcom.ac_if, "fw not running\n");
984263bc
MD
1007 return(ENXIO);
1008 }
1009
1010 /* Clear TX and CMD ring write registers */
1011 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL);
1012 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL);
1013 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL);
1014 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL);
1015
1016 return (0);
1017}
1018
1019static int
bd4539cc 1020txp_ioctl(ifp, command, data, cr)
984263bc
MD
1021 struct ifnet *ifp;
1022 u_long command;
1023 caddr_t data;
bd4539cc 1024 struct ucred *cr;
984263bc
MD
1025{
1026 struct txp_softc *sc = ifp->if_softc;
1027 struct ifreq *ifr = (struct ifreq *)data;
9228feed 1028 int error = 0;
984263bc 1029
9228feed 1030 crit_enter();
984263bc 1031
984263bc 1032 switch(command) {
984263bc
MD
1033 case SIOCSIFFLAGS:
1034 if (ifp->if_flags & IFF_UP) {
1035 txp_init(sc);
1036 } else {
1037 if (ifp->if_flags & IFF_RUNNING)
1038 txp_stop(sc);
1039 }
1040 break;
1041 case SIOCADDMULTI:
1042 case SIOCDELMULTI:
1043 /*
1044 * Multicast list has changed; set the hardware
1045 * filter accordingly.
1046 */
1047 txp_set_filter(sc);
1048 error = 0;
1049 break;
1050 case SIOCGIFMEDIA:
1051 case SIOCSIFMEDIA:
1052 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command);
1053 break;
1054 default:
417b83e4 1055 error = ether_ioctl(ifp, command, data);
984263bc
MD
1056 break;
1057 }
1058
9228feed 1059 crit_exit();
984263bc
MD
1060
1061 return(error);
1062}
1063
1064static int
1065txp_rxring_fill(sc)
1066 struct txp_softc *sc;
1067{
1068 int i;
1069 struct ifnet *ifp;
1070 struct txp_swdesc *sd;
1071
1072 ifp = &sc->sc_arpcom.ac_if;
1073
1074 for (i = 0; i < RXBUF_ENTRIES; i++) {
1075 sd = sc->sc_rxbufs[i].rb_sd;
74f1caca 1076 MGETHDR(sd->sd_mbuf, MB_DONTWAIT, MT_DATA);
984263bc
MD
1077 if (sd->sd_mbuf == NULL)
1078 return(ENOBUFS);
1079
74f1caca 1080 MCLGET(sd->sd_mbuf, MB_DONTWAIT);
984263bc
MD
1081 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) {
1082 m_freem(sd->sd_mbuf);
1083 return(ENOBUFS);
1084 }
1085 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES;
1086 sd->sd_mbuf->m_pkthdr.rcvif = ifp;
1087
1088 sc->sc_rxbufs[i].rb_paddrlo =
1089 vtophys(mtod(sd->sd_mbuf, vm_offset_t));
1090 sc->sc_rxbufs[i].rb_paddrhi = 0;
1091 }
1092
1093 sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) *
1094 sizeof(struct txp_rxbuf_desc);
1095
1096 return(0);
1097}
1098
1099static void
1100txp_rxring_empty(sc)
1101 struct txp_softc *sc;
1102{
1103 int i;
1104 struct txp_swdesc *sd;
1105
1106 if (sc->sc_rxbufs == NULL)
1107 return;
1108
1109 for (i = 0; i < RXBUF_ENTRIES; i++) {
1110 if (&sc->sc_rxbufs[i] == NULL)
1111 continue;
1112 sd = sc->sc_rxbufs[i].rb_sd;
1113 if (sd == NULL)
1114 continue;
1115 if (sd->sd_mbuf != NULL) {
1116 m_freem(sd->sd_mbuf);
1117 sd->sd_mbuf = NULL;
1118 }
1119 }
1120
1121 return;
1122}
1123
1124static void
1125txp_init(xsc)
1126 void *xsc;
1127{
1128 struct txp_softc *sc;
1129 struct ifnet *ifp;
1130 u_int16_t p1;
1131 u_int32_t p2;
984263bc
MD
1132
1133 sc = xsc;
1134 ifp = &sc->sc_arpcom.ac_if;
1135
1136 if (ifp->if_flags & IFF_RUNNING)
1137 return;
1138
1139 txp_stop(sc);
1140
9228feed 1141 crit_enter();
984263bc
MD
1142
1143 txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0,
1144 NULL, NULL, NULL, 1);
1145
1146 /* Set station address. */
1147 ((u_int8_t *)&p1)[1] = sc->sc_arpcom.ac_enaddr[0];
1148 ((u_int8_t *)&p1)[0] = sc->sc_arpcom.ac_enaddr[1];
1149 ((u_int8_t *)&p2)[3] = sc->sc_arpcom.ac_enaddr[2];
1150 ((u_int8_t *)&p2)[2] = sc->sc_arpcom.ac_enaddr[3];
1151 ((u_int8_t *)&p2)[1] = sc->sc_arpcom.ac_enaddr[4];
1152 ((u_int8_t *)&p2)[0] = sc->sc_arpcom.ac_enaddr[5];
1153 txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0,
1154 NULL, NULL, NULL, 1);
1155
1156 txp_set_filter(sc);
1157
1158 txp_rxring_fill(sc);
1159
1160 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1161 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1162
1163 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF |
1164 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
1165 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 |
1166 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
1167 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH);
1168 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3);
1169
1170 ifp->if_flags |= IFF_RUNNING;
1171 ifp->if_flags &= ~IFF_OACTIVE;
1172 ifp->if_timer = 0;
1173
9e6fd080 1174 callout_reset(&sc->txp_stat_timer, hz, txp_tick, sc);
984263bc 1175
9228feed 1176 crit_exit();
984263bc
MD
1177}
1178
1179static void
1180txp_tick(vsc)
1181 void *vsc;
1182{
1183 struct txp_softc *sc = vsc;
1184 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1185 struct txp_rsp_desc *rsp = NULL;
1186 struct txp_ext_desc *ext;
984263bc 1187
9228feed 1188 crit_enter();
984263bc
MD
1189 txp_rxbuf_reclaim(sc);
1190
1191 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0,
1192 &rsp, 1))
1193 goto out;
1194 if (rsp->rsp_numdesc != 6)
1195 goto out;
1196 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0,
1197 NULL, NULL, NULL, 1))
1198 goto out;
1199 ext = (struct txp_ext_desc *)(rsp + 1);
1200
1201 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 +
1202 ext[4].ext_1 + ext[4].ext_4;
1203 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 +
1204 ext[2].ext_1;
1205 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 +
1206 ext[1].ext_3;
1207 ifp->if_opackets += rsp->rsp_par2;
1208 ifp->if_ipackets += ext[2].ext_3;
1209
1210out:
1211 if (rsp != NULL)
1212 free(rsp, M_DEVBUF);
1213
9e6fd080 1214 callout_reset(&sc->txp_stat_timer, hz, txp_tick, sc);
7113465f 1215 crit_exit();
984263bc
MD
1216}
1217
1218static void
1219txp_start(ifp)
1220 struct ifnet *ifp;
1221{
1222 struct txp_softc *sc = ifp->if_softc;
1223 struct txp_tx_ring *r = &sc->sc_txhir;
1224 struct txp_tx_desc *txd;
1225 struct txp_frag_desc *fxd;
1226 struct mbuf *m, *m0;
1227 struct txp_swdesc *sd;
1228 u_int32_t firstprod, firstcnt, prod, cnt;
1229 struct ifvlan *ifv;
1230
1231 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1232 return;
1233
1234 prod = r->r_prod;
1235 cnt = r->r_cnt;
1236
1237 while (1) {
871d7209 1238 m = ifq_poll(&ifp->if_snd);
984263bc
MD
1239 if (m == NULL)
1240 break;
1241
1242 firstprod = prod;
1243 firstcnt = cnt;
1244
1245 sd = sc->sc_txd + prod;
1246 sd->sd_mbuf = m;
1247
1248 if ((TX_ENTRIES - cnt) < 4)
1249 goto oactive;
1250
1251 txd = r->r_desc + prod;
1252
1253 txd->tx_flags = TX_FLAGS_TYPE_DATA;
1254 txd->tx_numdesc = 0;
1255 txd->tx_addrlo = 0;
1256 txd->tx_addrhi = 0;
1257 txd->tx_totlen = 0;
1258 txd->tx_pflags = 0;
1259
1260 if (++prod == TX_ENTRIES)
1261 prod = 0;
1262
1263 if (++cnt >= (TX_ENTRIES - 4))
1264 goto oactive;
1265
1266 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1267 m->m_pkthdr.rcvif != NULL) {
1268 ifv = m->m_pkthdr.rcvif->if_softc;
1269 txd->tx_pflags = TX_PFLAGS_VLAN |
1270 (htons(ifv->ifv_tag) << TX_PFLAGS_VLANTAG_S);
1271 }
1272
1273 if (m->m_pkthdr.csum_flags & CSUM_IP)
1274 txd->tx_pflags |= TX_PFLAGS_IPCKSUM;
1275
1276#if 0
1277 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1278 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM;
1279 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1280 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM;
1281#endif
1282
1283 fxd = (struct txp_frag_desc *)(r->r_desc + prod);
1284 for (m0 = m; m0 != NULL; m0 = m0->m_next) {
1285 if (m0->m_len == 0)
1286 continue;
1287 if (++cnt >= (TX_ENTRIES - 4))
1288 goto oactive;
1289
1290 txd->tx_numdesc++;
1291
1292 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG;
1293 fxd->frag_rsvd1 = 0;
1294 fxd->frag_len = m0->m_len;
1295 fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t));
1296 fxd->frag_addrhi = 0;
1297 fxd->frag_rsvd2 = 0;
1298
1299 if (++prod == TX_ENTRIES) {
1300 fxd = (struct txp_frag_desc *)r->r_desc;
1301 prod = 0;
1302 } else
1303 fxd++;
1304
1305 }
1306
1307 ifp->if_timer = 5;
1308
871d7209 1309 m = ifq_dequeue(&ifp->if_snd);
7600679e 1310 BPF_MTAP(ifp, m);
984263bc
MD
1311 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod));
1312 }
1313
1314 r->r_prod = prod;
1315 r->r_cnt = cnt;
1316 return;
1317
1318oactive:
1319 ifp->if_flags |= IFF_OACTIVE;
1320 r->r_prod = firstprod;
1321 r->r_cnt = firstcnt;
984263bc
MD
1322 return;
1323}
1324
1325/*
1326 * Handle simple commands sent to the typhoon
1327 */
1328static int
1329txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait)
1330 struct txp_softc *sc;
1331 u_int16_t id, in1, *out1;
1332 u_int32_t in2, in3, *out2, *out3;
1333 int wait;
1334{
1335 struct txp_rsp_desc *rsp = NULL;
1336
1337 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait))
1338 return (-1);
1339
1340 if (!wait)
1341 return (0);
1342
1343 if (out1 != NULL)
1344 *out1 = rsp->rsp_par1;
1345 if (out2 != NULL)
1346 *out2 = rsp->rsp_par2;
1347 if (out3 != NULL)
1348 *out3 = rsp->rsp_par3;
1349 free(rsp, M_DEVBUF);
1350 return (0);
1351}
1352
1353static int
1354txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait)
1355 struct txp_softc *sc;
1356 u_int16_t id, in1;
1357 u_int32_t in2, in3;
1358 struct txp_ext_desc *in_extp;
1359 u_int8_t in_extn;
1360 struct txp_rsp_desc **rspp;
1361 int wait;
1362{
1363 struct txp_hostvar *hv = sc->sc_hostvar;
1364 struct txp_cmd_desc *cmd;
1365 struct txp_ext_desc *ext;
1366 u_int32_t idx, i;
1367 u_int16_t seq;
1368
1369 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) {
fcb8c909 1370 if_printf(&sc->sc_arpcom.ac_if, "no free cmd descriptors\n");
984263bc
MD
1371 return (-1);
1372 }
1373
1374 idx = sc->sc_cmdring.lastwrite;
1375 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx);
1376 bzero(cmd, sizeof(*cmd));
1377
1378 cmd->cmd_numdesc = in_extn;
1379 cmd->cmd_seq = seq = sc->sc_seq++;
1380 cmd->cmd_id = id;
1381 cmd->cmd_par1 = in1;
1382 cmd->cmd_par2 = in2;
1383 cmd->cmd_par3 = in3;
1384 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD |
1385 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID;
1386
1387 idx += sizeof(struct txp_cmd_desc);
1388 if (idx == sc->sc_cmdring.size)
1389 idx = 0;
1390
1391 for (i = 0; i < in_extn; i++) {
1392 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx);
1393 bcopy(in_extp, ext, sizeof(struct txp_ext_desc));
1394 in_extp++;
1395 idx += sizeof(struct txp_cmd_desc);
1396 if (idx == sc->sc_cmdring.size)
1397 idx = 0;
1398 }
1399
1400 sc->sc_cmdring.lastwrite = idx;
1401
1402 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite);
1403
1404 if (!wait)
1405 return (0);
1406
1407 for (i = 0; i < 10000; i++) {
1408 idx = hv->hv_resp_read_idx;
1409 if (idx != hv->hv_resp_write_idx) {
1410 *rspp = NULL;
1411 if (txp_response(sc, idx, id, seq, rspp))
1412 return (-1);
1413 if (*rspp != NULL)
1414 break;
1415 }
1416 DELAY(50);
1417 }
1418 if (i == 1000 || (*rspp) == NULL) {
fcb8c909 1419 if_printf(&sc->sc_arpcom.ac_if, "0x%x command failed\n", id);
984263bc
MD
1420 return (-1);
1421 }
1422
1423 return (0);
1424}
1425
1426static int
1427txp_response(sc, ridx, id, seq, rspp)
1428 struct txp_softc *sc;
1429 u_int32_t ridx;
1430 u_int16_t id;
1431 u_int16_t seq;
1432 struct txp_rsp_desc **rspp;
1433{
1434 struct txp_hostvar *hv = sc->sc_hostvar;
1435 struct txp_rsp_desc *rsp;
1436
1437 while (ridx != hv->hv_resp_write_idx) {
1438 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx);
1439
1440 if (id == rsp->rsp_id && rsp->rsp_seq == seq) {
1441 *rspp = (struct txp_rsp_desc *)malloc(
1442 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1),
c5541aee 1443 M_DEVBUF, M_INTWAIT);
984263bc
MD
1444 if ((*rspp) == NULL)
1445 return (-1);
1446 txp_rsp_fixup(sc, rsp, *rspp);
1447 return (0);
1448 }
1449
1450 if (rsp->rsp_flags & RSP_FLAGS_ERROR) {
fcb8c909 1451 if_printf(&sc->sc_arpcom.ac_if, "response error!\n");
984263bc
MD
1452 txp_rsp_fixup(sc, rsp, NULL);
1453 ridx = hv->hv_resp_read_idx;
1454 continue;
1455 }
1456
1457 switch (rsp->rsp_id) {
1458 case TXP_CMD_CYCLE_STATISTICS:
1459 case TXP_CMD_MEDIA_STATUS_READ:
1460 break;
1461 case TXP_CMD_HELLO_RESPONSE:
fcb8c909 1462 if_printf(&sc->sc_arpcom.ac_if, "hello\n");
984263bc
MD
1463 break;
1464 default:
fcb8c909 1465 if_printf(&sc->sc_arpcom.ac_if, "unknown id(0x%x)\n",
984263bc
MD
1466 rsp->rsp_id);
1467 }
1468
1469 txp_rsp_fixup(sc, rsp, NULL);
1470 ridx = hv->hv_resp_read_idx;
1471 hv->hv_resp_read_idx = ridx;
1472 }
1473
1474 return (0);
1475}
1476
1477static void
1478txp_rsp_fixup(sc, rsp, dst)
1479 struct txp_softc *sc;
1480 struct txp_rsp_desc *rsp, *dst;
1481{
1482 struct txp_rsp_desc *src = rsp;
1483 struct txp_hostvar *hv = sc->sc_hostvar;
1484 u_int32_t i, ridx;
1485
1486 ridx = hv->hv_resp_read_idx;
1487
1488 for (i = 0; i < rsp->rsp_numdesc + 1; i++) {
1489 if (dst != NULL)
1490 bcopy(src, dst++, sizeof(struct txp_rsp_desc));
1491 ridx += sizeof(struct txp_rsp_desc);
1492 if (ridx == sc->sc_rspring.size) {
1493 src = sc->sc_rspring.base;
1494 ridx = 0;
1495 } else
1496 src++;
1497 sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx;
1498 }
1499
1500 hv->hv_resp_read_idx = ridx;
1501}
1502
1503static int
1504txp_cmd_desc_numfree(sc)
1505 struct txp_softc *sc;
1506{
1507 struct txp_hostvar *hv = sc->sc_hostvar;
1508 struct txp_boot_record *br = sc->sc_boot;
1509 u_int32_t widx, ridx, nfree;
1510
1511 widx = sc->sc_cmdring.lastwrite;
1512 ridx = hv->hv_cmd_read_idx;
1513
1514 if (widx == ridx) {
1515 /* Ring is completely free */
1516 nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc);
1517 } else {
1518 if (widx > ridx)
1519 nfree = br->br_cmd_siz -
1520 (widx - ridx + sizeof(struct txp_cmd_desc));
1521 else
1522 nfree = ridx - widx - sizeof(struct txp_cmd_desc);
1523 }
1524
1525 return (nfree / sizeof(struct txp_cmd_desc));
1526}
1527
1528static void
1529txp_stop(sc)
1530 struct txp_softc *sc;
1531{
1532 struct ifnet *ifp;
1533
1534 ifp = &sc->sc_arpcom.ac_if;
1535
1536 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1537
9e6fd080 1538 callout_stop(&sc->txp_stat_timer);
984263bc
MD
1539
1540 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1541 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1542
1543 txp_rxring_empty(sc);
1544
1545 return;
1546}
1547
1548static void
1549txp_watchdog(ifp)
1550 struct ifnet *ifp;
1551{
1552 return;
1553}
1554
1555static int
1556txp_ifmedia_upd(ifp)
1557 struct ifnet *ifp;
1558{
1559 struct txp_softc *sc = ifp->if_softc;
1560 struct ifmedia *ifm = &sc->sc_ifmedia;
1561 u_int16_t new_xcvr;
1562
1563 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1564 return (EINVAL);
1565
1566 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) {
1567 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1568 new_xcvr = TXP_XCVR_10_FDX;
1569 else
1570 new_xcvr = TXP_XCVR_10_HDX;
1571 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
1572 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1573 new_xcvr = TXP_XCVR_100_FDX;
1574 else
1575 new_xcvr = TXP_XCVR_100_HDX;
1576 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
1577 new_xcvr = TXP_XCVR_AUTO;
1578 } else
1579 return (EINVAL);
1580
1581 /* nothing to do */
1582 if (sc->sc_xcvr == new_xcvr)
1583 return (0);
1584
1585 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0,
1586 NULL, NULL, NULL, 0);
1587 sc->sc_xcvr = new_xcvr;
1588
1589 return (0);
1590}
1591
1592static void
1593txp_ifmedia_sts(ifp, ifmr)
1594 struct ifnet *ifp;
1595 struct ifmediareq *ifmr;
1596{
1597 struct txp_softc *sc = ifp->if_softc;
1598 struct ifmedia *ifm = &sc->sc_ifmedia;
1599 u_int16_t bmsr, bmcr, anlpar;
1600
1601 ifmr->ifm_status = IFM_AVALID;
1602 ifmr->ifm_active = IFM_ETHER;
1603
1604 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0,
1605 &bmsr, NULL, NULL, 1))
1606 goto bail;
1607 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0,
1608 &bmsr, NULL, NULL, 1))
1609 goto bail;
1610
1611 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0,
1612 &bmcr, NULL, NULL, 1))
1613 goto bail;
1614
1615 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0,
1616 &anlpar, NULL, NULL, 1))
1617 goto bail;
1618
1619 if (bmsr & BMSR_LINK)
1620 ifmr->ifm_status |= IFM_ACTIVE;
1621
1622 if (bmcr & BMCR_ISO) {
1623 ifmr->ifm_active |= IFM_NONE;
1624 ifmr->ifm_status = 0;
1625 return;
1626 }
1627
1628 if (bmcr & BMCR_LOOP)
1629 ifmr->ifm_active |= IFM_LOOP;
1630
1631 if (bmcr & BMCR_AUTOEN) {
1632 if ((bmsr & BMSR_ACOMP) == 0) {
1633 ifmr->ifm_active |= IFM_NONE;
1634 return;
1635 }
1636
1637 if (anlpar & ANLPAR_T4)
1638 ifmr->ifm_active |= IFM_100_T4;
1639 else if (anlpar & ANLPAR_TX_FD)
1640 ifmr->ifm_active |= IFM_100_TX|IFM_FDX;
1641 else if (anlpar & ANLPAR_TX)
1642 ifmr->ifm_active |= IFM_100_TX;
1643 else if (anlpar & ANLPAR_10_FD)
1644 ifmr->ifm_active |= IFM_10_T|IFM_FDX;
1645 else if (anlpar & ANLPAR_10)
1646 ifmr->ifm_active |= IFM_10_T;
1647 else
1648 ifmr->ifm_active |= IFM_NONE;
1649 } else
1650 ifmr->ifm_active = ifm->ifm_cur->ifm_media;
1651 return;
1652
1653bail:
1654 ifmr->ifm_active |= IFM_NONE;
1655 ifmr->ifm_status &= ~IFM_AVALID;
1656}
1657
1658#ifdef TXP_DEBUG
1659static void
1660txp_show_descriptor(d)
1661 void *d;
1662{
1663 struct txp_cmd_desc *cmd = d;
1664 struct txp_rsp_desc *rsp = d;
1665 struct txp_tx_desc *txd = d;
1666 struct txp_frag_desc *frgd = d;
1667
1668 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) {
1669 case CMD_FLAGS_TYPE_CMD:
1670 /* command descriptor */
1671 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1672 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq,
1673 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3);
1674 break;
1675 case CMD_FLAGS_TYPE_RESP:
1676 /* response descriptor */
1677 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1678 rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq,
1679 rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3);
1680 break;
1681 case CMD_FLAGS_TYPE_DATA:
1682 /* data header (assuming tx for now) */
1683 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]",
1684 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen,
1685 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags);
1686 break;
1687 case CMD_FLAGS_TYPE_FRAG:
1688 /* fragment descriptor */
1689 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]",
1690 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len,
1691 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2);
1692 break;
1693 default:
1694 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1695 cmd->cmd_flags & CMD_FLAGS_TYPE_M,
1696 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq,
1697 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3);
1698 break;
1699 }
1700}
1701#endif
1702
1703static void
1704txp_set_filter(sc)
1705 struct txp_softc *sc;
1706{
1707 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1769a3b9 1708 uint16_t filter;
984263bc 1709 struct ifmultiaddr *ifma;
984263bc
MD
1710
1711 if (ifp->if_flags & IFF_PROMISC) {
1712 filter = TXP_RXFILT_PROMISC;
1713 goto setit;
1714 }
1715
1716 filter = TXP_RXFILT_DIRECT;
1717
1718 if (ifp->if_flags & IFF_BROADCAST)
1719 filter |= TXP_RXFILT_BROADCAST;
1720
1769a3b9 1721 if (ifp->if_flags & IFF_ALLMULTI) {
984263bc 1722 filter |= TXP_RXFILT_ALLMULTI;
1769a3b9
JS
1723 } else {
1724 uint32_t hashbit, hash[2];
1725 int mcnt = 0;
1726
984263bc
MD
1727 hash[0] = hash[1] = 0;
1728
1729 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1730 ifma = ifma->ifma_link.le_next) {
1731 if (ifma->ifma_addr->sa_family != AF_LINK)
1732 continue;
1733
984263bc 1734 mcnt++;
1769a3b9
JS
1735 hashbit = (uint16_t)(ether_crc32_be(
1736 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1737 ETHER_ADDR_LEN) & (64 - 1));
984263bc
MD
1738 hash[hashbit / 32] |= (1 << hashbit % 32);
1739 }
1740
1741 if (mcnt > 0) {
1742 filter |= TXP_RXFILT_HASHMULTI;
1743 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE,
1744 2, hash[0], hash[1], NULL, NULL, NULL, 0);
1745 }
1746 }
1747
1748setit:
984263bc
MD
1749 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0,
1750 NULL, NULL, NULL, 1);
984263bc
MD
1751}
1752
1753static void
1754txp_capabilities(sc)
1755 struct txp_softc *sc;
1756{
1757 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1758 struct txp_rsp_desc *rsp = NULL;
1759 struct txp_ext_desc *ext;
1760
1761 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1))
1762 goto out;
1763
1764 if (rsp->rsp_numdesc != 1)
1765 goto out;
1766 ext = (struct txp_ext_desc *)(rsp + 1);
1767
1768 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK;
1769 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK;
1770 ifp->if_capabilities = 0;
1771
1772 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) {
1773 sc->sc_tx_capability |= OFFLOAD_VLAN;
1774 sc->sc_rx_capability |= OFFLOAD_VLAN;
1775 }
1776
1777#if 0
1778 /* not ready yet */
1779 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) {
1780 sc->sc_tx_capability |= OFFLOAD_IPSEC;
1781 sc->sc_rx_capability |= OFFLOAD_IPSEC;
1782 ifp->if_capabilities |= IFCAP_IPSEC;
1783 }
1784#endif
1785
1786 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) {
1787 sc->sc_tx_capability |= OFFLOAD_IPCKSUM;
1788 sc->sc_rx_capability |= OFFLOAD_IPCKSUM;
1789 ifp->if_capabilities |= IFCAP_HWCSUM;
1790 ifp->if_hwassist |= CSUM_IP;
1791 }
1792
1793 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) {
1794#if 0
1795 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM;
1796#endif
1797 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM;
1798 ifp->if_capabilities |= IFCAP_HWCSUM;
1799 }
1800
1801 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) {
1802#if 0
1803 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM;
1804#endif
1805 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM;
1806 ifp->if_capabilities |= IFCAP_HWCSUM;
1807 }
1808 ifp->if_capenable = ifp->if_capabilities;
1809
1810 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0,
1811 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1))
1812 goto out;
1813
1814out:
1815 if (rsp != NULL)
1816 free(rsp, M_DEVBUF);
1817
1818 return;
1819}