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[dragonfly.git] / sys / bus / isa / pnpreg.h
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1/*
2 * Copyright (c) 1996, Sujal M. Patel
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Sujal M. Patel
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/isa/pnpreg.h,v 1.3.2.1 2000/05/11 11:10:35 nyan Exp $
1de703da 33 * $DragonFly: src/sys/bus/isa/pnpreg.h,v 1.2 2003/06/17 04:28:40 dillon Exp $
984263bc
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34 * from: pnp.h,v 1.7 1998/09/13 22:15:44 eivind Exp
35 */
36
37#ifndef _ISA_PNPREG_H_
38#define _ISA_PNPREG_H_
39
40/* Maximum Number of PnP Devices. 8 should be plenty */
41#define PNP_MAX_CARDS 8
42
43#if 0
44/*
45 * the following is the maximum number of PnP Logical devices that
46 * userconfig can handle.
47 */
48#define MAX_PNP_LDN 20
49#endif
50
51/* Static ports to access PnP state machine */
52#ifdef PC98
53#define _PNP_ADDRESS 0x259
54#define _PNP_WRITE_DATA 0xa59
55#else
56#define _PNP_ADDRESS 0x279
57#define _PNP_WRITE_DATA 0xa79
58#endif
59
60/* PnP Registers. Write to ADDRESS and then use WRITE/READ_DATA */
61#define PNP_SET_RD_DATA 0x00
62 /***
63 Writing to this location modifies the address of the port used for
64 reading from the Plug and Play ISA cards. Bits[7:0] become I/O
65 read port address bits[9:2]. Reads from this register are ignored.
66 ***/
67
68#define PNP_SERIAL_ISOLATION 0x01
69 /***
70 A read to this register causes a Plug and Play cards in the Isolation
71 state to compare one bit of the boards ID.
72 This register is read only.
73 ***/
74
75#define PNP_CONFIG_CONTROL 0x02
76#define PNP_CONFIG_CONTROL_RESET_CSN 0x04
77#define PNP_CONFIG_CONTROL_WAIT_FOR_KEY 0x02
78#define PNP_CONFIG_CONTROL_RESET 0x01
79 /***
80 Bit[2] Reset CSN to 0
81 Bit[1] Return to the Wait for Key state
82 Bit[0] Reset all logical devices and restore configuration
83 registers to their power-up values.
84
85 A write to bit[0] of this register performs a reset function on
86 all logical devices. This resets the contents of configuration
87 registers to their default state. All card's logical devices
88 enter their default state and the CSN is preserved.
89
90 A write to bit[1] of this register causes all cards to enter the
91 Wait for Key state but all CSNs are preserved and logical devices
92 are not affected.
93
94 A write to bit[2] of this register causes all cards to reset their
95 CSN to zero .
96
97 This register is write-only. The values are not sticky, that is,
98 hardware will automatically clear them and there is no need for
99 software to clear the bits.
100 ***/
101
102#define PNP_WAKE 0x03
103 /***
104 A write to this port will cause all cards that have a CSN that
105 matches the write data[7:0] to go from the Sleep state to the either
106 the Isolation state if the write data for this command is zero or
107 the Config state if the write data is not zero. Additionally, the
108 pointer to the byte-serial device is reset. This register is
109 writeonly.
110 ***/
111
112#define PNP_RESOURCE_DATA 0x04
113 /***
114 A read from this address reads the next byte of resource information.
115 The Status register must be polled until bit[0] is set before this
116 register may be read. This register is read only.
117 ***/
118
119#define PNP_STATUS 0x05
120 /***
121 Bit[0] when set indicates it is okay to read the next data byte
122 from the Resource Data register. This register is readonly.
123 ***/
124
125#define PNP_SET_CSN 0x06
126 /***
127 A write to this port sets a card's CSN. The CSN is a value uniquely
128 assigned to each ISA card after the serial identification process
129 so that each card may be individually selected during a Wake[CSN]
130 command. This register is read/write.
131 ***/
132
133#define PNP_SET_LDN 0x07
134 /***
135 Selects the current logical device. All reads and writes of memory,
136 I/O, interrupt and DMA configuration information access the registers
137 of the logical device written here. In addition, the I/O Range
138 Check and Activate commands operate only on the selected logical
139 device. This register is read/write. If a card has only 1 logical
140 device, this location should be a read-only value of 0x00.
141 ***/
142
143/*** addresses 0x08 - 0x1F Card Level Reserved for future use ***/
144/*** addresses 0x20 - 0x2F Card Level, Vendor Defined ***/
145
146#define PNP_ACTIVATE 0x30
147 /***
148 For each logical device there is one activate register that controls
149 whether or not the logical device is active on the ISA bus. Bit[0],
150 if set, activates the logical device. Bits[7:1] are reserved and
151 must return 0 on reads. This is a read/write register. Before a
152 logical device is activated, I/O range check must be disabled.
153 ***/
154
155#define PNP_IO_RANGE_CHECK 0x31
156#define PNP_IO_RANGE_CHECK_ENABLE 0x02
157#define PNP_IO_RANGE_CHECK_READ_AS_55 0x01
158 /***
159 This register is used to perform a conflict check on the I/O port
160 range programmed for use by a logical device.
161
162 Bit[7:2] Reserved and must return 0 on reads
163 Bit[1] Enable I/O Range check, if set then I/O Range Check
164 is enabled. I/O range check is only valid when the logical
165 device is inactive.
166
167 Bit[0], if set, forces the logical device to respond to I/O reads
168 of the logical device's assigned I/O range with a 0x55 when I/O
169 range check is in operation. If clear, the logical device drives
170 0xAA. This register is read/write.
171 ***/
172
173/*** addr 0x32 - 0x37 Logical Device Control Reserved for future use ***/
174/*** addr 0x38 - 0x3F Logical Device Control Vendor Define ***/
175
176#define PNP_MEM_BASE_HIGH(i) (0x40 + 8*(i))
177#define PNP_MEM_BASE_LOW(i) (0x41 + 8*(i))
178#define PNP_MEM_CONTROL(i) (0x42 * 8*(i))
179#define PNP_MEM_CONTROL_16BIT 0x2
180#define PNP_MEM_CONTROL_LIMIT 0x1
181#define PNP_MEM_RANGE_HIGH(i) (0x43 + 8*(i))
182#define PNP_MEM_RANGE_LOW(i) (0x44 + 8*(i))
183 /***
184 Four memory resource registers per range, four ranges.
185 Fill with 0 if no ranges are enabled.
186
187 Offset 0: RW Memory base address bits[23:16]
188 Offset 1: RW Memory base address bits[15:8]
189 Offset 2: Memory control
190 Bit[1] specifies 8/16-bit control. This bit is set to indicate
191 16-bit memory, and cleared to indicate 8-bit memory.
192 Bit[0], if cleared, indicates the next field can be used as a range
193 length for decode (implies range length and base alignment of memory
194 descriptor are equal).
195 Bit[0], if set, indicates the next field is the upper limit for
196 the address. - - Bit[0] is read-only.
197 Offset 3: RW upper limit or range len, bits[23:16]
198 Offset 4: RW upper limit or range len, bits[15:8]
199 Offset 5-Offset 7: filler, unused.
200 ***/
201
202#define PNP_IO_BASE_HIGH(i) (0x60 + 2*(i))
203#define PNP_IO_BASE_LOW(i) (0x61 + 2*(i))
204 /***
205 Eight ranges, two bytes per range.
206 Offset 0: I/O port base address bits[15:8]
207 Offset 1: I/O port base address bits[7:0]
208 ***/
209
210#define PNP_IRQ_LEVEL(i) (0x70 + 2*(i))
211#define PNP_IRQ_TYPE(i) (0x71 + 2*(i))
212 /***
213 Two entries, two bytes per entry.
214 Offset 0: RW interrupt level (1..15, 0=unused).
215 Offset 1: Bit[1]: level(1:hi, 0:low),
216 Bit[0]: type (1:level, 0:edge)
217 byte 1 can be readonly if 1 type of int is used.
218 ***/
219
220#define PNP_DMA_CHANNEL(i) (0x74 + 1*(i))
221 /***
222 Two entries, one byte per entry. Bits[2:0] select
223 which DMA channel is in use for DMA 0. Zero selects DMA channel
224 0, seven selects DMA channel 7. DMA channel 4, the cascade channel
225 is used to indicate no DMA channel is active.
226 ***/
227
228/*** 32-bit memory accesses are at 0x76 ***/
229
230/* Macros to parse Resource IDs */
231#define PNP_RES_TYPE(a) (a >> 7)
232#define PNP_SRES_NUM(a) (a >> 3)
233#define PNP_SRES_LEN(a) (a & 0x07)
234#define PNP_LRES_NUM(a) (a & 0x7f)
235
236/* Small Resource Item names */
237#define PNP_TAG_VERSION 0x1
238#define PNP_TAG_LOGICAL_DEVICE 0x2
239#define PNP_TAG_COMPAT_DEVICE 0x3
240#define PNP_TAG_IRQ_FORMAT 0x4
241#define PNP_TAG_DMA_FORMAT 0x5
242#define PNP_TAG_START_DEPENDANT 0x6
243#define PNP_TAG_END_DEPENDANT 0x7
244#define PNP_TAG_IO_RANGE 0x8
245#define PNP_TAG_IO_FIXED 0x9
246#define PNP_TAG_RESERVED 0xa-0xd
247#define PNP_TAG_VENDOR 0xe
248#define PNP_TAG_END 0xf
249
250/* Large Resource Item names */
251#define PNP_TAG_MEMORY_RANGE 0x1
252#define PNP_TAG_ID_ANSI 0x2
253#define PNP_TAG_ID_UNICODE 0x3
254#define PNP_TAG_LARGE_VENDOR 0x4
255#define PNP_TAG_MEMORY32_RANGE 0x5
256#define PNP_TAG_MEMORY32_FIXED 0x6
257#define PNP_TAG_LARGE_RESERVED 0x7-0x7f
258
259#endif /* !_ISA_PNPREG_H_ */