drm/i915: Fix Baytrail hangs with deeper C-states
[dragonfly.git] / sys / dev / drm / i915 / intel_pm.c
CommitLineData
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1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
87f57070 28#include "i915_drv.h"
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29#include "intel_drv.h"
30#include <linux/module.h>
c0bdd5d9 31#include <machine/clock.h>
87f57070 32
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33/**
34 * RC6 is a special power stage which allows the GPU to enter an very
35 * low-voltage mode when idle, using down to 0V while at this stage. This
36 * stage is entered automatically when the GPU is idle when RC6 support is
37 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
38 *
39 * There are different RC6 modes available in Intel GPU, which differentiate
40 * among each other with the latency required to enter and leave RC6 and
41 * voltage consumed by the GPU in different states.
42 *
43 * The combination of the following flags define which states GPU is allowed
44 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
45 * RC6pp is deepest RC6. Their support by hardware varies according to the
46 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
47 * which brings the most power savings; deeper states save more power, but
48 * require higher latency to switch to and wake up.
49 */
50#define INTEL_RC6_ENABLE (1<<0)
51#define INTEL_RC6p_ENABLE (1<<1)
52#define INTEL_RC6pp_ENABLE (1<<2)
e9243325 53
2c9916cd 54static void gen9_init_clock_gating(struct drm_device *dev)
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55{
56 struct drm_i915_private *dev_priv = dev->dev_private;
87f57070 57
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58 /* WaEnableLbsSlaRetryTimerDecrement:skl */
59 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
60 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
61}
a2fdbec6 62
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63static void skl_init_clock_gating(struct drm_device *dev)
64{
65 struct drm_i915_private *dev_priv = dev->dev_private;
87f57070 66
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67 gen9_init_clock_gating(dev);
68
19c468b4 69 if (INTEL_REVID(dev) <= SKL_REVID_B0) {
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70 /*
71 * WaDisableSDEUnitClockGating:skl
72 * WaSetGAPSunitClckGateDisable:skl
73 */
74 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
75 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
76 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
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77
78 /* WaDisableVFUnitClockGating:skl */
79 I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
80 GEN6_VFUNIT_CLOCK_GATE_DISABLE);
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81 }
82
83 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
84 /* WaDisableHDCInvalidation:skl */
85 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
86 BDW_DISABLE_HDC_INVALIDATION);
87
88 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
89 I915_WRITE(FF_SLICE_CS_CHICKEN2,
19c468b4 90 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
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91 }
92
93 if (INTEL_REVID(dev) <= SKL_REVID_E0)
94 /* WaDisableLSQCROPERFforOCL:skl */
95 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
96 GEN8_LQSC_RO_PERF_DIS);
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97}
98
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99static void bxt_init_clock_gating(struct drm_device *dev)
100{
101 struct drm_i915_private *dev_priv = dev->dev_private;
102
103 gen9_init_clock_gating(dev);
104
105 /*
106 * FIXME:
107 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
108 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
109 */
110 /* WaDisableSDEUnitClockGating:bxt */
111 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
112 GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
113 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
114
115 /* FIXME: apply on A0 only */
116 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
117}
118
0db36e9f 119static void i915_pineview_get_mem_freq(struct drm_device *dev)
bc9b2a29 120{
ba55f2f5 121 struct drm_i915_private *dev_priv = dev->dev_private;
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122 u32 tmp;
123
124 tmp = I915_READ(CLKCFG);
125
126 switch (tmp & CLKCFG_FSB_MASK) {
127 case CLKCFG_FSB_533:
128 dev_priv->fsb_freq = 533; /* 133*4 */
129 break;
130 case CLKCFG_FSB_800:
131 dev_priv->fsb_freq = 800; /* 200*4 */
132 break;
133 case CLKCFG_FSB_667:
134 dev_priv->fsb_freq = 667; /* 167*4 */
135 break;
136 case CLKCFG_FSB_400:
137 dev_priv->fsb_freq = 400; /* 100*4 */
138 break;
139 }
140
141 switch (tmp & CLKCFG_MEM_MASK) {
142 case CLKCFG_MEM_533:
143 dev_priv->mem_freq = 533;
144 break;
145 case CLKCFG_MEM_667:
146 dev_priv->mem_freq = 667;
147 break;
148 case CLKCFG_MEM_800:
149 dev_priv->mem_freq = 800;
150 break;
151 }
152
153 /* detect pineview DDR3 setting */
154 tmp = I915_READ(CSHRDDR3CTL);
155 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
156}
157
0db36e9f 158static void i915_ironlake_get_mem_freq(struct drm_device *dev)
bc9b2a29 159{
ba55f2f5 160 struct drm_i915_private *dev_priv = dev->dev_private;
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161 u16 ddrpll, csipll;
162
163 ddrpll = I915_READ16(DDRMPLL1);
164 csipll = I915_READ16(CSIPLL0);
165
166 switch (ddrpll & 0xff) {
167 case 0xc:
168 dev_priv->mem_freq = 800;
169 break;
170 case 0x10:
171 dev_priv->mem_freq = 1066;
172 break;
173 case 0x14:
174 dev_priv->mem_freq = 1333;
175 break;
176 case 0x18:
177 dev_priv->mem_freq = 1600;
178 break;
179 default:
0db36e9f 180 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
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181 ddrpll & 0xff);
182 dev_priv->mem_freq = 0;
183 break;
184 }
185
0db36e9f 186 dev_priv->ips.r_t = dev_priv->mem_freq;
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187
188 switch (csipll & 0x3ff) {
189 case 0x00c:
190 dev_priv->fsb_freq = 3200;
191 break;
192 case 0x00e:
193 dev_priv->fsb_freq = 3733;
194 break;
195 case 0x010:
196 dev_priv->fsb_freq = 4266;
197 break;
198 case 0x012:
199 dev_priv->fsb_freq = 4800;
200 break;
201 case 0x014:
202 dev_priv->fsb_freq = 5333;
203 break;
204 case 0x016:
205 dev_priv->fsb_freq = 5866;
206 break;
207 case 0x018:
208 dev_priv->fsb_freq = 6400;
209 break;
210 default:
0db36e9f 211 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
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212 csipll & 0x3ff);
213 dev_priv->fsb_freq = 0;
214 break;
215 }
216
217 if (dev_priv->fsb_freq == 3200) {
0db36e9f 218 dev_priv->ips.c_m = 0;
bc9b2a29 219 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
0db36e9f 220 dev_priv->ips.c_m = 1;
bc9b2a29 221 } else {
0db36e9f 222 dev_priv->ips.c_m = 2;
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223 }
224}
225
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226static const struct cxsr_latency cxsr_latency_table[] = {
227 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
228 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
229 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
230 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
231 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
232
233 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
234 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
235 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
236 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
237 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
238
239 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
240 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
241 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
242 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
243 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
244
245 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
246 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
247 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
248 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
249 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
250
251 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
252 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
253 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
254 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
255 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
256
257 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
258 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
259 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
260 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
261 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
262};
263
264static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
265 int is_ddr3,
266 int fsb,
267 int mem)
268{
269 const struct cxsr_latency *latency;
270 int i;
271
272 if (fsb == 0 || mem == 0)
273 return NULL;
274
275 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
276 latency = &cxsr_latency_table[i];
277 if (is_desktop == latency->is_desktop &&
278 is_ddr3 == latency->is_ddr3 &&
279 fsb == latency->fsb_freq && mem == latency->mem_freq)
280 return latency;
281 }
282
283 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
284
285 return NULL;
286}
287
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288static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
289{
290 u32 val;
291
292 mutex_lock(&dev_priv->rps.hw_lock);
293
294 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
295 if (enable)
296 val &= ~FORCE_DDR_HIGH_FREQ;
297 else
298 val |= FORCE_DDR_HIGH_FREQ;
299 val &= ~FORCE_DDR_LOW_FREQ;
300 val |= FORCE_DDR_FREQ_REQ_ACK;
301 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
302
303 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
304 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
305 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
306
307 mutex_unlock(&dev_priv->rps.hw_lock);
308}
309
310static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
311{
312 u32 val;
313
314 mutex_lock(&dev_priv->rps.hw_lock);
315
316 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
317 if (enable)
318 val |= DSP_MAXFIFO_PM5_ENABLE;
319 else
320 val &= ~DSP_MAXFIFO_PM5_ENABLE;
321 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
322
323 mutex_unlock(&dev_priv->rps.hw_lock);
324}
325
326#define FW_WM(value, plane) \
327 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
328
24edb884 329void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
c0bdd5d9 330{
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331 struct drm_device *dev = dev_priv->dev;
332 u32 val;
333
334 if (IS_VALLEYVIEW(dev)) {
335 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
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336 if (IS_CHERRYVIEW(dev))
337 chv_set_memory_pm5(dev_priv, enable);
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338 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
339 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
340 } else if (IS_PINEVIEW(dev)) {
341 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
342 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
343 I915_WRITE(DSPFW3, val);
344 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
345 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
346 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
347 I915_WRITE(FW_BLC_SELF, val);
348 } else if (IS_I915GM(dev)) {
349 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
350 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
351 I915_WRITE(INSTPM, val);
352 } else {
353 return;
354 }
c0bdd5d9 355
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356 DRM_DEBUG_KMS("memory self-refresh is %s\n",
357 enable ? "enabled" : "disabled");
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358}
359
477eb7f9 360
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361/*
362 * Latency for FIFO fetches is dependent on several factors:
363 * - memory configuration (speed, channels)
364 * - chipset
365 * - current MCH state
366 * It can be fairly high in some situations, so here we assume a fairly
367 * pessimal value. It's a tradeoff between extra memory fetches (if we
368 * set this value too high, the FIFO will fetch frequently to stay full)
369 * and power consumption (set it too low to save power and we might see
370 * FIFO underruns and display "flicker").
371 *
372 * A value of 5us seems to be a good balance; safe for very low end
373 * platforms but not overly aggressive on lower latency configs.
374 */
1b13d190 375static const int pessimal_latency_ns = 5000;
c0bdd5d9 376
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377#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
378 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
379
380static int vlv_get_fifo_size(struct drm_device *dev,
381 enum i915_pipe pipe, int plane)
382{
383 struct drm_i915_private *dev_priv = dev->dev_private;
384 int sprite0_start, sprite1_start, size;
385
386 switch (pipe) {
387 uint32_t dsparb, dsparb2, dsparb3;
388 case PIPE_A:
389 dsparb = I915_READ(DSPARB);
390 dsparb2 = I915_READ(DSPARB2);
391 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
392 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
393 break;
394 case PIPE_B:
395 dsparb = I915_READ(DSPARB);
396 dsparb2 = I915_READ(DSPARB2);
397 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
398 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
399 break;
400 case PIPE_C:
401 dsparb2 = I915_READ(DSPARB2);
402 dsparb3 = I915_READ(DSPARB3);
403 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
404 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
405 break;
406 default:
407 return 0;
408 }
409
410 switch (plane) {
411 case 0:
412 size = sprite0_start;
413 break;
414 case 1:
415 size = sprite1_start - sprite0_start;
416 break;
417 case 2:
418 size = 512 - 1 - sprite1_start;
419 break;
420 default:
421 return 0;
422 }
423
424 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
425 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
426 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
427 size);
428
429 return size;
430}
431
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432static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
433{
434 struct drm_i915_private *dev_priv = dev->dev_private;
435 uint32_t dsparb = I915_READ(DSPARB);
436 int size;
437
438 size = dsparb & 0x7f;
439 if (plane)
440 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
441
442 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
443 plane ? "B" : "A", size);
444
445 return size;
446}
447
9edbd4a0 448static int i830_get_fifo_size(struct drm_device *dev, int plane)
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FT
449{
450 struct drm_i915_private *dev_priv = dev->dev_private;
451 uint32_t dsparb = I915_READ(DSPARB);
452 int size;
453
454 size = dsparb & 0x1ff;
455 if (plane)
456 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
457 size >>= 1; /* Convert to cachelines */
458
459 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
460 plane ? "B" : "A", size);
461
462 return size;
463}
464
465static int i845_get_fifo_size(struct drm_device *dev, int plane)
466{
467 struct drm_i915_private *dev_priv = dev->dev_private;
468 uint32_t dsparb = I915_READ(DSPARB);
469 int size;
470
471 size = dsparb & 0x7f;
472 size >>= 2; /* Convert to cachelines */
473
474 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
475 plane ? "B" : "A",
476 size);
477
478 return size;
479}
480
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481/* Pineview has different values for various configs */
482static const struct intel_watermark_params pineview_display_wm = {
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483 .fifo_size = PINEVIEW_DISPLAY_FIFO,
484 .max_wm = PINEVIEW_MAX_WM,
485 .default_wm = PINEVIEW_DFT_WM,
486 .guard_size = PINEVIEW_GUARD_WM,
487 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
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488};
489static const struct intel_watermark_params pineview_display_hplloff_wm = {
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490 .fifo_size = PINEVIEW_DISPLAY_FIFO,
491 .max_wm = PINEVIEW_MAX_WM,
492 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
493 .guard_size = PINEVIEW_GUARD_WM,
494 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
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495};
496static const struct intel_watermark_params pineview_cursor_wm = {
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497 .fifo_size = PINEVIEW_CURSOR_FIFO,
498 .max_wm = PINEVIEW_CURSOR_MAX_WM,
499 .default_wm = PINEVIEW_CURSOR_DFT_WM,
500 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
501 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
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502};
503static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
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504 .fifo_size = PINEVIEW_CURSOR_FIFO,
505 .max_wm = PINEVIEW_CURSOR_MAX_WM,
506 .default_wm = PINEVIEW_CURSOR_DFT_WM,
507 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
508 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
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509};
510static const struct intel_watermark_params g4x_wm_info = {
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511 .fifo_size = G4X_FIFO_SIZE,
512 .max_wm = G4X_MAX_WM,
513 .default_wm = G4X_MAX_WM,
514 .guard_size = 2,
515 .cacheline_size = G4X_FIFO_LINE_SIZE,
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516};
517static const struct intel_watermark_params g4x_cursor_wm_info = {
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518 .fifo_size = I965_CURSOR_FIFO,
519 .max_wm = I965_CURSOR_MAX_WM,
520 .default_wm = I965_CURSOR_DFT_WM,
521 .guard_size = 2,
522 .cacheline_size = G4X_FIFO_LINE_SIZE,
87f57070 523};
0db36e9f 524static const struct intel_watermark_params valleyview_wm_info = {
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FT
525 .fifo_size = VALLEYVIEW_FIFO_SIZE,
526 .max_wm = VALLEYVIEW_MAX_WM,
527 .default_wm = VALLEYVIEW_MAX_WM,
528 .guard_size = 2,
529 .cacheline_size = G4X_FIFO_LINE_SIZE,
0db36e9f
FT
530};
531static const struct intel_watermark_params valleyview_cursor_wm_info = {
24edb884
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532 .fifo_size = I965_CURSOR_FIFO,
533 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
534 .default_wm = I965_CURSOR_DFT_WM,
535 .guard_size = 2,
536 .cacheline_size = G4X_FIFO_LINE_SIZE,
0db36e9f 537};
87f57070 538static const struct intel_watermark_params i965_cursor_wm_info = {
24edb884
FT
539 .fifo_size = I965_CURSOR_FIFO,
540 .max_wm = I965_CURSOR_MAX_WM,
541 .default_wm = I965_CURSOR_DFT_WM,
542 .guard_size = 2,
543 .cacheline_size = I915_FIFO_LINE_SIZE,
87f57070
FT
544};
545static const struct intel_watermark_params i945_wm_info = {
24edb884
FT
546 .fifo_size = I945_FIFO_SIZE,
547 .max_wm = I915_MAX_WM,
548 .default_wm = 1,
549 .guard_size = 2,
550 .cacheline_size = I915_FIFO_LINE_SIZE,
87f57070
FT
551};
552static const struct intel_watermark_params i915_wm_info = {
24edb884
FT
553 .fifo_size = I915_FIFO_SIZE,
554 .max_wm = I915_MAX_WM,
555 .default_wm = 1,
556 .guard_size = 2,
557 .cacheline_size = I915_FIFO_LINE_SIZE,
87f57070 558};
1b13d190 559static const struct intel_watermark_params i830_a_wm_info = {
24edb884
FT
560 .fifo_size = I855GM_FIFO_SIZE,
561 .max_wm = I915_MAX_WM,
562 .default_wm = 1,
563 .guard_size = 2,
564 .cacheline_size = I830_FIFO_LINE_SIZE,
87f57070 565};
1b13d190
FT
566static const struct intel_watermark_params i830_bc_wm_info = {
567 .fifo_size = I855GM_FIFO_SIZE,
568 .max_wm = I915_MAX_WM/2,
569 .default_wm = 1,
570 .guard_size = 2,
571 .cacheline_size = I830_FIFO_LINE_SIZE,
572};
9edbd4a0 573static const struct intel_watermark_params i845_wm_info = {
24edb884
FT
574 .fifo_size = I830_FIFO_SIZE,
575 .max_wm = I915_MAX_WM,
576 .default_wm = 1,
577 .guard_size = 2,
578 .cacheline_size = I830_FIFO_LINE_SIZE,
87f57070
FT
579};
580
87f57070
FT
581/**
582 * intel_calculate_wm - calculate watermark level
583 * @clock_in_khz: pixel clock
584 * @wm: chip FIFO params
585 * @pixel_size: display pixel size
586 * @latency_ns: memory latency for the platform
587 *
588 * Calculate the watermark level (the level at which the display plane will
589 * start fetching from memory again). Each chip has a different display
590 * FIFO size and allocation, so the caller needs to figure that out and pass
591 * in the correct intel_watermark_params structure.
592 *
593 * As the pixel clock runs, the FIFO will be drained at a rate that depends
594 * on the pixel size. When it reaches the watermark level, it'll start
595 * fetching FIFO line sized based chunks from memory until the FIFO fills
596 * past the watermark point. If the FIFO drains completely, a FIFO underrun
597 * will occur, and a display engine hang could result.
598 */
599static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
600 const struct intel_watermark_params *wm,
601 int fifo_size,
602 int pixel_size,
603 unsigned long latency_ns)
604{
605 long entries_required, wm_size;
606
607 /*
608 * Note: we need to make sure we don't overflow for various clock &
609 * latency values.
610 * clocks go from a few thousand to several hundred thousand.
611 * latency is usually a few thousand
612 */
613 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
614 1000;
c0bdd5d9 615 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
87f57070
FT
616
617 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
618
619 wm_size = fifo_size - (entries_required + wm->guard_size);
620
621 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
622
623 /* Don't promote wm_size to unsigned... */
624 if (wm_size > (long)wm->max_wm)
625 wm_size = wm->max_wm;
626 if (wm_size <= 0)
627 wm_size = wm->default_wm;
1b13d190
FT
628
629 /*
630 * Bspec seems to indicate that the value shouldn't be lower than
631 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
632 * Lets go for 8 which is the burst size since certain platforms
633 * already use a hardcoded 8 (which is what the spec says should be
634 * done).
635 */
636 if (wm_size <= 8)
637 wm_size = 8;
638
87f57070
FT
639 return wm_size;
640}
641
c0bdd5d9
FT
642static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
643{
644 struct drm_crtc *crtc, *enabled = NULL;
87f57070 645
ba55f2f5 646 for_each_crtc(dev, crtc) {
c0bdd5d9
FT
647 if (intel_crtc_active(crtc)) {
648 if (enabled)
649 return NULL;
650 enabled = crtc;
651 }
652 }
87f57070 653
c0bdd5d9
FT
654 return enabled;
655}
87f57070 656
9edbd4a0 657static void pineview_update_wm(struct drm_crtc *unused_crtc)
87f57070 658{
9edbd4a0 659 struct drm_device *dev = unused_crtc->dev;
c0bdd5d9
FT
660 struct drm_i915_private *dev_priv = dev->dev_private;
661 struct drm_crtc *crtc;
87f57070 662 const struct cxsr_latency *latency;
c0bdd5d9
FT
663 u32 reg;
664 unsigned long wm;
87f57070 665
c0bdd5d9
FT
666 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
667 dev_priv->fsb_freq, dev_priv->mem_freq);
668 if (!latency) {
669 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
24edb884 670 intel_set_memory_cxsr(dev_priv, false);
c0bdd5d9 671 return;
87f57070
FT
672 }
673
c0bdd5d9
FT
674 crtc = single_enabled_crtc(dev);
675 if (crtc) {
9edbd4a0 676 const struct drm_display_mode *adjusted_mode;
477eb7f9 677 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
9edbd4a0
FT
678 int clock;
679
2c9916cd 680 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
9edbd4a0 681 clock = adjusted_mode->crtc_clock;
87f57070 682
c0bdd5d9
FT
683 /* Display SR */
684 wm = intel_calculate_wm(clock, &pineview_display_wm,
685 pineview_display_wm.fifo_size,
686 pixel_size, latency->display_sr);
687 reg = I915_READ(DSPFW1);
688 reg &= ~DSPFW_SR_MASK;
477eb7f9 689 reg |= FW_WM(wm, SR);
c0bdd5d9
FT
690 I915_WRITE(DSPFW1, reg);
691 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
87f57070 692
c0bdd5d9
FT
693 /* cursor SR */
694 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
695 pineview_display_wm.fifo_size,
696 pixel_size, latency->cursor_sr);
697 reg = I915_READ(DSPFW3);
698 reg &= ~DSPFW_CURSOR_SR_MASK;
477eb7f9 699 reg |= FW_WM(wm, CURSOR_SR);
c0bdd5d9 700 I915_WRITE(DSPFW3, reg);
87f57070
FT
701
702 /* Display HPLL off SR */
703 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
704 pineview_display_hplloff_wm.fifo_size,
705 pixel_size, latency->display_hpll_disable);
706 reg = I915_READ(DSPFW3);
707 reg &= ~DSPFW_HPLL_SR_MASK;
477eb7f9 708 reg |= FW_WM(wm, HPLL_SR);
87f57070
FT
709 I915_WRITE(DSPFW3, reg);
710
711 /* cursor HPLL off SR */
712 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
713 pineview_display_hplloff_wm.fifo_size,
714 pixel_size, latency->cursor_hpll_disable);
715 reg = I915_READ(DSPFW3);
716 reg &= ~DSPFW_HPLL_CURSOR_MASK;
477eb7f9 717 reg |= FW_WM(wm, HPLL_CURSOR);
87f57070
FT
718 I915_WRITE(DSPFW3, reg);
719 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
720
24edb884 721 intel_set_memory_cxsr(dev_priv, true);
87f57070 722 } else {
24edb884 723 intel_set_memory_cxsr(dev_priv, false);
87f57070
FT
724 }
725}
726
727static bool g4x_compute_wm0(struct drm_device *dev,
728 int plane,
729 const struct intel_watermark_params *display,
730 int display_latency_ns,
731 const struct intel_watermark_params *cursor,
732 int cursor_latency_ns,
733 int *plane_wm,
734 int *cursor_wm)
735{
736 struct drm_crtc *crtc;
9edbd4a0 737 const struct drm_display_mode *adjusted_mode;
87f57070
FT
738 int htotal, hdisplay, clock, pixel_size;
739 int line_time_us, line_count;
740 int entries, tlb_miss;
741
742 crtc = intel_get_crtc_for_plane(dev, plane);
c0bdd5d9 743 if (!intel_crtc_active(crtc)) {
87f57070
FT
744 *cursor_wm = cursor->guard_size;
745 *plane_wm = display->guard_size;
746 return false;
747 }
748
2c9916cd 749 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
9edbd4a0
FT
750 clock = adjusted_mode->crtc_clock;
751 htotal = adjusted_mode->crtc_htotal;
2c9916cd 752 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
477eb7f9 753 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
87f57070
FT
754
755 /* Use the small buffer method to calculate plane watermark */
756 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
757 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
758 if (tlb_miss > 0)
759 entries += tlb_miss;
c0bdd5d9 760 entries = DIV_ROUND_UP(entries, display->cacheline_size);
87f57070
FT
761 *plane_wm = entries + display->guard_size;
762 if (*plane_wm > (int)display->max_wm)
763 *plane_wm = display->max_wm;
764
765 /* Use the large buffer method to calculate cursor watermark */
ba55f2f5 766 line_time_us = max(htotal * 1000 / clock, 1);
87f57070 767 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
477eb7f9 768 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
87f57070
FT
769 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
770 if (tlb_miss > 0)
771 entries += tlb_miss;
c0bdd5d9 772 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
87f57070
FT
773 *cursor_wm = entries + cursor->guard_size;
774 if (*cursor_wm > (int)cursor->max_wm)
775 *cursor_wm = (int)cursor->max_wm;
776
777 return true;
778}
779
780/*
781 * Check the wm result.
782 *
783 * If any calculated watermark values is larger than the maximum value that
784 * can be programmed into the associated watermark register, that watermark
785 * must be disabled.
786 */
787static bool g4x_check_srwm(struct drm_device *dev,
788 int display_wm, int cursor_wm,
789 const struct intel_watermark_params *display,
790 const struct intel_watermark_params *cursor)
791{
792 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
793 display_wm, cursor_wm);
794
795 if (display_wm > display->max_wm) {
796 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
797 display_wm, display->max_wm);
798 return false;
799 }
800
801 if (cursor_wm > cursor->max_wm) {
802 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
803 cursor_wm, cursor->max_wm);
804 return false;
805 }
806
807 if (!(display_wm || cursor_wm)) {
808 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
809 return false;
810 }
811
812 return true;
813}
814
815static bool g4x_compute_srwm(struct drm_device *dev,
816 int plane,
817 int latency_ns,
818 const struct intel_watermark_params *display,
819 const struct intel_watermark_params *cursor,
820 int *display_wm, int *cursor_wm)
821{
822 struct drm_crtc *crtc;
9edbd4a0 823 const struct drm_display_mode *adjusted_mode;
87f57070
FT
824 int hdisplay, htotal, pixel_size, clock;
825 unsigned long line_time_us;
826 int line_count, line_size;
827 int small, large;
828 int entries;
829
830 if (!latency_ns) {
831 *display_wm = *cursor_wm = 0;
832 return false;
833 }
834
835 crtc = intel_get_crtc_for_plane(dev, plane);
2c9916cd 836 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
9edbd4a0
FT
837 clock = adjusted_mode->crtc_clock;
838 htotal = adjusted_mode->crtc_htotal;
2c9916cd 839 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
477eb7f9 840 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
87f57070 841
ba55f2f5 842 line_time_us = max(htotal * 1000 / clock, 1);
87f57070
FT
843 line_count = (latency_ns / line_time_us + 1000) / 1000;
844 line_size = hdisplay * pixel_size;
845
846 /* Use the minimum of the small and large buffer method for primary */
847 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
848 large = line_count * line_size;
849
c0bdd5d9 850 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
87f57070
FT
851 *display_wm = entries + display->guard_size;
852
853 /* calculate the self-refresh watermark for display cursor */
477eb7f9 854 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
c0bdd5d9 855 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
87f57070
FT
856 *cursor_wm = entries + cursor->guard_size;
857
858 return g4x_check_srwm(dev,
859 *display_wm, *cursor_wm,
860 display, cursor);
861}
862
477eb7f9
FT
863#define FW_WM_VLV(value, plane) \
864 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
0db36e9f 865
477eb7f9
FT
866static void vlv_write_wm_values(struct intel_crtc *crtc,
867 const struct vlv_wm_values *wm)
868{
869 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
870 enum i915_pipe pipe = crtc->pipe;
0db36e9f 871
477eb7f9
FT
872 I915_WRITE(VLV_DDL(pipe),
873 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
874 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
875 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
876 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
0db36e9f 877
477eb7f9
FT
878 I915_WRITE(DSPFW1,
879 FW_WM(wm->sr.plane, SR) |
880 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
881 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
882 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
883 I915_WRITE(DSPFW2,
884 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
885 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
886 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
887 I915_WRITE(DSPFW3,
888 FW_WM(wm->sr.cursor, CURSOR_SR));
889
890 if (IS_CHERRYVIEW(dev_priv)) {
891 I915_WRITE(DSPFW7_CHV,
892 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
893 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
894 I915_WRITE(DSPFW8_CHV,
895 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
896 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
897 I915_WRITE(DSPFW9_CHV,
898 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
899 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
900 I915_WRITE(DSPHOWM,
901 FW_WM(wm->sr.plane >> 9, SR_HI) |
902 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
903 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
904 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
905 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
906 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
907 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
908 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
909 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
910 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
911 } else {
912 I915_WRITE(DSPFW7,
913 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
914 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
915 I915_WRITE(DSPHOWM,
916 FW_WM(wm->sr.plane >> 9, SR_HI) |
917 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
918 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
919 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
920 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
921 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
922 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
923 }
0db36e9f 924
477eb7f9 925 POSTING_READ(DSPFW1);
0db36e9f 926
477eb7f9 927 dev_priv->wm.vlv = *wm;
0db36e9f
FT
928}
929
477eb7f9 930#undef FW_WM_VLV
0db36e9f 931
477eb7f9
FT
932static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
933 struct drm_plane *plane)
0db36e9f 934{
2c9916cd 935 struct drm_device *dev = crtc->dev;
1b13d190 936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
477eb7f9
FT
937 int entries, prec_mult, drain_latency, pixel_size;
938 int clock = intel_crtc->config->base.adjusted_mode.crtc_clock;
939 const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
0db36e9f 940
477eb7f9
FT
941 /*
942 * FIXME the plane might have an fb
943 * but be invisible (eg. due to clipping)
944 */
945 if (!intel_crtc->active || !plane->state->fb)
946 return 0;
0db36e9f 947
477eb7f9
FT
948 if (WARN(clock == 0, "Pixel clock is zero!\n"))
949 return 0;
0db36e9f 950
477eb7f9 951 pixel_size = drm_format_plane_cpp(plane->state->fb->pixel_format, 0);
0db36e9f 952
477eb7f9
FT
953 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
954 return 0;
1b13d190 955
477eb7f9
FT
956 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
957
958 prec_mult = high_precision;
959 drain_latency = 64 * prec_mult * 4 / entries;
960
961 if (drain_latency > DRAIN_LATENCY_MASK) {
962 prec_mult /= 2;
963 drain_latency = 64 * prec_mult * 4 / entries;
0db36e9f 964 }
1b13d190 965
477eb7f9
FT
966 if (drain_latency > DRAIN_LATENCY_MASK)
967 drain_latency = DRAIN_LATENCY_MASK;
0db36e9f 968
477eb7f9
FT
969 return drain_latency | (prec_mult == high_precision ?
970 DDL_PRECISION_HIGH : DDL_PRECISION_LOW);
971}
87f57070 972
477eb7f9
FT
973static int vlv_compute_wm(struct intel_crtc *crtc,
974 struct intel_plane *plane,
975 int fifo_size)
0db36e9f 976{
477eb7f9 977 int clock, entries, pixel_size;
0db36e9f 978
477eb7f9
FT
979 /*
980 * FIXME the plane might have an fb
981 * but be invisible (eg. due to clipping)
982 */
983 if (!crtc->active || !plane->base.state->fb)
984 return 0;
0db36e9f 985
477eb7f9
FT
986 pixel_size = drm_format_plane_cpp(plane->base.state->fb->pixel_format, 0);
987 clock = crtc->config->base.adjusted_mode.crtc_clock;
0db36e9f 988
477eb7f9 989 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
0db36e9f 990
477eb7f9
FT
991 /*
992 * Set up the watermark such that we don't start issuing memory
993 * requests until we are within PND's max deadline value (256us).
994 * Idea being to be idle as long as possible while still taking
995 * advatange of PND's deadline scheduling. The limit of 8
996 * cachelines (used when the FIFO will anyway drain in less time
997 * than 256us) should match what we would be done if trickle
998 * feed were enabled.
999 */
1000 return fifo_size - clamp(DIV_ROUND_UP(256 * entries, 64), 0, fifo_size - 8);
1001}
1002
1003static bool vlv_compute_sr_wm(struct drm_device *dev,
1004 struct vlv_wm_values *wm)
1005{
1006 struct drm_i915_private *dev_priv = to_i915(dev);
1007 struct drm_crtc *crtc;
1008 enum i915_pipe pipe = INVALID_PIPE;
1009 int num_planes = 0;
1010 int fifo_size = 0;
1011 struct intel_plane *plane;
1012
1013 wm->sr.cursor = wm->sr.plane = 0;
1014
1015 crtc = single_enabled_crtc(dev);
1016 /* maxfifo not supported on pipe C */
1017 if (crtc && to_intel_crtc(crtc)->pipe != PIPE_C) {
1018 pipe = to_intel_crtc(crtc)->pipe;
1019 num_planes = !!wm->pipe[pipe].primary +
1020 !!wm->pipe[pipe].sprite[0] +
1021 !!wm->pipe[pipe].sprite[1];
1022 fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
0db36e9f
FT
1023 }
1024
477eb7f9
FT
1025 if (fifo_size == 0 || num_planes > 1)
1026 return false;
0db36e9f 1027
477eb7f9
FT
1028 wm->sr.cursor = vlv_compute_wm(to_intel_crtc(crtc),
1029 to_intel_plane(crtc->cursor), 0x3f);
24edb884 1030
477eb7f9
FT
1031 list_for_each_entry(plane, &dev->mode_config.plane_list, base.head) {
1032 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1033 continue;
1034
1035 if (plane->pipe != pipe)
1036 continue;
1037
1038 wm->sr.plane = vlv_compute_wm(to_intel_crtc(crtc),
1039 plane, fifo_size);
1040 if (wm->sr.plane != 0)
1041 break;
1042 }
1043
1044 return true;
0db36e9f
FT
1045}
1046
477eb7f9 1047static void valleyview_update_wm(struct drm_crtc *crtc)
1b13d190
FT
1048{
1049 struct drm_device *dev = crtc->dev;
1b13d190 1050 struct drm_i915_private *dev_priv = dev->dev_private;
477eb7f9
FT
1051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1052 enum i915_pipe pipe = intel_crtc->pipe;
1b13d190 1053 bool cxsr_enabled;
477eb7f9 1054 struct vlv_wm_values wm = dev_priv->wm.vlv;
1b13d190 1055
477eb7f9
FT
1056 wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);
1057 wm.pipe[pipe].primary = vlv_compute_wm(intel_crtc,
1058 to_intel_plane(crtc->primary),
1059 vlv_get_fifo_size(dev, pipe, 0));
1b13d190 1060
477eb7f9
FT
1061 wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);
1062 wm.pipe[pipe].cursor = vlv_compute_wm(intel_crtc,
1063 to_intel_plane(crtc->cursor),
1064 0x3f);
1b13d190 1065
477eb7f9 1066 cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
1b13d190 1067
477eb7f9
FT
1068 if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1069 return;
1b13d190 1070
477eb7f9
FT
1071 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1072 "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1073 wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1074 wm.sr.plane, wm.sr.cursor);
1b13d190 1075
477eb7f9
FT
1076 /*
1077 * FIXME DDR DVFS introduces massive memory latencies which
1078 * are not known to system agent so any deadline specified
1079 * by the display may not be respected. To support DDR DVFS
1080 * the watermark code needs to be rewritten to essentially
1081 * bypass deadline mechanism and rely solely on the
1082 * watermarks. For now disable DDR DVFS.
1083 */
1084 if (IS_CHERRYVIEW(dev_priv))
1085 chv_set_memory_dvfs(dev_priv, false);
1b13d190 1086
477eb7f9
FT
1087 if (!cxsr_enabled)
1088 intel_set_memory_cxsr(dev_priv, false);
1089
1090 vlv_write_wm_values(intel_crtc, &wm);
1b13d190
FT
1091
1092 if (cxsr_enabled)
1093 intel_set_memory_cxsr(dev_priv, true);
1094}
1095
1096static void valleyview_update_sprite_wm(struct drm_plane *plane,
1097 struct drm_crtc *crtc,
1098 uint32_t sprite_width,
1099 uint32_t sprite_height,
1100 int pixel_size,
1101 bool enabled, bool scaled)
1102{
1103 struct drm_device *dev = crtc->dev;
1104 struct drm_i915_private *dev_priv = dev->dev_private;
477eb7f9
FT
1105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1106 enum i915_pipe pipe = intel_crtc->pipe;
1b13d190 1107 int sprite = to_intel_plane(plane)->plane;
477eb7f9
FT
1108 bool cxsr_enabled;
1109 struct vlv_wm_values wm = dev_priv->wm.vlv;
1b13d190 1110
477eb7f9
FT
1111 if (enabled) {
1112 wm.ddl[pipe].sprite[sprite] =
1113 vlv_compute_drain_latency(crtc, plane);
1b13d190 1114
477eb7f9
FT
1115 wm.pipe[pipe].sprite[sprite] =
1116 vlv_compute_wm(intel_crtc,
1117 to_intel_plane(plane),
1118 vlv_get_fifo_size(dev, pipe, sprite+1));
1119 } else {
1120 wm.ddl[pipe].sprite[sprite] = 0;
1121 wm.pipe[pipe].sprite[sprite] = 0;
1b13d190
FT
1122 }
1123
477eb7f9
FT
1124 cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
1125
1126 if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1127 return;
1128
1129 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: sprite %c=%d, "
1130 "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1131 sprite_name(pipe, sprite),
1132 wm.pipe[pipe].sprite[sprite],
1133 wm.sr.plane, wm.sr.cursor);
1134
1135 if (!cxsr_enabled)
1136 intel_set_memory_cxsr(dev_priv, false);
1137
1138 vlv_write_wm_values(intel_crtc, &wm);
1139
1140 if (cxsr_enabled)
1141 intel_set_memory_cxsr(dev_priv, true);
1b13d190
FT
1142}
1143
477eb7f9
FT
1144#define single_plane_enabled(mask) is_power_of_2(mask)
1145
9edbd4a0 1146static void g4x_update_wm(struct drm_crtc *crtc)
87f57070 1147{
9edbd4a0 1148 struct drm_device *dev = crtc->dev;
87f57070
FT
1149 static const int sr_latency_ns = 12000;
1150 struct drm_i915_private *dev_priv = dev->dev_private;
1151 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1152 int plane_sr, cursor_sr;
1153 unsigned int enabled = 0;
24edb884 1154 bool cxsr_enabled;
87f57070 1155
8e26cdf6 1156 if (g4x_compute_wm0(dev, PIPE_A,
1b13d190
FT
1157 &g4x_wm_info, pessimal_latency_ns,
1158 &g4x_cursor_wm_info, pessimal_latency_ns,
87f57070 1159 &planea_wm, &cursora_wm))
8e26cdf6 1160 enabled |= 1 << PIPE_A;
87f57070 1161
8e26cdf6 1162 if (g4x_compute_wm0(dev, PIPE_B,
1b13d190
FT
1163 &g4x_wm_info, pessimal_latency_ns,
1164 &g4x_cursor_wm_info, pessimal_latency_ns,
87f57070 1165 &planeb_wm, &cursorb_wm))
8e26cdf6 1166 enabled |= 1 << PIPE_B;
87f57070 1167
87f57070
FT
1168 if (single_plane_enabled(enabled) &&
1169 g4x_compute_srwm(dev, ffs(enabled) - 1,
1170 sr_latency_ns,
1171 &g4x_wm_info,
1172 &g4x_cursor_wm_info,
c0bdd5d9 1173 &plane_sr, &cursor_sr)) {
24edb884 1174 cxsr_enabled = true;
c0bdd5d9 1175 } else {
24edb884
FT
1176 cxsr_enabled = false;
1177 intel_set_memory_cxsr(dev_priv, false);
c0bdd5d9
FT
1178 plane_sr = cursor_sr = 0;
1179 }
87f57070 1180
1b13d190
FT
1181 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1182 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
87f57070
FT
1183 planea_wm, cursora_wm,
1184 planeb_wm, cursorb_wm,
1185 plane_sr, cursor_sr);
1186
1187 I915_WRITE(DSPFW1,
477eb7f9
FT
1188 FW_WM(plane_sr, SR) |
1189 FW_WM(cursorb_wm, CURSORB) |
1190 FW_WM(planeb_wm, PLANEB) |
1191 FW_WM(planea_wm, PLANEA));
87f57070 1192 I915_WRITE(DSPFW2,
c0bdd5d9 1193 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
477eb7f9 1194 FW_WM(cursora_wm, CURSORA));
87f57070
FT
1195 /* HPLL off in SR has some issues on G4x... disable it */
1196 I915_WRITE(DSPFW3,
c0bdd5d9 1197 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
477eb7f9 1198 FW_WM(cursor_sr, CURSOR_SR));
24edb884
FT
1199
1200 if (cxsr_enabled)
1201 intel_set_memory_cxsr(dev_priv, true);
87f57070
FT
1202}
1203
9edbd4a0 1204static void i965_update_wm(struct drm_crtc *unused_crtc)
87f57070 1205{
9edbd4a0 1206 struct drm_device *dev = unused_crtc->dev;
87f57070
FT
1207 struct drm_i915_private *dev_priv = dev->dev_private;
1208 struct drm_crtc *crtc;
1209 int srwm = 1;
1210 int cursor_sr = 16;
24edb884 1211 bool cxsr_enabled;
87f57070
FT
1212
1213 /* Calc sr entries for one plane configs */
1214 crtc = single_enabled_crtc(dev);
1215 if (crtc) {
1216 /* self-refresh has much higher latency */
1217 static const int sr_latency_ns = 12000;
9edbd4a0 1218 const struct drm_display_mode *adjusted_mode =
2c9916cd 1219 &to_intel_crtc(crtc)->config->base.adjusted_mode;
9edbd4a0
FT
1220 int clock = adjusted_mode->crtc_clock;
1221 int htotal = adjusted_mode->crtc_htotal;
2c9916cd 1222 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
477eb7f9 1223 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
87f57070
FT
1224 unsigned long line_time_us;
1225 int entries;
1226
ba55f2f5 1227 line_time_us = max(htotal * 1000 / clock, 1);
87f57070
FT
1228
1229 /* Use ns/us then divide to preserve precision */
1230 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1231 pixel_size * hdisplay;
c0bdd5d9 1232 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
87f57070
FT
1233 srwm = I965_FIFO_SIZE - entries;
1234 if (srwm < 0)
1235 srwm = 1;
1236 srwm &= 0x1ff;
1237 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1238 entries, srwm);
1239
1240 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
477eb7f9 1241 pixel_size * crtc->cursor->state->crtc_w;
c0bdd5d9
FT
1242 entries = DIV_ROUND_UP(entries,
1243 i965_cursor_wm_info.cacheline_size);
87f57070
FT
1244 cursor_sr = i965_cursor_wm_info.fifo_size -
1245 (entries + i965_cursor_wm_info.guard_size);
1246
1247 if (cursor_sr > i965_cursor_wm_info.max_wm)
1248 cursor_sr = i965_cursor_wm_info.max_wm;
1249
1250 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1251 "cursor %d\n", srwm, cursor_sr);
1252
24edb884 1253 cxsr_enabled = true;
87f57070 1254 } else {
24edb884 1255 cxsr_enabled = false;
87f57070 1256 /* Turn off self refresh if both pipes are enabled */
24edb884 1257 intel_set_memory_cxsr(dev_priv, false);
87f57070
FT
1258 }
1259
1260 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1261 srwm);
1262
1263 /* 965 has limitations... */
477eb7f9
FT
1264 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1265 FW_WM(8, CURSORB) |
1266 FW_WM(8, PLANEB) |
1267 FW_WM(8, PLANEA));
1268 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1269 FW_WM(8, PLANEC_OLD));
87f57070 1270 /* update cursor SR watermark */
477eb7f9 1271 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
24edb884
FT
1272
1273 if (cxsr_enabled)
1274 intel_set_memory_cxsr(dev_priv, true);
87f57070
FT
1275}
1276
477eb7f9
FT
1277#undef FW_WM
1278
9edbd4a0 1279static void i9xx_update_wm(struct drm_crtc *unused_crtc)
87f57070 1280{
9edbd4a0 1281 struct drm_device *dev = unused_crtc->dev;
87f57070
FT
1282 struct drm_i915_private *dev_priv = dev->dev_private;
1283 const struct intel_watermark_params *wm_info;
1284 uint32_t fwater_lo;
1285 uint32_t fwater_hi;
1286 int cwm, srwm = 1;
1287 int fifo_size;
1288 int planea_wm, planeb_wm;
1289 struct drm_crtc *crtc, *enabled = NULL;
1290
1291 if (IS_I945GM(dev))
1292 wm_info = &i945_wm_info;
1293 else if (!IS_GEN2(dev))
1294 wm_info = &i915_wm_info;
1295 else
1b13d190 1296 wm_info = &i830_a_wm_info;
87f57070
FT
1297
1298 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1299 crtc = intel_get_crtc_for_plane(dev, 0);
c0bdd5d9 1300 if (intel_crtc_active(crtc)) {
9edbd4a0 1301 const struct drm_display_mode *adjusted_mode;
477eb7f9 1302 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
c0bdd5d9
FT
1303 if (IS_GEN2(dev))
1304 cpp = 4;
1305
2c9916cd 1306 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
9edbd4a0 1307 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
c0bdd5d9 1308 wm_info, fifo_size, cpp,
1b13d190 1309 pessimal_latency_ns);
87f57070 1310 enabled = crtc;
1b13d190 1311 } else {
87f57070 1312 planea_wm = fifo_size - wm_info->guard_size;
1b13d190
FT
1313 if (planea_wm > (long)wm_info->max_wm)
1314 planea_wm = wm_info->max_wm;
1315 }
1316
1317 if (IS_GEN2(dev))
1318 wm_info = &i830_bc_wm_info;
87f57070
FT
1319
1320 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1321 crtc = intel_get_crtc_for_plane(dev, 1);
c0bdd5d9 1322 if (intel_crtc_active(crtc)) {
9edbd4a0 1323 const struct drm_display_mode *adjusted_mode;
477eb7f9 1324 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
c0bdd5d9
FT
1325 if (IS_GEN2(dev))
1326 cpp = 4;
1327
2c9916cd 1328 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
9edbd4a0 1329 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
c0bdd5d9 1330 wm_info, fifo_size, cpp,
1b13d190 1331 pessimal_latency_ns);
87f57070
FT
1332 if (enabled == NULL)
1333 enabled = crtc;
1334 else
1335 enabled = NULL;
1b13d190 1336 } else {
87f57070 1337 planeb_wm = fifo_size - wm_info->guard_size;
1b13d190
FT
1338 if (planeb_wm > (long)wm_info->max_wm)
1339 planeb_wm = wm_info->max_wm;
1340 }
87f57070
FT
1341
1342 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1343
ba55f2f5 1344 if (IS_I915GM(dev) && enabled) {
24edb884 1345 struct drm_i915_gem_object *obj;
ba55f2f5 1346
477eb7f9 1347 obj = intel_fb_obj(enabled->primary->state->fb);
ba55f2f5
FT
1348
1349 /* self-refresh seems busted with untiled */
24edb884 1350 if (obj->tiling_mode == I915_TILING_NONE)
ba55f2f5
FT
1351 enabled = NULL;
1352 }
1353
87f57070
FT
1354 /*
1355 * Overlay gets an aggressive default since video jitter is bad.
1356 */
1357 cwm = 2;
1358
1359 /* Play safe and disable self-refresh before adjusting watermarks. */
24edb884 1360 intel_set_memory_cxsr(dev_priv, false);
87f57070
FT
1361
1362 /* Calc sr entries for one plane configs */
1363 if (HAS_FW_BLC(dev) && enabled) {
1364 /* self-refresh has much higher latency */
1365 static const int sr_latency_ns = 6000;
9edbd4a0 1366 const struct drm_display_mode *adjusted_mode =
2c9916cd 1367 &to_intel_crtc(enabled)->config->base.adjusted_mode;
9edbd4a0
FT
1368 int clock = adjusted_mode->crtc_clock;
1369 int htotal = adjusted_mode->crtc_htotal;
2c9916cd 1370 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
477eb7f9 1371 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
87f57070
FT
1372 unsigned long line_time_us;
1373 int entries;
1374
ba55f2f5 1375 line_time_us = max(htotal * 1000 / clock, 1);
87f57070
FT
1376
1377 /* Use ns/us then divide to preserve precision */
1378 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1379 pixel_size * hdisplay;
c0bdd5d9 1380 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
87f57070
FT
1381 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1382 srwm = wm_info->fifo_size - entries;
1383 if (srwm < 0)
1384 srwm = 1;
1385
1386 if (IS_I945G(dev) || IS_I945GM(dev))
1387 I915_WRITE(FW_BLC_SELF,
1388 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1389 else if (IS_I915GM(dev))
1390 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1391 }
1392
1393 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1394 planea_wm, planeb_wm, cwm, srwm);
1395
1396 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1397 fwater_hi = (cwm & 0x1f);
1398
1399 /* Set request length to 8 cachelines per fetch */
1400 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1401 fwater_hi = fwater_hi | (1 << 8);
1402
1403 I915_WRITE(FW_BLC, fwater_lo);
1404 I915_WRITE(FW_BLC2, fwater_hi);
1405
24edb884
FT
1406 if (enabled)
1407 intel_set_memory_cxsr(dev_priv, true);
87f57070
FT
1408}
1409
9edbd4a0 1410static void i845_update_wm(struct drm_crtc *unused_crtc)
87f57070 1411{
9edbd4a0 1412 struct drm_device *dev = unused_crtc->dev;
87f57070
FT
1413 struct drm_i915_private *dev_priv = dev->dev_private;
1414 struct drm_crtc *crtc;
9edbd4a0 1415 const struct drm_display_mode *adjusted_mode;
87f57070
FT
1416 uint32_t fwater_lo;
1417 int planea_wm;
1418
1419 crtc = single_enabled_crtc(dev);
1420 if (crtc == NULL)
1421 return;
1422
2c9916cd 1423 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
9edbd4a0
FT
1424 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1425 &i845_wm_info,
87f57070 1426 dev_priv->display.get_fifo_size(dev, 0),
1b13d190 1427 4, pessimal_latency_ns);
87f57070
FT
1428 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1429 fwater_lo |= (3<<8) | planea_wm;
1430
1431 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1432
1433 I915_WRITE(FW_BLC, fwater_lo);
1434}
1435
9edbd4a0
FT
1436static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1437 struct drm_crtc *crtc)
5d0b1887
FT
1438{
1439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9edbd4a0 1440 uint32_t pixel_rate;
5d0b1887 1441
2c9916cd 1442 pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock;
5d0b1887
FT
1443
1444 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1445 * adjust the pixel_rate here. */
1446
2c9916cd 1447 if (intel_crtc->config->pch_pfit.enabled) {
5d0b1887 1448 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2c9916cd 1449 uint32_t pfit_size = intel_crtc->config->pch_pfit.size;
5d0b1887 1450
2c9916cd
FT
1451 pipe_w = intel_crtc->config->pipe_src_w;
1452 pipe_h = intel_crtc->config->pipe_src_h;
5d0b1887
FT
1453 pfit_w = (pfit_size >> 16) & 0xFFFF;
1454 pfit_h = pfit_size & 0xFFFF;
1455 if (pipe_w < pfit_w)
1456 pipe_w = pfit_w;
1457 if (pipe_h < pfit_h)
1458 pipe_h = pfit_h;
1459
1460 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1461 pfit_w * pfit_h);
1462 }
1463
1464 return pixel_rate;
1465}
1466
9edbd4a0
FT
1467/* latency must be in 0.1us units. */
1468static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
5d0b1887
FT
1469 uint32_t latency)
1470{
1471 uint64_t ret;
1472
9edbd4a0
FT
1473 if (WARN(latency == 0, "Latency value missing\n"))
1474 return UINT_MAX;
1475
5d0b1887
FT
1476 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1477 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1478
1479 return ret;
1480}
1481
9edbd4a0
FT
1482/* latency must be in 0.1us units. */
1483static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
5d0b1887
FT
1484 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1485 uint32_t latency)
1486{
1487 uint32_t ret;
1488
9edbd4a0
FT
1489 if (WARN(latency == 0, "Latency value missing\n"))
1490 return UINT_MAX;
1491
5d0b1887
FT
1492 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1493 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1494 ret = DIV_ROUND_UP(ret, 64) + 2;
1495 return ret;
1496}
1497
9edbd4a0 1498static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
5d0b1887
FT
1499 uint8_t bytes_per_pixel)
1500{
1501 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1502}
1503
2c9916cd
FT
1504struct skl_pipe_wm_parameters {
1505 bool active;
1506 uint32_t pipe_htotal;
1507 uint32_t pixel_rate; /* in KHz */
1508 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1509 struct intel_plane_wm_parameters cursor;
1510};
1511
9edbd4a0 1512struct ilk_pipe_wm_parameters {
5d0b1887 1513 bool active;
5d0b1887
FT
1514 uint32_t pipe_htotal;
1515 uint32_t pixel_rate;
9edbd4a0
FT
1516 struct intel_plane_wm_parameters pri;
1517 struct intel_plane_wm_parameters spr;
1518 struct intel_plane_wm_parameters cur;
5d0b1887
FT
1519};
1520
9edbd4a0 1521struct ilk_wm_maximums {
5d0b1887
FT
1522 uint16_t pri;
1523 uint16_t spr;
1524 uint16_t cur;
1525 uint16_t fbc;
1526};
1527
9edbd4a0
FT
1528/* used in computing the new watermarks state */
1529struct intel_wm_config {
1530 unsigned int num_pipes_active;
1531 bool sprites_enabled;
1532 bool sprites_scaled;
5d0b1887
FT
1533};
1534
9edbd4a0
FT
1535/*
1536 * For both WM_PIPE and WM_LP.
1537 * mem_value must be in 0.1us units.
1538 */
1539static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
5d0b1887
FT
1540 uint32_t mem_value,
1541 bool is_lp)
1542{
1543 uint32_t method1, method2;
1544
9edbd4a0 1545 if (!params->active || !params->pri.enabled)
5d0b1887
FT
1546 return 0;
1547
9edbd4a0
FT
1548 method1 = ilk_wm_method1(params->pixel_rate,
1549 params->pri.bytes_per_pixel,
5d0b1887
FT
1550 mem_value);
1551
1552 if (!is_lp)
1553 return method1;
1554
9edbd4a0 1555 method2 = ilk_wm_method2(params->pixel_rate,
5d0b1887 1556 params->pipe_htotal,
9edbd4a0
FT
1557 params->pri.horiz_pixels,
1558 params->pri.bytes_per_pixel,
5d0b1887
FT
1559 mem_value);
1560
1561 return min(method1, method2);
1562}
1563
9edbd4a0
FT
1564/*
1565 * For both WM_PIPE and WM_LP.
1566 * mem_value must be in 0.1us units.
1567 */
1568static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
5d0b1887
FT
1569 uint32_t mem_value)
1570{
1571 uint32_t method1, method2;
1572
9edbd4a0 1573 if (!params->active || !params->spr.enabled)
5d0b1887
FT
1574 return 0;
1575
9edbd4a0
FT
1576 method1 = ilk_wm_method1(params->pixel_rate,
1577 params->spr.bytes_per_pixel,
5d0b1887 1578 mem_value);
9edbd4a0 1579 method2 = ilk_wm_method2(params->pixel_rate,
5d0b1887 1580 params->pipe_htotal,
9edbd4a0
FT
1581 params->spr.horiz_pixels,
1582 params->spr.bytes_per_pixel,
5d0b1887
FT
1583 mem_value);
1584 return min(method1, method2);
1585}
1586
9edbd4a0
FT
1587/*
1588 * For both WM_PIPE and WM_LP.
1589 * mem_value must be in 0.1us units.
1590 */
1591static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
5d0b1887
FT
1592 uint32_t mem_value)
1593{
9edbd4a0 1594 if (!params->active || !params->cur.enabled)
5d0b1887
FT
1595 return 0;
1596
9edbd4a0 1597 return ilk_wm_method2(params->pixel_rate,
5d0b1887 1598 params->pipe_htotal,
9edbd4a0
FT
1599 params->cur.horiz_pixels,
1600 params->cur.bytes_per_pixel,
5d0b1887
FT
1601 mem_value);
1602}
1603
1604/* Only for WM_LP. */
9edbd4a0
FT
1605static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1606 uint32_t pri_val)
5d0b1887 1607{
9edbd4a0 1608 if (!params->active || !params->pri.enabled)
5d0b1887
FT
1609 return 0;
1610
9edbd4a0
FT
1611 return ilk_wm_fbc(pri_val,
1612 params->pri.horiz_pixels,
1613 params->pri.bytes_per_pixel);
5d0b1887
FT
1614}
1615
9edbd4a0 1616static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
5d0b1887 1617{
9edbd4a0
FT
1618 if (INTEL_INFO(dev)->gen >= 8)
1619 return 3072;
1620 else if (INTEL_INFO(dev)->gen >= 7)
1621 return 768;
1622 else
1623 return 512;
1624}
5d0b1887 1625
ba55f2f5
FT
1626static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1627 int level, bool is_sprite)
1628{
1629 if (INTEL_INFO(dev)->gen >= 8)
1630 /* BDW primary/sprite plane watermarks */
1631 return level == 0 ? 255 : 2047;
1632 else if (INTEL_INFO(dev)->gen >= 7)
1633 /* IVB/HSW primary/sprite plane watermarks */
1634 return level == 0 ? 127 : 1023;
1635 else if (!is_sprite)
1636 /* ILK/SNB primary plane watermarks */
1637 return level == 0 ? 127 : 511;
1638 else
1639 /* ILK/SNB sprite plane watermarks */
1640 return level == 0 ? 63 : 255;
1641}
1642
1643static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1644 int level)
1645{
1646 if (INTEL_INFO(dev)->gen >= 7)
1647 return level == 0 ? 63 : 255;
1648 else
1649 return level == 0 ? 31 : 63;
1650}
1651
1652static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1653{
1654 if (INTEL_INFO(dev)->gen >= 8)
1655 return 31;
1656 else
1657 return 15;
1658}
1659
9edbd4a0
FT
1660/* Calculate the maximum primary/sprite plane watermark */
1661static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1662 int level,
1663 const struct intel_wm_config *config,
1664 enum intel_ddb_partitioning ddb_partitioning,
1665 bool is_sprite)
1666{
1667 unsigned int fifo_size = ilk_display_fifo_size(dev);
5d0b1887 1668
9edbd4a0
FT
1669 /* if sprites aren't enabled, sprites get nothing */
1670 if (is_sprite && !config->sprites_enabled)
1671 return 0;
5d0b1887 1672
9edbd4a0
FT
1673 /* HSW allows LP1+ watermarks even with multiple pipes */
1674 if (level == 0 || config->num_pipes_active > 1) {
1675 fifo_size /= INTEL_INFO(dev)->num_pipes;
5d0b1887 1676
9edbd4a0
FT
1677 /*
1678 * For some reason the non self refresh
1679 * FIFO size is only half of the self
1680 * refresh FIFO size on ILK/SNB.
1681 */
1682 if (INTEL_INFO(dev)->gen <= 6)
1683 fifo_size /= 2;
5d0b1887
FT
1684 }
1685
9edbd4a0
FT
1686 if (config->sprites_enabled) {
1687 /* level 0 is always calculated with 1:1 split */
1688 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1689 if (is_sprite)
1690 fifo_size *= 5;
1691 fifo_size /= 6;
1692 } else {
1693 fifo_size /= 2;
1694 }
1695 }
1696
1697 /* clamp to max that the registers can hold */
ba55f2f5 1698 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
5d0b1887
FT
1699}
1700
9edbd4a0
FT
1701/* Calculate the maximum cursor plane watermark */
1702static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1703 int level,
1704 const struct intel_wm_config *config)
5d0b1887 1705{
9edbd4a0
FT
1706 /* HSW LP1+ watermarks w/ multiple pipes */
1707 if (level > 0 && config->num_pipes_active > 1)
1708 return 64;
5d0b1887 1709
9edbd4a0 1710 /* otherwise just report max that registers can hold */
ba55f2f5 1711 return ilk_cursor_wm_reg_max(dev, level);
9edbd4a0 1712}
5d0b1887 1713
ba55f2f5 1714static void ilk_compute_wm_maximums(const struct drm_device *dev,
9edbd4a0
FT
1715 int level,
1716 const struct intel_wm_config *config,
1717 enum intel_ddb_partitioning ddb_partitioning,
1718 struct ilk_wm_maximums *max)
1719{
1720 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1721 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1722 max->cur = ilk_cursor_wm_max(dev, level, config);
ba55f2f5
FT
1723 max->fbc = ilk_fbc_wm_reg_max(dev);
1724}
1725
1726static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1727 int level,
1728 struct ilk_wm_maximums *max)
1729{
1730 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1731 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1732 max->cur = ilk_cursor_wm_reg_max(dev, level);
1733 max->fbc = ilk_fbc_wm_reg_max(dev);
9edbd4a0
FT
1734}
1735
1736static bool ilk_validate_wm_level(int level,
1737 const struct ilk_wm_maximums *max,
1738 struct intel_wm_level *result)
1739{
1740 bool ret;
1741
1742 /* already determined to be invalid? */
1743 if (!result->enable)
1744 return false;
1745
1746 result->enable = result->pri_val <= max->pri &&
1747 result->spr_val <= max->spr &&
1748 result->cur_val <= max->cur;
1749
1750 ret = result->enable;
1751
1752 /*
1753 * HACK until we can pre-compute everything,
1754 * and thus fail gracefully if LP0 watermarks
1755 * are exceeded...
1756 */
1757 if (level == 0 && !result->enable) {
1758 if (result->pri_val > max->pri)
1759 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1760 level, result->pri_val, max->pri);
1761 if (result->spr_val > max->spr)
1762 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1763 level, result->spr_val, max->spr);
1764 if (result->cur_val > max->cur)
1765 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1766 level, result->cur_val, max->cur);
1767
1768 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1769 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1770 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1771 result->enable = true;
1772 }
1773
1774 return ret;
1775}
1776
ba55f2f5 1777static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
9edbd4a0
FT
1778 int level,
1779 const struct ilk_pipe_wm_parameters *p,
1780 struct intel_wm_level *result)
1781{
1782 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1783 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1784 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1785
1786 /* WM1+ latency values stored in 0.5us units */
1787 if (level > 0) {
1788 pri_latency *= 5;
1789 spr_latency *= 5;
1790 cur_latency *= 5;
1791 }
1792
1793 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1794 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1795 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1796 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1797 result->enable = true;
5d0b1887
FT
1798}
1799
1800static uint32_t
1801hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
0db36e9f
FT
1802{
1803 struct drm_i915_private *dev_priv = dev->dev_private;
5d0b1887 1804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c9916cd 1805 struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
5d0b1887 1806 u32 linetime, ips_linetime;
0db36e9f 1807
477eb7f9 1808 if (!intel_crtc->active)
5d0b1887 1809 return 0;
0db36e9f
FT
1810
1811 /* The WM are computed with base on how long it takes to fill a single
1812 * row at the given clock rate, multiplied by 8.
1813 * */
9edbd4a0
FT
1814 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1815 mode->crtc_clock);
1816 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
19c468b4 1817 dev_priv->display.get_display_clock_speed(dev_priv->dev));
0db36e9f 1818
5d0b1887
FT
1819 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
1820 PIPE_WM_LINETIME_TIME(linetime);
1821}
1822
2c9916cd 1823static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
5d0b1887
FT
1824{
1825 struct drm_i915_private *dev_priv = dev->dev_private;
5d0b1887 1826
2c9916cd
FT
1827 if (IS_GEN9(dev)) {
1828 uint32_t val;
1829 int ret, i;
1830 int level, max_level = ilk_wm_max_level(dev);
9edbd4a0 1831
2c9916cd
FT
1832 /* read the first set of memory latencies[0:3] */
1833 val = 0; /* data0 to be programmed to 0 for first set */
1834 mutex_lock(&dev_priv->rps.hw_lock);
1835 ret = sandybridge_pcode_read(dev_priv,
1836 GEN9_PCODE_READ_MEM_LATENCY,
1837 &val);
1838 mutex_unlock(&dev_priv->rps.hw_lock);
1839
1840 if (ret) {
1841 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1842 return;
1843 }
1844
1845 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1846 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1847 GEN9_MEM_LATENCY_LEVEL_MASK;
1848 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1849 GEN9_MEM_LATENCY_LEVEL_MASK;
1850 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1851 GEN9_MEM_LATENCY_LEVEL_MASK;
1852
1853 /* read the second set of memory latencies[4:7] */
1854 val = 1; /* data0 to be programmed to 1 for second set */
1855 mutex_lock(&dev_priv->rps.hw_lock);
1856 ret = sandybridge_pcode_read(dev_priv,
1857 GEN9_PCODE_READ_MEM_LATENCY,
1858 &val);
1859 mutex_unlock(&dev_priv->rps.hw_lock);
1860 if (ret) {
1861 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1862 return;
1863 }
1864
1865 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1866 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1867 GEN9_MEM_LATENCY_LEVEL_MASK;
1868 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1869 GEN9_MEM_LATENCY_LEVEL_MASK;
1870 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1871 GEN9_MEM_LATENCY_LEVEL_MASK;
1872
1873 /*
477eb7f9
FT
1874 * WaWmMemoryReadLatency:skl
1875 *
2c9916cd
FT
1876 * punit doesn't take into account the read latency so we need
1877 * to add 2us to the various latency levels we retrieve from
1878 * the punit.
1879 * - W0 is a bit special in that it's the only level that
1880 * can't be disabled if we want to have display working, so
1881 * we always add 2us there.
1882 * - For levels >=1, punit returns 0us latency when they are
1883 * disabled, so we respect that and don't add 2us then
1884 *
1885 * Additionally, if a level n (n > 1) has a 0us latency, all
1886 * levels m (m >= n) need to be disabled. We make sure to
1887 * sanitize the values out of the punit to satisfy this
1888 * requirement.
1889 */
1890 wm[0] += 2;
1891 for (level = 1; level <= max_level; level++)
1892 if (wm[level] != 0)
1893 wm[level] += 2;
1894 else {
1895 for (i = level + 1; i <= max_level; i++)
1896 wm[i] = 0;
1897
1898 break;
1899 }
1900 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1901 uint64_t sskpd = I915_READ64(MCH_SSKPD);
1902
1903 wm[0] = (sskpd >> 56) & 0xFF;
1904 if (wm[0] == 0)
1905 wm[0] = sskpd & 0xF;
1906 wm[1] = (sskpd >> 4) & 0xFF;
1907 wm[2] = (sskpd >> 12) & 0xFF;
9edbd4a0
FT
1908 wm[3] = (sskpd >> 20) & 0x1FF;
1909 wm[4] = (sskpd >> 32) & 0x1FF;
1910 } else if (INTEL_INFO(dev)->gen >= 6) {
1911 uint32_t sskpd = I915_READ(MCH_SSKPD);
1912
1913 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
1914 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
1915 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
1916 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
1917 } else if (INTEL_INFO(dev)->gen >= 5) {
1918 uint32_t mltr = I915_READ(MLTR_ILK);
1919
1920 /* ILK primary LP0 latency is 700 ns */
1921 wm[0] = 7;
1922 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
1923 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
1924 }
1925}
1926
1927static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
1928{
1929 /* ILK sprite LP0 latency is 1300 ns */
1930 if (INTEL_INFO(dev)->gen == 5)
1931 wm[0] = 13;
1932}
1933
1934static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
1935{
1936 /* ILK cursor LP0 latency is 1300 ns */
1937 if (INTEL_INFO(dev)->gen == 5)
1938 wm[0] = 13;
1939
1940 /* WaDoubleCursorLP3Latency:ivb */
1941 if (IS_IVYBRIDGE(dev))
1942 wm[3] *= 2;
1943}
1944
ba55f2f5 1945int ilk_wm_max_level(const struct drm_device *dev)
9edbd4a0
FT
1946{
1947 /* how many WM levels are we expecting */
19c468b4 1948 if (INTEL_INFO(dev)->gen >= 9)
2c9916cd
FT
1949 return 7;
1950 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9edbd4a0
FT
1951 return 4;
1952 else if (INTEL_INFO(dev)->gen >= 6)
1953 return 3;
5d0b1887 1954 else
9edbd4a0
FT
1955 return 2;
1956}
5d0b1887 1957
9edbd4a0
FT
1958static void intel_print_wm_latency(struct drm_device *dev,
1959 const char *name,
2c9916cd 1960 const uint16_t wm[8])
9edbd4a0
FT
1961{
1962 int level, max_level = ilk_wm_max_level(dev);
5d0b1887 1963
9edbd4a0
FT
1964 for (level = 0; level <= max_level; level++) {
1965 unsigned int latency = wm[level];
5d0b1887 1966
9edbd4a0
FT
1967 if (latency == 0) {
1968 DRM_ERROR("%s WM%d latency not provided\n",
1969 name, level);
5d0b1887 1970 continue;
9edbd4a0 1971 }
5d0b1887 1972
2c9916cd
FT
1973 /*
1974 * - latencies are in us on gen9.
1975 * - before then, WM1+ latency values are in 0.5us units
1976 */
1977 if (IS_GEN9(dev))
1978 latency *= 10;
1979 else if (level > 0)
9edbd4a0 1980 latency *= 5;
5d0b1887 1981
9edbd4a0
FT
1982 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
1983 name, level, wm[level],
1984 latency / 10, latency % 10);
5d0b1887 1985 }
9edbd4a0 1986}
5d0b1887 1987
ba55f2f5
FT
1988static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
1989 uint16_t wm[5], uint16_t min)
1990{
1991 int level, max_level = ilk_wm_max_level(dev_priv->dev);
1992
1993 if (wm[0] >= min)
1994 return false;
1995
1996 wm[0] = max(wm[0], min);
1997 for (level = 1; level <= max_level; level++)
1998 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
1999
2000 return true;
2001}
2002
2003static void snb_wm_latency_quirk(struct drm_device *dev)
2004{
2005 struct drm_i915_private *dev_priv = dev->dev_private;
2006 bool changed;
2007
2008 /*
2009 * The BIOS provided WM memory latency values are often
2010 * inadequate for high resolution displays. Adjust them.
2011 */
2012 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2013 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2014 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2015
2016 if (!changed)
2017 return;
2018
2019 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2020 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2021 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2022 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2023}
2024
2025static void ilk_setup_wm_latency(struct drm_device *dev)
9edbd4a0
FT
2026{
2027 struct drm_i915_private *dev_priv = dev->dev_private;
2028
2029 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
5d0b1887 2030
9edbd4a0
FT
2031 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2032 sizeof(dev_priv->wm.pri_latency));
2033 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2034 sizeof(dev_priv->wm.pri_latency));
5d0b1887 2035
9edbd4a0
FT
2036 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2037 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
5d0b1887 2038
9edbd4a0
FT
2039 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2040 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2041 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
ba55f2f5
FT
2042
2043 if (IS_GEN6(dev))
2044 snb_wm_latency_quirk(dev);
9edbd4a0
FT
2045}
2046
2c9916cd
FT
2047static void skl_setup_wm_latency(struct drm_device *dev)
2048{
2049 struct drm_i915_private *dev_priv = dev->dev_private;
2050
2051 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2052 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2053}
2054
9edbd4a0 2055static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
ba55f2f5 2056 struct ilk_pipe_wm_parameters *p)
9edbd4a0
FT
2057{
2058 struct drm_device *dev = crtc->dev;
2059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2060 enum i915_pipe pipe = intel_crtc->pipe;
2061 struct drm_plane *plane;
2062
477eb7f9 2063 if (!intel_crtc->active)
ba55f2f5 2064 return;
9edbd4a0 2065
ba55f2f5 2066 p->active = true;
2c9916cd 2067 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
ba55f2f5 2068 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
477eb7f9
FT
2069
2070 if (crtc->primary->state->fb)
2071 p->pri.bytes_per_pixel =
2072 crtc->primary->state->fb->bits_per_pixel / 8;
2073 else
2074 p->pri.bytes_per_pixel = 4;
2075
ba55f2f5 2076 p->cur.bytes_per_pixel = 4;
477eb7f9
FT
2077 /*
2078 * TODO: for now, assume primary and cursor planes are always enabled.
2079 * Setting them to false makes the screen flicker.
2080 */
ba55f2f5
FT
2081 p->pri.enabled = true;
2082 p->cur.enabled = true;
2083
477eb7f9
FT
2084 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
2085 p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
2086
ba55f2f5 2087 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
9edbd4a0
FT
2088 struct intel_plane *intel_plane = to_intel_plane(plane);
2089
ba55f2f5 2090 if (intel_plane->pipe == pipe) {
9edbd4a0 2091 p->spr = intel_plane->wm;
ba55f2f5
FT
2092 break;
2093 }
2094 }
2095}
2096
2097static void ilk_compute_wm_config(struct drm_device *dev,
2098 struct intel_wm_config *config)
2099{
2100 struct intel_crtc *intel_crtc;
2101
2102 /* Compute the currently _active_ config */
2103 for_each_intel_crtc(dev, intel_crtc) {
2104 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2105
2106 if (!wm->pipe_enabled)
2107 continue;
9edbd4a0 2108
ba55f2f5
FT
2109 config->sprites_enabled |= wm->sprites_enabled;
2110 config->sprites_scaled |= wm->sprites_scaled;
2111 config->num_pipes_active++;
5d0b1887 2112 }
5d0b1887
FT
2113}
2114
9edbd4a0
FT
2115/* Compute new watermarks for the pipe */
2116static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2117 const struct ilk_pipe_wm_parameters *params,
2118 struct intel_pipe_wm *pipe_wm)
5d0b1887 2119{
9edbd4a0 2120 struct drm_device *dev = crtc->dev;
ba55f2f5 2121 const struct drm_i915_private *dev_priv = dev->dev_private;
9edbd4a0
FT
2122 int level, max_level = ilk_wm_max_level(dev);
2123 /* LP0 watermark maximums depend on this pipe alone */
2124 struct intel_wm_config config = {
2125 .num_pipes_active = 1,
2126 .sprites_enabled = params->spr.enabled,
2127 .sprites_scaled = params->spr.scaled,
2128 };
2129 struct ilk_wm_maximums max;
5d0b1887 2130
ba55f2f5
FT
2131 pipe_wm->pipe_enabled = params->active;
2132 pipe_wm->sprites_enabled = params->spr.enabled;
2133 pipe_wm->sprites_scaled = params->spr.scaled;
9edbd4a0
FT
2134
2135 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2136 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2137 max_level = 1;
2138
2139 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2140 if (params->spr.scaled)
2141 max_level = 0;
2142
ba55f2f5 2143 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
5d0b1887 2144
9edbd4a0
FT
2145 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2146 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2147
ba55f2f5
FT
2148 /* LP0 watermarks always use 1/2 DDB partitioning */
2149 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2150
9edbd4a0 2151 /* At least LP0 must be valid */
ba55f2f5
FT
2152 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2153 return false;
2154
2155 ilk_compute_wm_reg_maximums(dev, 1, &max);
2156
2157 for (level = 1; level <= max_level; level++) {
2158 struct intel_wm_level wm = {};
2159
2160 ilk_compute_wm_level(dev_priv, level, params, &wm);
2161
2162 /*
2163 * Disable any watermark level that exceeds the
2164 * register maximums since such watermarks are
2165 * always invalid.
2166 */
2167 if (!ilk_validate_wm_level(level, &max, &wm))
2168 break;
2169
2170 pipe_wm->wm[level] = wm;
2171 }
2172
2173 return true;
9edbd4a0
FT
2174}
2175
2176/*
2177 * Merge the watermarks from all active pipes for a specific level.
2178 */
2179static void ilk_merge_wm_level(struct drm_device *dev,
2180 int level,
2181 struct intel_wm_level *ret_wm)
2182{
2183 struct intel_crtc *intel_crtc;
2184
ba55f2f5
FT
2185 ret_wm->enable = true;
2186
2187 for_each_intel_crtc(dev, intel_crtc) {
2188 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2189 const struct intel_wm_level *wm = &active->wm[level];
2190
2191 if (!active->pipe_enabled)
2192 continue;
9edbd4a0 2193
ba55f2f5
FT
2194 /*
2195 * The watermark values may have been used in the past,
2196 * so we must maintain them in the registers for some
2197 * time even if the level is now disabled.
2198 */
9edbd4a0 2199 if (!wm->enable)
ba55f2f5 2200 ret_wm->enable = false;
9edbd4a0
FT
2201
2202 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2203 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2204 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2205 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2206 }
9edbd4a0
FT
2207}
2208
2209/*
2210 * Merge all low power watermarks for all active pipes.
2211 */
2212static void ilk_wm_merge(struct drm_device *dev,
2213 const struct intel_wm_config *config,
2214 const struct ilk_wm_maximums *max,
2215 struct intel_pipe_wm *merged)
2216{
2217 int level, max_level = ilk_wm_max_level(dev);
ba55f2f5 2218 int last_enabled_level = max_level;
9edbd4a0
FT
2219
2220 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2221 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2222 config->num_pipes_active > 1)
2223 return;
2224
2225 /* ILK: FBC WM must be disabled always */
2226 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2227
2228 /* merge each WM1+ level */
5d0b1887 2229 for (level = 1; level <= max_level; level++) {
9edbd4a0
FT
2230 struct intel_wm_level *wm = &merged->wm[level];
2231
2232 ilk_merge_wm_level(dev, level, wm);
2233
ba55f2f5
FT
2234 if (level > last_enabled_level)
2235 wm->enable = false;
2236 else if (!ilk_validate_wm_level(level, max, wm))
2237 /* make sure all following levels get disabled */
2238 last_enabled_level = level - 1;
9edbd4a0
FT
2239
2240 /*
2241 * The spec says it is preferred to disable
2242 * FBC WMs instead of disabling a WM level.
2243 */
2244 if (wm->fbc_val > max->fbc) {
ba55f2f5
FT
2245 if (wm->enable)
2246 merged->fbc_wm_enabled = false;
9edbd4a0 2247 wm->fbc_val = 0;
5d0b1887
FT
2248 }
2249 }
2250
9edbd4a0
FT
2251 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2252 /*
2253 * FIXME this is racy. FBC might get enabled later.
2254 * What we should check here is whether FBC can be
2255 * enabled sometime later.
2256 */
2257 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2258 for (level = 2; level <= max_level; level++) {
2259 struct intel_wm_level *wm = &merged->wm[level];
2260
2261 wm->enable = false;
2262 }
2263 }
2264}
2265
2266static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2267{
2268 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2269 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2270}
2271
2272/* The value we need to program into the WM_LPx latency field */
2273static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2274{
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2276
2277 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2278 return 2 * level;
2279 else
2280 return dev_priv->wm.pri_latency[level];
2281}
2282
2283static void ilk_compute_wm_results(struct drm_device *dev,
2284 const struct intel_pipe_wm *merged,
2285 enum intel_ddb_partitioning partitioning,
2286 struct ilk_wm_values *results)
2287{
2288 struct intel_crtc *intel_crtc;
2289 int level, wm_lp;
2290
2291 results->enable_fbc_wm = merged->fbc_wm_enabled;
2292 results->partitioning = partitioning;
2293
2294 /* LP1+ register values */
5d0b1887 2295 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
9edbd4a0 2296 const struct intel_wm_level *r;
5d0b1887 2297
9edbd4a0
FT
2298 level = ilk_wm_lp_to_level(wm_lp, merged);
2299
2300 r = &merged->wm[level];
5d0b1887 2301
ba55f2f5
FT
2302 /*
2303 * Maintain the watermark values even if the level is
2304 * disabled. Doing otherwise could cause underruns.
2305 */
2306 results->wm_lp[wm_lp - 1] =
9edbd4a0
FT
2307 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2308 (r->pri_val << WM1_LP_SR_SHIFT) |
2309 r->cur_val;
2310
ba55f2f5
FT
2311 if (r->enable)
2312 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2313
9edbd4a0
FT
2314 if (INTEL_INFO(dev)->gen >= 8)
2315 results->wm_lp[wm_lp - 1] |=
2316 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2317 else
2318 results->wm_lp[wm_lp - 1] |=
2319 r->fbc_val << WM1_LP_FBC_SHIFT;
2320
ba55f2f5
FT
2321 /*
2322 * Always set WM1S_LP_EN when spr_val != 0, even if the
2323 * level is disabled. Doing otherwise could cause underruns.
2324 */
9edbd4a0
FT
2325 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2326 WARN_ON(wm_lp != 1);
2327 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2328 } else
2329 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
5d0b1887
FT
2330 }
2331
9edbd4a0 2332 /* LP0 register values */
ba55f2f5 2333 for_each_intel_crtc(dev, intel_crtc) {
9edbd4a0
FT
2334 enum i915_pipe pipe = intel_crtc->pipe;
2335 const struct intel_wm_level *r =
2336 &intel_crtc->wm.active.wm[0];
5d0b1887 2337
9edbd4a0
FT
2338 if (WARN_ON(!r->enable))
2339 continue;
2340
2341 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2342
2343 results->wm_pipe[pipe] =
2344 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2345 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2346 r->cur_val;
5d0b1887
FT
2347 }
2348}
2349
2350/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2351 * case both are at the same level. Prefer r1 in case they're the same. */
9edbd4a0
FT
2352static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2353 struct intel_pipe_wm *r1,
2354 struct intel_pipe_wm *r2)
5d0b1887 2355{
9edbd4a0
FT
2356 int level, max_level = ilk_wm_max_level(dev);
2357 int level1 = 0, level2 = 0;
5d0b1887 2358
9edbd4a0
FT
2359 for (level = 1; level <= max_level; level++) {
2360 if (r1->wm[level].enable)
2361 level1 = level;
2362 if (r2->wm[level].enable)
2363 level2 = level;
5d0b1887
FT
2364 }
2365
9edbd4a0
FT
2366 if (level1 == level2) {
2367 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
5d0b1887
FT
2368 return r2;
2369 else
2370 return r1;
9edbd4a0 2371 } else if (level1 > level2) {
5d0b1887
FT
2372 return r1;
2373 } else {
2374 return r2;
2375 }
2376}
2377
9edbd4a0
FT
2378/* dirty bits used to track which watermarks need changes */
2379#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2380#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2381#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2382#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2383#define WM_DIRTY_FBC (1 << 24)
2384#define WM_DIRTY_DDB (1 << 25)
2385
1b13d190 2386static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
9edbd4a0
FT
2387 const struct ilk_wm_values *old,
2388 const struct ilk_wm_values *new)
2389{
2390 unsigned int dirty = 0;
2391 enum i915_pipe pipe;
2392 int wm_lp;
2393
1b13d190 2394 for_each_pipe(dev_priv, pipe) {
9edbd4a0
FT
2395 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2396 dirty |= WM_DIRTY_LINETIME(pipe);
2397 /* Must disable LP1+ watermarks too */
2398 dirty |= WM_DIRTY_LP_ALL;
2399 }
2400
2401 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2402 dirty |= WM_DIRTY_PIPE(pipe);
2403 /* Must disable LP1+ watermarks too */
2404 dirty |= WM_DIRTY_LP_ALL;
2405 }
2406 }
2407
2408 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2409 dirty |= WM_DIRTY_FBC;
2410 /* Must disable LP1+ watermarks too */
2411 dirty |= WM_DIRTY_LP_ALL;
2412 }
2413
2414 if (old->partitioning != new->partitioning) {
2415 dirty |= WM_DIRTY_DDB;
2416 /* Must disable LP1+ watermarks too */
2417 dirty |= WM_DIRTY_LP_ALL;
2418 }
2419
2420 /* LP1+ watermarks already deemed dirty, no need to continue */
2421 if (dirty & WM_DIRTY_LP_ALL)
2422 return dirty;
2423
2424 /* Find the lowest numbered LP1+ watermark in need of an update... */
2425 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2426 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2427 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2428 break;
2429 }
2430
2431 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2432 for (; wm_lp <= 3; wm_lp++)
2433 dirty |= WM_DIRTY_LP(wm_lp);
2434
2435 return dirty;
2436}
2437
2438static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2439 unsigned int dirty)
2440{
2441 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2442 bool changed = false;
2443
2444 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2445 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2446 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2447 changed = true;
2448 }
2449 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2450 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2451 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2452 changed = true;
2453 }
2454 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2455 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2456 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2457 changed = true;
2458 }
2459
2460 /*
2461 * Don't touch WM1S_LP_EN here.
2462 * Doing so could cause underruns.
2463 */
2464
2465 return changed;
2466}
2467
5d0b1887
FT
2468/*
2469 * The spec says we shouldn't write when we don't need, because every write
2470 * causes WMs to be re-evaluated, expending some power.
2471 */
9edbd4a0
FT
2472static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2473 struct ilk_wm_values *results)
5d0b1887 2474{
9edbd4a0
FT
2475 struct drm_device *dev = dev_priv->dev;
2476 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2477 unsigned int dirty;
5d0b1887 2478 uint32_t val;
9edbd4a0 2479
1b13d190 2480 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
9edbd4a0 2481 if (!dirty)
5d0b1887
FT
2482 return;
2483
9edbd4a0 2484 _ilk_disable_lp_wm(dev_priv, dirty);
5d0b1887 2485
9edbd4a0 2486 if (dirty & WM_DIRTY_PIPE(PIPE_A))
5d0b1887 2487 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
9edbd4a0 2488 if (dirty & WM_DIRTY_PIPE(PIPE_B))
5d0b1887 2489 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
9edbd4a0 2490 if (dirty & WM_DIRTY_PIPE(PIPE_C))
5d0b1887
FT
2491 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2492
9edbd4a0 2493 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
5d0b1887 2494 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
9edbd4a0 2495 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
5d0b1887 2496 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
9edbd4a0 2497 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
5d0b1887
FT
2498 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2499
9edbd4a0
FT
2500 if (dirty & WM_DIRTY_DDB) {
2501 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2502 val = I915_READ(WM_MISC);
2503 if (results->partitioning == INTEL_DDB_PART_1_2)
2504 val &= ~WM_MISC_DATA_PARTITION_5_6;
2505 else
2506 val |= WM_MISC_DATA_PARTITION_5_6;
2507 I915_WRITE(WM_MISC, val);
2508 } else {
2509 val = I915_READ(DISP_ARB_CTL2);
2510 if (results->partitioning == INTEL_DDB_PART_1_2)
2511 val &= ~DISP_DATA_PARTITION_5_6;
2512 else
2513 val |= DISP_DATA_PARTITION_5_6;
2514 I915_WRITE(DISP_ARB_CTL2, val);
2515 }
5d0b1887
FT
2516 }
2517
9edbd4a0 2518 if (dirty & WM_DIRTY_FBC) {
5d0b1887
FT
2519 val = I915_READ(DISP_ARB_CTL);
2520 if (results->enable_fbc_wm)
2521 val &= ~DISP_FBC_WM_DIS;
2522 else
2523 val |= DISP_FBC_WM_DIS;
2524 I915_WRITE(DISP_ARB_CTL, val);
2525 }
2526
9edbd4a0
FT
2527 if (dirty & WM_DIRTY_LP(1) &&
2528 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
5d0b1887 2529 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
5d0b1887 2530
9edbd4a0
FT
2531 if (INTEL_INFO(dev)->gen >= 7) {
2532 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2533 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2534 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2535 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2536 }
2537
2538 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
5d0b1887 2539 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
9edbd4a0 2540 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
5d0b1887 2541 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
9edbd4a0 2542 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
5d0b1887 2543 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
9edbd4a0
FT
2544
2545 dev_priv->wm.hw = *results;
5d0b1887
FT
2546}
2547
9edbd4a0 2548static bool ilk_disable_lp_wm(struct drm_device *dev)
5d0b1887
FT
2549{
2550 struct drm_i915_private *dev_priv = dev->dev_private;
5d0b1887 2551
9edbd4a0 2552 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
5d0b1887
FT
2553}
2554
2c9916cd
FT
2555/*
2556 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2557 * different active planes.
2558 */
5d0b1887 2559
2c9916cd 2560#define SKL_DDB_SIZE 896 /* in blocks */
19c468b4 2561#define BXT_DDB_SIZE 512
5d0b1887 2562
2c9916cd
FT
2563static void
2564skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2565 struct drm_crtc *for_crtc,
2566 const struct intel_wm_config *config,
2567 const struct skl_pipe_wm_parameters *params,
2568 struct skl_ddb_entry *alloc /* out */)
2569{
2570 struct drm_crtc *crtc;
2571 unsigned int pipe_size, ddb_size;
2572 int nth_active_pipe;
0db36e9f 2573
2c9916cd
FT
2574 if (!params->active) {
2575 alloc->start = 0;
2576 alloc->end = 0;
9edbd4a0 2577 return;
2c9916cd 2578 }
0db36e9f 2579
19c468b4
FT
2580 if (IS_BROXTON(dev))
2581 ddb_size = BXT_DDB_SIZE;
2582 else
2583 ddb_size = SKL_DDB_SIZE;
87f57070 2584
2c9916cd 2585 ddb_size -= 4; /* 4 blocks for bypass path allocation */
ba55f2f5 2586
2c9916cd
FT
2587 nth_active_pipe = 0;
2588 for_each_crtc(dev, crtc) {
477eb7f9 2589 if (!to_intel_crtc(crtc)->active)
2c9916cd 2590 continue;
9edbd4a0 2591
2c9916cd
FT
2592 if (crtc == for_crtc)
2593 break;
9edbd4a0 2594
2c9916cd 2595 nth_active_pipe++;
87f57070
FT
2596 }
2597
2c9916cd
FT
2598 pipe_size = ddb_size / config->num_pipes_active;
2599 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2600 alloc->end = alloc->start + pipe_size;
2601}
87f57070 2602
2c9916cd
FT
2603static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2604{
2605 if (config->num_pipes_active == 1)
2606 return 32;
87f57070 2607
2c9916cd 2608 return 8;
87f57070
FT
2609}
2610
2c9916cd 2611static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
87f57070 2612{
2c9916cd
FT
2613 entry->start = reg & 0x3ff;
2614 entry->end = (reg >> 16) & 0x3ff;
2615 if (entry->end)
2616 entry->end += 1;
2617}
87f57070 2618
2c9916cd
FT
2619void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2620 struct skl_ddb_allocation *ddb /* out */)
2621{
2c9916cd
FT
2622 enum i915_pipe pipe;
2623 int plane;
2624 u32 val;
87f57070 2625
2c9916cd 2626 for_each_pipe(dev_priv, pipe) {
477eb7f9 2627 for_each_plane(dev_priv, pipe, plane) {
2c9916cd
FT
2628 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2629 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2630 val);
2631 }
87f57070 2632
2c9916cd
FT
2633 val = I915_READ(CUR_BUF_CFG(pipe));
2634 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2635 }
87f57070
FT
2636}
2637
2c9916cd 2638static unsigned int
19c468b4 2639skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
2c9916cd 2640{
19c468b4
FT
2641
2642 /* for planar format */
2643 if (p->y_bytes_per_pixel) {
2644 if (y) /* y-plane data rate */
2645 return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2646 else /* uv-plane data rate */
2647 return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2648 }
2649
2650 /* for packed formats */
2c9916cd
FT
2651 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2652}
2653
2654/*
2655 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2656 * a 8192x4096@32bpp framebuffer:
2657 * 3 * 4096 * 8192 * 4 < 2^32
2658 */
2659static unsigned int
2660skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2661 const struct skl_pipe_wm_parameters *params)
2662{
2663 unsigned int total_data_rate = 0;
2664 int plane;
2665
2666 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2667 const struct intel_plane_wm_parameters *p;
2668
2669 p = &params->plane[plane];
2670 if (!p->enabled)
2671 continue;
2672
19c468b4
FT
2673 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2674 if (p->y_bytes_per_pixel) {
2675 total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2676 }
2c9916cd
FT
2677 }
2678
2679 return total_data_rate;
2680}
2681
2682static void
2683skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2684 const struct intel_wm_config *config,
2685 const struct skl_pipe_wm_parameters *params,
2686 struct skl_ddb_allocation *ddb /* out */)
87f57070 2687{
9edbd4a0 2688 struct drm_device *dev = crtc->dev;
477eb7f9 2689 struct drm_i915_private *dev_priv = dev->dev_private;
9edbd4a0 2690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9edbd4a0 2691 enum i915_pipe pipe = intel_crtc->pipe;
2c9916cd
FT
2692 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2693 uint16_t alloc_size, start, cursor_blocks;
477eb7f9 2694 uint16_t minimum[I915_MAX_PLANES];
19c468b4 2695 uint16_t y_minimum[I915_MAX_PLANES];
2c9916cd
FT
2696 unsigned int total_data_rate;
2697 int plane;
2698
2699 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2700 alloc_size = skl_ddb_entry_size(alloc);
2701 if (alloc_size == 0) {
2702 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2703 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2704 return;
2705 }
87f57070 2706
2c9916cd
FT
2707 cursor_blocks = skl_cursor_allocation(config);
2708 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2709 ddb->cursor[pipe].end = alloc->end;
5d0b1887 2710
2c9916cd
FT
2711 alloc_size -= cursor_blocks;
2712 alloc->end -= cursor_blocks;
ba55f2f5 2713
477eb7f9
FT
2714 /* 1. Allocate the mininum required blocks for each active plane */
2715 for_each_plane(dev_priv, pipe, plane) {
2716 const struct intel_plane_wm_parameters *p;
2717
2718 p = &params->plane[plane];
2719 if (!p->enabled)
2720 continue;
2721
2722 minimum[plane] = 8;
2723 alloc_size -= minimum[plane];
19c468b4
FT
2724 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
2725 alloc_size -= y_minimum[plane];
477eb7f9
FT
2726 }
2727
2c9916cd 2728 /*
477eb7f9
FT
2729 * 2. Distribute the remaining space in proportion to the amount of
2730 * data each plane needs to fetch from memory.
2c9916cd
FT
2731 *
2732 * FIXME: we may not allocate every single block here.
2733 */
2734 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
87f57070 2735
2c9916cd
FT
2736 start = alloc->start;
2737 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2738 const struct intel_plane_wm_parameters *p;
19c468b4
FT
2739 unsigned int data_rate, y_data_rate;
2740 uint16_t plane_blocks, y_plane_blocks = 0;
2c9916cd
FT
2741
2742 p = &params->plane[plane];
2743 if (!p->enabled)
2744 continue;
2745
19c468b4 2746 data_rate = skl_plane_relative_data_rate(p, 0);
9edbd4a0
FT
2747
2748 /*
19c468b4 2749 * allocation for (packed formats) or (uv-plane part of planar format):
2c9916cd
FT
2750 * promote the expression to 64 bits to avoid overflowing, the
2751 * result is < available as data_rate / total_data_rate < 1
9edbd4a0 2752 */
477eb7f9
FT
2753 plane_blocks = minimum[plane];
2754 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2755 total_data_rate);
2c9916cd
FT
2756
2757 ddb->plane[pipe][plane].start = start;
2758 ddb->plane[pipe][plane].end = start + plane_blocks;
2759
2760 start += plane_blocks;
19c468b4
FT
2761
2762 /*
2763 * allocation for y_plane part of planar format:
2764 */
2765 if (p->y_bytes_per_pixel) {
2766 y_data_rate = skl_plane_relative_data_rate(p, 1);
2767 y_plane_blocks = y_minimum[plane];
2768 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
2769 total_data_rate);
2770
2771 ddb->y_plane[pipe][plane].start = start;
2772 ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
2773
2774 start += y_plane_blocks;
2775 }
2776
87f57070 2777 }
2c9916cd 2778
9edbd4a0 2779}
87f57070 2780
2c9916cd 2781static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
9edbd4a0 2782{
2c9916cd
FT
2783 /* TODO: Take into account the scalers once we support them */
2784 return config->base.adjusted_mode.crtc_clock;
2785}
87f57070 2786
2c9916cd
FT
2787/*
2788 * The max latency should be 257 (max the punit can code is 255 and we add 2us
2789 * for the read latency) and bytes_per_pixel should always be <= 8, so that
2790 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
2791 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
2792*/
2793static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2794 uint32_t latency)
2795{
2796 uint32_t wm_intermediate_val, ret;
87f57070 2797
2c9916cd
FT
2798 if (latency == 0)
2799 return UINT_MAX;
87f57070 2800
477eb7f9 2801 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2c9916cd 2802 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
87f57070 2803
2c9916cd 2804 return ret;
87f57070
FT
2805}
2806
2c9916cd
FT
2807static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2808 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
477eb7f9 2809 uint64_t tiling, uint32_t latency)
87f57070 2810{
477eb7f9
FT
2811 uint32_t ret;
2812 uint32_t plane_bytes_per_line, plane_blocks_per_line;
2813 uint32_t wm_intermediate_val;
87f57070 2814
2c9916cd
FT
2815 if (latency == 0)
2816 return UINT_MAX;
2817
2818 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
477eb7f9
FT
2819
2820 if (tiling == I915_FORMAT_MOD_Y_TILED ||
2821 tiling == I915_FORMAT_MOD_Yf_TILED) {
2822 plane_bytes_per_line *= 4;
2823 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2824 plane_blocks_per_line /= 4;
2825 } else {
2826 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2827 }
2828
2c9916cd
FT
2829 wm_intermediate_val = latency * pixel_rate;
2830 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
477eb7f9 2831 plane_blocks_per_line;
2c9916cd
FT
2832
2833 return ret;
87f57070
FT
2834}
2835
2c9916cd
FT
2836static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
2837 const struct intel_crtc *intel_crtc)
87f57070 2838{
2c9916cd
FT
2839 struct drm_device *dev = intel_crtc->base.dev;
2840 struct drm_i915_private *dev_priv = dev->dev_private;
2841 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2842 enum i915_pipe pipe = intel_crtc->pipe;
87f57070 2843
2c9916cd
FT
2844 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
2845 sizeof(new_ddb->plane[pipe])))
2846 return true;
2847
2848 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
2849 sizeof(new_ddb->cursor[pipe])))
2850 return true;
2851
2852 return false;
87f57070
FT
2853}
2854
2c9916cd
FT
2855static void skl_compute_wm_global_parameters(struct drm_device *dev,
2856 struct intel_wm_config *config)
87f57070 2857{
2c9916cd
FT
2858 struct drm_crtc *crtc;
2859 struct drm_plane *plane;
87f57070 2860
2c9916cd 2861 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
477eb7f9 2862 config->num_pipes_active += to_intel_crtc(crtc)->active;
87f57070 2863
2c9916cd
FT
2864 /* FIXME: I don't think we need those two global parameters on SKL */
2865 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2866 struct intel_plane *intel_plane = to_intel_plane(plane);
87f57070 2867
2c9916cd
FT
2868 config->sprites_enabled |= intel_plane->wm.enabled;
2869 config->sprites_scaled |= intel_plane->wm.scaled;
87f57070 2870 }
2c9916cd 2871}
87f57070 2872
2c9916cd
FT
2873static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
2874 struct skl_pipe_wm_parameters *p)
2875{
2876 struct drm_device *dev = crtc->dev;
2877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2878 enum i915_pipe pipe = intel_crtc->pipe;
2879 struct drm_plane *plane;
477eb7f9 2880 struct drm_framebuffer *fb;
2c9916cd
FT
2881 int i = 1; /* Index for sprite planes start */
2882
477eb7f9 2883 p->active = intel_crtc->active;
2c9916cd
FT
2884 if (p->active) {
2885 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2886 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
2887
477eb7f9 2888 fb = crtc->primary->state->fb;
19c468b4 2889 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
477eb7f9
FT
2890 if (fb) {
2891 p->plane[0].enabled = true;
19c468b4
FT
2892 p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
2893 drm_format_plane_cpp(fb->pixel_format, 1) : fb->bits_per_pixel / 8;
2894 p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
2895 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
477eb7f9
FT
2896 p->plane[0].tiling = fb->modifier[0];
2897 } else {
2898 p->plane[0].enabled = false;
2899 p->plane[0].bytes_per_pixel = 0;
19c468b4 2900 p->plane[0].y_bytes_per_pixel = 0;
477eb7f9
FT
2901 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
2902 }
2c9916cd
FT
2903 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
2904 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
477eb7f9
FT
2905 p->plane[0].rotation = crtc->primary->state->rotation;
2906
2907 fb = crtc->cursor->state->fb;
19c468b4 2908 p->cursor.y_bytes_per_pixel = 0;
477eb7f9
FT
2909 if (fb) {
2910 p->cursor.enabled = true;
2911 p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
2912 p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
2913 p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
2914 } else {
2915 p->cursor.enabled = false;
2916 p->cursor.bytes_per_pixel = 0;
2917 p->cursor.horiz_pixels = 64;
2918 p->cursor.vert_pixels = 64;
2919 }
87f57070
FT
2920 }
2921
2c9916cd
FT
2922 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2923 struct intel_plane *intel_plane = to_intel_plane(plane);
87f57070 2924
2c9916cd
FT
2925 if (intel_plane->pipe == pipe &&
2926 plane->type == DRM_PLANE_TYPE_OVERLAY)
2927 p->plane[i++] = intel_plane->wm;
2928 }
87f57070
FT
2929}
2930
477eb7f9
FT
2931static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
2932 struct skl_pipe_wm_parameters *p,
2c9916cd
FT
2933 struct intel_plane_wm_parameters *p_params,
2934 uint16_t ddb_allocation,
477eb7f9 2935 int level,
2c9916cd
FT
2936 uint16_t *out_blocks, /* out */
2937 uint8_t *out_lines /* out */)
2938{
477eb7f9
FT
2939 uint32_t latency = dev_priv->wm.skl_latency[level];
2940 uint32_t method1, method2;
2941 uint32_t plane_bytes_per_line, plane_blocks_per_line;
2942 uint32_t res_blocks, res_lines;
2943 uint32_t selected_result;
19c468b4 2944 uint8_t bytes_per_pixel;
bc9b2a29 2945
477eb7f9 2946 if (latency == 0 || !p->active || !p_params->enabled)
2c9916cd 2947 return false;
bc9b2a29 2948
19c468b4
FT
2949 bytes_per_pixel = p_params->y_bytes_per_pixel ?
2950 p_params->y_bytes_per_pixel :
2951 p_params->bytes_per_pixel;
2c9916cd 2952 method1 = skl_wm_method1(p->pixel_rate,
19c468b4 2953 bytes_per_pixel,
477eb7f9 2954 latency);
2c9916cd
FT
2955 method2 = skl_wm_method2(p->pixel_rate,
2956 p->pipe_htotal,
2957 p_params->horiz_pixels,
19c468b4 2958 bytes_per_pixel,
477eb7f9
FT
2959 p_params->tiling,
2960 latency);
2c9916cd 2961
19c468b4 2962 plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
477eb7f9
FT
2963 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2964
2965 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2966 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
2967 uint32_t min_scanlines = 4;
2968 uint32_t y_tile_minimum;
2969 if (intel_rotation_90_or_270(p_params->rotation)) {
2970 switch (p_params->bytes_per_pixel) {
2971 case 1:
2972 min_scanlines = 16;
2973 break;
2974 case 2:
2975 min_scanlines = 8;
2976 break;
2977 case 8:
2978 WARN(1, "Unsupported pixel depth for rotation");
2979 }
2980 }
2981 y_tile_minimum = plane_blocks_per_line * min_scanlines;
2982 selected_result = max(method2, y_tile_minimum);
2983 } else {
2984 if ((ddb_allocation / plane_blocks_per_line) >= 1)
2985 selected_result = min(method1, method2);
2986 else
2987 selected_result = method1;
2988 }
2c9916cd 2989
477eb7f9
FT
2990 res_blocks = selected_result + 1;
2991 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
2c9916cd 2992
477eb7f9
FT
2993 if (level >= 1 && level <= 7) {
2994 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2995 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
2996 res_lines += 4;
2997 else
2998 res_blocks++;
2999 }
2c9916cd 3000
477eb7f9 3001 if (res_blocks >= ddb_allocation || res_lines > 31)
2c9916cd
FT
3002 return false;
3003
3004 *out_blocks = res_blocks;
3005 *out_lines = res_lines;
3006
3007 return true;
3008}
3009
3010static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3011 struct skl_ddb_allocation *ddb,
3012 struct skl_pipe_wm_parameters *p,
3013 enum i915_pipe pipe,
3014 int level,
3015 int num_planes,
3016 struct skl_wm_level *result)
87f57070 3017{
2c9916cd
FT
3018 uint16_t ddb_blocks;
3019 int i;
87f57070 3020
2c9916cd
FT
3021 for (i = 0; i < num_planes; i++) {
3022 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
9edbd4a0 3023
477eb7f9
FT
3024 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3025 p, &p->plane[i],
2c9916cd 3026 ddb_blocks,
477eb7f9 3027 level,
2c9916cd
FT
3028 &result->plane_res_b[i],
3029 &result->plane_res_l[i]);
87f57070
FT
3030 }
3031
2c9916cd 3032 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
477eb7f9
FT
3033 result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
3034 ddb_blocks, level,
3035 &result->cursor_res_b,
2c9916cd
FT
3036 &result->cursor_res_l);
3037}
87f57070 3038
2c9916cd
FT
3039static uint32_t
3040skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3041{
477eb7f9 3042 if (!to_intel_crtc(crtc)->active)
2c9916cd
FT
3043 return 0;
3044
3045 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
87f57070 3046
87f57070
FT
3047}
3048
2c9916cd
FT
3049static void skl_compute_transition_wm(struct drm_crtc *crtc,
3050 struct skl_pipe_wm_parameters *params,
3051 struct skl_wm_level *trans_wm /* out */)
87f57070 3052{
2c9916cd
FT
3053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3054 int i;
87f57070 3055
2c9916cd
FT
3056 if (!params->active)
3057 return;
c0bdd5d9 3058
2c9916cd
FT
3059 /* Until we know more, just disable transition WMs */
3060 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3061 trans_wm->plane_en[i] = false;
3062 trans_wm->cursor_en = false;
3063}
87f57070 3064
2c9916cd
FT
3065static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3066 struct skl_ddb_allocation *ddb,
3067 struct skl_pipe_wm_parameters *params,
3068 struct skl_pipe_wm *pipe_wm)
3069{
3070 struct drm_device *dev = crtc->dev;
3071 const struct drm_i915_private *dev_priv = dev->dev_private;
3072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3073 int level, max_level = ilk_wm_max_level(dev);
87f57070 3074
2c9916cd
FT
3075 for (level = 0; level <= max_level; level++) {
3076 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3077 level, intel_num_planes(intel_crtc),
3078 &pipe_wm->wm[level]);
3079 }
3080 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
87f57070 3081
2c9916cd
FT
3082 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
3083}
87f57070 3084
2c9916cd
FT
3085static void skl_compute_wm_results(struct drm_device *dev,
3086 struct skl_pipe_wm_parameters *p,
3087 struct skl_pipe_wm *p_wm,
3088 struct skl_wm_values *r,
3089 struct intel_crtc *intel_crtc)
3090{
3091 int level, max_level = ilk_wm_max_level(dev);
3092 enum i915_pipe pipe = intel_crtc->pipe;
3093 uint32_t temp;
3094 int i;
87f57070 3095
2c9916cd
FT
3096 for (level = 0; level <= max_level; level++) {
3097 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3098 temp = 0;
87f57070 3099
2c9916cd
FT
3100 temp |= p_wm->wm[level].plane_res_l[i] <<
3101 PLANE_WM_LINES_SHIFT;
3102 temp |= p_wm->wm[level].plane_res_b[i];
3103 if (p_wm->wm[level].plane_en[i])
3104 temp |= PLANE_WM_EN;
87f57070 3105
2c9916cd
FT
3106 r->plane[pipe][i][level] = temp;
3107 }
87f57070 3108
2c9916cd 3109 temp = 0;
87f57070 3110
2c9916cd
FT
3111 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3112 temp |= p_wm->wm[level].cursor_res_b;
87f57070 3113
2c9916cd
FT
3114 if (p_wm->wm[level].cursor_en)
3115 temp |= PLANE_WM_EN;
87f57070 3116
2c9916cd 3117 r->cursor[pipe][level] = temp;
87f57070 3118
2c9916cd 3119 }
87f57070 3120
2c9916cd
FT
3121 /* transition WMs */
3122 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3123 temp = 0;
3124 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3125 temp |= p_wm->trans_wm.plane_res_b[i];
3126 if (p_wm->trans_wm.plane_en[i])
3127 temp |= PLANE_WM_EN;
87f57070 3128
2c9916cd
FT
3129 r->plane_trans[pipe][i] = temp;
3130 }
87f57070 3131
2c9916cd
FT
3132 temp = 0;
3133 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3134 temp |= p_wm->trans_wm.cursor_res_b;
3135 if (p_wm->trans_wm.cursor_en)
3136 temp |= PLANE_WM_EN;
c0bdd5d9 3137
2c9916cd
FT
3138 r->cursor_trans[pipe] = temp;
3139
3140 r->wm_linetime[pipe] = p_wm->linetime;
87f57070
FT
3141}
3142
2c9916cd
FT
3143static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3144 const struct skl_ddb_entry *entry)
87f57070 3145{
2c9916cd
FT
3146 if (entry->end)
3147 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3148 else
3149 I915_WRITE(reg, 0);
3150}
c0bdd5d9 3151
2c9916cd
FT
3152static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3153 const struct skl_wm_values *new)
3154{
3155 struct drm_device *dev = dev_priv->dev;
3156 struct intel_crtc *crtc;
c0bdd5d9 3157
2c9916cd
FT
3158 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3159 int i, level, max_level = ilk_wm_max_level(dev);
3160 enum i915_pipe pipe = crtc->pipe;
87f57070 3161
2c9916cd
FT
3162 if (!new->dirty[pipe])
3163 continue;
87f57070 3164
2c9916cd 3165 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
87f57070 3166
2c9916cd
FT
3167 for (level = 0; level <= max_level; level++) {
3168 for (i = 0; i < intel_num_planes(crtc); i++)
3169 I915_WRITE(PLANE_WM(pipe, i, level),
3170 new->plane[pipe][i][level]);
3171 I915_WRITE(CUR_WM(pipe, level),
3172 new->cursor[pipe][level]);
3173 }
3174 for (i = 0; i < intel_num_planes(crtc); i++)
3175 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3176 new->plane_trans[pipe][i]);
3177 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3178
19c468b4 3179 for (i = 0; i < intel_num_planes(crtc); i++) {
2c9916cd
FT
3180 skl_ddb_entry_write(dev_priv,
3181 PLANE_BUF_CFG(pipe, i),
3182 &new->ddb.plane[pipe][i]);
19c468b4
FT
3183 skl_ddb_entry_write(dev_priv,
3184 PLANE_NV12_BUF_CFG(pipe, i),
3185 &new->ddb.y_plane[pipe][i]);
3186 }
2c9916cd
FT
3187
3188 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3189 &new->ddb.cursor[pipe]);
3190 }
c0bdd5d9
FT
3191}
3192
2c9916cd
FT
3193/*
3194 * When setting up a new DDB allocation arrangement, we need to correctly
3195 * sequence the times at which the new allocations for the pipes are taken into
3196 * account or we'll have pipes fetching from space previously allocated to
3197 * another pipe.
3198 *
3199 * Roughly the sequence looks like:
3200 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3201 * overlapping with a previous light-up pipe (another way to put it is:
3202 * pipes with their new allocation strickly included into their old ones).
3203 * 2. re-allocate the other pipes that get their allocation reduced
3204 * 3. allocate the pipes having their allocation increased
3205 *
3206 * Steps 1. and 2. are here to take care of the following case:
3207 * - Initially DDB looks like this:
3208 * | B | C |
3209 * - enable pipe A.
3210 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3211 * allocation
3212 * | A | B | C |
3213 *
3214 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
c0bdd5d9 3215 */
2c9916cd
FT
3216
3217static void
3218skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int pass)
c0bdd5d9 3219{
2c9916cd 3220 int plane;
c0bdd5d9 3221
2c9916cd 3222 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
c0bdd5d9 3223
477eb7f9 3224 for_each_plane(dev_priv, pipe, plane) {
2c9916cd
FT
3225 I915_WRITE(PLANE_SURF(pipe, plane),
3226 I915_READ(PLANE_SURF(pipe, plane)));
3227 }
3228 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
87f57070
FT
3229}
3230
2c9916cd
FT
3231static bool
3232skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3233 const struct skl_ddb_allocation *new,
3234 enum i915_pipe pipe)
9edbd4a0 3235{
2c9916cd 3236 uint16_t old_size, new_size;
9edbd4a0 3237
2c9916cd
FT
3238 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3239 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
9edbd4a0 3240
2c9916cd
FT
3241 return old_size != new_size &&
3242 new->pipe[pipe].start >= old->pipe[pipe].start &&
3243 new->pipe[pipe].end <= old->pipe[pipe].end;
3244}
9edbd4a0 3245
2c9916cd
FT
3246static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3247 struct skl_wm_values *new_values)
3248{
3249 struct drm_device *dev = dev_priv->dev;
3250 struct skl_ddb_allocation *cur_ddb, *new_ddb;
19c468b4 3251 bool reallocated[I915_MAX_PIPES] = {};
2c9916cd
FT
3252 struct intel_crtc *crtc;
3253 enum i915_pipe pipe;
9edbd4a0 3254
2c9916cd
FT
3255 new_ddb = &new_values->ddb;
3256 cur_ddb = &dev_priv->wm.skl_hw.ddb;
9edbd4a0 3257
2c9916cd
FT
3258 /*
3259 * First pass: flush the pipes with the new allocation contained into
3260 * the old space.
3261 *
3262 * We'll wait for the vblank on those pipes to ensure we can safely
3263 * re-allocate the freed space without this pipe fetching from it.
3264 */
3265 for_each_intel_crtc(dev, crtc) {
3266 if (!crtc->active)
3267 continue;
9edbd4a0 3268
2c9916cd 3269 pipe = crtc->pipe;
9edbd4a0 3270
2c9916cd
FT
3271 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3272 continue;
9edbd4a0 3273
2c9916cd
FT
3274 skl_wm_flush_pipe(dev_priv, pipe, 1);
3275 intel_wait_for_vblank(dev, pipe);
9edbd4a0 3276
2c9916cd 3277 reallocated[pipe] = true;
9edbd4a0
FT
3278 }
3279
9edbd4a0 3280
2c9916cd
FT
3281 /*
3282 * Second pass: flush the pipes that are having their allocation
3283 * reduced, but overlapping with a previous allocation.
3284 *
3285 * Here as well we need to wait for the vblank to make sure the freed
3286 * space is not used anymore.
3287 */
3288 for_each_intel_crtc(dev, crtc) {
3289 if (!crtc->active)
3290 continue;
ba55f2f5 3291
2c9916cd 3292 pipe = crtc->pipe;
ba55f2f5 3293
2c9916cd
FT
3294 if (reallocated[pipe])
3295 continue;
3296
3297 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3298 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3299 skl_wm_flush_pipe(dev_priv, pipe, 2);
3300 intel_wait_for_vblank(dev, pipe);
3301 reallocated[pipe] = true;
3302 }
3303 }
24edb884 3304
2c9916cd
FT
3305 /*
3306 * Third pass: flush the pipes that got more space allocated.
3307 *
3308 * We don't need to actively wait for the update here, next vblank
3309 * will just get more DDB space with the correct WM values.
ba55f2f5 3310 */
2c9916cd
FT
3311 for_each_intel_crtc(dev, crtc) {
3312 if (!crtc->active)
3313 continue;
ba55f2f5 3314
2c9916cd 3315 pipe = crtc->pipe;
ba55f2f5 3316
2c9916cd
FT
3317 /*
3318 * At this point, only the pipes more space than before are
3319 * left to re-allocate.
3320 */
3321 if (reallocated[pipe])
3322 continue;
3323
3324 skl_wm_flush_pipe(dev_priv, pipe, 3);
3325 }
ba55f2f5
FT
3326}
3327
2c9916cd
FT
3328static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3329 struct skl_pipe_wm_parameters *params,
3330 struct intel_wm_config *config,
3331 struct skl_ddb_allocation *ddb, /* out */
3332 struct skl_pipe_wm *pipe_wm /* out */)
87f57070 3333{
2c9916cd 3334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c0bdd5d9 3335
2c9916cd
FT
3336 skl_compute_wm_pipe_parameters(crtc, params);
3337 skl_allocate_pipe_ddb(crtc, config, params, ddb);
3338 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
87f57070 3339
2c9916cd
FT
3340 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3341 return false;
c0bdd5d9 3342
2c9916cd 3343 intel_crtc->wm.skl_active = *pipe_wm;
19c468b4 3344
2c9916cd 3345 return true;
87f57070
FT
3346}
3347
2c9916cd
FT
3348static void skl_update_other_pipe_wm(struct drm_device *dev,
3349 struct drm_crtc *crtc,
3350 struct intel_wm_config *config,
3351 struct skl_wm_values *r)
ba55f2f5 3352{
2c9916cd
FT
3353 struct intel_crtc *intel_crtc;
3354 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
ba55f2f5 3355
2c9916cd
FT
3356 /*
3357 * If the WM update hasn't changed the allocation for this_crtc (the
3358 * crtc we are currently computing the new WM values for), other
3359 * enabled crtcs will keep the same allocation and we don't need to
3360 * recompute anything for them.
3361 */
3362 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
ba55f2f5 3363 return;
ba55f2f5
FT
3364
3365 /*
2c9916cd
FT
3366 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3367 * other active pipes need new DDB allocation and WM values.
ba55f2f5 3368 */
2c9916cd
FT
3369 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3370 base.head) {
3371 struct skl_pipe_wm_parameters params = {};
3372 struct skl_pipe_wm pipe_wm = {};
3373 bool wm_changed;
ba55f2f5 3374
2c9916cd
FT
3375 if (this_crtc->pipe == intel_crtc->pipe)
3376 continue;
ba55f2f5 3377
2c9916cd
FT
3378 if (!intel_crtc->active)
3379 continue;
ba55f2f5 3380
2c9916cd
FT
3381 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3382 &params, config,
3383 &r->ddb, &pipe_wm);
ba55f2f5 3384
2c9916cd
FT
3385 /*
3386 * If we end up re-computing the other pipe WM values, it's
3387 * because it was really needed, so we expect the WM values to
3388 * be different.
3389 */
3390 WARN_ON(!wm_changed);
ba55f2f5 3391
2c9916cd
FT
3392 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3393 r->dirty[intel_crtc->pipe] = true;
3394 }
3395}
ba55f2f5 3396
2c9916cd
FT
3397static void skl_update_wm(struct drm_crtc *crtc)
3398{
3399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3400 struct drm_device *dev = crtc->dev;
3401 struct drm_i915_private *dev_priv = dev->dev_private;
3402 struct skl_pipe_wm_parameters params = {};
3403 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3404 struct skl_pipe_wm pipe_wm = {};
3405 struct intel_wm_config config = {};
ba55f2f5 3406
2c9916cd 3407 memset(results, 0, sizeof(*results));
ba55f2f5 3408
2c9916cd 3409 skl_compute_wm_global_parameters(dev, &config);
ba55f2f5 3410
2c9916cd
FT
3411 if (!skl_update_pipe_wm(crtc, &params, &config,
3412 &results->ddb, &pipe_wm))
3413 return;
5d0b1887 3414
2c9916cd
FT
3415 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3416 results->dirty[intel_crtc->pipe] = true;
3417
3418 skl_update_other_pipe_wm(dev, crtc, &config, results);
3419 skl_write_wm_values(dev_priv, results);
3420 skl_flush_wm_values(dev_priv, results);
3421
3422 /* store the new configuration */
3423 dev_priv->wm.skl_hw = *results;
9edbd4a0 3424}
5d0b1887 3425
2c9916cd
FT
3426static void
3427skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3428 uint32_t sprite_width, uint32_t sprite_height,
3429 int pixel_size, bool enabled, bool scaled)
9edbd4a0 3430{
2c9916cd 3431 struct intel_plane *intel_plane = to_intel_plane(plane);
477eb7f9 3432 struct drm_framebuffer *fb = plane->state->fb;
5d0b1887 3433
2c9916cd
FT
3434 intel_plane->wm.enabled = enabled;
3435 intel_plane->wm.scaled = scaled;
3436 intel_plane->wm.horiz_pixels = sprite_width;
3437 intel_plane->wm.vert_pixels = sprite_height;
477eb7f9 3438 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
19c468b4
FT
3439
3440 /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3441 intel_plane->wm.bytes_per_pixel =
3442 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3443 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3444 intel_plane->wm.y_bytes_per_pixel =
3445 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3446 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3447
477eb7f9
FT
3448 /*
3449 * Framebuffer can be NULL on plane disable, but it does not
3450 * matter for watermarks if we assume no tiling in that case.
3451 */
3452 if (fb)
3453 intel_plane->wm.tiling = fb->modifier[0];
3454 intel_plane->wm.rotation = plane->state->rotation;
2c9916cd
FT
3455
3456 skl_update_wm(crtc);
5d0b1887
FT
3457}
3458
2c9916cd 3459static void ilk_update_wm(struct drm_crtc *crtc)
5d0b1887 3460{
2c9916cd
FT
3461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3462 struct drm_device *dev = crtc->dev;
5d0b1887 3463 struct drm_i915_private *dev_priv = dev->dev_private;
2c9916cd
FT
3464 struct ilk_wm_maximums max;