Move the m_freem from vr_encap to vr_start, making the passed mbuf effectively
[dragonfly.git] / sys / dev / netif / vr / if_vr.c
CommitLineData
984263bc
MD
1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $
5f0a6e55 33 * $DragonFly: src/sys/dev/netif/vr/if_vr.c,v 1.18 2005/02/20 03:21:58 joerg Exp $
1de703da
MD
34 *
35 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $
984263bc
MD
36 */
37
38/*
39 * VIA Rhine fast ethernet PCI NIC driver
40 *
41 * Supports various network adapters based on the VIA Rhine
42 * and Rhine II PCI controllers, including the D-Link DFE530TX.
43 * Datasheets are available at http://www.via.com.tw.
44 *
45 * Written by Bill Paul <wpaul@ctr.columbia.edu>
46 * Electrical Engineering Department
47 * Columbia University, New York City
48 */
49
50/*
51 * The VIA Rhine controllers are similar in some respects to the
52 * the DEC tulip chips, except less complicated. The controller
53 * uses an MII bus and an external physical layer interface. The
54 * receiver has a one entry perfect filter and a 64-bit hash table
55 * multicast filter. Transmit and receive descriptors are similar
56 * to the tulip.
57 *
58 * The Rhine has a serious flaw in its transmit DMA mechanism:
59 * transmit buffers must be longword aligned. Unfortunately,
60 * FreeBSD doesn't guarantee that mbufs will be filled in starting
61 * at longword boundaries, so we have to do a buffer copy before
62 * transmission.
63 */
64
65#include <sys/param.h>
66#include <sys/systm.h>
67#include <sys/sockio.h>
68#include <sys/mbuf.h>
69#include <sys/malloc.h>
70#include <sys/kernel.h>
71#include <sys/socket.h>
72
73#include <net/if.h>
74#include <net/if_arp.h>
75#include <net/ethernet.h>
76#include <net/if_dl.h>
77#include <net/if_media.h>
78
79#include <net/bpf.h>
80
81#include <vm/vm.h> /* for vtophys */
82#include <vm/pmap.h> /* for vtophys */
984263bc
MD
83#include <machine/bus_pio.h>
84#include <machine/bus_memio.h>
85#include <machine/bus.h>
86#include <machine/resource.h>
87#include <sys/bus.h>
88#include <sys/rman.h>
89
fa23be1c
JS
90#include <dev/netif/mii_layer/mii.h>
91#include <dev/netif/mii_layer/miivar.h>
984263bc 92
1f2de5d4
MD
93#include <bus/pci/pcireg.h>
94#include <bus/pci/pcivar.h>
984263bc
MD
95
96#define VR_USEIOSPACE
97
fa23be1c 98#include <dev/netif/vr/if_vrreg.h>
984263bc
MD
99
100/* "controller miibus0" required. See GENERIC if you get errors here. */
101#include "miibus_if.h"
102
984263bc
MD
103#undef VR_USESWSHIFT
104
105/*
106 * Various supported device vendors/types and their names.
107 */
108static struct vr_type vr_devs[] = {
109 { VIA_VENDORID, VIA_DEVICEID_RHINE,
110 "VIA VT3043 Rhine I 10/100BaseTX" },
111 { VIA_VENDORID, VIA_DEVICEID_RHINE_II,
112 "VIA VT86C100A Rhine II 10/100BaseTX" },
113 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2,
114 "VIA VT6102 Rhine II 10/100BaseTX" },
115 { VIA_VENDORID, VIA_DEVICEID_RHINE_III,
116 "VIA VT6105 Rhine III 10/100BaseTX" },
117 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M,
118 "VIA VT6105M Rhine III 10/100BaseTX" },
119 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II,
120 "Delta Electronics Rhine II 10/100BaseTX" },
121 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II,
122 "Addtron Technology Rhine II 10/100BaseTX" },
123 { 0, 0, NULL }
124};
125
fa23be1c
JS
126static int vr_probe(device_t);
127static int vr_attach(device_t);
128static int vr_detach(device_t);
129
130static int vr_newbuf(struct vr_softc *, struct vr_chain_onefrag *,
131 struct mbuf *);
132static int vr_encap(struct vr_softc *, struct vr_chain *, struct mbuf * );
133
134static void vr_rxeof(struct vr_softc *);
135static void vr_rxeoc(struct vr_softc *);
136static void vr_txeof(struct vr_softc *);
137static void vr_txeoc(struct vr_softc *);
138static void vr_tick(void *);
139static void vr_intr(void *);
140static void vr_start(struct ifnet *);
141static int vr_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
142static void vr_init(void *);
143static void vr_stop(struct vr_softc *);
144static void vr_watchdog(struct ifnet *);
145static void vr_shutdown(device_t);
146static int vr_ifmedia_upd(struct ifnet *);
147static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *);
984263bc
MD
148
149#ifdef VR_USESWSHIFT
fa23be1c
JS
150static void vr_mii_sync(struct vr_softc *);
151static void vr_mii_send(struct vr_softc *, uint32_t, int);
984263bc 152#endif
fa23be1c
JS
153static int vr_mii_readreg(struct vr_softc *, struct vr_mii_frame *);
154static int vr_mii_writereg(struct vr_softc *, struct vr_mii_frame *);
155static int vr_miibus_readreg(device_t, int, int);
156static int vr_miibus_writereg(device_t, int, int, int);
157static void vr_miibus_statchg(device_t);
158
159static void vr_setcfg(struct vr_softc *, int);
160static uint8_t vr_calchash(uint8_t *);
161static void vr_setmulti(struct vr_softc *);
162static void vr_reset(struct vr_softc *);
163static int vr_list_rx_init(struct vr_softc *);
164static int vr_list_tx_init(struct vr_softc *);
984263bc
MD
165
166#ifdef VR_USEIOSPACE
167#define VR_RES SYS_RES_IOPORT
168#define VR_RID VR_PCI_LOIO
169#else
170#define VR_RES SYS_RES_MEMORY
171#define VR_RID VR_PCI_LOMEM
172#endif
173
174static device_method_t vr_methods[] = {
175 /* Device interface */
176 DEVMETHOD(device_probe, vr_probe),
177 DEVMETHOD(device_attach, vr_attach),
178 DEVMETHOD(device_detach, vr_detach),
179 DEVMETHOD(device_shutdown, vr_shutdown),
180
181 /* bus interface */
182 DEVMETHOD(bus_print_child, bus_generic_print_child),
183 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
184
185 /* MII interface */
186 DEVMETHOD(miibus_readreg, vr_miibus_readreg),
187 DEVMETHOD(miibus_writereg, vr_miibus_writereg),
188 DEVMETHOD(miibus_statchg, vr_miibus_statchg),
189
190 { 0, 0 }
191};
192
193static driver_t vr_driver = {
194 "vr",
195 vr_methods,
196 sizeof(struct vr_softc)
197};
198
199static devclass_t vr_devclass;
200
32832096 201DECLARE_DUMMY_MODULE(if_vr);
984263bc
MD
202DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0);
203DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0);
204
205#define VR_SETBIT(sc, reg, x) \
206 CSR_WRITE_1(sc, reg, \
fa23be1c 207 CSR_READ_1(sc, reg) | (x))
984263bc
MD
208
209#define VR_CLRBIT(sc, reg, x) \
210 CSR_WRITE_1(sc, reg, \
fa23be1c 211 CSR_READ_1(sc, reg) & ~(x))
984263bc
MD
212
213#define VR_SETBIT16(sc, reg, x) \
214 CSR_WRITE_2(sc, reg, \
fa23be1c 215 CSR_READ_2(sc, reg) | (x))
984263bc
MD
216
217#define VR_CLRBIT16(sc, reg, x) \
218 CSR_WRITE_2(sc, reg, \
fa23be1c 219 CSR_READ_2(sc, reg) & ~(x))
984263bc
MD
220
221#define VR_SETBIT32(sc, reg, x) \
222 CSR_WRITE_4(sc, reg, \
fa23be1c 223 CSR_READ_4(sc, reg) | (x))
984263bc
MD
224
225#define VR_CLRBIT32(sc, reg, x) \
226 CSR_WRITE_4(sc, reg, \
fa23be1c 227 CSR_READ_4(sc, reg) & ~(x))
984263bc
MD
228
229#define SIO_SET(x) \
230 CSR_WRITE_1(sc, VR_MIICMD, \
fa23be1c 231 CSR_READ_1(sc, VR_MIICMD) | (x))
984263bc
MD
232
233#define SIO_CLR(x) \
234 CSR_WRITE_1(sc, VR_MIICMD, \
fa23be1c 235 CSR_READ_1(sc, VR_MIICMD) & ~(x))
984263bc
MD
236
237#ifdef VR_USESWSHIFT
238/*
239 * Sync the PHYs by setting data bit and strobing the clock 32 times.
240 */
fa23be1c
JS
241static void
242vr_mii_sync(struct vr_softc *sc)
984263bc 243{
fa23be1c 244 int i;
984263bc
MD
245
246 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN);
247
248 for (i = 0; i < 32; i++) {
249 SIO_SET(VR_MIICMD_CLK);
250 DELAY(1);
251 SIO_CLR(VR_MIICMD_CLK);
252 DELAY(1);
253 }
984263bc
MD
254}
255
256/*
257 * Clock a series of bits through the MII.
258 */
fa23be1c
JS
259static void
260vr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt)
984263bc 261{
fa23be1c 262 int i;
984263bc
MD
263
264 SIO_CLR(VR_MIICMD_CLK);
265
266 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
fa23be1c 267 if (bits & i)
984263bc 268 SIO_SET(VR_MIICMD_DATAIN);
fa23be1c 269 else
984263bc 270 SIO_CLR(VR_MIICMD_DATAIN);
984263bc
MD
271 DELAY(1);
272 SIO_CLR(VR_MIICMD_CLK);
273 DELAY(1);
274 SIO_SET(VR_MIICMD_CLK);
275 }
276}
277#endif
278
279/*
280 * Read an PHY register through the MII.
281 */
fa23be1c
JS
282static int
283vr_mii_readreg(struct vr_softc *sc, struct vr_mii_frame *frame)
984263bc
MD
284#ifdef VR_USESWSHIFT
285{
fa23be1c 286 int i, ack, s;
984263bc
MD
287
288 s = splimp();
289
fa23be1c 290 /* Set up frame for RX. */
984263bc
MD
291 frame->mii_stdelim = VR_MII_STARTDELIM;
292 frame->mii_opcode = VR_MII_READOP;
293 frame->mii_turnaround = 0;
294 frame->mii_data = 0;
295
296 CSR_WRITE_1(sc, VR_MIICMD, 0);
297 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
298
fa23be1c 299 /* Turn on data xmit. */
984263bc
MD
300 SIO_SET(VR_MIICMD_DIR);
301
302 vr_mii_sync(sc);
303
fa23be1c 304 /* Send command/address info. */
984263bc
MD
305 vr_mii_send(sc, frame->mii_stdelim, 2);
306 vr_mii_send(sc, frame->mii_opcode, 2);
307 vr_mii_send(sc, frame->mii_phyaddr, 5);
308 vr_mii_send(sc, frame->mii_regaddr, 5);
309
fa23be1c 310 /* Idle bit. */
984263bc
MD
311 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN));
312 DELAY(1);
313 SIO_SET(VR_MIICMD_CLK);
314 DELAY(1);
315
316 /* Turn off xmit. */
317 SIO_CLR(VR_MIICMD_DIR);
318
319 /* Check for ack */
320 SIO_CLR(VR_MIICMD_CLK);
321 DELAY(1);
322 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;
323 SIO_SET(VR_MIICMD_CLK);
324 DELAY(1);
325
326 /*
327 * Now try reading data bits. If the ack failed, we still
328 * need to clock through 16 cycles to keep the PHY(s) in sync.
329 */
330 if (ack) {
331 for(i = 0; i < 16; i++) {
332 SIO_CLR(VR_MIICMD_CLK);
333 DELAY(1);
334 SIO_SET(VR_MIICMD_CLK);
335 DELAY(1);
336 }
337 goto fail;
338 }
339
340 for (i = 0x8000; i; i >>= 1) {
341 SIO_CLR(VR_MIICMD_CLK);
342 DELAY(1);
343 if (!ack) {
344 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT)
345 frame->mii_data |= i;
346 DELAY(1);
347 }
348 SIO_SET(VR_MIICMD_CLK);
349 DELAY(1);
350 }
351
352fail:
984263bc
MD
353 SIO_CLR(VR_MIICMD_CLK);
354 DELAY(1);
355 SIO_SET(VR_MIICMD_CLK);
356 DELAY(1);
357
358 splx(s);
359
360 if (ack)
361 return(1);
362 return(0);
363}
364#else
365{
fa23be1c 366 int s, i;
984263bc
MD
367
368 s = splimp();
369
fa23be1c 370 /* Set the PHY address. */
984263bc
MD
371 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
372 frame->mii_phyaddr);
373
fa23be1c 374 /* Set the register address. */
984263bc
MD
375 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
376 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB);
377
378 for (i = 0; i < 10000; i++) {
379 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
380 break;
381 DELAY(1);
382 }
984263bc
MD
383 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA);
384
fa23be1c 385 splx(s);
984263bc
MD
386
387 return(0);
388}
389#endif
390
391
392/*
393 * Write to a PHY register through the MII.
394 */
fa23be1c
JS
395static int
396vr_mii_writereg(struct vr_softc *sc, struct vr_mii_frame *frame)
984263bc
MD
397#ifdef VR_USESWSHIFT
398{
fa23be1c 399 int s;
984263bc
MD
400
401 s = splimp();
402
403 CSR_WRITE_1(sc, VR_MIICMD, 0);
404 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
405
fa23be1c 406 /* Set up frame for TX. */
984263bc
MD
407 frame->mii_stdelim = VR_MII_STARTDELIM;
408 frame->mii_opcode = VR_MII_WRITEOP;
409 frame->mii_turnaround = VR_MII_TURNAROUND;
410
fa23be1c 411 /* Turn on data output. */
984263bc
MD
412 SIO_SET(VR_MIICMD_DIR);
413
414 vr_mii_sync(sc);
415
416 vr_mii_send(sc, frame->mii_stdelim, 2);
417 vr_mii_send(sc, frame->mii_opcode, 2);
418 vr_mii_send(sc, frame->mii_phyaddr, 5);
419 vr_mii_send(sc, frame->mii_regaddr, 5);
420 vr_mii_send(sc, frame->mii_turnaround, 2);
421 vr_mii_send(sc, frame->mii_data, 16);
422
423 /* Idle bit. */
424 SIO_SET(VR_MIICMD_CLK);
425 DELAY(1);
426 SIO_CLR(VR_MIICMD_CLK);
427 DELAY(1);
428
fa23be1c 429 /* Turn off xmit. */
984263bc
MD
430 SIO_CLR(VR_MIICMD_DIR);
431
432 splx(s);
433
434 return(0);
435}
436#else
437{
fa23be1c 438 int s, i;
984263bc
MD
439
440 s = splimp();
441
442 /* Set the PHY-adress */
443 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
444 frame->mii_phyaddr);
445
fa23be1c 446 /* Set the register address and data to write. */
984263bc
MD
447 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
448 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data);
449
450 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB);
451
452 for (i = 0; i < 10000; i++) {
453 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
454 break;
455 DELAY(1);
456 }
457
fa23be1c 458 splx(s);
984263bc
MD
459
460 return(0);
461}
462#endif
463
fa23be1c
JS
464static int
465vr_miibus_readreg(device_t dev, int phy, int reg)
984263bc 466{
fa23be1c
JS
467 struct vr_mii_frame frame;
468 struct vr_softc *sc;
984263bc
MD
469
470 sc = device_get_softc(dev);
471
472 switch (sc->vr_revid) {
fa23be1c
JS
473 case REV_ID_VT6102_APOLLO:
474 if (phy != 1)
475 return(0);
476 break;
477 default:
478 break;
479 }
984263bc 480
fa23be1c 481 bzero(&frame, sizeof(frame));
984263bc
MD
482
483 frame.mii_phyaddr = phy;
484 frame.mii_regaddr = reg;
485 vr_mii_readreg(sc, &frame);
486
487 return(frame.mii_data);
488}
489
fa23be1c
JS
490static int
491vr_miibus_writereg(device_t dev, int phy, int reg, int data)
984263bc 492{
fa23be1c
JS
493 struct vr_mii_frame frame;
494 struct vr_softc *sc;
984263bc
MD
495
496 sc = device_get_softc(dev);
497
498 switch (sc->vr_revid) {
fa23be1c
JS
499 case REV_ID_VT6102_APOLLO:
500 if (phy != 1)
501 return 0;
502 break;
503 default:
504 break;
505 }
984263bc 506
fa23be1c 507 bzero(&frame, sizeof(frame));
984263bc
MD
508
509 frame.mii_phyaddr = phy;
510 frame.mii_regaddr = reg;
511 frame.mii_data = data;
512
513 vr_mii_writereg(sc, &frame);
514
515 return(0);
516}
517
fa23be1c
JS
518static void
519vr_miibus_statchg(device_t dev)
984263bc 520{
fa23be1c
JS
521 struct mii_data *mii;
522 struct vr_softc *sc;
984263bc
MD
523
524 sc = device_get_softc(dev);
525 mii = device_get_softc(sc->vr_miibus);
526 vr_setcfg(sc, mii->mii_media_active);
984263bc
MD
527}
528
529/*
530 * Calculate CRC of a multicast group address, return the lower 6 bits.
531 */
fa23be1c
JS
532static uint8_t
533vr_calchash(uint8_t *addr)
984263bc 534{
fa23be1c
JS
535 uint32_t crc, carry;
536 int i, j;
537 uint8_t c;
984263bc
MD
538
539 /* Compute CRC for the address value. */
540 crc = 0xFFFFFFFF; /* initial value */
541
542 for (i = 0; i < 6; i++) {
543 c = *(addr + i);
544 for (j = 0; j < 8; j++) {
545 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
546 crc <<= 1;
547 c >>= 1;
548 if (carry)
549 crc = (crc ^ 0x04c11db6) | carry;
550 }
551 }
552
553 /* return the filter bit position */
554 return((crc >> 26) & 0x0000003F);
555}
556
557/*
558 * Program the 64-bit multicast hash filter.
559 */
fa23be1c
JS
560static void
561vr_setmulti(struct vr_softc *sc)
984263bc 562{
fa23be1c
JS
563 struct ifnet *ifp;
564 int h = 0;
565 uint32_t hashes[2] = { 0, 0 };
566 struct ifmultiaddr *ifma;
567 uint8_t rxfilt;
568 int mcnt = 0;
984263bc
MD
569
570 ifp = &sc->arpcom.ac_if;
571
572 rxfilt = CSR_READ_1(sc, VR_RXCFG);
573
574 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
575 rxfilt |= VR_RXCFG_RX_MULTI;
576 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
577 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF);
578 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF);
579 return;
580 }
581
fa23be1c 582 /* First, zero out all the existing hash bits. */
984263bc
MD
583 CSR_WRITE_4(sc, VR_MAR0, 0);
584 CSR_WRITE_4(sc, VR_MAR1, 0);
585
fa23be1c 586 /* Now program new ones. */
984263bc
MD
587 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
588 ifma = ifma->ifma_link.le_next) {
589 if (ifma->ifma_addr->sa_family != AF_LINK)
590 continue;
591 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
592 if (h < 32)
593 hashes[0] |= (1 << h);
594 else
595 hashes[1] |= (1 << (h - 32));
596 mcnt++;
597 }
598
599 if (mcnt)
600 rxfilt |= VR_RXCFG_RX_MULTI;
601 else
602 rxfilt &= ~VR_RXCFG_RX_MULTI;
603
604 CSR_WRITE_4(sc, VR_MAR0, hashes[0]);
605 CSR_WRITE_4(sc, VR_MAR1, hashes[1]);
606 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
984263bc
MD
607}
608
609/*
610 * In order to fiddle with the
611 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
612 * first have to put the transmit and/or receive logic in the idle state.
613 */
fa23be1c
JS
614static void
615vr_setcfg(struct vr_softc *sc, int media)
984263bc 616{
fa23be1c 617 int restart = 0;
984263bc
MD
618
619 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) {
620 restart = 1;
621 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON));
622 }
623
624 if ((media & IFM_GMASK) == IFM_FDX)
625 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
626 else
627 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
628
629 if (restart)
630 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON);
984263bc
MD
631}
632
fa23be1c
JS
633static void
634vr_reset(struct vr_softc *sc)
984263bc 635{
fa23be1c 636 int i;
984263bc
MD
637
638 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET);
639
640 for (i = 0; i < VR_TIMEOUT; i++) {
641 DELAY(10);
642 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET))
643 break;
644 }
645 if (i == VR_TIMEOUT) {
fa23be1c
JS
646 struct ifnet *ifp = &sc->arpcom.ac_if;
647
648 if (sc->vr_revid < REV_ID_VT3065_A) {
649 if_printf(ifp, "reset never completed!\n");
650 } else {
984263bc 651 /* Use newer force reset command */
fa23be1c 652 if_printf(ifp, "Using force reset command.\n");
984263bc
MD
653 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST);
654 }
655 }
656
657 /* Wait a little while for the chip to get its brains in order. */
658 DELAY(1000);
984263bc
MD
659}
660
661/*
662 * Probe for a VIA Rhine chip. Check the PCI vendor and device
663 * IDs against our list and return a device name if we find a match.
664 */
fa23be1c
JS
665static int
666vr_probe(device_t dev)
984263bc 667{
fa23be1c 668 struct vr_type *t;
984263bc
MD
669
670 t = vr_devs;
671
672 while(t->vr_name != NULL) {
673 if ((pci_get_vendor(dev) == t->vr_vid) &&
674 (pci_get_device(dev) == t->vr_did)) {
675 device_set_desc(dev, t->vr_name);
676 return(0);
677 }
678 t++;
679 }
680
681 return(ENXIO);
682}
683
684/*
685 * Attach the interface. Allocate softc structures, do ifmedia
686 * setup and ethernet/BPF attach.
687 */
fa23be1c
JS
688static int
689vr_attach(device_t dev)
984263bc 690{
fa23be1c
JS
691 int i, s;
692 uint8_t eaddr[ETHER_ADDR_LEN];
693 uint32_t command;
694 struct vr_softc *sc;
695 struct ifnet *ifp;
696 int unit, error = 0, rid;
984263bc
MD
697
698 s = splimp();
699
700 sc = device_get_softc(dev);
701 unit = device_get_unit(dev);
9e6fd080 702 callout_init(&sc->vr_stat_timer);
984263bc
MD
703
704 /*
705 * Handle power management nonsense.
706 */
707
708 command = pci_read_config(dev, VR_PCI_CAPID, 4) & 0x000000FF;
709 if (command == 0x01) {
984263bc
MD
710 command = pci_read_config(dev, VR_PCI_PWRMGMTCTRL, 4);
711 if (command & VR_PSTATE_MASK) {
fa23be1c 712 uint32_t iobase, membase, irq;
984263bc
MD
713
714 /* Save important PCI config data. */
715 iobase = pci_read_config(dev, VR_PCI_LOIO, 4);
716 membase = pci_read_config(dev, VR_PCI_LOMEM, 4);
717 irq = pci_read_config(dev, VR_PCI_INTLINE, 4);
718
719 /* Reset the power state. */
fa23be1c
JS
720 device_printf(dev, "chip is in D%d power mode "
721 "-- setting to D0\n", command & VR_PSTATE_MASK);
984263bc
MD
722 command &= 0xFFFFFFFC;
723 pci_write_config(dev, VR_PCI_PWRMGMTCTRL, command, 4);
724
725 /* Restore PCI config data. */
726 pci_write_config(dev, VR_PCI_LOIO, iobase, 4);
727 pci_write_config(dev, VR_PCI_LOMEM, membase, 4);
728 pci_write_config(dev, VR_PCI_INTLINE, irq, 4);
729 }
730 }
731
732 /*
733 * Map control/status registers.
734 */
735 command = pci_read_config(dev, PCIR_COMMAND, 4);
736 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
737 pci_write_config(dev, PCIR_COMMAND, command, 4);
738 command = pci_read_config(dev, PCIR_COMMAND, 4);
739 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF;
740
741#ifdef VR_USEIOSPACE
742 if (!(command & PCIM_CMD_PORTEN)) {
fa23be1c 743 device_printf(dev, "failed to enable I/O ports!\n");
984263bc
MD
744 free(sc, M_DEVBUF);
745 goto fail;
746 }
747#else
748 if (!(command & PCIM_CMD_MEMEN)) {
fa23be1c 749 device_printf(dev, "failed to enable memory mapping!\n");
984263bc
MD
750 goto fail;
751 }
752#endif
753
754 rid = VR_RID;
fa23be1c 755 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE);
984263bc
MD
756
757 if (sc->vr_res == NULL) {
fa23be1c 758 device_printf(dev, "couldn't map ports/memory\n");
984263bc
MD
759 error = ENXIO;
760 goto fail;
761 }
762
763 sc->vr_btag = rman_get_bustag(sc->vr_res);
764 sc->vr_bhandle = rman_get_bushandle(sc->vr_res);
765
766 /* Allocate interrupt */
767 rid = 0;
fa23be1c
JS
768 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
769 RF_SHAREABLE | RF_ACTIVE);
984263bc
MD
770
771 if (sc->vr_irq == NULL) {
fa23be1c 772 device_printf(dev, "couldn't map interrupt\n");
984263bc
MD
773 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
774 error = ENXIO;
775 goto fail;
776 }
777
778 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET,
779 vr_intr, sc, &sc->vr_intrhand);
780
781 if (error) {
782 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
783 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
fa23be1c 784 device_printf(dev, "couldn't set up irq\n");
984263bc
MD
785 goto fail;
786 }
787
788 /*
789 * Windows may put the chip in suspend mode when it
790 * shuts down. Be sure to kick it in the head to wake it
791 * up again.
792 */
793 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1));
794
795 /* Reset the adapter. */
796 vr_reset(sc);
797
798 /*
799 * Turn on bit2 (MIION) in PCI configuration register 0x53 during
800 * initialization and disable AUTOPOLL.
801 */
802 pci_write_config(dev, VR_PCI_MODE,
803 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4);
804 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL);
805
806 /*
807 * Get station address. The way the Rhine chips work,
808 * you're not allowed to directly access the EEPROM once
809 * they've been programmed a special way. Consequently,
810 * we need to read the node address from the PAR0 and PAR1
811 * registers.
812 */
813 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
814 DELAY(200);
815 for (i = 0; i < ETHER_ADDR_LEN; i++)
816 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
817
984263bc
MD
818 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF,
819 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
820
821 if (sc->vr_ldata == NULL) {
fa23be1c 822 device_printf(dev, "no memory for list buffers!\n");
984263bc
MD
823 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
824 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
825 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
826 error = ENXIO;
827 goto fail;
828 }
829
830 bzero(sc->vr_ldata, sizeof(struct vr_list_data));
831
832 ifp = &sc->arpcom.ac_if;
833 ifp->if_softc = sc;
fa23be1c 834 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
984263bc
MD
835 ifp->if_mtu = ETHERMTU;
836 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
837 ifp->if_ioctl = vr_ioctl;
984263bc
MD
838 ifp->if_start = vr_start;
839 ifp->if_watchdog = vr_watchdog;
840 ifp->if_init = vr_init;
841 ifp->if_baudrate = 10000000;
842 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1;
843
844 /*
845 * Do MII setup.
846 */
847 if (mii_phy_probe(dev, &sc->vr_miibus,
848 vr_ifmedia_upd, vr_ifmedia_sts)) {
fa23be1c 849 if_printf(ifp, "MII without any phy!\n");
984263bc
MD
850 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
851 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
852 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
853 contigfree(sc->vr_ldata,
854 sizeof(struct vr_list_data), M_DEVBUF);
855 error = ENXIO;
856 goto fail;
857 }
858
fa23be1c 859 /* Call MI attach routine. */
0a8b5977 860 ether_ifattach(ifp, eaddr);
984263bc
MD
861
862fail:
863 splx(s);
864 return(error);
865}
866
fa23be1c
JS
867static int
868vr_detach(device_t dev)
984263bc 869{
fa23be1c
JS
870 struct vr_softc *sc;
871 struct ifnet *ifp;
872 int s;
984263bc
MD
873
874 s = splimp();
875
876 sc = device_get_softc(dev);
877 ifp = &sc->arpcom.ac_if;
878
879 vr_stop(sc);
0a8b5977 880 ether_ifdetach(ifp);
984263bc
MD
881
882 bus_generic_detach(dev);
883 device_delete_child(dev, sc->vr_miibus);
884
885 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
886 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
887 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
888
889 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF);
890
891 splx(s);
892
893 return(0);
894}
895
896/*
897 * Initialize the transmit descriptors.
898 */
fa23be1c
JS
899static int
900vr_list_tx_init(struct vr_softc *sc)
984263bc 901{
fa23be1c
JS
902 struct vr_chain_data *cd;
903 struct vr_list_data *ld;
904 int i, nexti;
984263bc
MD
905
906 cd = &sc->vr_cdata;
907 ld = sc->vr_ldata;
908 for (i = 0; i < VR_TX_LIST_CNT; i++) {
909 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i];
910 if (i == (VR_TX_LIST_CNT - 1))
fa23be1c 911 nexti = 0;
984263bc 912 else
fa23be1c
JS
913 nexti = i + 1;
914 cd->vr_tx_chain[i].vr_nextdesc = &cd->vr_tx_chain[nexti];
984263bc
MD
915 }
916
917 cd->vr_tx_free = &cd->vr_tx_chain[0];
918 cd->vr_tx_tail = cd->vr_tx_head = NULL;
919
920 return(0);
921}
922
923
924/*
925 * Initialize the RX descriptors and allocate mbufs for them. Note that
926 * we arrange the descriptors in a closed ring, so that the last descriptor
927 * points back to the first.
928 */
fa23be1c
JS
929static int
930vr_list_rx_init(struct vr_softc *sc)
984263bc 931{
fa23be1c
JS
932 struct vr_chain_data *cd;
933 struct vr_list_data *ld;
934 int i, nexti;
984263bc
MD
935
936 cd = &sc->vr_cdata;
937 ld = sc->vr_ldata;
938
939 for (i = 0; i < VR_RX_LIST_CNT; i++) {
fa23be1c 940 cd->vr_rx_chain[i].vr_ptr = (struct vr_desc *)&ld->vr_rx_list[i];
984263bc
MD
941 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS)
942 return(ENOBUFS);
fa23be1c
JS
943 if (i == (VR_RX_LIST_CNT - 1))
944 nexti = 0;
945 else
946 nexti = i + 1;
947 cd->vr_rx_chain[i].vr_nextdesc = &cd->vr_rx_chain[nexti];
948 ld->vr_rx_list[i].vr_next = vtophys(&ld->vr_rx_list[nexti]);
984263bc
MD
949 }
950
951 cd->vr_rx_head = &cd->vr_rx_chain[0];
952
953 return(0);
954}
955
956/*
957 * Initialize an RX descriptor and attach an MBUF cluster.
958 * Note: the length fields are only 11 bits wide, which means the
959 * largest size we can specify is 2047. This is important because
960 * MCLBYTES is 2048, so we have to subtract one otherwise we'll
961 * overflow the field and make a mess.
962 */
fa23be1c
JS
963static int
964vr_newbuf(struct vr_softc *sc, struct vr_chain_onefrag *c, struct mbuf *m)
984263bc 965{
fa23be1c 966 struct mbuf *m_new = NULL;
984263bc
MD
967
968 if (m == NULL) {
74f1caca 969 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
984263bc
MD
970 if (m_new == NULL)
971 return(ENOBUFS);
972
74f1caca 973 MCLGET(m_new, MB_DONTWAIT);
984263bc
MD
974 if (!(m_new->m_flags & M_EXT)) {
975 m_freem(m_new);
976 return(ENOBUFS);
977 }
978 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
979 } else {
980 m_new = m;
981 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
982 m_new->m_data = m_new->m_ext.ext_buf;
983 }
984
fa23be1c 985 m_adj(m_new, sizeof(uint64_t));
984263bc
MD
986
987 c->vr_mbuf = m_new;
988 c->vr_ptr->vr_status = VR_RXSTAT;
989 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t));
990 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN;
991
992 return(0);
993}
994
995/*
996 * A frame has been uploaded: pass the resulting mbuf chain up to
997 * the higher level protocols.
998 */
fa23be1c
JS
999static void
1000vr_rxeof(struct vr_softc *sc)
984263bc 1001{
fa23be1c
JS
1002 struct mbuf *m;
1003 struct ifnet *ifp;
1004 struct vr_chain_onefrag *cur_rx;
1005 int total_len = 0;
1006 uint32_t rxstat;
984263bc
MD
1007
1008 ifp = &sc->arpcom.ac_if;
1009
1010 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) &
1011 VR_RXSTAT_OWN)) {
fa23be1c 1012 struct mbuf *m0 = NULL;
984263bc
MD
1013
1014 cur_rx = sc->vr_cdata.vr_rx_head;
1015 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc;
1016 m = cur_rx->vr_mbuf;
1017
1018 /*
1019 * If an error occurs, update stats, clear the
1020 * status word and leave the mbuf cluster in place:
1021 * it should simply get re-used next time this descriptor
1022 * comes up in the ring.
1023 */
1024 if (rxstat & VR_RXSTAT_RXERR) {
1025 ifp->if_ierrors++;
fa23be1c 1026 if_printf(ifp, "rx error (%02x):", rxstat & 0x000000ff);
984263bc
MD
1027 if (rxstat & VR_RXSTAT_CRCERR)
1028 printf(" crc error");
1029 if (rxstat & VR_RXSTAT_FRAMEALIGNERR)
1030 printf(" frame alignment error\n");
1031 if (rxstat & VR_RXSTAT_FIFOOFLOW)
1032 printf(" FIFO overflow");
1033 if (rxstat & VR_RXSTAT_GIANT)
1034 printf(" received giant packet");
1035 if (rxstat & VR_RXSTAT_RUNT)
1036 printf(" received runt packet");
1037 if (rxstat & VR_RXSTAT_BUSERR)
1038 printf(" system bus error");
1039 if (rxstat & VR_RXSTAT_BUFFERR)
1040 printf("rx buffer error");
1041 printf("\n");
1042 vr_newbuf(sc, cur_rx, m);
1043 continue;
1044 }
1045
1046 /* No errors; receive the packet. */
1047 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status);
1048
1049 /*
1050 * XXX The VIA Rhine chip includes the CRC with every
1051 * received frame, and there's no way to turn this
1052 * behavior off (at least, I can't find anything in
1053 * the manual that explains how to do it) so we have
1054 * to trim off the CRC manually.
1055 */
1056 total_len -= ETHER_CRC_LEN;
1057
1058 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1059 total_len + ETHER_ALIGN, 0, ifp, NULL);
1060 vr_newbuf(sc, cur_rx, m);
1061 if (m0 == NULL) {
1062 ifp->if_ierrors++;
1063 continue;
1064 }
1065 m_adj(m0, ETHER_ALIGN);
1066 m = m0;
1067
1068 ifp->if_ipackets++;
3013ac0e 1069 (*ifp->if_input)(ifp, m);
984263bc 1070 }
984263bc
MD
1071}
1072
fa23be1c
JS
1073static void
1074vr_rxeoc(struct vr_softc *sc)
984263bc 1075{
fa23be1c
JS
1076 struct ifnet *ifp;
1077 int i;
984263bc
MD
1078
1079 ifp = &sc->arpcom.ac_if;
1080
1081 ifp->if_ierrors++;
1082
1083 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1084 DELAY(10000);
1085
fa23be1c 1086 /* Wait for receiver to stop */
984263bc
MD
1087 for (i = 0x400;
1088 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON);
1089 i--)
1090 ; /* Wait for receiver to stop */
1091
fa23be1c
JS
1092 if (i == 0) {
1093 if_printf(ifp, "rx shutdown error!\n");
984263bc
MD
1094 sc->vr_flags |= VR_F_RESTART;
1095 return;
fa23be1c 1096 }
984263bc
MD
1097
1098 vr_rxeof(sc);
1099
1100 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr));
1101 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1102 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO);
984263bc
MD
1103}
1104
1105/*
1106 * A frame was downloaded to the chip. It's safe for us to clean up
1107 * the list buffers.
1108 */
fa23be1c
JS
1109static void
1110vr_txeof(struct vr_softc *sc)
984263bc 1111{
fa23be1c
JS
1112 struct vr_chain *cur_tx;
1113 struct ifnet *ifp;
984263bc
MD
1114
1115 ifp = &sc->arpcom.ac_if;
1116
1117 /* Reset the timeout timer; if_txeoc will clear it. */
1118 ifp->if_timer = 5;
1119
1120 /* Sanity check. */
1121 if (sc->vr_cdata.vr_tx_head == NULL)
1122 return;
1123
1124 /*
1125 * Go through our tx list and free mbufs for those
1126 * frames that have been transmitted.
1127 */
1128 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) {
fa23be1c
JS
1129 uint32_t txstat;
1130 int i;
984263bc
MD
1131
1132 cur_tx = sc->vr_cdata.vr_tx_head;
1133 txstat = cur_tx->vr_ptr->vr_status;
1134
1135 if ((txstat & VR_TXSTAT_ABRT) ||
1136 (txstat & VR_TXSTAT_UDF)) {
1137 for (i = 0x400;
1138 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON);
1139 i--)
1140 ; /* Wait for chip to shutdown */
fa23be1c
JS
1141 if (i == 0) {
1142 if_printf(ifp, "tx shutdown timeout\n");
984263bc
MD
1143 sc->vr_flags |= VR_F_RESTART;
1144 break;
1145 }
1146 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1147 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr));
1148 break;
1149 }
1150
1151 if (txstat & VR_TXSTAT_OWN)
1152 break;
1153
1154 if (txstat & VR_TXSTAT_ERRSUM) {
1155 ifp->if_oerrors++;
1156 if (txstat & VR_TXSTAT_DEFER)
1157 ifp->if_collisions++;
1158 if (txstat & VR_TXSTAT_LATECOLL)
1159 ifp->if_collisions++;
1160 }
1161
1162 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3;
1163
1164 ifp->if_opackets++;
1165 if (cur_tx->vr_mbuf != NULL) {
1166 m_freem(cur_tx->vr_mbuf);
1167 cur_tx->vr_mbuf = NULL;
1168 }
1169
1170 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) {
1171 sc->vr_cdata.vr_tx_head = NULL;
1172 sc->vr_cdata.vr_tx_tail = NULL;
1173 break;
1174 }
1175
1176 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc;
1177 }
984263bc
MD
1178}
1179
1180/*
1181 * TX 'end of channel' interrupt handler.
1182 */
fa23be1c
JS
1183static void
1184vr_txeoc(struct vr_softc *sc)
984263bc 1185{
fa23be1c 1186 struct ifnet *ifp;
984263bc
MD
1187
1188 ifp = &sc->arpcom.ac_if;
1189
1190 if (sc->vr_cdata.vr_tx_head == NULL) {
1191 ifp->if_flags &= ~IFF_OACTIVE;
1192 sc->vr_cdata.vr_tx_tail = NULL;
1193 ifp->if_timer = 0;
1194 }
984263bc
MD
1195}
1196
fa23be1c
JS
1197static void
1198vr_tick(void *xsc)
984263bc 1199{
fa23be1c
JS
1200 struct vr_softc *sc;
1201 struct mii_data *mii;
1202 int s;
984263bc
MD
1203
1204 s = splimp();
1205
1206 sc = xsc;
1207 if (sc->vr_flags & VR_F_RESTART) {
fa23be1c 1208 if_printf(&sc->arpcom.ac_if, "restarting\n");
984263bc
MD
1209 vr_stop(sc);
1210 vr_reset(sc);
1211 vr_init(sc);
1212 sc->vr_flags &= ~VR_F_RESTART;
1213 }
1214
1215 mii = device_get_softc(sc->vr_miibus);
1216 mii_tick(mii);
1217
9e6fd080 1218 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc);
984263bc
MD
1219
1220 splx(s);
984263bc
MD
1221}
1222
fa23be1c
JS
1223static void
1224vr_intr(void *arg)
984263bc 1225{
fa23be1c
JS
1226 struct vr_softc *sc;
1227 struct ifnet *ifp;
1228 uint16_t status;
984263bc
MD
1229
1230 sc = arg;
1231 ifp = &sc->arpcom.ac_if;
1232
1233 /* Supress unwanted interrupts. */
1234 if (!(ifp->if_flags & IFF_UP)) {
1235 vr_stop(sc);
1236 return;
1237 }
1238
1239 /* Disable interrupts. */
c8fb08d8
MD
1240 if ((ifp->if_flags & IFF_POLLING) == 0)
1241 CSR_WRITE_2(sc, VR_IMR, 0x0000);
984263bc
MD
1242
1243 for (;;) {
984263bc
MD
1244 status = CSR_READ_2(sc, VR_ISR);
1245 if (status)
1246 CSR_WRITE_2(sc, VR_ISR, status);
1247
1248 if ((status & VR_INTRS) == 0)
1249 break;
1250
1251 if (status & VR_ISR_RX_OK)
1252 vr_rxeof(sc);
1253
1254 if (status & VR_ISR_RX_DROPPED) {
fa23be1c 1255 if_printf(ifp, "rx packet lost\n");
984263bc
MD
1256 ifp->if_ierrors++;
1257 }
1258
1259 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) ||
1260 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) {
fa23be1c 1261 if_printf(ifp, "receive error (%04x)", status);
984263bc
MD
1262 if (status & VR_ISR_RX_NOBUF)
1263 printf(" no buffers");
1264 if (status & VR_ISR_RX_OFLOW)
1265 printf(" overflow");
1266 if (status & VR_ISR_RX_DROPPED)
1267 printf(" packet lost");
1268 printf("\n");
1269 vr_rxeoc(sc);
1270 }
1271
1272 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) {
1273 vr_reset(sc);
1274 vr_init(sc);
1275 break;
1276 }
1277
1278 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) ||
1279 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) {
1280 vr_txeof(sc);
1281 if ((status & VR_ISR_UDFI) ||
1282 (status & VR_ISR_TX_ABRT2) ||
1283 (status & VR_ISR_TX_ABRT)) {
1284 ifp->if_oerrors++;
1285 if (sc->vr_cdata.vr_tx_head != NULL) {
1286 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON);
1287 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO);
1288 }
fa23be1c 1289 } else {
984263bc 1290 vr_txeoc(sc);
fa23be1c 1291 }
984263bc
MD
1292 }
1293
1294 }
1295
1296 /* Re-enable interrupts. */
c8fb08d8
MD
1297 if ((ifp->if_flags & IFF_POLLING) == 0)
1298 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
984263bc 1299
fa23be1c 1300 if (ifp->if_snd.ifq_head != NULL)
984263bc 1301 vr_start(ifp);
984263bc
MD
1302}
1303
1304/*
1305 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1306 * pointers to the fragment pointers.
1307 */
fa23be1c
JS
1308static int
1309vr_encap(struct vr_softc *sc, struct vr_chain *c, struct mbuf *m_head)
984263bc 1310{
fa23be1c
JS
1311 int frag = 0;
1312 struct vr_desc *f = NULL;
1313 int total_len;
5f0a6e55 1314 struct mbuf *m_new;
984263bc 1315
984263bc
MD
1316 total_len = 0;
1317
1318 /*
1319 * The VIA Rhine wants packet buffers to be longword
1320 * aligned, but very often our mbufs aren't. Rather than
1321 * waste time trying to decide when to copy and when not
1322 * to copy, just do it all the time.
1323 */
5f0a6e55
JS
1324 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1325 if (m_new == NULL) {
1326 if_printf(&sc->arpcom.ac_if, "no memory for tx list\n");
1327 return(1);
1328 }
1329 if (m_head->m_pkthdr.len > MHLEN) {
1330 MCLGET(m_new, MB_DONTWAIT);
1331 if (!(m_new->m_flags & M_EXT)) {
1332 m_freem(m_new);
1333 if_printf(&sc->arpcom.ac_if,
1334 "no memory for tx list\n");
984263bc
MD
1335 return(1);
1336 }
984263bc 1337 }
5f0a6e55
JS
1338 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1339 mtod(m_new, caddr_t));
1340 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1341 /*
1342 * The Rhine chip doesn't auto-pad, so we have to make
1343 * sure to pad short frames out to the minimum frame length
1344 * ourselves.
1345 */
1346 if (m_new->m_len < VR_MIN_FRAMELEN) {
1347 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len;
1348 m_new->m_len = m_new->m_pkthdr.len;
1349 }
1350 f = c->vr_ptr;
1351 f->vr_data = vtophys(mtod(m_new, caddr_t));
1352 f->vr_ctl = total_len = m_new->m_len;
1353 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG;
1354 f->vr_status = 0;
1355 frag = 1;
984263bc 1356
5f0a6e55 1357 c->vr_mbuf = m_new;
984263bc
MD
1358 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT;
1359 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr);
1360
1361 return(0);
1362}
1363
1364/*
1365 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1366 * to the mbuf data regions directly in the transmit lists. We also save a
1367 * copy of the pointers since the transmit list fragment pointers are
1368 * physical addresses.
1369 */
fa23be1c
JS
1370static void
1371vr_start(struct ifnet *ifp)
984263bc 1372{
fa23be1c
JS
1373 struct vr_softc *sc;
1374 struct mbuf *m_head = NULL;
1375 struct vr_chain *cur_tx = NULL, *start_tx;
984263bc
MD
1376
1377 sc = ifp->if_softc;
1378
1379 if (ifp->if_flags & IFF_OACTIVE)
1380 return;
1381
fa23be1c 1382 /* Check for an available queue slot. If there are none, punt. */
984263bc
MD
1383 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) {
1384 ifp->if_flags |= IFF_OACTIVE;
1385 return;
1386 }
1387
1388 start_tx = sc->vr_cdata.vr_tx_free;
1389
1390 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) {
1391 IF_DEQUEUE(&ifp->if_snd, m_head);
1392 if (m_head == NULL)
1393 break;
1394
1395 /* Pick a descriptor off the free list. */
1396 cur_tx = sc->vr_cdata.vr_tx_free;
1397 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc;
1398
1399 /* Pack the data into the descriptor. */
1400 if (vr_encap(sc, cur_tx, m_head)) {
1401 IF_PREPEND(&ifp->if_snd, m_head);
1402 ifp->if_flags |= IFF_OACTIVE;
1403 cur_tx = NULL;
1404 break;
1405 }
1406
1407 if (cur_tx != start_tx)
1408 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1409
5f0a6e55
JS
1410 BPF_MTAP(ifp, m_head);
1411 m_freem(m_head);
984263bc
MD
1412
1413 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1414 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO);
1415 }
1416
fa23be1c 1417 /* If there are no frames queued, bail. */
984263bc
MD
1418 if (cur_tx == NULL)
1419 return;
1420
1421 sc->vr_cdata.vr_tx_tail = cur_tx;
1422
1423 if (sc->vr_cdata.vr_tx_head == NULL)
1424 sc->vr_cdata.vr_tx_head = start_tx;
1425
1426 /*
1427 * Set a timeout in case the chip goes out to lunch.
1428 */
1429 ifp->if_timer = 5;
984263bc
MD
1430}
1431
fa23be1c
JS
1432static void
1433vr_init(void *xsc)
984263bc 1434{
fa23be1c
JS
1435 struct vr_softc *sc = xsc;
1436 struct ifnet *ifp = &sc->arpcom.ac_if;
1437 struct mii_data *mii;
1438 int s, i;
984263bc
MD
1439
1440 s = splimp();
1441
1442 mii = device_get_softc(sc->vr_miibus);
1443
fa23be1c 1444 /* Cancel pending I/O and free all RX/TX buffers. */
984263bc
MD
1445 vr_stop(sc);
1446 vr_reset(sc);
1447
fa23be1c 1448 /* Set our station address. */
984263bc
MD
1449 for (i = 0; i < ETHER_ADDR_LEN; i++)
1450 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]);
fa23be1c
JS
1451
1452 /* Set DMA size. */
984263bc
MD
1453 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH);
1454 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD);
1455
fa23be1c 1456 /*
984263bc
MD
1457 * BCR0 and BCR1 can override the RXCFG and TXCFG registers,
1458 * so we must set both.
1459 */
1460 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH);
1461 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES);
1462
1463 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH);
1464 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD);
1465
1466 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH);
1467 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES);
1468
1469 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH);
1470 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD);
1471
1472 /* Init circular RX list. */
1473 if (vr_list_rx_init(sc) == ENOBUFS) {
fa23be1c 1474 if_printf(ifp, "initialization failed: no memory for rx buffers\n");
984263bc 1475 vr_stop(sc);
fa23be1c 1476 splx(s);
984263bc
MD
1477 return;
1478 }
1479
fa23be1c 1480 /* Init tx descriptors. */
984263bc
MD
1481 vr_list_tx_init(sc);
1482
1483 /* If we want promiscuous mode, set the allframes bit. */
1484 if (ifp->if_flags & IFF_PROMISC)
1485 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1486 else
1487 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1488
1489 /* Set capture broadcast bit to capture broadcast frames. */
1490 if (ifp->if_flags & IFF_BROADCAST)
1491 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1492 else
1493 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1494
1495 /*
1496 * Program the multicast filter, if necessary.
1497 */
1498 vr_setmulti(sc);
1499
1500 /*
1501 * Load the address of the RX list.
1502 */
1503 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr));
1504
1505 /* Enable receiver and transmitter. */
1506 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START|
1507 VR_CMD_TX_ON|VR_CMD_RX_ON|
1508 VR_CMD_RX_GO);
1509
1510 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0]));
1511
1512 /*
c8fb08d8 1513 * Enable interrupts, unless we are polling.
984263bc
MD
1514 */
1515 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
60cf96dd 1516 if ((ifp->if_flags & IFF_POLLING) == 0)
c8fb08d8 1517 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
984263bc
MD
1518
1519 mii_mediachg(mii);
1520
1521 ifp->if_flags |= IFF_RUNNING;
1522 ifp->if_flags &= ~IFF_OACTIVE;
1523
fa23be1c 1524 splx(s);
984263bc 1525
9e6fd080 1526 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc);
984263bc
MD
1527}
1528
1529/*
1530 * Set media options.
1531 */
fa23be1c
JS
1532static int
1533vr_ifmedia_upd(struct ifnet *ifp)
984263bc 1534{
fa23be1c 1535 struct vr_softc *sc;
984263bc
MD
1536
1537 sc = ifp->if_softc;
1538
1539 if (ifp->if_flags & IFF_UP)
1540 vr_init(sc);
1541
1542 return(0);
1543}
1544
1545/*
1546 * Report current media status.
1547 */
fa23be1c
JS
1548static void
1549vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc 1550{
fa23be1c
JS
1551 struct vr_softc *sc;
1552 struct mii_data *mii;
984263bc
MD
1553
1554 sc = ifp->if_softc;
1555 mii = device_get_softc(sc->vr_miibus);
1556 mii_pollstat(mii);
1557 ifmr->ifm_active = mii->mii_media_active;
1558 ifmr->ifm_status = mii->mii_media_status;
984263bc
MD
1559}
1560
fa23be1c
JS
1561static int
1562vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc 1563{
fa23be1c
JS
1564 struct vr_softc *sc = ifp->if_softc;
1565 struct ifreq *ifr = (struct ifreq *) data;
1566 struct mii_data *mii;
1567 int s, error = 0;
984263bc
MD
1568
1569 s = splimp();
1570
1571 switch(command) {
1572 case SIOCSIFADDR:
1573 case SIOCGIFADDR:
1574 case SIOCSIFMTU:
1575 error = ether_ioctl(ifp, command, data);
1576 break;
1577 case SIOCSIFFLAGS:
1578 if (ifp->if_flags & IFF_UP) {
1579 vr_init(sc);
1580 } else {
1581 if (ifp->if_flags & IFF_RUNNING)
1582 vr_stop(sc);
1583 }
1584 error = 0;
1585 break;
1586 case SIOCADDMULTI:
1587 case SIOCDELMULTI:
1588 vr_setmulti(sc);
1589 error = 0;
1590 break;
1591 case SIOCGIFMEDIA:
1592 case SIOCSIFMEDIA:
1593 mii = device_get_softc(sc->vr_miibus);
1594 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1595 break;
1596 default:
1597 error = EINVAL;
1598 break;
1599 }
1600
fa23be1c 1601 splx(s);
984263bc
MD
1602
1603 return(error);
1604}
1605
c8fb08d8 1606#ifdef DEVICE_POLLING
fa23be1c 1607static void
c8fb08d8
MD
1608vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1609{
1610 struct vr_softc *sc = ifp->if_softc;
1611
fa23be1c 1612 if (cmd == POLL_DEREGISTER)
c8fb08d8 1613 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
fa23be1c 1614 else
c8fb08d8 1615 vr_intr(sc);
c8fb08d8 1616}
c8fb08d8
MD
1617#endif
1618
fa23be1c
JS
1619static void
1620vr_watchdog(struct ifnet *ifp)
984263bc 1621{
fa23be1c 1622 struct vr_softc *sc;
984263bc
MD
1623
1624 sc = ifp->if_softc;
1625
1626 ifp->if_oerrors++;
fa23be1c 1627 if_printf(ifp, "watchdog timeout\n");
984263bc 1628
c8fb08d8
MD
1629#ifdef DEVICE_POLLING
1630 if (++sc->vr_wdogerrors == 1 && (ifp->if_flags & IFF_POLLING) == 0) {
fa23be1c
JS
1631 if_printf(ifp, "ints don't seem to be working, "
1632 "emergency switch to polling\n");
c8fb08d8 1633 emergency_poll_enable("if_vr");
fa23be1c 1634 if (ether_poll_register(vr_poll, ifp))
c8fb08d8 1635 CSR_WRITE_2(sc, VR_IMR, 0x0000);
c8fb08d8
MD
1636 } else
1637#endif
1638 {
1639 vr_stop(sc);
1640 vr_reset(sc);
1641 vr_init(sc);
1642 }
984263bc
MD
1643
1644 if (ifp->if_snd.ifq_head != NULL)
1645 vr_start(ifp);
984263bc
MD
1646}
1647
1648/*
1649 * Stop the adapter and free any mbufs allocated to the
1650 * RX and TX lists.
1651 */
fa23be1c
JS
1652static void
1653vr_stop(struct vr_softc *sc)
984263bc 1654{
fa23be1c
JS
1655 int i;
1656 struct ifnet *ifp;
984263bc
MD
1657
1658 ifp = &sc->arpcom.ac_if;
1659 ifp->if_timer = 0;
1660
9e6fd080 1661 callout_stop(&sc->vr_stat_timer);
984263bc
MD
1662
1663 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP);
1664 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON));
1665 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1666 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000);
1667 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000);
1668
1669 /*
1670 * Free data in the RX lists.
1671 */
1672 for (i = 0; i < VR_RX_LIST_CNT; i++) {
1673 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) {
1674 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf);
1675 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL;
1676 }
1677 }
1678 bzero((char *)&sc->vr_ldata->vr_rx_list,
1679 sizeof(sc->vr_ldata->vr_rx_list));
1680
1681 /*
1682 * Free the TX list buffers.
1683 */
1684 for (i = 0; i < VR_TX_LIST_CNT; i++) {
1685 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) {
1686 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf);
1687 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL;
1688 }
1689 }
1690
1691 bzero((char *)&sc->vr_ldata->vr_tx_list,
1692 sizeof(sc->vr_ldata->vr_tx_list));
1693
1694 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
984263bc
MD
1695}
1696
1697/*
1698 * Stop all chip I/O so that the kernel's probe routines don't
1699 * get confused by errant DMAs when rebooting.
1700 */
fa23be1c
JS
1701static void
1702vr_shutdown(device_t dev)
984263bc 1703{
fa23be1c 1704 struct vr_softc *sc;
984263bc
MD
1705
1706 sc = device_get_softc(dev);
1707
1708 vr_stop(sc);
984263bc 1709}