- Add codec id for Realtek ALC268.
[dragonfly.git] / sys / dev / sound / pci / hda / hdac.c
CommitLineData
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1/*-
2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
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27 * $FreeBSD: src/sys/dev/sound/pci/hda/hdac.c,v 1.36.2.5 2007/07/12 06:39:08 ariff Exp $
28 * $DragonFly: src/sys/dev/sound/pci/hda/hdac.c,v 1.11 2007/11/30 07:47:44 hasso Exp $
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29 */
30
31/*
32 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised
33 * that this driver still in its early stage, and possible of rewrite are
34 * pretty much guaranteed. There are supposedly several distinct parent/child
35 * busses to make this "perfect", but as for now and for the sake of
36 * simplicity, everything is gobble up within single source.
37 *
38 * List of subsys:
39 * 1) HDA Controller support
40 * 2) HDA Codecs support, which may include
41 * - HDA
42 * - Modem
43 * - HDMI
44 * 3) Widget parser - the real magic of why this driver works on so
45 * many hardwares with minimal vendor specific quirk. The original
46 * parser was written using Ruby and can be found at
47 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude
48 * ruby parser take the verbose dmesg dump as its input. Refer to
49 * http://www.microsoft.com/whdc/device/audio/default.mspx for various
4886ec58 50 * interesting documents, especially UAA (Universal Audio Architecture).
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51 * 4) Possible vendor specific support.
52 * (snd_hda_intel, snd_hda_ati, etc..)
53 *
54 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the
55 * Compaq V3000 with Conexant HDA.
56 *
57 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
58 * * *
59 * * This driver is a collaborative effort made by: *
60 * * *
61 * * Stephane E. Potvin <sepotvin@videotron.ca> *
62 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> *
63 * * Wesley Morgan <morganw@chemikals.org> *
64 * * Daniel Eischen <deischen@FreeBSD.org> *
65 * * Maxime Guillaud <bsd-ports@mguillaud.net> *
66 * * Ariff Abdullah <ariff@FreeBSD.org> *
67 * * *
68 * * ....and various people from freebsd-multimedia@FreeBSD.org *
69 * * *
70 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
71 */
72
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73#include <dev/sound/pcm/sound.h>
74#include <bus/pci/pcireg.h>
75#include <bus/pci/pcivar.h>
76
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77#include <sys/ctype.h>
78#include <sys/taskqueue.h>
79
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80#include <dev/sound/pci/hda/hdac_private.h>
81#include <dev/sound/pci/hda/hdac_reg.h>
82#include <dev/sound/pci/hda/hda_reg.h>
83#include <dev/sound/pci/hda/hdac.h>
84
85#include "mixer_if.h"
86
6ef811ff 87#define HDA_DRV_TEST_REV "20070710_0047"
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88#define HDA_WIDGET_PARSER_REV 1
89
6ef811ff 90SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/hda/hdac.c,v 1.11 2007/11/30 07:47:44 hasso Exp $");
558a398b 91
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92#define HDA_BOOTVERBOSE(stmt) do { \
93 if (bootverbose != 0) { \
94 stmt \
95 } \
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96} while(0)
97
98#if 1
99#undef HDAC_INTR_EXTRA
100#define HDAC_INTR_EXTRA 1
101#endif
102
103#define hdac_lock(sc) snd_mtxlock((sc)->lock)
104#define hdac_unlock(sc) snd_mtxunlock((sc)->lock)
105#define hdac_lockassert(sc) snd_mtxassert((sc)->lock)
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106#define hdac_lockowned(sc) (1)/* mtx_owned((sc)->lock) */
107
108#if 0 /* TODO: No uncacheable DMA support in DragonFly. */
109#include <machine/specialreg.h>
110#define HDAC_DMA_ATTR(sc, v, s, attr) do { \
111 vm_offset_t va = (vm_offset_t)(v); \
112 vm_size_t sz = (vm_size_t)(s); \
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113 if ((sc) != NULL && ((sc)->flags & HDAC_F_DMA_NOCACHE) && \
114 va != 0 && sz != 0) \
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115 (void)pmap_change_attr(va, sz, (attr)); \
116} while(0)
117#else
118#define HDAC_DMA_ATTR(...)
119#endif
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120
121#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v))
122#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \
123 (fl) == 0xffffffff || \
124 (((fl) & 0xffff0000) == 0xffff0000 && \
125 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \
126 (((fl) & 0x0000ffff) == 0x0000ffff && \
127 ((fl) & 0xffff0000) == ((v) & 0xffff0000)))
128#define HDA_MATCH_ALL 0xffffffff
129#define HDAC_INVALID 0xffffffff
130
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131/* Default controller / jack sense poll: 250ms */
132#define HDAC_POLL_INTERVAL max(hz >> 2, 1)
133
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134/*
135 * Make room for possible 4096 playback/record channels, in 100 years to come.
136 */
137#define HDAC_TRIGGER_NONE 0x00000000
138#define HDAC_TRIGGER_PLAY 0x00000fff
139#define HDAC_TRIGGER_REC 0x00fff000
140#define HDAC_TRIGGER_UNSOL 0x80000000
141
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142#define HDA_MODEL_CONSTRUCT(vendor, model) \
143 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff))
144
145/* Controller models */
146
147/* Intel */
148#define INTEL_VENDORID 0x8086
149#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668)
6ef811ff 150#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a)
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151#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8)
152#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b)
6ef811ff 153#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e)
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154#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff)
155
156/* Nvidia */
157#define NVIDIA_VENDORID 0x10de
158#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c)
159#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371)
160#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4)
161#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0)
162#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a)
163#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b)
164#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff)
165
166/* ATI */
167#define ATI_VENDORID 0x1002
168#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b)
169#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383)
170#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff)
171
172/* VIA */
173#define VIA_VENDORID 0x1106
174#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288)
175#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff)
176
177/* SiS */
178#define SIS_VENDORID 0x1039
179#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502)
180#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff)
181
182/* OEM/subvendors */
183
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184/* Intel */
185#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600)
186
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187/* HP/Compaq */
188#define HP_VENDORID 0x103c
189#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5)
190#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2)
191#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa)
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192#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0)
193#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013)
194#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010)
195#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5)
558a398b 196#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff)
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197/* What is wrong with XN 2563 anyway? (Got the picture ?) */
198#define HP_NX6325_SUBVENDORX 0x103c30b0
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199
200/* Dell */
201#define DELL_VENDORID 0x1028
202#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc)
203#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9)
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204#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7)
205#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da)
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206#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff)
207
208/* Clevo */
209#define CLEVO_VENDORID 0x1558
210#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900)
211#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff)
212
213/* Acer */
214#define ACER_VENDORID 0x1025
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215#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f)
216#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110)
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217#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff)
218
219/* Asus */
220#define ASUS_VENDORID 0x1043
221#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993)
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222#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
223#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153)
224#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
225#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323)
226#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2)
227#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
228#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971)
229#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338)
230#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7)
231#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234)
232#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
233#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec)
19c72e40 234#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84)
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235#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff)
236
237/* IBM / Lenovo */
238#define IBM_VENDORID 0x1014
239#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6)
240#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff)
241
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242/* Lenovo */
243#define LENOVO_VENDORID 0x17aa
244#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066)
245#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff)
246
247/* Samsung */
248#define SAMSUNG_VENDORID 0x144d
249#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027)
250#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff)
251
252/* Medion ? */
253#define MEDION_VENDORID 0x161f
254#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d)
255#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff)
256
257/*
258 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id
259 * instead of their own, which is beyond my comprehension
260 * (see HDA_CODEC_STAC9221 below).
261 */
262#define APPLE_INTEL_MAC 0x76808384
263
264/* LG Electronics */
265#define LG_VENDORID 0x1854
266#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018)
267#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff)
268
269/* Fujitsu Siemens */
270#define FS_VENDORID 0x1734
271#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8)
272#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff)
273
274/* Toshiba */
275#define TOSHIBA_VENDORID 0x1179
276#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001)
277#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff)
278
279/* Micro-Star International (MSI) */
280#define MSI_VENDORID 0x1462
281#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349)
282#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff)
283
284/* Uniwill ? */
285#define UNIWILL_VENDORID 0x1584
286#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075)
ef72a265 287#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080)
4886ec58 288
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289
290/* Misc constants.. */
291#define HDA_AMP_MUTE_DEFAULT (0xffffffff)
292#define HDA_AMP_MUTE_NONE (0)
293#define HDA_AMP_MUTE_LEFT (1 << 0)
294#define HDA_AMP_MUTE_RIGHT (1 << 1)
295#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT)
296
297#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT))
298#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1)
299
300#define HDA_DAC_PATH (1 << 0)
301#define HDA_ADC_PATH (1 << 1)
302#define HDA_ADC_RECSEL (1 << 2)
303
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304#define HDA_DAC_LOCKED (1 << 3)
305#define HDA_ADC_LOCKED (1 << 4)
306
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307#define HDA_CTL_OUT (1 << 0)
308#define HDA_CTL_IN (1 << 1)
309#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT)
310
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311#define HDA_GPIO_MAX 8
312/* 0 - 7 = GPIO , 8 = Flush */
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313#define HDA_QUIRK_GPIO0 (1 << 0)
314#define HDA_QUIRK_GPIO1 (1 << 1)
315#define HDA_QUIRK_GPIO2 (1 << 2)
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316#define HDA_QUIRK_GPIO3 (1 << 3)
317#define HDA_QUIRK_GPIO4 (1 << 4)
318#define HDA_QUIRK_GPIO5 (1 << 5)
319#define HDA_QUIRK_GPIO6 (1 << 6)
320#define HDA_QUIRK_GPIO7 (1 << 7)
321#define HDA_QUIRK_GPIOFLUSH (1 << 8)
322
323/* 9 - 25 = anything else */
324#define HDA_QUIRK_SOFTPCMVOL (1 << 9)
325#define HDA_QUIRK_FIXEDRATE (1 << 10)
326#define HDA_QUIRK_FORCESTEREO (1 << 11)
327#define HDA_QUIRK_EAPDINV (1 << 12)
328#define HDA_QUIRK_DMAPOS (1 << 13)
329
330/* 26 - 31 = vrefs */
331#define HDA_QUIRK_IVREF50 (1 << 26)
332#define HDA_QUIRK_IVREF80 (1 << 27)
333#define HDA_QUIRK_IVREF100 (1 << 28)
334#define HDA_QUIRK_OVREF50 (1 << 29)
335#define HDA_QUIRK_OVREF80 (1 << 30)
336#define HDA_QUIRK_OVREF100 (1 << 31)
337
338#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \
339 HDA_QUIRK_IVREF100)
340#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \
341 HDA_QUIRK_OVREF100)
342#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF)
343
344#define SOUND_MASK_SKIP (1 << 30)
345#define SOUND_MASK_DISABLE (1 << 31)
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346
347static const struct {
348 char *key;
349 uint32_t value;
350} hdac_quirks_tab[] = {
351 { "gpio0", HDA_QUIRK_GPIO0 },
352 { "gpio1", HDA_QUIRK_GPIO1 },
353 { "gpio2", HDA_QUIRK_GPIO2 },
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354 { "gpio3", HDA_QUIRK_GPIO3 },
355 { "gpio4", HDA_QUIRK_GPIO4 },
356 { "gpio5", HDA_QUIRK_GPIO5 },
357 { "gpio6", HDA_QUIRK_GPIO6 },
358 { "gpio7", HDA_QUIRK_GPIO7 },
359 { "gpioflush", HDA_QUIRK_GPIOFLUSH },
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360 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL },
361 { "fixedrate", HDA_QUIRK_FIXEDRATE },
362 { "forcestereo", HDA_QUIRK_FORCESTEREO },
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363 { "eapdinv", HDA_QUIRK_EAPDINV },
364 { "dmapos", HDA_QUIRK_DMAPOS },
365 { "ivref50", HDA_QUIRK_IVREF50 },
366 { "ivref80", HDA_QUIRK_IVREF80 },
367 { "ivref100", HDA_QUIRK_IVREF100 },
368 { "ovref50", HDA_QUIRK_OVREF50 },
369 { "ovref80", HDA_QUIRK_OVREF80 },
370 { "ovref100", HDA_QUIRK_OVREF100 },
371 { "ivref", HDA_QUIRK_IVREF },
372 { "ovref", HDA_QUIRK_OVREF },
373 { "vref", HDA_QUIRK_VREF },
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374};
375#define HDAC_QUIRKS_TAB_LEN \
376 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0]))
377
378#define HDA_BDL_MIN 2
379#define HDA_BDL_MAX 256
380#define HDA_BDL_DEFAULT HDA_BDL_MIN
381
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382#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT
383#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1))
384
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385#define HDA_BUFSZ_MIN 4096
386#define HDA_BUFSZ_MAX 65536
387#define HDA_BUFSZ_DEFAULT 16384
388
389#define HDA_PARSE_MAXDEPTH 10
390
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391#define HDAC_UNSOLTAG_EVENT_HP 0x00
392#define HDAC_UNSOLTAG_EVENT_TEST 0x01
558a398b 393
4886ec58 394MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller");
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395
396enum {
397 HDA_PARSE_MIXER,
398 HDA_PARSE_DIRECT
399};
400
401/* Default */
402static uint32_t hdac_fmt[] = {
403 AFMT_STEREO | AFMT_S16_LE,
404 0
405};
406
407static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0};
408
409static const struct {
410 uint32_t model;
411 char *desc;
412} hdac_devices[] = {
413 { HDA_INTEL_82801F, "Intel 82801F" },
6ef811ff 414 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" },
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415 { HDA_INTEL_82801G, "Intel 82801G" },
416 { HDA_INTEL_82801H, "Intel 82801H" },
6ef811ff 417 { HDA_INTEL_82801I, "Intel 82801I" },
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418 { HDA_NVIDIA_MCP51, "NVidia MCP51" },
419 { HDA_NVIDIA_MCP55, "NVidia MCP55" },
420 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" },
421 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" },
422 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" },
423 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" },
424 { HDA_ATI_SB450, "ATI SB450" },
425 { HDA_ATI_SB600, "ATI SB600" },
426 { HDA_VIA_VT82XX, "VIA VT8251/8237A" },
427 { HDA_SIS_966, "SiS 966" },
428 /* Unknown */
429 { HDA_INTEL_ALL, "Intel (Unknown)" },
430 { HDA_NVIDIA_ALL, "NVidia (Unknown)" },
431 { HDA_ATI_ALL, "ATI (Unknown)" },
432 { HDA_VIA_ALL, "VIA (Unknown)" },
433 { HDA_SIS_ALL, "SiS (Unknown)" },
434};
435#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0]))
436
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437static const struct {
438 uint16_t vendor;
439 uint8_t reg;
440 uint8_t mask;
441 uint8_t enable;
442} hdac_pcie_snoop[] = {
443 { INTEL_VENDORID, 0x00, 0x00, 0x00 },
444 { ATI_VENDORID, 0x42, 0xf8, 0x02 },
445 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f },
446};
447#define HDAC_PCIESNOOP_LEN \
448 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0]))
449
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450static const struct {
451 uint32_t rate;
452 int valid;
453 uint16_t base;
454 uint16_t mul;
455 uint16_t div;
456} hda_rate_tab[] = {
457 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */
458 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */
459 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */
460 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */
461 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */
462 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */
463 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */
464 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */
465 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */
466 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */
467 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */
468 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */
469 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */
470 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */
471 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */
472 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */
473 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */
474 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */
475 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */
476 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */
477 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */
478 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */
479 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */
480 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */
481 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */
482 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */
483 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */
484 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */
485 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */
486 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */
487 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */
488 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */
489 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */
490 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */
491 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */
492};
493#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0]))
494
495/* All codecs you can eat... */
496#define HDA_CODEC_CONSTRUCT(vendor, id) \
497 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff))
498
499/* Realtek */
500#define REALTEK_VENDORID 0x10ec
501#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260)
4886ec58 502#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262)
6ef811ff 503#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268)
4886ec58 504#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660)
558a398b 505#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861)
4886ec58 506#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862)
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507#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880)
508#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882)
509#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883)
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510#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885)
511#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888)
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512#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff)
513
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514/* Analog Devices */
515#define ANALOGDEVICES_VENDORID 0x11d4
516#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981)
517#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983)
518#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986)
519#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988)
520#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b)
521#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff)
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522
523/* CMedia */
524#define CMEDIA_VENDORID 0x434d
525#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980)
526#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff)
527
528/* Sigmatel */
529#define SIGMATEL_VENDORID 0x8384
530#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680)
531#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683)
532#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690)
533#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681)
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534#define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618)
535#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627)
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536#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff)
537
538/*
539 * Conexant
540 *
541 * Ok, the truth is, I don't have any idea at all whether
542 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only
543 * place that tell me it is "Venice" is from its Windows driver INF.
544 *
545 * Venice - CX?????
546 * Waikiki - CX20551-22
547 */
548#define CONEXANT_VENDORID 0x14f1
549#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045)
550#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047)
551#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff)
552
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553/* VIA */
554#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708)
555#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709)
556#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a)
557#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b)
558#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710)
559#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711)
560#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712)
561#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713)
562#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714)
563#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715)
564#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716)
565#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717)
566#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff)
567
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568
569/* Codecs */
570static const struct {
571 uint32_t id;
572 char *name;
573} hdac_codecs[] = {
574 { HDA_CODEC_ALC260, "Realtek ALC260" },
4886ec58 575 { HDA_CODEC_ALC262, "Realtek ALC262" },
6ef811ff 576 { HDA_CODEC_ALC268, "Realtek ALC268" },
4886ec58 577 { HDA_CODEC_ALC660, "Realtek ALC660" },
558a398b 578 { HDA_CODEC_ALC861, "Realtek ALC861" },
4886ec58 579 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" },
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580 { HDA_CODEC_ALC880, "Realtek ALC880" },
581 { HDA_CODEC_ALC882, "Realtek ALC882" },
582 { HDA_CODEC_ALC883, "Realtek ALC883" },
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583 { HDA_CODEC_ALC885, "Realtek ALC885" },
584 { HDA_CODEC_ALC888, "Realtek ALC888" },
585 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" },
586 { HDA_CODEC_AD1983, "Analog Devices AD1983" },
587 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" },
588 { HDA_CODEC_AD1988, "Analog Devices AD1988" },
589 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" },
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590 { HDA_CODEC_CMI9880, "CMedia CMI9880" },
591 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" },
592 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" },
593 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" },
594 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" },
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595 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" },
596 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" },
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597 { HDA_CODEC_CXVENICE, "Conexant Venice" },
598 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" },
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599 { HDA_CODEC_VT1708_8, "VIA VT1708_8" },
600 { HDA_CODEC_VT1708_9, "VIA VT1708_9" },
601 { HDA_CODEC_VT1708_A, "VIA VT1708_A" },
602 { HDA_CODEC_VT1708_B, "VIA VT1708_B" },
603 { HDA_CODEC_VT1709_0, "VIA VT1709_0" },
604 { HDA_CODEC_VT1709_1, "VIA VT1709_1" },
605 { HDA_CODEC_VT1709_2, "VIA VT1709_2" },
606 { HDA_CODEC_VT1709_3, "VIA VT1709_3" },
607 { HDA_CODEC_VT1709_4, "VIA VT1709_4" },
608 { HDA_CODEC_VT1709_5, "VIA VT1709_5" },
609 { HDA_CODEC_VT1709_6, "VIA VT1709_6" },
610 { HDA_CODEC_VT1709_7, "VIA VT1709_7" },
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611 /* Unknown codec */
612 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" },
4886ec58 613 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" },
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614 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" },
615 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" },
616 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" },
4886ec58 617 { HDA_CODEC_VTXXXX, "VIA (Unknown)" },
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618};
619#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0]))
620
621enum {
622 HDAC_HP_SWITCH_CTL,
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623 HDAC_HP_SWITCH_CTRL,
624 HDAC_HP_SWITCH_DEBUG
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625};
626
627static const struct {
628 uint32_t model;
629 uint32_t id;
630 int type;
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631 int inverted;
632 int polling;
633 int execsense;
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634 nid_t hpnid;
635 nid_t spkrnid[8];
636 nid_t eapdnid;
637} hdac_hp_switch[] = {
638 /* Specific OEM models */
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639 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL,
640 0, 0, -1, 17, { 16, -1 }, 16 },
641 /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL,
642 0, 0, -1, 21, { 16, 17, -1 }, -1 } */
643 /*{ HP_3010_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG,
644 0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 },*/
558a398b 645 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
4886ec58 646 0, 0, -1, 6, { 5, -1 }, 5 },
558a398b 647 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
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648 0, 0, -1, 6, { 5, -1 }, 5 },
649 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
650 0, 0, -1, 6, { 5, -1 }, 5 },
651 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
652 0, 0, -1, 6, { 5, -1 }, -1 },
558a398b 653 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
4886ec58 654 0, 0, -1, 13, { 14, -1 }, -1 },
558a398b 655 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
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656 0, 0, -1, 13, { 14, -1 }, -1 },
657 { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL,
658 0, 0, -1, 6, { 5, 7, -1 }, -1 },
659 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL,
660 0, 0, -1, 10, { 13, -1 }, -1 },
661 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL,
662 1, 0, -1, 26, { 27, -1 }, -1 },
663 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL,
664 0, 0, -1, 27, { 20, -1 }, -1 },
665 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
666 0, 0, -1, 20, { 21, -1 }, -1 },
667 { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
668 0, 0, -1, 20, { 21, -1 }, -1 },
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669 { UNIWILL_9080_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
670 0, 0, -1, 20, { 21, -1 }, -1 },
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671 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
672 0, 0, -1, 20, { 27, -1 }, -1 },
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673 /*
674 * All models that at least come from the same vendor with
675 * simmilar codec.
676 */
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677 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL,
678 0, 0, -1, 17, { 16, -1 }, 16 },
558a398b 679 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
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680 0, 0, -1, 6, { 5, -1 }, 5 },
681 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
682 0, 0, -1, 6, { 5, -1 }, -1 },
558a398b 683 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
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684 0, 0, -1, 13, { 14, -1 }, -1 },
685 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL,
686 1, 0, -1, 26, { 27, -1 }, -1 },
687#if 0
688 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
689 0, 0, -1, 20, { 21, -1 }, -1 },
690#endif
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691};
692#define HDAC_HP_SWITCH_LEN \
693 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0]))
694
695static const struct {
696 uint32_t model;
697 uint32_t id;
698 nid_t eapdnid;
699 int hp_switch;
700} hdac_eapd_switch[] = {
701 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 },
702 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 },
703 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 },
704};
705#define HDAC_EAPD_SWITCH_LEN \
706 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0]))
707
708/****************************************************************************
709 * Function prototypes
710 ****************************************************************************/
711static void hdac_intr_handler(void *);
712static int hdac_reset(struct hdac_softc *);
713static int hdac_get_capabilities(struct hdac_softc *);
714static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int);
715static int hdac_dma_alloc(struct hdac_softc *,
716 struct hdac_dma *, bus_size_t);
4886ec58 717static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *);
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718static int hdac_mem_alloc(struct hdac_softc *);
719static void hdac_mem_free(struct hdac_softc *);
720static int hdac_irq_alloc(struct hdac_softc *);
721static void hdac_irq_free(struct hdac_softc *);
722static void hdac_corb_init(struct hdac_softc *);
723static void hdac_rirb_init(struct hdac_softc *);
724static void hdac_corb_start(struct hdac_softc *);
725static void hdac_rirb_start(struct hdac_softc *);
726static void hdac_scan_codecs(struct hdac_softc *);
727static int hdac_probe_codec(struct hdac_codec *);
728static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t);
729static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *);
730
731static void hdac_attach2(void *);
732
733static uint32_t hdac_command_sendone_internal(struct hdac_softc *,
734 uint32_t, int);
735static void hdac_command_send_internal(struct hdac_softc *,
736 struct hdac_command_list *, int);
737
738static int hdac_probe(device_t);
739static int hdac_attach(device_t);
740static int hdac_detach(device_t);
741static void hdac_widget_connection_select(struct hdac_widget *, uint8_t);
742static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *,
743 uint32_t, int, int);
744static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *,
745 nid_t, int, int);
746static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *,
747 nid_t, nid_t, int, int, int, int, int, int);
748static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *);
749static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t);
750
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751static int hdac_rirb_flush(struct hdac_softc *sc);
752static int hdac_unsolq_flush(struct hdac_softc *sc);
753
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754#define hdac_command(a1, a2, a3) \
755 hdac_command_sendone_internal(a1, a2, a3)
756
757#define hdac_codec_id(d) \
758 ((uint32_t)((d == NULL) ? 0x00000000 : \
759 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \
760 ((uint32_t)(d)->device_id & 0x0000ffff))))
761
762static char *
763hdac_codec_name(struct hdac_devinfo *devinfo)
764{
765 uint32_t id;
766 int i;
767
768 id = hdac_codec_id(devinfo);
769
770 for (i = 0; i < HDAC_CODECS_LEN; i++) {
771 if (HDA_DEV_MATCH(hdac_codecs[i].id, id))
772 return (hdac_codecs[i].name);
773 }
774
775 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec");
776}
777
778static char *
779hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask)
780{
781 static char *ossname[] = SOUND_DEVICE_NAMES;
782 static char *unknown = "???";
783 int i;
784
785 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) {
786 if (devmask & (1 << i))
787 return (ossname[i]);
788 }
789 return (unknown);
790}
791
792static void
793hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len)
794{
795 static char *ossname[] = SOUND_DEVICE_NAMES;
796 int i, first = 1;
797
798 bzero(buf, len);
799 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
800 if (mask & (1 << i)) {
801 if (first == 0)
802 strlcat(buf, ", ", len);
803 strlcat(buf, ossname[i], len);
804 first = 0;
805 }
806 }
807}
808
809static struct hdac_audio_ctl *
810hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index)
811{
812 if (devinfo == NULL ||
813 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO ||
814 index == NULL || devinfo->function.audio.ctl == NULL ||
815 devinfo->function.audio.ctlcnt < 1 ||
816 *index < 0 || *index >= devinfo->function.audio.ctlcnt)
817 return (NULL);
818 return (&devinfo->function.audio.ctl[(*index)++]);
819}
820
821static struct hdac_audio_ctl *
822hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid,
823 int index, int cnt)
824{
825 struct hdac_audio_ctl *ctl, *retctl = NULL;
826 int i, at, atindex, found = 0;
827
828 if (devinfo == NULL || devinfo->function.audio.ctl == NULL)
829 return (NULL);
830
831 at = cnt;
832 if (at == 0)
833 at = 1;
834 else if (at < 0)
835 at = -1;
836 atindex = index;
837 if (atindex < 0)
838 atindex = -1;
839
840 i = 0;
841 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
842 if (ctl->enable == 0 || ctl->widget == NULL)
843 continue;
844 if (!(ctl->widget->nid == nid && (atindex == -1 ||
845 ctl->index == atindex)))
846 continue;
847 found++;
848 if (found == cnt)
849 return (ctl);
850 retctl = ctl;
851 }
852
853 return ((at == -1) ? retctl : NULL);
854}
855
856static void
857hdac_hp_switch_handler(struct hdac_devinfo *devinfo)
858{
859 struct hdac_softc *sc;
860 struct hdac_widget *w;
861 struct hdac_audio_ctl *ctl;
4886ec58 862 uint32_t val, id, res;
19c72e40 863 int i = 0, j, timeout, forcemute;
558a398b
SS
864 nid_t cad;
865
866 if (devinfo == NULL || devinfo->codec == NULL ||
867 devinfo->codec->sc == NULL)
868 return;
869
870 sc = devinfo->codec->sc;
871 cad = devinfo->codec->cad;
872 id = hdac_codec_id(devinfo);
873 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) {
874 if (HDA_DEV_MATCH(hdac_hp_switch[i].model,
875 sc->pci_subvendor) &&
876 hdac_hp_switch[i].id == id)
877 break;
878 }
879
880 if (i >= HDAC_HP_SWITCH_LEN)
881 return;
882
883 forcemute = 0;
884 if (hdac_hp_switch[i].eapdnid != -1) {
885 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid);
886 if (w != NULL && w->param.eapdbtl != HDAC_INVALID)
887 forcemute = (w->param.eapdbtl &
888 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1;
889 }
890
4886ec58
HT
891 if (hdac_hp_switch[i].execsense != -1)
892 hdac_command(sc,
893 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid,
894 hdac_hp_switch[i].execsense), cad);
19c72e40
HT
895
896 timeout = 10000;
897 do {
898 res = hdac_command(sc,
899 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid),
900 cad);
901 if (hdac_hp_switch[i].execsense == -1 || res != 0x7fffffff)
902 break;
903 DELAY(10);
904 } while (--timeout != 0);
905
558a398b
SS
906 HDA_BOOTVERBOSE(
907 device_printf(sc->dev,
19c72e40
HT
908 "HDA_DEBUG: Pin sense: nid=%d timeout=%d res=0x%08x\n",
909 hdac_hp_switch[i].hpnid, timeout, res);
558a398b 910 );
19c72e40 911
4886ec58
HT
912 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res);
913 res ^= hdac_hp_switch[i].inverted;
558a398b
SS
914
915 switch (hdac_hp_switch[i].type) {
916 case HDAC_HP_SWITCH_CTL:
917 ctl = hdac_audio_ctl_amp_get(devinfo,
918 hdac_hp_switch[i].hpnid, 0, 1);
919 if (ctl != NULL) {
4886ec58 920 val = (res != 0 && forcemute == 0) ?
558a398b 921 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL;
4886ec58
HT
922 if (val != ctl->muted) {
923 ctl->muted = val;
558a398b
SS
924 hdac_audio_ctl_amp_set(ctl,
925 HDA_AMP_MUTE_DEFAULT, ctl->left,
926 ctl->right);
927 }
928 }
4886ec58
HT
929 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
930 ctl = hdac_audio_ctl_amp_get(devinfo,
931 hdac_hp_switch[i].spkrnid[j], 0, 1);
932 if (ctl == NULL)
933 continue;
934 val = (res != 0 || forcemute == 1) ?
935 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE;
936 if (val == ctl->muted)
937 continue;
938 ctl->muted = val;
939 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT,
940 ctl->left, ctl->right);
941 }
558a398b
SS
942 break;
943 case HDAC_HP_SWITCH_CTRL:
944 if (res != 0) {
945 /* HP in */
946 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
947 if (w != NULL && w->type ==
948 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
949 if (forcemute == 0)
4886ec58 950 val = w->wclass.pin.ctrl |
558a398b
SS
951 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
952 else
4886ec58 953 val = w->wclass.pin.ctrl &
558a398b 954 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
4886ec58
HT
955 if (val != w->wclass.pin.ctrl) {
956 w->wclass.pin.ctrl = val;
957 hdac_command(sc,
958 HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
959 w->nid, w->wclass.pin.ctrl), cad);
960 }
558a398b
SS
961 }
962 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
963 w = hdac_widget_get(devinfo,
964 hdac_hp_switch[i].spkrnid[j]);
4886ec58
HT
965 if (w == NULL || w->type !=
966 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
967 continue;
968 val = w->wclass.pin.ctrl &
969 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
970 if (val == w->wclass.pin.ctrl)
971 continue;
972 w->wclass.pin.ctrl = val;
973 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL(
974 cad, w->nid, w->wclass.pin.ctrl), cad);
558a398b
SS
975 }
976 } else {
977 /* HP out */
978 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
979 if (w != NULL && w->type ==
980 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
4886ec58 981 val = w->wclass.pin.ctrl &
558a398b 982 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
4886ec58
HT
983 if (val != w->wclass.pin.ctrl) {
984 w->wclass.pin.ctrl = val;
985 hdac_command(sc,
986 HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
987 w->nid, w->wclass.pin.ctrl), cad);
988 }
558a398b
SS
989 }
990 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
991 w = hdac_widget_get(devinfo,
992 hdac_hp_switch[i].spkrnid[j]);
4886ec58
HT
993 if (w == NULL || w->type !=
994 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
995 continue;
996 if (forcemute == 0)
997 val = w->wclass.pin.ctrl |
998 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
999 else
1000 val = w->wclass.pin.ctrl &
1001 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1002 if (val == w->wclass.pin.ctrl)
1003 continue;
1004 w->wclass.pin.ctrl = val;
1005 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL(
1006 cad, w->nid, w->wclass.pin.ctrl), cad);
558a398b
SS
1007 }
1008 }
1009 break;
4886ec58
HT
1010 case HDAC_HP_SWITCH_DEBUG:
1011 if (hdac_hp_switch[i].execsense != -1)
1012 hdac_command(sc,
1013 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid,
1014 hdac_hp_switch[i].execsense), cad);
1015 res = hdac_command(sc,
1016 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad);
1017 device_printf(sc->dev,
1018 "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n",
1019 hdac_hp_switch[i].hpnid, res);
1020 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
1021 w = hdac_widget_get(devinfo,
1022 hdac_hp_switch[i].spkrnid[j]);
1023 if (w == NULL || w->type !=
1024 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
1025 continue;
1026 if (hdac_hp_switch[i].execsense != -1)
1027 hdac_command(sc,
1028 HDA_CMD_SET_PIN_SENSE(cad, w->nid,
1029 hdac_hp_switch[i].execsense), cad);
1030 res = hdac_command(sc,
1031 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad);
1032 device_printf(sc->dev,
1033 "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n",
1034 j + 1, w->nid, res);
1035 }
1036 break;
558a398b
SS
1037 default:
1038 break;
1039 }
1040}
1041
1042static void
1043hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag)
1044{
1045 struct hdac_softc *sc;
1046 struct hdac_devinfo *devinfo = NULL;
1047 device_t *devlist = NULL;
1048 int devcount, i;
1049
1050 if (codec == NULL || codec->sc == NULL)
1051 return;
1052
1053 sc = codec->sc;
1054
1055 HDA_BOOTVERBOSE(
1056 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag);
1057 );
1058
1059 device_get_children(sc->dev, &devlist, &devcount);
1060 for (i = 0; devlist != NULL && i < devcount; i++) {
1061 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
1062 if (devinfo != NULL && devinfo->node_type ==
1063 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO &&
1064 devinfo->codec != NULL &&
1065 devinfo->codec->cad == codec->cad) {
1066 break;
1067 } else
1068 devinfo = NULL;
1069 }
1070 if (devlist != NULL)
1071 kfree(devlist, M_TEMP);
1072
1073 if (devinfo == NULL)
1074 return;
1075
1076 switch (tag) {
1077 case HDAC_UNSOLTAG_EVENT_HP:
1078 hdac_hp_switch_handler(devinfo);
1079 break;
4886ec58
HT
1080 case HDAC_UNSOLTAG_EVENT_TEST:
1081 device_printf(sc->dev, "Unsol Test!\n");
1082 break;
558a398b
SS
1083 default:
1084 break;
1085 }
1086}
1087
4886ec58 1088static int
558a398b
SS
1089hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch)
1090{
1091 /* XXX to be removed */
1092#ifdef HDAC_INTR_EXTRA
1093 uint32_t res;
1094#endif
1095
6ef811ff 1096 if (!(ch->flags & HDAC_CHN_RUNNING))
4886ec58 1097 return (0);
558a398b
SS
1098
1099 /* XXX to be removed */
1100#ifdef HDAC_INTR_EXTRA
1101 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS);
1102#endif
1103
1104 /* XXX to be removed */
1105#ifdef HDAC_INTR_EXTRA
1106 HDA_BOOTVERBOSE(
1107 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE))
1108 device_printf(sc->dev,
1109 "PCMDIR_%s intr triggered beyond stream boundary:"
1110 "%08x\n",
1111 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res);
1112 );
1113#endif
1114
1115 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS,
1116 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
1117
1118 /* XXX to be removed */
1119#ifdef HDAC_INTR_EXTRA
1120 if (res & HDAC_SDSTS_BCIS) {
1121#endif
4886ec58 1122 return (1);
558a398b
SS
1123 /* XXX to be removed */
1124#ifdef HDAC_INTR_EXTRA
1125 }
1126#endif
4886ec58
HT
1127
1128 return (0);
558a398b
SS
1129}
1130
1131/****************************************************************************
1132 * void hdac_intr_handler(void *)
1133 *
1134 * Interrupt handler. Processes interrupts received from the hdac.
1135 ****************************************************************************/
1136static void
1137hdac_intr_handler(void *context)
1138{
1139 struct hdac_softc *sc;
1140 uint32_t intsts;
1141 uint8_t rirbsts;
4886ec58 1142 struct hdac_rirb *rirb_base;
19c72e40 1143 uint32_t trigger;
558a398b
SS
1144
1145 sc = (struct hdac_softc *)context;
1146
1147 hdac_lock(sc);
4886ec58
HT
1148 if (sc->polling != 0) {
1149 hdac_unlock(sc);
1150 return;
1151 }
19c72e40 1152
558a398b
SS
1153 /* Do we have anything to do? */
1154 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
1155 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) {
1156 hdac_unlock(sc);
1157 return;
1158 }
1159
19c72e40
HT
1160 trigger = 0;
1161
558a398b
SS
1162 /* Was this a controller interrupt? */
1163 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) {
1164 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
1165 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1166 /* Get as many responses that we can */
1167 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) {
4886ec58
HT
1168 HDAC_WRITE_1(&sc->mem,
1169 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL);
19c72e40
HT
1170 if (hdac_rirb_flush(sc) != 0)
1171 trigger |= HDAC_TRIGGER_UNSOL;
558a398b
SS
1172 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1173 }
1174 /* XXX to be removed */
1175 /* Clear interrupt and exit */
1176#ifdef HDAC_INTR_EXTRA
1177 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS);
1178#endif
1179 }
4886ec58 1180
558a398b 1181 if (intsts & HDAC_INTSTS_SIS_MASK) {
4886ec58
HT
1182 if ((intsts & (1 << sc->num_iss)) &&
1183 hdac_stream_intr(sc, &sc->play) != 0)
19c72e40 1184 trigger |= HDAC_TRIGGER_PLAY;
4886ec58
HT
1185 if ((intsts & (1 << 0)) &&
1186 hdac_stream_intr(sc, &sc->rec) != 0)
19c72e40 1187 trigger |= HDAC_TRIGGER_REC;
558a398b
SS
1188 /* XXX to be removed */
1189#ifdef HDAC_INTR_EXTRA
4886ec58
HT
1190 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts &
1191 HDAC_INTSTS_SIS_MASK);
558a398b
SS
1192#endif
1193 }
1194
558a398b 1195 hdac_unlock(sc);
4886ec58 1196
19c72e40 1197 if (trigger & HDAC_TRIGGER_PLAY)
4886ec58 1198 chn_intr(sc->play.c);
19c72e40 1199 if (trigger & HDAC_TRIGGER_REC)
4886ec58 1200 chn_intr(sc->rec.c);
19c72e40
HT
1201 if (trigger & HDAC_TRIGGER_UNSOL)
1202 taskqueue_enqueue(taskqueue_swi, &sc->unsolq_task);
558a398b
SS
1203}
1204
1205/****************************************************************************
1206 * int hdac_reset(hdac_softc *)
1207 *
1208 * Reset the hdac to a quiescent and known state.
1209 ****************************************************************************/
1210static int
1211hdac_reset(struct hdac_softc *sc)
1212{
1213 uint32_t gctl;
1214 int count, i;
1215
1216 /*
1217 * Stop all Streams DMA engine
1218 */
1219 for (i = 0; i < sc->num_iss; i++)
1220 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
1221 for (i = 0; i < sc->num_oss; i++)
1222 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
1223 for (i = 0; i < sc->num_bss; i++)
1224 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
1225
1226 /*
4886ec58 1227 * Stop Control DMA engines.
558a398b
SS
1228 */
1229 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
1230 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
1231
4886ec58
HT
1232 /*
1233 * Reset DMA position buffer.
1234 */
1235 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0);
1236 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0);
1237
558a398b
SS
1238 /*
1239 * Reset the controller. The reset must remain asserted for
1240 * a minimum of 100us.
1241 */
1242 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1243 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
1244 count = 10000;
1245 do {
1246 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1247 if (!(gctl & HDAC_GCTL_CRST))
1248 break;
1249 DELAY(10);
1250 } while (--count);
1251 if (gctl & HDAC_GCTL_CRST) {
1252 device_printf(sc->dev, "Unable to put hdac in reset\n");
1253 return (ENXIO);
1254 }
1255 DELAY(100);
1256 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1257 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
1258 count = 10000;
1259 do {
1260 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1261 if (gctl & HDAC_GCTL_CRST)
1262 break;
1263 DELAY(10);
1264 } while (--count);
1265 if (!(gctl & HDAC_GCTL_CRST)) {
1266 device_printf(sc->dev, "Device stuck in reset\n");
1267 return (ENXIO);
1268 }
1269
1270 /*
1271 * Wait for codecs to finish their own reset sequence. The delay here
1272 * should be of 250us but for some reasons, on it's not enough on my
1273 * computer. Let's use twice as much as necessary to make sure that
1274 * it's reset properly.
1275 */
1276 DELAY(1000);
1277
1278 return (0);
1279}
1280
1281
1282/****************************************************************************
1283 * int hdac_get_capabilities(struct hdac_softc *);
1284 *
1285 * Retreive the general capabilities of the hdac;
1286 * Number of Input Streams
1287 * Number of Output Streams
1288 * Number of bidirectional Streams
1289 * 64bit ready
1290 * CORB and RIRB sizes
1291 ****************************************************************************/
1292static int
1293hdac_get_capabilities(struct hdac_softc *sc)
1294{
1295 uint16_t gcap;
1296 uint8_t corbsize, rirbsize;
1297
1298 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
1299 sc->num_iss = HDAC_GCAP_ISS(gcap);
1300 sc->num_oss = HDAC_GCAP_OSS(gcap);
1301 sc->num_bss = HDAC_GCAP_BSS(gcap);
1302
1303 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK);
1304
1305 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
1306 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) ==
1307 HDAC_CORBSIZE_CORBSZCAP_256)
1308 sc->corb_size = 256;
1309 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) ==
1310 HDAC_CORBSIZE_CORBSZCAP_16)
1311 sc->corb_size = 16;
1312 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) ==
1313 HDAC_CORBSIZE_CORBSZCAP_2)
1314 sc->corb_size = 2;
1315 else {
1316 device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
1317 __func__, corbsize);
1318 return (ENXIO);
1319 }
1320
1321 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
1322 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) ==
1323 HDAC_RIRBSIZE_RIRBSZCAP_256)
1324 sc->rirb_size = 256;
1325 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) ==
1326 HDAC_RIRBSIZE_RIRBSZCAP_16)
1327 sc->rirb_size = 16;
1328 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) ==
1329 HDAC_RIRBSIZE_RIRBSZCAP_2)
1330 sc->rirb_size = 2;
1331 else {
1332 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
1333 __func__, rirbsize);
1334 return (ENXIO);
1335 }
1336
1337 return (0);
1338}
1339
1340
1341/****************************************************************************
1342 * void hdac_dma_cb
1343 *
1344 * This function is called by bus_dmamap_load when the mapping has been
1345 * established. We just record the physical address of the mapping into
1346 * the struct hdac_dma passed in.
1347 ****************************************************************************/
1348static void
1349hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error)
1350{
1351 struct hdac_dma *dma;
1352
1353 if (error == 0) {
1354 dma = (struct hdac_dma *)callback_arg;
1355 dma->dma_paddr = segs[0].ds_addr;
1356 }
1357}
1358
558a398b
SS
1359
1360/****************************************************************************
1361 * int hdac_dma_alloc
1362 *
1363 * This function allocate and setup a dma region (struct hdac_dma).
1364 * It must be freed by a corresponding hdac_dma_free.
1365 ****************************************************************************/
1366static int
1367hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size)
1368{
4886ec58 1369 bus_size_t roundsz;
558a398b
SS
1370 int result;
1371 int lowaddr;
1372
4886ec58 1373 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT);
558a398b
SS
1374 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1375 BUS_SPACE_MAXADDR_32BIT;
1376 bzero(dma, sizeof(*dma));
1377
1378 /*
1379 * Create a DMA tag
1380 */
1381 result = bus_dma_tag_create(NULL, /* parent */
1382 HDAC_DMA_ALIGNMENT, /* alignment */
1383 0, /* boundary */
1384 lowaddr, /* lowaddr */
1385 BUS_SPACE_MAXADDR, /* highaddr */
1386 NULL, /* filtfunc */
1387 NULL, /* fistfuncarg */
4886ec58 1388 roundsz, /* maxsize */
558a398b 1389 1, /* nsegments */
4886ec58 1390 roundsz, /* maxsegsz */
558a398b
SS
1391 0, /* flags */
1392 &dma->dma_tag); /* dmat */
1393 if (result != 0) {
1394 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n",
1395 __func__, result);
4886ec58 1396 goto hdac_dma_alloc_fail;
558a398b
SS
1397 }
1398
1399 /*
1400 * Allocate DMA memory
1401 */
4886ec58
HT
1402#if 0 /* TODO: No uncacheable DMA support in DragonFly. */
1403 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
1404 BUS_DMA_NOWAIT | BUS_DMA_ZERO |
6ef811ff
HT
1405 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0),
1406 &dma->dma_map);
4886ec58 1407#else
558a398b 1408 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
4886ec58
HT
1409 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &dma->dma_map);
1410#endif
558a398b
SS
1411 if (result != 0) {
1412 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n",
1413 __func__, result);
4886ec58 1414 goto hdac_dma_alloc_fail;
558a398b
SS
1415 }
1416
4886ec58
HT
1417 dma->dma_size = roundsz;
1418
558a398b
SS
1419 /*
1420 * Map the memory
1421 */
1422 result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
4886ec58 1423 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0);
558a398b 1424 if (result != 0 || dma->dma_paddr == 0) {
4886ec58
HT
1425 if (result == 0)
1426 result = ENOMEM;
558a398b
SS
1427 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n",
1428 __func__, result);
4886ec58 1429 goto hdac_dma_alloc_fail;
558a398b 1430 }
4886ec58
HT
1431
1432 HDA_BOOTVERBOSE(
1433 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n",
1434 __func__, (uintmax_t)size, (uintmax_t)roundsz);
1435 );
558a398b
SS
1436
1437 return (0);
4886ec58
HT
1438
1439hdac_dma_alloc_fail:
1440 hdac_dma_free(sc, dma);
1441
558a398b
SS
1442 return (result);
1443}
1444
1445
1446/****************************************************************************
4886ec58 1447 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *)
558a398b
SS
1448 *
1449 * Free a struct dhac_dma that has been previously allocated via the
1450 * hdac_dma_alloc function.
1451 ****************************************************************************/
1452static void
4886ec58 1453hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma)
558a398b 1454{
4886ec58
HT
1455 if (dma->dma_map != NULL) {
1456#if 0
558a398b
SS
1457 /* Flush caches */
1458 bus_dmamap_sync(dma->dma_tag, dma->dma_map,
1459 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4886ec58 1460#endif
558a398b 1461 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
4886ec58
HT
1462 }
1463 if (dma->dma_vaddr != NULL) {
558a398b 1464 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
4886ec58
HT
1465 dma->dma_vaddr = NULL;
1466 }
1467 dma->dma_map = NULL;
1468 if (dma->dma_tag != NULL) {
558a398b 1469 bus_dma_tag_destroy(dma->dma_tag);
4886ec58 1470 dma->dma_tag = NULL;
558a398b 1471 }
4886ec58 1472 dma->dma_size = 0;
558a398b
SS
1473}
1474
1475/****************************************************************************
1476 * int hdac_mem_alloc(struct hdac_softc *)
1477 *
1478 * Allocate all the bus resources necessary to speak with the physical
1479 * controller.
1480 ****************************************************************************/
1481static int
1482hdac_mem_alloc(struct hdac_softc *sc)
1483{
1484 struct hdac_mem *mem;
1485
1486 mem = &sc->mem;
1487 mem->mem_rid = PCIR_BAR(0);
1488 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1489 &mem->mem_rid, RF_ACTIVE);
1490 if (mem->mem_res == NULL) {
1491 device_printf(sc->dev,
1492 "%s: Unable to allocate memory resource\n", __func__);
1493 return (ENOMEM);
1494 }
1495 mem->mem_tag = rman_get_bustag(mem->mem_res);
1496 mem->mem_handle = rman_get_bushandle(mem->mem_res);
1497
1498 return (0);
1499}
1500
1501/****************************************************************************
1502 * void hdac_mem_free(struct hdac_softc *)
1503 *
1504 * Free up resources previously allocated by hdac_mem_alloc.
1505 ****************************************************************************/
1506static void
1507hdac_mem_free(struct hdac_softc *sc)
1508{
1509 struct hdac_mem *mem;
1510
1511 mem = &sc->mem;
1512 if (mem->mem_res != NULL)
1513 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
1514 mem->mem_res);
4886ec58 1515 mem->mem_res = NULL;
558a398b
SS
1516}
1517
1518/****************************************************************************
1519 * int hdac_irq_alloc(struct hdac_softc *)
1520 *
1521 * Allocate and setup the resources necessary for interrupt handling.
1522 ****************************************************************************/
1523static int
1524hdac_irq_alloc(struct hdac_softc *sc)
1525{
1526 struct hdac_irq *irq;
1527 int result;
1528
1529 irq = &sc->irq;
1530 irq->irq_rid = 0x0;
6ef811ff
HT
1531
1532#if 0 /* TODO: No MSI support in DragonFly yet. */
1533 if ((sc->flags & HDAC_F_MSI) &&
1534 (result = pci_msi_count(sc->dev)) == 1 &&
1535 pci_alloc_msi(sc->dev, &result) == 0)
1536 irq->irq_rid = 0x1;
1537 else
1538#endif
1539 sc->flags &= ~HDAC_F_MSI;
1540
558a398b
SS
1541 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
1542 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE);
1543 if (irq->irq_res == NULL) {
1544 device_printf(sc->dev, "%s: Unable to allocate irq\n",
1545 __func__);
4886ec58 1546 goto hdac_irq_alloc_fail;
558a398b
SS
1547 }
1548 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE,
4886ec58 1549 hdac_intr_handler, sc, &irq->irq_handle);
558a398b
SS
1550 if (result != 0) {
1551 device_printf(sc->dev,
1552 "%s: Unable to setup interrupt handler (%x)\n",
1553 __func__, result);
4886ec58 1554 goto hdac_irq_alloc_fail;
558a398b
SS
1555 }
1556
1557 return (0);
1558
4886ec58
HT
1559hdac_irq_alloc_fail:
1560 hdac_irq_free(sc);
1561
558a398b
SS
1562 return (ENXIO);
1563}
1564
1565/****************************************************************************
1566 * void hdac_irq_free(struct hdac_softc *)
1567 *
1568 * Free up resources previously allocated by hdac_irq_alloc.
1569 ****************************************************************************/
1570static void
1571hdac_irq_free(struct hdac_softc *sc)
1572{
1573 struct hdac_irq *irq;
1574
1575 irq = &sc->irq;
4886ec58 1576 if (irq->irq_res != NULL && irq->irq_handle != NULL)
558a398b
SS
1577 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
1578 if (irq->irq_res != NULL)
1579 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
1580 irq->irq_res);
6ef811ff
HT
1581#if 0 /* TODO: No MSI support in DragonFly yet. */
1582 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1)
1583 pci_release_msi(sc->dev);
1584#endif
4886ec58
HT
1585 irq->irq_handle = NULL;
1586 irq->irq_res = NULL;
6ef811ff 1587 irq->irq_rid = 0x0;
558a398b
SS
1588}
1589
1590/****************************************************************************
1591 * void hdac_corb_init(struct hdac_softc *)
1592 *
1593 * Initialize the corb registers for operations but do not start it up yet.
1594 * The CORB engine must not be running when this function is called.
1595 ****************************************************************************/
1596static void
1597hdac_corb_init(struct hdac_softc *sc)
1598{
1599 uint8_t corbsize;
1600 uint64_t corbpaddr;
1601
1602 /* Setup the CORB size. */
1603 switch (sc->corb_size) {
1604 case 256:
1605 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
1606 break;
1607 case 16:
1608 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16);
1609 break;
1610 case 2:
1611 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2);
1612 break;
1613 default:
1614 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size);
1615 }
1616 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
1617
1618 /* Setup the CORB Address in the hdac */
1619 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
1620 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
1621 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
1622
1623 /* Set the WP and RP */
1624 sc->corb_wp = 0;
1625 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
1626 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
1627 /*
1628 * The HDA specification indicates that the CORBRPRST bit will always
1629 * read as zero. Unfortunately, it seems that at least the 82801G
1630 * doesn't reset the bit to zero, which stalls the corb engine.
1631 * manually reset the bit to zero before continuing.
1632 */
1633 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
1634
1635 /* Enable CORB error reporting */
1636#if 0
1637 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
1638#endif
1639}
1640
1641/****************************************************************************
1642 * void hdac_rirb_init(struct hdac_softc *)
1643 *
1644 * Initialize the rirb registers for operations but do not start it up yet.
1645 * The RIRB engine must not be running when this function is called.
1646 ****************************************************************************/
1647static void
1648hdac_rirb_init(struct hdac_softc *sc)
1649{
1650 uint8_t rirbsize;
1651 uint64_t rirbpaddr;
1652
1653 /* Setup the RIRB size. */
1654 switch (sc->rirb_size) {
1655 case 256:
1656 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
1657 break;
1658 case 16:
1659 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16);
1660 break;
1661 case 2:
1662 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2);
1663 break;
1664 default:
1665 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size);
1666 }
1667 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
1668
1669 /* Setup the RIRB Address in the hdac */
1670 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
1671 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
1672 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
1673
1674 /* Setup the WP and RP */
1675 sc->rirb_rp = 0;
1676 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
1677
4886ec58
HT
1678 if (sc->polling == 0) {
1679 /* Setup the interrupt threshold */
1680 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
558a398b 1681
4886ec58 1682 /* Enable Overrun and response received reporting */
558a398b 1683#if 0
4886ec58
HT
1684 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
1685 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL);
558a398b 1686#else
4886ec58 1687 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
558a398b 1688#endif
4886ec58 1689 }
558a398b 1690
4886ec58 1691#if 0
558a398b
SS
1692 /*
1693 * Make sure that the Host CPU cache doesn't contain any dirty
1694 * cache lines that falls in the rirb. If I understood correctly, it
1695 * should be sufficient to do this only once as the rirb is purely
1696 * read-only from now on.
1697 */
1698 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
1699 BUS_DMASYNC_PREREAD);
4886ec58 1700#endif
558a398b
SS
1701}
1702
1703/****************************************************************************
1704 * void hdac_corb_start(hdac_softc *)
1705 *
1706 * Startup the corb DMA engine
1707 ****************************************************************************/
1708static void
1709hdac_corb_start(struct hdac_softc *sc)
1710{
1711 uint32_t corbctl;
1712
1713 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
1714 corbctl |= HDAC_CORBCTL_CORBRUN;
1715 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
1716}
1717
1718/****************************************************************************
1719 * void hdac_rirb_start(hdac_softc *)
1720 *
1721 * Startup the rirb DMA engine
1722 ****************************************************************************/
1723static void
1724hdac_rirb_start(struct hdac_softc *sc)
1725{
1726 uint32_t rirbctl;
1727
1728 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
1729 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN;
1730 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
1731}
1732
1733
1734/****************************************************************************
1735 * void hdac_scan_codecs(struct hdac_softc *)
1736 *
1737 * Scan the bus for available codecs.
1738 ****************************************************************************/
1739static void
1740hdac_scan_codecs(struct hdac_softc *sc)
1741{
1742 struct hdac_codec *codec;
1743 int i;
1744 uint16_t statests;
1745
1746 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
1747 for (i = 0; i < HDAC_CODEC_MAX; i++) {
1748 if (HDAC_STATESTS_SDIWAKE(statests, i)) {
1749 /* We have found a codec. */
558a398b
SS
1750 codec = (struct hdac_codec *)kmalloc(sizeof(*codec),
1751 M_HDAC, M_ZERO | M_NOWAIT);
558a398b
SS
1752 if (codec == NULL) {
1753 device_printf(sc->dev,
1754 "Unable to allocate memory for codec\n");
1755 continue;
1756 }
4886ec58
HT
1757 codec->commands = NULL;
1758 codec->responses_received = 0;
558a398b
SS
1759 codec->verbs_sent = 0;
1760 codec->sc = sc;
1761 codec->cad = i;
1762 sc->codecs[i] = codec;
1763 if (hdac_probe_codec(codec) != 0)
1764 break;
1765 }
1766 }
1767 /* All codecs have been probed, now try to attach drivers to them */
1768 /* bus_generic_attach(sc->dev); */
1769}
1770
1771/****************************************************************************
1772 * void hdac_probe_codec(struct hdac_softc *, int)
1773 *
1774 * Probe a the given codec_id for available function groups.
1775 ****************************************************************************/
1776static int
1777hdac_probe_codec(struct hdac_codec *codec)
1778{
1779 struct hdac_softc *sc = codec->sc;
1780 struct hdac_devinfo *devinfo;
1781 uint32_t vendorid, revisionid, subnode;
1782 int startnode;
1783 int endnode;
1784 int i;
1785 nid_t cad = codec->cad;
1786
1787 HDA_BOOTVERBOSE(
1788 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad);
1789 );
1790 vendorid = hdac_command(sc,
1791 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID),
1792 cad);
1793 revisionid = hdac_command(sc,
1794 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID),
1795 cad);
1796 subnode = hdac_command(sc,
1797 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT),
1798 cad);
1799 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode);
1800 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode);
1801
558a398b
SS
1802 HDA_BOOTVERBOSE(
1803 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n",
1804 startnode, endnode);
1805 );
1806 for (i = startnode; i < endnode; i++) {
1807 devinfo = hdac_probe_function(codec, i);
1808 if (devinfo != NULL) {
1809 /* XXX Ignore other FG. */
1810 devinfo->vendor_id =
1811 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid);
1812 devinfo->device_id =
1813 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid);
1814 devinfo->revision_id =
1815 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid);
1816 devinfo->stepping_id =
1817 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid);
1818 HDA_BOOTVERBOSE(
1819 device_printf(sc->dev,
1820 "HDA_DEBUG: \tFound AFG nid=%d "
1821 "[startnode=%d endnode=%d]\n",
1822 devinfo->nid, startnode, endnode);
1823 );
1824 return (1);
1825 }
1826 }
1827
1828 HDA_BOOTVERBOSE(
1829 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n");
1830 );
1831 return (0);
1832}
1833
1834static struct hdac_devinfo *
1835hdac_probe_function(struct hdac_codec *codec, nid_t nid)
1836{
1837 struct hdac_softc *sc = codec->sc;
1838 struct hdac_devinfo *devinfo;
1839 uint32_t fctgrptype;
1840 nid_t cad = codec->cad;
1841
1842 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc,
1843 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad));
1844
1845 /* XXX For now, ignore other FG. */
1846 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO)
1847 return (NULL);
1848
558a398b
SS
1849 devinfo = (struct hdac_devinfo *)kmalloc(sizeof(*devinfo), M_HDAC,
1850 M_NOWAIT | M_ZERO);
558a398b
SS
1851 if (devinfo == NULL) {
1852 device_printf(sc->dev, "%s: Unable to allocate ivar\n",
1853 __func__);
1854 return (NULL);
1855 }
1856
1857 devinfo->nid = nid;
1858 devinfo->node_type = fctgrptype;
1859 devinfo->codec = codec;
1860
1861 hdac_add_child(sc, devinfo);
1862
1863 return (devinfo);
1864}
1865
1866static void
1867hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo)
1868{
1869 devinfo->dev = device_add_child(sc->dev, NULL, -1);
1870 device_set_ivars(devinfo->dev, (void *)devinfo);
1871 /* XXX - Print more information when booting verbose??? */
1872}
1873
1874static void
1875hdac_widget_connection_parse(struct hdac_widget *w)
1876{
1877 struct hdac_softc *sc = w->devinfo->codec->sc;
1878 uint32_t res;
4886ec58 1879 int i, j, max, ents, entnum;
558a398b
SS
1880 nid_t cad = w->devinfo->codec->cad;
1881 nid_t nid = w->nid;
4886ec58
HT
1882 nid_t cnid, addcnid, prevcnid;
1883
1884 w->nconns = 0;
558a398b
SS
1885
1886 res = hdac_command(sc,
1887 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad);
1888
4886ec58 1889 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res);
558a398b 1890
4886ec58 1891 if (ents < 1)
558a398b
SS
1892 return;
1893
1894 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4;
558a398b 1895 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1;
4886ec58
HT
1896 prevcnid = 0;
1897
1898#define CONN_RMASK(e) (1 << ((32 / (e)) - 1))
1899#define CONN_NMASK(e) (CONN_RMASK(e) - 1)
1900#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n)))
1901#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e))
1902#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e))
558a398b 1903
4886ec58 1904 for (i = 0; i < ents; i += entnum) {
558a398b
SS
1905 res = hdac_command(sc,
1906 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad);
1907 for (j = 0; j < entnum; j++) {
4886ec58
HT
1908 cnid = CONN_CNID(res, entnum, j);
1909 if (cnid == 0) {
1910 if (w->nconns < ents)
1911 device_printf(sc->dev,
1912 "%s: nid=%d WARNING: zero cnid "
1913 "entnum=%d j=%d index=%d "
1914 "entries=%d found=%d res=0x%08x\n",
1915 __func__, nid, entnum, j, i,
1916 ents, w->nconns, res);
1917 else
1918 goto getconns_out;
1919 }
1920 if (cnid < w->devinfo->startnode ||
1921 cnid >= w->devinfo->endnode) {
1922 HDA_BOOTVERBOSE(
1923 device_printf(sc->dev,
1924 "%s: GHOST: nid=%d j=%d "
1925 "entnum=%d index=%d res=0x%08x\n",
1926 __func__, nid, j, entnum, i, res);
1927 );
1928 }
1929 if (CONN_RANGE(res, entnum, j) == 0)
1930 addcnid = cnid;
1931 else if (prevcnid == 0 || prevcnid >= cnid) {
558a398b 1932 device_printf(sc->dev,
4886ec58
HT
1933 "%s: WARNING: Invalid child range "
1934 "nid=%d index=%d j=%d entnum=%d "
1935 "prevcnid=%d cnid=%d res=0x%08x\n",
1936 __func__, nid, i, j, entnum, prevcnid,
1937 cnid, res);
1938 addcnid = cnid;
1939 } else
1940 addcnid = prevcnid + 1;
1941 while (addcnid <= cnid) {
1942 if (w->nconns > max) {
1943 device_printf(sc->dev,
1944 "%s: nid=%d: Adding %d: "
1945 "Max connection reached! max=%d\n",
1946 __func__, nid, addcnid, max + 1);
1947 goto getconns_out;
1948 }
1949 w->conns[w->nconns++] = addcnid++;
558a398b 1950 }
4886ec58 1951 prevcnid = cnid;
558a398b 1952 }
558a398b
SS
1953 }
1954
4886ec58 1955getconns_out:
558a398b 1956 HDA_BOOTVERBOSE(
4886ec58
HT
1957 device_printf(sc->dev,
1958 "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n",
1959 __func__, nid, ents, w->nconns);
558a398b 1960 );
4886ec58 1961 return;
558a398b
SS
1962}
1963
1964static uint32_t
1965hdac_widget_pin_getconfig(struct hdac_widget *w)
1966{
1967 struct hdac_softc *sc;
4886ec58 1968 uint32_t config, orig, id;
558a398b
SS
1969 nid_t cad, nid;
1970
1971 sc = w->devinfo->codec->sc;
1972 cad = w->devinfo->codec->cad;
1973 nid = w->nid;
1974 id = hdac_codec_id(w->devinfo);
1975
1976 config = hdac_command(sc,
1977 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid),
1978 cad);
4886ec58
HT
1979 orig = config;
1980
558a398b
SS
1981 /*
1982 * XXX REWRITE!!!! Don't argue!
1983 */
4886ec58
HT
1984 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) {
1985 switch (nid) {
1986 case 26:
1987 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1988 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
1989 break;
1990 case 27:
1991 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1992 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT;
1993 break;
1994 default:
1995 break;
1996 }
1997 } else if (id == HDA_CODEC_ALC880 &&
558a398b
SS
1998 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR ||
1999 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) {
2000 /*
2001 * Super broken BIOS
2002 */
2003 switch (nid) {
2004 case 20:
2005 break;
2006 case 21:
2007 break;
2008 case 22:
2009 break;
2010 case 23:
2011 break;
2012 case 24: /* MIC1 */
2013 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2014 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2015 break;
2016 case 25: /* XXX MIC2 */
2017 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2018 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2019 break;
2020 case 26: /* LINE1 */
2021 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2022 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2023 break;
2024 case 27: /* XXX LINE2 */
2025 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2026 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2027 break;
2028 case 28: /* CD */
2029 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2030 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD;
2031 break;
2032 case 30:
2033 break;
2034 case 31:
2035 break;
2036 default:
2037 break;
2038 }
4886ec58
HT
2039 } else if (id == HDA_CODEC_ALC883 &&
2040 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) {
2041 switch (nid) {
2042 case 25:
2043 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2044 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2045 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2046 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2047 break;
2048 case 28:
2049 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2050 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2051 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2052 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2053 break;
2054 default:
2055 break;
2056 }
2057 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor ==
2058 HP_V3000_SUBVENDOR) {
2059 switch (nid) {
2060 case 18:
2061 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2062 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2063 break;
2064 case 20:
2065 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2066 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2067 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2068 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2069 break;
2070 case 21:
2071 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2072 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2073 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2074 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2075 break;
2076 default:
2077 break;
2078 }
2079 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor ==
2080 HP_DV5000_SUBVENDOR) {
2081 switch (nid) {
2082 case 20:
2083 case 21:
2084 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2085 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2086 break;
2087 default:
2088 break;
2089 }
2090 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2091 ASUS_W6F_SUBVENDOR) {
2092 switch (nid) {
2093 case 11:
2094 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2095 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2096 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT |
2097 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2098 break;
2099 case 15:
2100 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2101 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2102 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2103 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2104 break;
2105 default:
2106 break;
2107 }
2108 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2109 UNIWILL_9075_SUBVENDOR) {
2110 switch (nid) {
2111 case 15:
2112 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2113 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2114 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2115 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2116 break;
2117 default:
2118 break;
2119 }
9c553cf8
SS
2120 } else if (id == HDA_CODEC_AD1986A &&
2121 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR ||
19c72e40 2122 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) {
4886ec58
HT
2123 switch (nid) {
2124 case 28: /* LINE */
2125 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2126 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2127 break;
2128 case 29: /* MIC */
2129 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2130 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2131 break;
2132 default:
2133 break;
2134 }
558a398b
SS
2135 }
2136
4886ec58
HT
2137 HDA_BOOTVERBOSE(
2138 if (config != orig)
2139 device_printf(sc->dev,
2140 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n",
2141 nid, orig, config);
2142 );
2143
558a398b
SS
2144 return (config);
2145}
2146
4886ec58
HT
2147static uint32_t
2148hdac_widget_pin_getcaps(struct hdac_widget *w)
2149{
2150 struct hdac_softc *sc;
2151 uint32_t caps, orig, id;
2152 nid_t cad, nid;
2153
2154 sc = w->devinfo->codec->sc;
2155 cad = w->devinfo->codec->cad;
2156 nid = w->nid;
2157 id = hdac_codec_id(w->devinfo);
2158
2159 caps = hdac_command(sc,
2160 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad);
2161 orig = caps;
2162
2163 HDA_BOOTVERBOSE(
2164 if (caps != orig)
2165 device_printf(sc->dev,
2166 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n",
2167 nid, orig, caps);
2168 );
2169
2170 return (caps);
2171}
2172
558a398b
SS
2173static void
2174hdac_widget_pin_parse(struct hdac_widget *w)
2175{
2176 struct hdac_softc *sc = w->devinfo->codec->sc;
2177 uint32_t config, pincap;
2178 char *devstr, *connstr;
2179 nid_t cad = w->devinfo->codec->cad;
2180 nid_t nid = w->nid;
2181
2182 config = hdac_widget_pin_getconfig(w);
2183 w->wclass.pin.config = config;
2184
4886ec58 2185 pincap = hdac_widget_pin_getcaps(w);
558a398b
SS
2186 w->wclass.pin.cap = pincap;
2187
2188 w->wclass.pin.ctrl = hdac_command(sc,
4886ec58
HT
2189 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) &
2190 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE |
2191 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
2192 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE |
2193 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK);
558a398b
SS
2194
2195 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap))
2196 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE;
2197 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
2198 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
2199 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
2200 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE;
2201 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) {
2202 w->param.eapdbtl = hdac_command(sc,
2203 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad);
2204 w->param.eapdbtl &= 0x7;
2205 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
2206 } else
2207 w->param.eapdbtl = HDAC_INVALID;
2208
2209 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) {
2210 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT:
2211 devstr = "line out";
2212 break;
2213 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER:
2214 devstr = "speaker";
2215 break;
2216 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT:
2217 devstr = "headphones out";
2218 break;
2219 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD:
2220 devstr = "CD";
2221 break;
2222 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT:
2223 devstr = "SPDIF out";
2224 break;
2225 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT:
2226 devstr = "digital (other) out";
2227 break;
2228 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE:
2229 devstr = "modem, line side";
2230 break;
2231 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET:
2232 devstr = "modem, handset side";
2233 break;
2234 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN:
2235 devstr = "line in";
2236 break;
2237 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX:
2238 devstr = "AUX";
2239 break;
2240 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
2241 devstr = "Mic in";
2242 break;
2243 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY:
2244 devstr = "telephony";
2245 break;
2246 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN:
2247 devstr = "SPDIF in";
2248 break;
2249 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN:
2250 devstr = "digital (other) in";
2251 break;
2252 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER:
2253 devstr = "other";
2254 break;
2255 default:
2256 devstr = "unknown";
2257 break;
2258 }
2259
2260 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) {
2261 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK:
2262 connstr = "jack";
2263 break;
2264 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE:
2265 connstr = "none";
2266 break;
2267 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED:
2268 connstr = "fixed";
2269 break;
2270 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH:
2271 connstr = "jack / fixed";
2272 break;
2273 default:
2274 connstr = "unknown";
2275 break;
2276 }
2277
2278 strlcat(w->name, ": ", sizeof(w->name));
2279 strlcat(w->name, devstr, sizeof(w->name));
2280 strlcat(w->name, " (", sizeof(w->name));
2281 strlcat(w->name, connstr, sizeof(w->name));
2282 strlcat(w->name, ")", sizeof(w->name));
2283}
2284
2285static void
2286hdac_widget_parse(struct hdac_widget *w)
2287{
2288 struct hdac_softc *sc = w->devinfo->codec->sc;
2289 uint32_t wcap, cap;
2290 char *typestr;
2291 nid_t cad = w->devinfo->codec->cad;
2292 nid_t nid = w->nid;
2293
2294 wcap = hdac_command(sc,
2295 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP),
2296 cad);
2297 w->param.widget_cap = wcap;
2298 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap);
2299
2300 switch (w->type) {
2301 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
2302 typestr = "audio output";
2303 break;
2304 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
2305 typestr = "audio input";
2306 break;
2307 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
2308 typestr = "audio mixer";
2309 break;
2310 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
2311 typestr = "audio selector";
2312 break;
2313 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
2314 typestr = "pin";
2315 break;
2316 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET:
2317 typestr = "power widget";
2318 break;
2319 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET:
2320 typestr = "volume widget";
2321 break;
2322 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET:
2323 typestr = "beep widget";
2324 break;
2325 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET:
2326 typestr = "vendor widget";
2327 break;
2328 default:
2329 typestr = "unknown type";
2330 break;
2331 }
2332
2333 strlcpy(w->name, typestr, sizeof(w->name));
2334
2335 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) {
2336 hdac_command(sc,
2337 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0),
2338 cad);
2339 DELAY(1000);
2340 }
2341
2342 hdac_widget_connection_parse(w);
2343
2344 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) {
2345 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2346 w->param.outamp_cap =
2347 hdac_command(sc,
2348 HDA_CMD_GET_PARAMETER(cad, nid,
2349 HDA_PARAM_OUTPUT_AMP_CAP), cad);
2350 else
2351 w->param.outamp_cap =
2352 w->devinfo->function.audio.outamp_cap;
2353 } else
2354 w->param.outamp_cap = 0;
2355
2356 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) {
2357 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2358 w->param.inamp_cap =
2359 hdac_command(sc,
2360 HDA_CMD_GET_PARAMETER(cad, nid,
2361 HDA_PARAM_INPUT_AMP_CAP), cad);
2362 else
2363 w->param.inamp_cap =
2364 w->devinfo->function.audio.inamp_cap;
2365 } else
2366 w->param.inamp_cap = 0;
2367
2368 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
2369 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
2370 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) {
2371 cap = hdac_command(sc,
2372 HDA_CMD_GET_PARAMETER(cad, nid,
2373 HDA_PARAM_SUPP_STREAM_FORMATS), cad);
2374 w->param.supp_stream_formats = (cap != 0) ? cap :
2375 w->devinfo->function.audio.supp_stream_formats;
2376 cap = hdac_command(sc,
2377 HDA_CMD_GET_PARAMETER(cad, nid,
2378 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad);
2379 w->param.supp_pcm_size_rate = (cap != 0) ? cap :
2380 w->devinfo->function.audio.supp_pcm_size_rate;
2381 } else {
2382 w->param.supp_stream_formats =
2383 w->devinfo->function.audio.supp_stream_formats;
2384 w->param.supp_pcm_size_rate =
2385 w->devinfo->function.audio.supp_pcm_size_rate;
2386 }
2387 } else {
2388 w->param.supp_stream_formats = 0;
2389 w->param.supp_pcm_size_rate = 0;
2390 }
2391
2392 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
2393 hdac_widget_pin_parse(w);
2394}
2395
2396static struct hdac_widget *
2397hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid)
2398{
2399 if (devinfo == NULL || devinfo->widget == NULL ||
2400 nid < devinfo->startnode || nid >= devinfo->endnode)
2401 return (NULL);
2402 return (&devinfo->widget[nid - devinfo->startnode]);
2403}
2404
4886ec58
HT
2405static __inline int
2406hda_poll_channel(struct hdac_chan *ch)
2407{
2408 uint32_t sz, delta;
2409 volatile uint32_t ptr;
2410
6ef811ff 2411 if (!(ch->flags & HDAC_CHN_RUNNING))
4886ec58
HT
2412 return (0);
2413
2414 sz = ch->blksz * ch->blkcnt;
2415 if (ch->dmapos != NULL)
2416 ptr = *(ch->dmapos);
2417 else
2418 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem,
2419 ch->off + HDAC_SDLPIB);
2420 ch->ptr = ptr;
2421 ptr %= sz;
2422 ptr &= ~(ch->blksz - 1);
2423 delta = (sz + ptr - ch->prevptr) % sz;
2424
2425 if (delta < ch->blksz)
2426 return (0);
2427
2428 ch->prevptr = ptr;
2429
2430 return (1);
2431}
2432
6ef811ff
HT
2433#define hda_chan_active(sc) (((sc)->play.flags | (sc)->rec.flags) & \
2434 HDAC_CHN_RUNNING)
4886ec58
HT
2435
2436static void
2437hda_poll_callback(void *arg)
2438{
2439 struct hdac_softc *sc = arg;
19c72e40 2440 uint32_t trigger;
4886ec58
HT
2441
2442 if (sc == NULL)
2443 return;
2444
2445 hdac_lock(sc);
2446 if (sc->polling == 0 || hda_chan_active(sc) == 0) {
2447 hdac_unlock(sc);
2448 return;
2449 }
2450
19c72e40
HT
2451 trigger = 0;
2452 trigger |= (hda_poll_channel(&sc->play) != 0) ? HDAC_TRIGGER_PLAY : 0;
2453 trigger |= (hda_poll_channel(&sc->rec)) != 0 ? HDAC_TRIGGER_REC : 0;
4886ec58
HT
2454
2455 /* XXX */
2456 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/,
2457 hda_poll_callback, sc);
2458
2459 hdac_unlock(sc);
2460
19c72e40 2461 if (trigger & HDAC_TRIGGER_PLAY)
4886ec58 2462 chn_intr(sc->play.c);
19c72e40 2463 if (trigger & HDAC_TRIGGER_REC)
4886ec58
HT
2464 chn_intr(sc->rec.c);
2465}
2466
2467static int
2468hdac_rirb_flush(struct hdac_softc *sc)
2469{
2470 struct hdac_rirb *rirb_base, *rirb;
2471 struct hdac_codec *codec;
2472 struct hdac_command_list *commands;
2473 nid_t cad;
2474 uint32_t resp;
2475 uint8_t rirbwp;
19c72e40 2476 int ret;
4886ec58
HT
2477
2478 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
2479 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
2480#if 0
2481 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
2482 BUS_DMASYNC_POSTREAD);
2483#endif
19c72e40 2484 ret = 0;
4886ec58
HT
2485
2486 while (sc->rirb_rp != rirbwp) {
2487 sc->rirb_rp++;
2488 sc->rirb_rp %= sc->rirb_size;
2489 rirb = &rirb_base[sc->rirb_rp];
2490 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex);
2491 if (cad < 0 || cad >= HDAC_CODEC_MAX ||
2492 sc->codecs[cad] == NULL)
2493 continue;
2494 resp = rirb->response;
2495 codec = sc->codecs[cad];
2496 commands = codec->commands;
2497 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
2498 sc->unsolq[sc->unsolq_wp++] = (cad << 16) |
2499 ((resp >> 26) & 0xffff);
2500 sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
2501 } else if (commands != NULL && commands->num_commands > 0 &&
2502 codec->responses_received < commands->num_commands)
2503 commands->responses[codec->responses_received++] =
2504 resp;
2505 ret++;
2506 }
2507
2508 return (ret);
2509}
2510
2511static int
2512hdac_unsolq_flush(struct hdac_softc *sc)
2513{
2514 nid_t cad;
2515 uint32_t tag;
2516 int ret = 0;
2517
2518 if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
2519 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
2520 while (sc->unsolq_rp != sc->unsolq_wp) {
2521 cad = sc->unsolq[sc->unsolq_rp] >> 16;
2522 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff;
2523 sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
2524 hdac_unsolicited_handler(sc->codecs[cad], tag);
2525 ret++;
2526 }
2527 sc->unsolq_st = HDAC_UNSOLQ_READY;
2528 }
2529
2530 return (ret);
2531}
2532
2533static void
2534hdac_poll_callback(void *arg)
2535{
2536 struct hdac_softc *sc = arg;
2537 if (sc == NULL)
2538 return;
2539
2540 hdac_lock(sc);
2541 if (sc->polling == 0 || sc->poll_ival == 0) {
2542 hdac_unlock(sc);
2543 return;
2544 }
19c72e40
HT
2545 if (hdac_rirb_flush(sc) != 0)
2546 hdac_unsolq_flush(sc);
4886ec58
HT
2547 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc);
2548 hdac_unlock(sc);
2549}
2550
558a398b
SS
2551static void
2552hdac_stream_stop(struct hdac_chan *ch)
2553{
2554 struct hdac_softc *sc = ch->devinfo->codec->sc;
2555 uint32_t ctl;
2556
2557 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2558 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
2559 HDAC_SDCTL_RUN);
2560 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2561
6ef811ff 2562 ch->flags &= ~HDAC_CHN_RUNNING;
4886ec58
HT
2563
2564 if (sc->polling != 0) {
2565 int pollticks;
2566
2567 if (hda_chan_active(sc) == 0) {
2568 callout_stop(&sc->poll_hda);
2569 sc->poll_ticks = 1;
2570 } else {
6ef811ff 2571 if (sc->play.flags & HDAC_CHN_RUNNING)
4886ec58
HT
2572 ch = &sc->play;
2573 else
2574 ch = &sc->rec;
2575 pollticks = ((uint64_t)hz * ch->blksz) /
2576 ((uint64_t)sndbuf_getbps(ch->b) *
2577 sndbuf_getspd(ch->b));
2578 pollticks >>= 2;
2579 if (pollticks > hz)
2580 pollticks = hz;
2581 if (pollticks < 1) {
2582 HDA_BOOTVERBOSE(
2583 device_printf(sc->dev,
2584 "%s: pollticks=%d < 1 !\n",
2585 __func__, pollticks);
2586 );
2587 pollticks = 1;
2588 }
2589 if (pollticks > sc->poll_ticks) {
2590 HDA_BOOTVERBOSE(
2591 device_printf(sc->dev,
2592 "%s: pollticks %d -> %d\n",
2593 __func__, sc->poll_ticks,
2594 pollticks);
2595 );
2596 sc->poll_ticks = pollticks;
2597 callout_reset(&sc->poll_hda, 1,
2598 hda_poll_callback, sc);
2599 }
2600 }
2601 } else {
2602 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
2603 ctl &= ~(1 << (ch->off >> 5));
2604 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
2605 }
558a398b
SS
2606}
2607
2608static void
2609hdac_stream_start(struct hdac_chan *ch)
2610{
2611 struct hdac_softc *sc = ch->devinfo->codec->sc;
2612 uint32_t ctl;
2613
4886ec58
HT
2614 if (sc->polling != 0) {
2615 int pollticks;
558a398b 2616
4886ec58
HT
2617 pollticks = ((uint64_t)hz * ch->blksz) /
2618 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b));
2619 pollticks >>= 2;
2620 if (pollticks > hz)
2621 pollticks = hz;
2622 if (pollticks < 1) {
2623 HDA_BOOTVERBOSE(
2624 device_printf(sc->dev,
2625 "%s: pollticks=%d < 1 !\n",
2626 __func__, pollticks);
2627 );
2628 pollticks = 1;
2629 }
2630 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) {
2631 HDA_BOOTVERBOSE(
2632 if (hda_chan_active(sc) == 0) {
2633 device_printf(sc->dev,
2634 "%s: pollticks=%d\n",
2635 __func__, pollticks);
2636 } else {
2637 device_printf(sc->dev,
2638 "%s: pollticks %d -> %d\n",
2639 __func__, sc->poll_ticks,
2640 pollticks);
2641 }
2642 );
2643 sc->poll_ticks = pollticks;
2644 callout_reset(&sc->poll_hda, 1, hda_poll_callback,
2645 sc);
2646 }
2647 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2648 ctl |= HDAC_SDCTL_RUN;
2649 } else {
2650 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
2651 ctl |= 1 << (ch->off >> 5);
2652 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
2653 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2654 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
2655 HDAC_SDCTL_RUN;
2656 }
558a398b 2657 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
4886ec58 2658
6ef811ff 2659 ch->flags |= HDAC_CHN_RUNNING;
558a398b
SS
2660}
2661
2662static void
2663hdac_stream_reset(struct hdac_chan *ch)
2664{
2665 struct hdac_softc *sc = ch->devinfo->codec->sc;
2666 int timeout = 1000;
2667 int to = timeout;
2668 uint32_t ctl;
2669
2670 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2671 ctl |= HDAC_SDCTL_SRST;
2672 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2673 do {
2674 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2675 if (ctl & HDAC_SDCTL_SRST)
2676 break;
2677 DELAY(10);
2678 } while (--to);
2679 if (!(ctl & HDAC_SDCTL_SRST)) {
2680 device_printf(sc->dev, "timeout in reset\n");
2681 }
2682 ctl &= ~HDAC_SDCTL_SRST;
2683 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2684 to = timeout;
2685 do {
2686 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2687 if (!(ctl & HDAC_SDCTL_SRST))
2688 break;
2689 DELAY(10);
2690 } while (--to);
2691 if (ctl & HDAC_SDCTL_SRST)
2692 device_printf(sc->dev, "can't reset!\n");
2693}
2694
2695static void
2696hdac_stream_setid(struct hdac_chan *ch)
2697{
2698 struct hdac_softc *sc = ch->devinfo->codec->sc;
2699 uint32_t ctl;
2700
2701 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2);
2702 ctl &= ~HDAC_SDCTL2_STRM_MASK;
2703 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT;
2704 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl);
2705}
2706
2707static void
2708hdac_bdl_setup(struct hdac_chan *ch)
2709{
2710 struct hdac_softc *sc = ch->devinfo->codec->sc;
558a398b 2711 struct hdac_bdle *bdle;
4886ec58
HT
2712 uint64_t addr;
2713 uint32_t blksz, blkcnt;
558a398b
SS
2714 int i;
2715
2716 addr = (uint64_t)sndbuf_getbufaddr(ch->b);
4886ec58
HT
2717 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr;
2718
2719 if (sc->polling != 0) {
2720 blksz = ch->blksz * ch->blkcnt;
2721 blkcnt = 1;
2722 } else {
2723 blksz = ch->blksz;
2724 blkcnt = ch->blkcnt;
2725 }
558a398b 2726
4886ec58 2727 for (i = 0; i < blkcnt; i++, bdle++) {
558a398b
SS
2728 bdle->addrl = (uint32_t)addr;
2729 bdle->addrh = (uint32_t)(addr >> 32);
4886ec58
HT
2730 bdle->len = blksz;
2731 bdle->ioc = 1 ^ sc->polling;
2732 addr += blksz;
558a398b
SS
2733 }
2734
4886ec58
HT
2735 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt);
2736 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1);
558a398b
SS
2737 addr = ch->bdl_dma.dma_paddr;
2738 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr);
2739 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
4886ec58
HT
2740 if (ch->dmapos != NULL &&
2741 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) {
2742 addr = sc->pos_dma.dma_paddr;
2743 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE,
2744 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001);
2745 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32));
2746 }
558a398b
SS
2747}
2748
2749static int
2750hdac_bdl_alloc(struct hdac_chan *ch)
2751{
2752 struct hdac_softc *sc = ch->devinfo->codec->sc;
2753 int rc;
2754
2755 rc = hdac_dma_alloc(sc, &ch->bdl_dma,
2756 sizeof(struct hdac_bdle) * HDA_BDL_MAX);
2757 if (rc) {
2758 device_printf(sc->dev, "can't alloc bdl\n");
2759 return (rc);
2760 }
558a398b
SS
2761
2762 return (0);
2763}
2764
2765static void
2766hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid,
2767 int index, int lmute, int rmute,
2768 int left, int right, int dir)
2769{
2770 uint16_t v = 0;
2771
2772 if (sc == NULL)
2773 return;
2774
2775 if (left != right || lmute != rmute) {
2776 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) |
2777 (lmute << 7) | left;
2778 hdac_command(sc,
4886ec58 2779 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
558a398b
SS
2780 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) |
2781 (rmute << 7) | right;
2782 } else
2783 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) |
2784 (lmute << 7) | left;
2785
2786 hdac_command(sc,
2787 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
2788}
2789
2790static void
2791hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute,
2792 int left, int right)
2793{
2794 struct hdac_softc *sc;
2795 nid_t nid, cad;
2796 int lmute, rmute;
2797
2798 if (ctl == NULL || ctl->widget == NULL ||
2799 ctl->widget->devinfo == NULL ||
2800 ctl->widget->devinfo->codec == NULL ||
2801 ctl->widget->devinfo->codec->sc == NULL)
2802 return;
2803
2804 sc = ctl->widget->devinfo->codec->sc;
2805 cad = ctl->widget->devinfo->codec->cad;
2806 nid = ctl->widget->nid;
2807
2808 if (mute == HDA_AMP_MUTE_DEFAULT) {
2809 lmute = HDA_AMP_LEFT_MUTED(ctl->muted);
2810 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted);
2811 } else {
2812 lmute = HDA_AMP_LEFT_MUTED(mute);
2813 rmute = HDA_AMP_RIGHT_MUTED(mute);
2814 }
2815
2816 if (ctl->dir & HDA_CTL_OUT)
2817 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
2818 lmute, rmute, left, right, 0);
2819 if (ctl->dir & HDA_CTL_IN)
2820 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
2821 lmute, rmute, left, right, 1);
2822 ctl->left = left;
2823 ctl->right = right;
2824}
2825
2826static void
2827hdac_widget_connection_select(struct hdac_widget *w, uint8_t index)
2828{
2829 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1))
2830 return;
2831 hdac_command(w->devinfo->codec->sc,
2832 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad,
2833 w->nid, index), w->devinfo->codec->cad);
2834 w->selconn = index;
2835}
2836
2837
2838/****************************************************************************
2839 * uint32_t hdac_command_sendone_internal
2840 *
2841 * Wrapper function that sends only one command to a given codec
2842 ****************************************************************************/
2843static uint32_t
2844hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad)
2845{
2846 struct hdac_command_list cl;
2847 uint32_t response = HDAC_INVALID;
2848
2849 if (!hdac_lockowned(sc))
2850 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n");
2851 cl.num_commands = 1;
2852 cl.verbs = &verb;
2853 cl.responses = &response;
2854
2855 hdac_command_send_internal(sc, &cl, cad);
2856
2857 return (response);
2858}
2859
2860/****************************************************************************
2861 * hdac_command_send_internal
2862 *
2863 * Send a command list to the codec via the corb. We queue as much verbs as
2864 * we can and msleep on the codec. When the interrupt get the responses
2865 * back from the rirb, it will wake us up so we can queue the remaining verbs
2866 * if any.
2867 ****************************************************************************/
2868static void
2869hdac_command_send_internal(struct hdac_softc *sc,
2870 struct hdac_command_list *commands, nid_t cad)
2871{
2872 struct hdac_codec *codec;
2873 int corbrp;
2874 uint32_t *corb;
558a398b
SS
2875 int timeout;
2876 int retry = 10;
4886ec58 2877 struct hdac_rirb *rirb_base;
558a398b 2878
4886ec58
HT
2879 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL ||
2880 commands->num_commands < 1)
558a398b
SS
2881 return;
2882
2883 codec = sc->codecs[cad];
2884 codec->commands = commands;
2885 codec->responses_received = 0;
2886 codec->verbs_sent = 0;
2887 corb = (uint32_t *)sc->corb_dma.dma_vaddr;
2888 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
2889
2890 do {
2891 if (codec->verbs_sent != commands->num_commands) {
2892 /* Queue as many verbs as possible */
2893 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP);
4886ec58 2894#if 0
558a398b
SS
2895 bus_dmamap_sync(sc->corb_dma.dma_tag,
2896 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
4886ec58 2897#endif
558a398b
SS
2898 while (codec->verbs_sent != commands->num_commands &&
2899 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) {
2900 sc->corb_wp++;
2901 sc->corb_wp %= sc->corb_size;
2902 corb[sc->corb_wp] =
2903 commands->verbs[codec->verbs_sent++];
2904 }
2905
2906 /* Send the verbs to the codecs */
4886ec58 2907#if 0
558a398b
SS
2908 bus_dmamap_sync(sc->corb_dma.dma_tag,
2909 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
4886ec58 2910#endif
558a398b
SS
2911 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
2912 }
2913
4886ec58
HT
2914 timeout = 1000;
2915 while (hdac_rirb_flush(sc) == 0 && --timeout)
558a398b 2916 DELAY(10);
558a398b 2917 } while ((codec->verbs_sent != commands->num_commands ||
4886ec58 2918 codec->responses_received != commands->num_commands) && --retry);
558a398b
SS
2919
2920 if (retry == 0)
2921 device_printf(sc->dev,
4886ec58
HT
2922 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n",
2923 __func__, commands->num_commands, codec->verbs_sent,
2924 codec->responses_received);
558a398b 2925
4886ec58
HT
2926 codec->commands = NULL;
2927 codec->responses_received = 0;
558a398b
SS
2928 codec->verbs_sent = 0;
2929
4886ec58 2930 hdac_unsolq_flush(sc);
558a398b
SS
2931}
2932
2933
2934/****************************************************************************
2935 * Device Methods
2936 ****************************************************************************/
2937
2938/****************************************************************************
2939 * int hdac_probe(device_t)
2940 *
2941 * Probe for the presence of an hdac. If none is found, check for a generic
2942 * match using the subclass of the device.
2943 ****************************************************************************/
2944static int
2945hdac_probe(device_t dev)
2946{
2947 int i, result;
2948 uint32_t model;
2949 uint16_t class, subclass;
2950 char desc[64];
2951
2952 model = (uint32_t)pci_get_device(dev) << 16;
2953 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
2954 class = pci_get_class(dev);
2955 subclass = pci_get_subclass(dev);
2956
2957 bzero(desc, sizeof(desc));
2958 result = ENXIO;
2959 for (i = 0; i < HDAC_DEVICES_LEN; i++) {
2960 if (hdac_devices[i].model == model) {
2961 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
4886ec58 2962 result = BUS_PROBE_DEFAULT;
558a398b
SS
2963 break;
2964 }
2965 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
2966 class == PCIC_MULTIMEDIA &&
2967 subclass == PCIS_MULTIMEDIA_HDA) {
2968 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
4886ec58 2969 result = BUS_PROBE_GENERIC;
558a398b
SS
2970 break;
2971 }
2972 }
2973 if (result == ENXIO && class == PCIC_MULTIMEDIA &&
2974 subclass == PCIS_MULTIMEDIA_HDA) {
2975 strlcpy(desc, "Generic", sizeof(desc));
4886ec58 2976 result = BUS_PROBE_GENERIC;
558a398b
SS
2977 }
2978 if (result != ENXIO) {
2979 strlcat(desc, " High Definition Audio Controller",
2980 sizeof(desc));
2981 device_set_desc_copy(dev, desc);
2982 }
2983
2984 return (result);
2985}
2986
2987static void *
2988hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b,
2989 struct pcm_channel *c, int dir)
2990{
2991 struct hdac_devinfo *devinfo = data;
2992 struct hdac_softc *sc = devinfo->codec->sc;
2993 struct hdac_chan *ch;
2994
2995 hdac_lock(sc);
2996 if (dir == PCMDIR_PLAY) {
2997 ch = &sc->play;
2998 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5;
558a398b
SS
2999 devinfo->function.audio.playcnt++;
3000 } else {
3001 ch = &sc->rec;
3002 ch->off = devinfo->function.audio.reccnt << 5;
558a398b
SS
3003 devinfo->function.audio.reccnt++;
3004 }
3005 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) {
3006 ch->caps.minspeed = ch->caps.maxspeed = 48000;
3007 ch->pcmrates[0] = 48000;
3008 ch->pcmrates[1] = 0;
3009 }
4886ec58
HT
3010 if (sc->pos_dma.dma_vaddr != NULL)
3011 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr +
3012 (sc->streamcnt * 8));
3013 else
3014 ch->dmapos = NULL;
3015 ch->sid = ++sc->streamcnt;
3016 ch->dir = dir;
558a398b
SS
3017 ch->b = b;
3018 ch->c = c;
3019 ch->devinfo = devinfo;
3020 ch->blksz = sc->chan_size / sc->chan_blkcnt;
3021 ch->blkcnt = sc->chan_blkcnt;
3022 hdac_unlock(sc);
3023
3024 if (hdac_bdl_alloc(ch) != 0) {
3025 ch->blkcnt = 0;
3026 return (NULL);
3027 }
3028
3029 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0)
3030 return (NULL);
3031
4886ec58
HT
3032 HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b), sndbuf_getmaxsize(ch->b),
3033 PAT_UNCACHEABLE);
558a398b
SS
3034
3035 return (ch);
3036}
3037
4886ec58
HT
3038static int
3039hdac_channel_free(kobj_t obj, void *data)
3040{
3041 struct hdac_softc *sc;
3042 struct hdac_chan *ch;
3043
3044 ch = (struct hdac_chan *)data;
3045 sc = (ch != NULL && ch->devinfo != NULL && ch->devinfo->codec != NULL) ?
3046 ch->devinfo->codec->sc : NULL;
3047 if (ch != NULL && sc != NULL) {
3048 HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b),
3049 sndbuf_getmaxsize(ch->b), PAT_WRITE_BACK);
3050 }
3051
3052 return (1);
3053}
3054
558a398b
SS
3055static int
3056hdac_channel_setformat(kobj_t obj, void *data, uint32_t format)
3057{
3058 struct hdac_chan *ch = data;
3059 int i;
3060
3061 for (i = 0; ch->caps.fmtlist[i] != 0; i++) {
3062 if (format == ch->caps.fmtlist[i]) {
3063 ch->fmt = format;
3064 return (0);
3065 }
3066 }
3067
3068 return (EINVAL);
3069}
3070
3071static int
3072hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed)
3073{
3074 struct hdac_chan *ch = data;
4886ec58 3075 uint32_t spd = 0, threshold;
558a398b
SS
3076 int i;
3077
3078 for (i = 0; ch->pcmrates[i] != 0; i++) {
3079 spd = ch->pcmrates[i];
4886ec58
HT
3080 threshold = spd + ((ch->pcmrates[i + 1] != 0) ?
3081 ((ch->pcmrates[i + 1] - spd) >> 1) : 0);
3082 if (speed < threshold)
558a398b
SS
3083 break;
3084 }
3085
4886ec58 3086 if (spd == 0) /* impossible */
558a398b
SS
3087 ch->spd = 48000;
3088 else
3089 ch->spd = spd;
3090
3091 return (ch->spd);
3092}
3093
3094static void
3095hdac_stream_setup(struct hdac_chan *ch)
3096{
3097 struct hdac_softc *sc = ch->devinfo->codec->sc;
3098 int i;
3099 nid_t cad = ch->devinfo->codec->cad;
3100 uint16_t fmt;
3101
3102 fmt = 0;
3103 if (ch->fmt & AFMT_S16_LE)
3104 fmt |= ch->bit16 << 4;
3105 else if (ch->fmt & AFMT_S32_LE)
3106 fmt |= ch->bit32 << 4;
3107 else
3108 fmt |= 1 << 4;
3109
3110 for (i = 0; i < HDA_RATE_TAB_LEN; i++) {
3111 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) {
3112 fmt |= hda_rate_tab[i].base;
3113 fmt |= hda_rate_tab[i].mul;
3114 fmt |= hda_rate_tab[i].div;
3115 break;
3116 }
3117 }
3118
3119 if (ch->fmt & AFMT_STEREO)
3120 fmt |= 1;
3121
3122 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt);
3123
3124 for (i = 0; ch->io[i] != -1; i++) {
3125 HDA_BOOTVERBOSE(
3126 device_printf(sc->dev,
3127 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d "
3128 "fmt=0x%08x\n",
3129 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC",
3130 ch->io[i], fmt);
3131 );
3132 hdac_command(sc,
3133 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad);
3134 hdac_command(sc,
3135 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3136 ch->sid << 4), cad);
3137 }
3138}
3139
3140static int
4886ec58
HT
3141hdac_channel_setfragments(kobj_t obj, void *data,
3142 uint32_t blksz, uint32_t blkcnt)
3143{
3144 struct hdac_chan *ch = data;
3145 struct hdac_softc *sc = ch->devinfo->codec->sc;
3146
3147 blksz &= HDA_BLK_ALIGN;
3148
3149 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN))
3150 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN;
3151 if (blksz < HDA_BLK_MIN)
3152 blksz = HDA_BLK_MIN;
3153 if (blkcnt > HDA_BDL_MAX)
3154 blkcnt = HDA_BDL_MAX;
3155 if (blkcnt < HDA_BDL_MIN)
3156 blkcnt = HDA_BDL_MIN;
3157
3158 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) {
3159 if ((blkcnt >> 1) >= HDA_BDL_MIN)
3160 blkcnt >>= 1;
3161 else if ((blksz >> 1) >= HDA_BLK_MIN)
3162 blksz >>= 1;
3163 else
3164 break;
3165 }
3166
3167 if ((sndbuf_getblksz(ch->b) != blksz ||
3168 sndbuf_getblkcnt(ch->b) != blkcnt) &&
3169 sndbuf_resize(ch->b, blkcnt, blksz) != 0)
3170 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n",
3171 __func__, blksz, blkcnt);
3172
3173 ch->blksz = sndbuf_getblksz(ch->b);
3174 ch->blkcnt = sndbuf_getblkcnt(ch->b);
3175
3176 return (1);
3177}
3178
3179static int
3180hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz)
558a398b
SS
3181{
3182 struct hdac_chan *ch = data;
4886ec58 3183 struct hdac_softc *sc = ch->devinfo->codec->sc;
558a398b 3184
4886ec58 3185 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt);
558a398b
SS
3186
3187 return (ch->blksz);
3188}
3189
3190static void
3191hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch)
3192{
3193 struct hdac_devinfo *devinfo = ch->devinfo;
3194 nid_t cad = devinfo->codec->cad;
3195 int i;
3196
3197 hdac_stream_stop(ch);
3198
3199 for (i = 0; ch->io[i] != -1; i++) {
3200 hdac_command(sc,
3201 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3202 0), cad);
3203 }
3204}
3205
3206static void
3207hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch)
3208{
3209 ch->ptr = 0;
3210 ch->prevptr = 0;
3211 hdac_stream_stop(ch);
3212 hdac_stream_reset(ch);
3213 hdac_bdl_setup(ch);
3214 hdac_stream_setid(ch);
3215 hdac_stream_setup(ch);
3216 hdac_stream_start(ch);
3217}
3218
3219static int
3220hdac_channel_trigger(kobj_t obj, void *data, int go)
3221{
3222 struct hdac_chan *ch = data;
3223 struct hdac_softc *sc = ch->devinfo->codec->sc;
3224
4886ec58
HT
3225 if (!(go == PCMTRIG_START || go == PCMTRIG_STOP || go == PCMTRIG_ABORT))
3226 return (0);
3227
558a398b
SS
3228 hdac_lock(sc);
3229 switch (go) {
3230 case PCMTRIG_START:
3231 hdac_channel_start(sc, ch);
3232 break;
3233 case PCMTRIG_STOP:
3234 case PCMTRIG_ABORT:
3235 hdac_channel_stop(sc, ch);
3236 break;
4886ec58
HT
3237 default:
3238 break;
558a398b
SS
3239 }
3240 hdac_unlock(sc);
3241
3242 return (0);
3243}
3244
3245static int
3246hdac_channel_getptr(kobj_t obj, void *data)
3247{
3248 struct hdac_chan *ch = data;
3249 struct hdac_softc *sc = ch->devinfo->codec->sc;
558a398b
SS
3250 uint32_t ptr;
3251
3252 hdac_lock(sc);
4886ec58
HT
3253 if (sc->polling != 0)
3254 ptr = ch->ptr;
3255 else if (ch->dmapos != NULL)
3256 ptr = *(ch->dmapos);
3257 else
3258 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB);
558a398b
SS
3259 hdac_unlock(sc);
3260
4886ec58
HT
3261 /*
3262 * Round to available space and force 128 bytes aligment.
3263 */
3264 ptr %= ch->blksz * ch->blkcnt;
3265 ptr &= HDA_BLK_ALIGN;
558a398b
SS
3266
3267 return (ptr);
3268}
3269
3270static struct pcmchan_caps *
3271hdac_channel_getcaps(kobj_t obj, void *data)
3272{
3273 return (&((struct hdac_chan *)data)->caps);
3274}
3275
3276static kobj_method_t hdac_channel_methods[] = {
3277 KOBJMETHOD(channel_init, hdac_channel_init),
4886ec58 3278 KOBJMETHOD(channel_free, hdac_channel_free),
558a398b
SS
3279 KOBJMETHOD(channel_setformat, hdac_channel_setformat),
3280 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed),
3281 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize),
3282 KOBJMETHOD(channel_trigger, hdac_channel_trigger),
3283 KOBJMETHOD(channel_getptr, hdac_channel_getptr),
3284 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps),
3285 { 0, 0 }
3286};
3287CHANNEL_DECLARE(hdac_channel);
3288
4886ec58
HT
3289static void
3290hdac_jack_poll_callback(void *arg)
3291{
3292 struct hdac_devinfo *devinfo = arg;
3293 struct hdac_softc *sc;
3294
3295 if (devinfo == NULL || devinfo->codec == NULL ||
3296 devinfo->codec->sc == NULL)
3297 return;
3298 sc = devinfo->codec->sc;
3299 hdac_lock(sc);
3300 if (sc->poll_ival == 0) {
3301 hdac_unlock(sc);
3302 return;
3303 }
3304 hdac_hp_switch_handler(devinfo);
3305 callout_reset(&sc->poll_jack, sc->poll_ival,
3306 hdac_jack_poll_callback, devinfo);
3307 hdac_unlock(sc);
3308}
3309
558a398b
SS
3310static int
3311hdac_audio_ctl_ossmixer_init(struct snd_mixer *m)
3312{
3313 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3314 struct hdac_softc *sc = devinfo->codec->sc;
3315 struct hdac_widget *w, *cw;
3316 struct hdac_audio_ctl *ctl;
3317 uint32_t mask, recmask, id;
3318 int i, j, softpcmvol;
3319 nid_t cad;
3320
3321 hdac_lock(sc);
3322
3323 mask = 0;
3324 recmask = 0;
3325
3326 id = hdac_codec_id(devinfo);
3327 cad = devinfo->codec->cad;
3328 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) {
3329 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model,
4886ec58 3330 sc->pci_subvendor) && hdac_hp_switch[i].id == id))
558a398b
SS
3331 continue;
3332 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
4886ec58
HT
3333 if (w == NULL || w->enable == 0 || w->type !=
3334 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
3335 continue;
3336 if (hdac_hp_switch[i].polling != 0)
3337 callout_reset(&sc->poll_jack, 1,
3338 hdac_jack_poll_callback, devinfo);
3339 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap))
558a398b 3340 hdac_command(sc,
4886ec58
HT
3341 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid,
3342 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE |
558a398b 3343 HDAC_UNSOLTAG_EVENT_HP), cad);
4886ec58
HT
3344 else
3345 continue;
3346 hdac_hp_switch_handler(devinfo);
3347 HDA_BOOTVERBOSE(
3348 device_printf(sc->dev,
3349 "HDA_DEBUG: Enabling headphone/speaker "
3350 "audio routing switching:\n");
3351 device_printf(sc->dev,
3352 "HDA_DEBUG: \tindex=%d nid=%d "
3353 "pci_subvendor=0x%08x "
3354 "codec=0x%08x [%s]\n",
3355 i, w->nid, sc->pci_subvendor, id,
3356 (hdac_hp_switch[i].polling != 0) ? "POLL" :
3357 "UNSOL");
3358 );
558a398b
SS
3359 break;
3360 }
3361 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) {
3362 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model,
3363 sc->pci_subvendor) &&
3364 hdac_eapd_switch[i].id == id))
3365 continue;
3366 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid);
3367 if (w == NULL || w->enable == 0)
3368 break;
3369 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3370 w->param.eapdbtl == HDAC_INVALID)
3371 break;
3372 mask |= SOUND_MASK_OGAIN;
3373 break;
3374 }
3375
3376 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3377 w = hdac_widget_get(devinfo, i);
3378 if (w == NULL || w->enable == 0)
3379 continue;
3380 mask |= w->ctlflags;
3381 if (!(w->pflags & HDA_ADC_RECSEL))
3382 continue;
3383 for (j = 0; j < w->nconns; j++) {
3384 cw = hdac_widget_get(devinfo, w->conns[j]);
3385 if (cw == NULL || cw->enable == 0)
3386 continue;
3387 recmask |= cw->ctlflags;
3388 }
3389 }
3390
3391 if (!(mask & SOUND_MASK_PCM)) {
3392 softpcmvol = 1;
3393 mask |= SOUND_MASK_PCM;
3394 } else
3395 softpcmvol = (devinfo->function.audio.quirks &
3396 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0;
3397
3398 i = 0;
3399 ctl = NULL;
3400 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3401 if (ctl->widget == NULL || ctl->enable == 0)
3402 continue;
3403 if (!(ctl->ossmask & SOUND_MASK_PCM))
3404 continue;
3405 if (ctl->step > 0)
3406 break;
3407 }
3408
3409 if (softpcmvol == 1 || ctl == NULL) {
4886ec58
HT
3410 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL);
3411 HDA_BOOTVERBOSE(
3412 device_printf(sc->dev,
3413 "HDA_DEBUG: %s Soft PCM volume\n",
3414 (softpcmvol == 1) ?
3415 "Forcing" : "Enabling");
3416 );
558a398b
SS
3417 i = 0;
3418 /*
3419 * XXX Temporary quirk for STAC9220, until the parser
3420 * become smarter.
3421 */
3422 if (id == HDA_CODEC_STAC9220) {
3423 mask |= SOUND_MASK_VOLUME;
3424 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3425 NULL) {
3426 if (ctl->widget == NULL || ctl->enable == 0)
3427 continue;
3428 if (ctl->widget->nid == 11 && ctl->index == 0) {
3429 ctl->ossmask = SOUND_MASK_VOLUME;
3430 ctl->ossval = 100 | (100 << 8);
3431 } else
3432 ctl->ossmask &= ~SOUND_MASK_VOLUME;
3433 }
4886ec58
HT
3434 } else if (id == HDA_CODEC_STAC9221) {
3435 mask |= SOUND_MASK_VOLUME;
3436 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3437 NULL) {
3438 if (ctl->widget == NULL)
3439 continue;
3440 if (ctl->widget->type ==
3441 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT &&
3442 ctl->index == 0 && (ctl->widget->nid == 2 ||
3443 ctl->widget->enable != 0)) {
3444 ctl->enable = 1;
3445 ctl->ossmask = SOUND_MASK_VOLUME;
3446 ctl->ossval = 100 | (100 << 8);
3447 } else if (ctl->enable == 0)
3448 continue;
3449 else
3450 ctl->ossmask &= ~SOUND_MASK_VOLUME;
3451 }
558a398b
SS
3452 } else {
3453 mix_setparentchild(m, SOUND_MIXER_VOLUME,
3454 SOUND_MASK_PCM);
3455 if (!(mask & SOUND_MASK_VOLUME))
3456 mix_setrealdev(m, SOUND_MIXER_VOLUME,
3457 SOUND_MIXER_NONE);
3458 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3459 NULL) {
3460 if (ctl->widget == NULL || ctl->enable == 0)
3461 continue;
3462 if (!HDA_FLAG_MATCH(ctl->ossmask,
3463 SOUND_MASK_VOLUME | SOUND_MASK_PCM))
3464 continue;
3465 if (!(ctl->mute == 1 && ctl->step == 0))
3466 ctl->enable = 0;
3467 }
3468 }
558a398b
SS
3469 }
3470
4886ec58
HT
3471 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER |
3472 SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN |
3473 SOUND_MASK_OGAIN);
3474 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3475 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
558a398b
SS
3476
3477 mix_setrecdevs(m, recmask);
3478 mix_setdevs(m, mask);
3479
3480 hdac_unlock(sc);
3481
3482 return (0);
3483}
3484
3485static int
3486hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev,
3487 unsigned left, unsigned right)
3488{
3489 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3490 struct hdac_softc *sc = devinfo->codec->sc;
3491 struct hdac_widget *w;
3492 struct hdac_audio_ctl *ctl;
3493 uint32_t id, mute;
3494 int lvol, rvol, mlvol, mrvol;
3495 int i = 0;
3496
3497 hdac_lock(sc);
3498 if (dev == SOUND_MIXER_OGAIN) {
3499 uint32_t orig;
3500 /*if (left != right || !(left == 0 || left == 1)) {
3501 hdac_unlock(sc);
3502 return (-1);
3503 }*/
3504 id = hdac_codec_id(devinfo);
3505 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) {
3506 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model,
3507 sc->pci_subvendor) &&
3508 hdac_eapd_switch[i].id == id)
3509 break;
3510 }
3511 if (i >= HDAC_EAPD_SWITCH_LEN) {
3512 hdac_unlock(sc);
3513 return (-1);
3514 }
3515 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid);
3516 if (w == NULL ||
3517 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3518 w->param.eapdbtl == HDAC_INVALID) {
3519 hdac_unlock(sc);
3520 return (-1);
3521 }
3522 orig = w->param.eapdbtl;
3523 if (left == 0)
3524 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3525 else
3526 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3527 if (orig != w->param.eapdbtl) {
4886ec58
HT
3528 uint32_t val;
3529
558a398b
SS
3530 if (hdac_eapd_switch[i].hp_switch != 0)
3531 hdac_hp_switch_handler(devinfo);
4886ec58
HT
3532 val = w->param.eapdbtl;
3533 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV)
3534 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
558a398b
SS
3535 hdac_command(sc,
3536 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad,
4886ec58 3537 w->nid, val), devinfo->codec->cad);
558a398b
SS
3538 }
3539 hdac_unlock(sc);
3540 return (left | (left << 8));
3541 }
3542 if (dev == SOUND_MIXER_VOLUME)
3543 devinfo->function.audio.mvol = left | (right << 8);
3544
3545 mlvol = devinfo->function.audio.mvol & 0x7f;
3546 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f;
3547 lvol = 0;
3548 rvol = 0;
3549
3550 i = 0;
3551 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3552 if (ctl->widget == NULL || ctl->enable == 0 ||
3553 !(ctl->ossmask & (1 << dev)))
3554 continue;
3555 switch (dev) {
3556 case SOUND_MIXER_VOLUME:
3557 lvol = ((ctl->ossval & 0x7f) * left) / 100;
3558 lvol = (lvol * ctl->step) / 100;
3559 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100;
3560 rvol = (rvol * ctl->step) / 100;
3561 break;
3562 default:
3563 if (ctl->ossmask & SOUND_MASK_VOLUME) {
3564 lvol = (left * mlvol) / 100;
3565 lvol = (lvol * ctl->step) / 100;
3566 rvol = (right * mrvol) / 100;
3567 rvol = (rvol * ctl->step) / 100;
3568 } else {
3569 lvol = (left * ctl->step) / 100;
3570 rvol = (right * ctl->step) / 100;
3571 }
3572 ctl->ossval = left | (right << 8);
3573 break;
3574 }
3575 mute = 0;
3576 if (ctl->step < 1) {
3577 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT :
3578 (ctl->muted & HDA_AMP_MUTE_LEFT);
3579 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT :
3580 (ctl->muted & HDA_AMP_MUTE_RIGHT);
3581 } else {
3582 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT :
3583 (ctl->muted & HDA_AMP_MUTE_LEFT);
3584 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT :
3585 (ctl->muted & HDA_AMP_MUTE_RIGHT);
3586 }
3587 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol);
3588 }
3589 hdac_unlock(sc);
3590
3591 return (left | (right << 8));
3592}
3593
3594static int
3595hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src)
3596{
3597 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3598 struct hdac_widget *w, *cw;
3599 struct hdac_softc *sc = devinfo->codec->sc;
3600 uint32_t ret = src, target;
3601 int i, j;
3602
3603 target = 0;
3604 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
3605 if (src & (1 << i)) {
3606 target = 1 << i;
3607 break;
3608 }
3609 }
3610
3611 hdac_lock(sc);
3612
3613 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3614 w = hdac_widget_get(devinfo, i);
3615 if (w == NULL || w->enable == 0)
3616 continue;
3617 if (!(w->pflags & HDA_ADC_RECSEL))
3618 continue;
3619 for (j = 0; j < w->nconns; j++) {
3620 cw = hdac_widget_get(devinfo, w->conns[j]);
3621 if (cw == NULL || cw->enable == 0)
3622 continue;
3623 if ((target == SOUND_MASK_VOLUME &&
3624 cw->type !=
3625 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) ||
3626 (target != SOUND_MASK_VOLUME &&
3627 cw->type ==
3628 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER))
3629 continue;
3630 if (cw->ctlflags & target) {
4886ec58
HT
3631 if (!(w->pflags & HDA_ADC_LOCKED))
3632 hdac_widget_connection_select(w, j);
558a398b
SS
3633 ret = target;
3634 j += w->nconns;
3635 }
3636 }
3637 }
3638
3639 hdac_unlock(sc);
3640
3641 return (ret);
3642}
3643
3644static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = {
3645 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init),
3646 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set),
3647 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc),
3648 { 0, 0 }
3649};
3650MIXER_DECLARE(hdac_audio_ctl_ossmixer);
3651
19c72e40
HT
3652static void
3653hdac_unsolq_task(void *context, int pending)
3654{
3655 struct hdac_softc *sc;
3656
3657 sc = (struct hdac_softc *)context;
3658
3659 hdac_lock(sc);
3660 hdac_unsolq_flush(sc);
3661 hdac_unlock(sc);
3662}
3663
558a398b
SS
3664/****************************************************************************
3665 * int hdac_attach(device_t)
3666 *
3667 * Attach the device into the kernel. Interrupts usually won't be enabled
3668 * when this function is called. Setup everything that doesn't require
3669 * interrupts and defer probing of codecs until interrupts are enabled.
3670 ****************************************************************************/
3671static int
3672hdac_attach(device_t dev)
3673{
3674 struct hdac_softc *sc;
3675 int result;
4886ec58
HT
3676 int i;
3677 uint16_t vendor;
3678 uint8_t v;
558a398b 3679
ac1bf0d0 3680 sc = kmalloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
558a398b 3681 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME);
558a398b
SS
3682 sc->dev = dev;
3683 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16;
3684 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff;
4886ec58
HT
3685 vendor = pci_get_vendor(dev);
3686
3687 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) {
3688 /* Screw nx6325 - subdevice/subvendor swapped */
3689 sc->pci_subvendor = HP_NX6325_SUBVENDOR;
3690 }
3691
3692 callout_init(&sc->poll_hda);
3693 callout_init(&sc->poll_hdac);
3694 callout_init(&sc->poll_jack);
3695
19c72e40
HT
3696 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc);
3697
4886ec58
HT
3698 sc->poll_ticks = 1;
3699 sc->poll_ival = HDAC_POLL_INTERVAL;
3700 if (resource_int_value(device_get_name(dev),
3701 device_get_unit(dev), "polling", &i) == 0 && i != 0)
3702 sc->polling = 1;
3703 else
3704 sc->polling = 0;
558a398b
SS
3705
3706 sc->chan_size = pcm_getbuffersize(dev,
4886ec58
HT
3707 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX);
3708
3709 if (resource_int_value(device_get_name(dev),
3710 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) {
3711 i &= HDA_BLK_ALIGN;
3712 if (i < HDA_BLK_MIN)
3713 i = HDA_BLK_MIN;
558a398b
SS
3714 sc->chan_blkcnt = sc->chan_size / i;
3715 i = 0;
3716 while (sc->chan_blkcnt >> i)
3717 i++;
3718 sc->chan_blkcnt = 1 << (i - 1);
3719 if (sc->chan_blkcnt < HDA_BDL_MIN)
3720 sc->chan_blkcnt = HDA_BDL_MIN;
3721 else if (sc->chan_blkcnt > HDA_BDL_MAX)
3722 sc->chan_blkcnt = HDA_BDL_MAX;
3723 } else
3724 sc->chan_blkcnt = HDA_BDL_DEFAULT;
3725
3726 result = bus_dma_tag_create(NULL, /* parent */
3727 HDAC_DMA_ALIGNMENT, /* alignment */
3728 0, /* boundary */
3729 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
3730 BUS_SPACE_MAXADDR, /* highaddr */
3731 NULL, /* filtfunc */
3732 NULL, /* fistfuncarg */
4886ec58 3733 sc->chan_size, /* maxsize */
558a398b 3734 1, /* nsegments */
4886ec58 3735 sc->chan_size, /* maxsegsz */
558a398b
SS
3736 0, /* flags */
3737 &sc->chan_dmat); /* dmat */
3738 if (result != 0) {
4886ec58 3739 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n",
558a398b
SS
3740 __func__, result);
3741 snd_mtxfree(sc->lock);
3742 kfree(sc, M_DEVBUF);
3743 return (ENXIO);
3744 }
3745
3746
3747 sc->hdabus = NULL;
3748 for (i = 0; i < HDAC_CODEC_MAX; i++)
3749 sc->codecs[i] = NULL;
3750
3751 pci_enable_busmaster(dev);
3752
4886ec58
HT
3753 if (vendor == INTEL_VENDORID) {
3754 /* TCSEL -> TC0 */
3755 v = pci_read_config(dev, 0x44, 1);
3756 pci_write_config(dev, 0x44, v & 0xf8, 1);
3757 HDA_BOOTVERBOSE(
3758 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v,
3759 pci_read_config(dev, 0x44, 1));
3760 );
3761 }
6ef811ff
HT
3762#if 0 /* TODO: No MSI support yet in DragonFly. */
3763 if (resource_int_value(device_get_name(dev),
3764 device_get_unit(dev), "msi", &i) == 0 && i != 0 &&
3765 pci_msi_count(dev) == 1)
3766 sc->flags |= HDAC_F_MSI;
3767 else
3768#endif
3769 sc->flags &= ~HDAC_F_MSI;
4886ec58
HT
3770
3771#if 0 /* TODO: No uncacheable DMA support in DragonFly. */
6ef811ff 3772 sc->flags |= HDAC_F_DMA_NOCACHE;
4886ec58
HT
3773
3774 if (resource_int_value(device_get_name(dev),
3775 device_get_unit(dev), "snoop", &i) == 0 && i != 0) {
3776#else
6ef811ff 3777 sc->flags &= ~HDAC_F_DMA_NOCACHE;
4886ec58
HT
3778#endif
3779 /*
3780 * Try to enable PCIe snoop to avoid messing around with
3781 * uncacheable DMA attribute. Since PCIe snoop register
3782 * config is pretty much vendor specific, there are no
3783 * general solutions on how to enable it, forcing us (even
3784 * Microsoft) to enable uncacheable or write combined DMA
3785 * by default.
3786 *
3787 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx
3788 */
3789 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) {
3790 if (hdac_pcie_snoop[i].vendor != vendor)
3791 continue;
6ef811ff