drm/linux: Improve request_firmware() compatibility
[dragonfly.git] / sys / dev / drm / radeon / cik.c
CommitLineData
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1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
57e252bf 24#include <linux/firmware.h>
fcd4983f 25#include <linux/module.h>
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26#include <drm/drmP.h>
27#include "radeon.h"
28#include "radeon_asic.h"
29#include "cikd.h"
30#include "atom.h"
31#include "cik_blit_shaders.h"
4cd92098 32#include "radeon_ucode.h"
33#include "clearstate_ci.h"
57e252bf 34
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35MODULE_FIRMWARE("radeon/BONAIRE_pfp.bin");
36MODULE_FIRMWARE("radeon/BONAIRE_me.bin");
37MODULE_FIRMWARE("radeon/BONAIRE_ce.bin");
38MODULE_FIRMWARE("radeon/BONAIRE_mec.bin");
39MODULE_FIRMWARE("radeon/BONAIRE_mc.bin");
c6f73aab 40MODULE_FIRMWARE("radeon/BONAIRE_mc2.bin");
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41MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin");
42MODULE_FIRMWARE("radeon/BONAIRE_sdma.bin");
4cd92098 43MODULE_FIRMWARE("radeon/BONAIRE_smc.bin");
cb754608
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44
45MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
46MODULE_FIRMWARE("radeon/bonaire_me.bin");
47MODULE_FIRMWARE("radeon/bonaire_ce.bin");
48MODULE_FIRMWARE("radeon/bonaire_mec.bin");
49MODULE_FIRMWARE("radeon/bonaire_mc.bin");
50MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
51MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
52MODULE_FIRMWARE("radeon/bonaire_smc.bin");
53
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54MODULE_FIRMWARE("radeon/HAWAII_pfp.bin");
55MODULE_FIRMWARE("radeon/HAWAII_me.bin");
56MODULE_FIRMWARE("radeon/HAWAII_ce.bin");
57MODULE_FIRMWARE("radeon/HAWAII_mec.bin");
58MODULE_FIRMWARE("radeon/HAWAII_mc.bin");
59MODULE_FIRMWARE("radeon/HAWAII_mc2.bin");
60MODULE_FIRMWARE("radeon/HAWAII_rlc.bin");
61MODULE_FIRMWARE("radeon/HAWAII_sdma.bin");
62MODULE_FIRMWARE("radeon/HAWAII_smc.bin");
cb754608
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63
64MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
65MODULE_FIRMWARE("radeon/hawaii_me.bin");
66MODULE_FIRMWARE("radeon/hawaii_ce.bin");
67MODULE_FIRMWARE("radeon/hawaii_mec.bin");
68MODULE_FIRMWARE("radeon/hawaii_mc.bin");
69MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
70MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
71MODULE_FIRMWARE("radeon/hawaii_smc.bin");
72
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73MODULE_FIRMWARE("radeon/KAVERI_pfp.bin");
74MODULE_FIRMWARE("radeon/KAVERI_me.bin");
75MODULE_FIRMWARE("radeon/KAVERI_ce.bin");
76MODULE_FIRMWARE("radeon/KAVERI_mec.bin");
77MODULE_FIRMWARE("radeon/KAVERI_rlc.bin");
78MODULE_FIRMWARE("radeon/KAVERI_sdma.bin");
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79
80MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
81MODULE_FIRMWARE("radeon/kaveri_me.bin");
82MODULE_FIRMWARE("radeon/kaveri_ce.bin");
83MODULE_FIRMWARE("radeon/kaveri_mec.bin");
84MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
85MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
86MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
87
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88MODULE_FIRMWARE("radeon/KABINI_pfp.bin");
89MODULE_FIRMWARE("radeon/KABINI_me.bin");
90MODULE_FIRMWARE("radeon/KABINI_ce.bin");
91MODULE_FIRMWARE("radeon/KABINI_mec.bin");
92MODULE_FIRMWARE("radeon/KABINI_rlc.bin");
93MODULE_FIRMWARE("radeon/KABINI_sdma.bin");
cb754608
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94
95MODULE_FIRMWARE("radeon/kabini_pfp.bin");
96MODULE_FIRMWARE("radeon/kabini_me.bin");
97MODULE_FIRMWARE("radeon/kabini_ce.bin");
98MODULE_FIRMWARE("radeon/kabini_mec.bin");
99MODULE_FIRMWARE("radeon/kabini_rlc.bin");
100MODULE_FIRMWARE("radeon/kabini_sdma.bin");
101
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102MODULE_FIRMWARE("radeon/MULLINS_pfp.bin");
103MODULE_FIRMWARE("radeon/MULLINS_me.bin");
104MODULE_FIRMWARE("radeon/MULLINS_ce.bin");
105MODULE_FIRMWARE("radeon/MULLINS_mec.bin");
106MODULE_FIRMWARE("radeon/MULLINS_rlc.bin");
107MODULE_FIRMWARE("radeon/MULLINS_sdma.bin");
108
cb754608
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109MODULE_FIRMWARE("radeon/mullins_pfp.bin");
110MODULE_FIRMWARE("radeon/mullins_me.bin");
111MODULE_FIRMWARE("radeon/mullins_ce.bin");
112MODULE_FIRMWARE("radeon/mullins_mec.bin");
113MODULE_FIRMWARE("radeon/mullins_rlc.bin");
114MODULE_FIRMWARE("radeon/mullins_sdma.bin");
115
c6f73aab 116static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh);
57e252bf 117static void cik_rlc_stop(struct radeon_device *rdev);
4cd92098 118static void cik_pcie_gen3_enable(struct radeon_device *rdev);
119static void cik_program_aspm(struct radeon_device *rdev);
120static void cik_init_pg(struct radeon_device *rdev);
121static void cik_init_cg(struct radeon_device *rdev);
122static void cik_fini_pg(struct radeon_device *rdev);
123static void cik_fini_cg(struct radeon_device *rdev);
124static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
125 bool enable);
126
127/* get temperature in millidegrees */
128int ci_get_temp(struct radeon_device *rdev)
129{
130 u32 temp;
131 int actual_temp = 0;
132
133 temp = (RREG32_SMC(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
134 CTF_TEMP_SHIFT;
135
136 if (temp & 0x200)
137 actual_temp = 255;
138 else
139 actual_temp = temp & 0x1ff;
140
141 actual_temp = actual_temp * 1000;
142
143 return actual_temp;
144}
145
146/* get temperature in millidegrees */
147int kv_get_temp(struct radeon_device *rdev)
148{
149 u32 temp;
150 int actual_temp = 0;
151
152 temp = RREG32_SMC(0xC0300E0C);
153
154 if (temp)
155 actual_temp = (temp / 8) - 49;
156 else
157 actual_temp = 0;
158
159 actual_temp = actual_temp * 1000;
160
161 return actual_temp;
162}
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163
164/*
165 * Indirect registers accessor
166 */
167u32 cik_pciep_rreg(struct radeon_device *rdev, u32 reg)
168{
169 u32 r;
170
c6f73aab 171 spin_lock(&rdev->pciep_idx_lock);
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172 WREG32(PCIE_INDEX, reg);
173 (void)RREG32(PCIE_INDEX);
174 r = RREG32(PCIE_DATA);
c6f73aab 175 spin_unlock(&rdev->pciep_idx_lock);
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176 return r;
177}
178
179void cik_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
180{
c6f73aab 181 spin_lock(&rdev->pciep_idx_lock);
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182 WREG32(PCIE_INDEX, reg);
183 (void)RREG32(PCIE_INDEX);
184 WREG32(PCIE_DATA, v);
185 (void)RREG32(PCIE_DATA);
c6f73aab 186 spin_unlock(&rdev->pciep_idx_lock);
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187}
188
4cd92098 189static const u32 spectre_rlc_save_restore_register_list[] =
190{
191 (0x0e00 << 16) | (0xc12c >> 2),
192 0x00000000,
193 (0x0e00 << 16) | (0xc140 >> 2),
194 0x00000000,
195 (0x0e00 << 16) | (0xc150 >> 2),
196 0x00000000,
197 (0x0e00 << 16) | (0xc15c >> 2),
198 0x00000000,
199 (0x0e00 << 16) | (0xc168 >> 2),
200 0x00000000,
201 (0x0e00 << 16) | (0xc170 >> 2),
202 0x00000000,
203 (0x0e00 << 16) | (0xc178 >> 2),
204 0x00000000,
205 (0x0e00 << 16) | (0xc204 >> 2),
206 0x00000000,
207 (0x0e00 << 16) | (0xc2b4 >> 2),
208 0x00000000,
209 (0x0e00 << 16) | (0xc2b8 >> 2),
210 0x00000000,
211 (0x0e00 << 16) | (0xc2bc >> 2),
212 0x00000000,
213 (0x0e00 << 16) | (0xc2c0 >> 2),
214 0x00000000,
215 (0x0e00 << 16) | (0x8228 >> 2),
216 0x00000000,
217 (0x0e00 << 16) | (0x829c >> 2),
218 0x00000000,
219 (0x0e00 << 16) | (0x869c >> 2),
220 0x00000000,
221 (0x0600 << 16) | (0x98f4 >> 2),
222 0x00000000,
223 (0x0e00 << 16) | (0x98f8 >> 2),
224 0x00000000,
225 (0x0e00 << 16) | (0x9900 >> 2),
226 0x00000000,
227 (0x0e00 << 16) | (0xc260 >> 2),
228 0x00000000,
229 (0x0e00 << 16) | (0x90e8 >> 2),
230 0x00000000,
231 (0x0e00 << 16) | (0x3c000 >> 2),
232 0x00000000,
233 (0x0e00 << 16) | (0x3c00c >> 2),
234 0x00000000,
235 (0x0e00 << 16) | (0x8c1c >> 2),
236 0x00000000,
237 (0x0e00 << 16) | (0x9700 >> 2),
238 0x00000000,
239 (0x0e00 << 16) | (0xcd20 >> 2),
240 0x00000000,
241 (0x4e00 << 16) | (0xcd20 >> 2),
242 0x00000000,
243 (0x5e00 << 16) | (0xcd20 >> 2),
244 0x00000000,
245 (0x6e00 << 16) | (0xcd20 >> 2),
246 0x00000000,
247 (0x7e00 << 16) | (0xcd20 >> 2),
248 0x00000000,
249 (0x8e00 << 16) | (0xcd20 >> 2),
250 0x00000000,
251 (0x9e00 << 16) | (0xcd20 >> 2),
252 0x00000000,
253 (0xae00 << 16) | (0xcd20 >> 2),
254 0x00000000,
255 (0xbe00 << 16) | (0xcd20 >> 2),
256 0x00000000,
257 (0x0e00 << 16) | (0x89bc >> 2),
258 0x00000000,
259 (0x0e00 << 16) | (0x8900 >> 2),
260 0x00000000,
261 0x3,
262 (0x0e00 << 16) | (0xc130 >> 2),
263 0x00000000,
264 (0x0e00 << 16) | (0xc134 >> 2),
265 0x00000000,
266 (0x0e00 << 16) | (0xc1fc >> 2),
267 0x00000000,
268 (0x0e00 << 16) | (0xc208 >> 2),
269 0x00000000,
270 (0x0e00 << 16) | (0xc264 >> 2),
271 0x00000000,
272 (0x0e00 << 16) | (0xc268 >> 2),
273 0x00000000,
274 (0x0e00 << 16) | (0xc26c >> 2),
275 0x00000000,
276 (0x0e00 << 16) | (0xc270 >> 2),
277 0x00000000,
278 (0x0e00 << 16) | (0xc274 >> 2),
279 0x00000000,
280 (0x0e00 << 16) | (0xc278 >> 2),
281 0x00000000,
282 (0x0e00 << 16) | (0xc27c >> 2),
283 0x00000000,
284 (0x0e00 << 16) | (0xc280 >> 2),
285 0x00000000,
286 (0x0e00 << 16) | (0xc284 >> 2),
287 0x00000000,
288 (0x0e00 << 16) | (0xc288 >> 2),
289 0x00000000,
290 (0x0e00 << 16) | (0xc28c >> 2),
291 0x00000000,
292 (0x0e00 << 16) | (0xc290 >> 2),
293 0x00000000,
294 (0x0e00 << 16) | (0xc294 >> 2),
295 0x00000000,
296 (0x0e00 << 16) | (0xc298 >> 2),
297 0x00000000,
298 (0x0e00 << 16) | (0xc29c >> 2),
299 0x00000000,
300 (0x0e00 << 16) | (0xc2a0 >> 2),
301 0x00000000,
302 (0x0e00 << 16) | (0xc2a4 >> 2),
303 0x00000000,
304 (0x0e00 << 16) | (0xc2a8 >> 2),
305 0x00000000,
306 (0x0e00 << 16) | (0xc2ac >> 2),
307 0x00000000,
308 (0x0e00 << 16) | (0xc2b0 >> 2),
309 0x00000000,
310 (0x0e00 << 16) | (0x301d0 >> 2),
311 0x00000000,
312 (0x0e00 << 16) | (0x30238 >> 2),
313 0x00000000,
314 (0x0e00 << 16) | (0x30250 >> 2),
315 0x00000000,
316 (0x0e00 << 16) | (0x30254 >> 2),
317 0x00000000,
318 (0x0e00 << 16) | (0x30258 >> 2),
319 0x00000000,
320 (0x0e00 << 16) | (0x3025c >> 2),
321 0x00000000,
322 (0x4e00 << 16) | (0xc900 >> 2),
323 0x00000000,
324 (0x5e00 << 16) | (0xc900 >> 2),
325 0x00000000,
326 (0x6e00 << 16) | (0xc900 >> 2),
327 0x00000000,
328 (0x7e00 << 16) | (0xc900 >> 2),
329 0x00000000,
330 (0x8e00 << 16) | (0xc900 >> 2),
331 0x00000000,
332 (0x9e00 << 16) | (0xc900 >> 2),
333 0x00000000,
334 (0xae00 << 16) | (0xc900 >> 2),
335 0x00000000,
336 (0xbe00 << 16) | (0xc900 >> 2),
337 0x00000000,
338 (0x4e00 << 16) | (0xc904 >> 2),
339 0x00000000,
340 (0x5e00 << 16) | (0xc904 >> 2),
341 0x00000000,
342 (0x6e00 << 16) | (0xc904 >> 2),
343 0x00000000,
344 (0x7e00 << 16) | (0xc904 >> 2),
345 0x00000000,
346 (0x8e00 << 16) | (0xc904 >> 2),
347 0x00000000,
348 (0x9e00 << 16) | (0xc904 >> 2),
349 0x00000000,
350 (0xae00 << 16) | (0xc904 >> 2),
351 0x00000000,
352 (0xbe00 << 16) | (0xc904 >> 2),
353 0x00000000,
354 (0x4e00 << 16) | (0xc908 >> 2),
355 0x00000000,
356 (0x5e00 << 16) | (0xc908 >> 2),
357 0x00000000,
358 (0x6e00 << 16) | (0xc908 >> 2),
359 0x00000000,
360 (0x7e00 << 16) | (0xc908 >> 2),
361 0x00000000,
362 (0x8e00 << 16) | (0xc908 >> 2),
363 0x00000000,
364 (0x9e00 << 16) | (0xc908 >> 2),
365 0x00000000,
366 (0xae00 << 16) | (0xc908 >> 2),
367 0x00000000,
368 (0xbe00 << 16) | (0xc908 >> 2),
369 0x00000000,
370 (0x4e00 << 16) | (0xc90c >> 2),
371 0x00000000,
372 (0x5e00 << 16) | (0xc90c >> 2),
373 0x00000000,
374 (0x6e00 << 16) | (0xc90c >> 2),
375 0x00000000,
376 (0x7e00 << 16) | (0xc90c >> 2),
377 0x00000000,
378 (0x8e00 << 16) | (0xc90c >> 2),
379 0x00000000,
380 (0x9e00 << 16) | (0xc90c >> 2),
381 0x00000000,
382 (0xae00 << 16) | (0xc90c >> 2),
383 0x00000000,
384 (0xbe00 << 16) | (0xc90c >> 2),
385 0x00000000,
386 (0x4e00 << 16) | (0xc910 >> 2),
387 0x00000000,
388 (0x5e00 << 16) | (0xc910 >> 2),
389 0x00000000,
390 (0x6e00 << 16) | (0xc910 >> 2),
391 0x00000000,
392 (0x7e00 << 16) | (0xc910 >> 2),
393 0x00000000,
394 (0x8e00 << 16) | (0xc910 >> 2),
395 0x00000000,
396 (0x9e00 << 16) | (0xc910 >> 2),
397 0x00000000,
398 (0xae00 << 16) | (0xc910 >> 2),
399 0x00000000,
400 (0xbe00 << 16) | (0xc910 >> 2),
401 0x00000000,
402 (0x0e00 << 16) | (0xc99c >> 2),
403 0x00000000,
404 (0x0e00 << 16) | (0x9834 >> 2),
405 0x00000000,
406 (0x0000 << 16) | (0x30f00 >> 2),
407 0x00000000,
408 (0x0001 << 16) | (0x30f00 >> 2),
409 0x00000000,
410 (0x0000 << 16) | (0x30f04 >> 2),
411 0x00000000,
412 (0x0001 << 16) | (0x30f04 >> 2),
413 0x00000000,
414 (0x0000 << 16) | (0x30f08 >> 2),
415 0x00000000,
416 (0x0001 << 16) | (0x30f08 >> 2),
417 0x00000000,
418 (0x0000 << 16) | (0x30f0c >> 2),
419 0x00000000,
420 (0x0001 << 16) | (0x30f0c >> 2),
421 0x00000000,
422 (0x0600 << 16) | (0x9b7c >> 2),
423 0x00000000,
424 (0x0e00 << 16) | (0x8a14 >> 2),
425 0x00000000,
426 (0x0e00 << 16) | (0x8a18 >> 2),
427 0x00000000,
428 (0x0600 << 16) | (0x30a00 >> 2),
429 0x00000000,
430 (0x0e00 << 16) | (0x8bf0 >> 2),
431 0x00000000,
432 (0x0e00 << 16) | (0x8bcc >> 2),
433 0x00000000,
434 (0x0e00 << 16) | (0x8b24 >> 2),
435 0x00000000,
436 (0x0e00 << 16) | (0x30a04 >> 2),
437 0x00000000,
438 (0x0600 << 16) | (0x30a10 >> 2),
439 0x00000000,
440 (0x0600 << 16) | (0x30a14 >> 2),
441 0x00000000,
442 (0x0600 << 16) | (0x30a18 >> 2),
443 0x00000000,
444 (0x0600 << 16) | (0x30a2c >> 2),
445 0x00000000,
446 (0x0e00 << 16) | (0xc700 >> 2),
447 0x00000000,
448 (0x0e00 << 16) | (0xc704 >> 2),
449 0x00000000,
450 (0x0e00 << 16) | (0xc708 >> 2),
451 0x00000000,
452 (0x0e00 << 16) | (0xc768 >> 2),
453 0x00000000,
454 (0x0400 << 16) | (0xc770 >> 2),
455 0x00000000,
456 (0x0400 << 16) | (0xc774 >> 2),
457 0x00000000,
458 (0x0400 << 16) | (0xc778 >> 2),
459 0x00000000,
460 (0x0400 << 16) | (0xc77c >> 2),
461 0x00000000,
462 (0x0400 << 16) | (0xc780 >> 2),
463 0x00000000,
464 (0x0400 << 16) | (0xc784 >> 2),
465 0x00000000,
466 (0x0400 << 16) | (0xc788 >> 2),
467 0x00000000,
468 (0x0400 << 16) | (0xc78c >> 2),
469 0x00000000,
470 (0x0400 << 16) | (0xc798 >> 2),
471 0x00000000,
472 (0x0400 << 16) | (0xc79c >> 2),
473 0x00000000,
474 (0x0400 << 16) | (0xc7a0 >> 2),
475 0x00000000,
476 (0x0400 << 16) | (0xc7a4 >> 2),
477 0x00000000,
478 (0x0400 << 16) | (0xc7a8 >> 2),
479 0x00000000,
480 (0x0400 << 16) | (0xc7ac >> 2),
481 0x00000000,
482 (0x0400 << 16) | (0xc7b0 >> 2),
483 0x00000000,
484 (0x0400 << 16) | (0xc7b4 >> 2),
485 0x00000000,
486 (0x0e00 << 16) | (0x9100 >> 2),
487 0x00000000,
488 (0x0e00 << 16) | (0x3c010 >> 2),
489 0x00000000,
490 (0x0e00 << 16) | (0x92a8 >> 2),
491 0x00000000,
492 (0x0e00 << 16) | (0x92ac >> 2),
493 0x00000000,
494 (0x0e00 << 16) | (0x92b4 >> 2),
495 0x00000000,
496 (0x0e00 << 16) | (0x92b8 >> 2),
497 0x00000000,
498 (0x0e00 << 16) | (0x92bc >> 2),
499 0x00000000,
500 (0x0e00 << 16) | (0x92c0 >> 2),
501 0x00000000,
502 (0x0e00 << 16) | (0x92c4 >> 2),
503 0x00000000,
504 (0x0e00 << 16) | (0x92c8 >> 2),
505 0x00000000,
506 (0x0e00 << 16) | (0x92cc >> 2),
507 0x00000000,
508 (0x0e00 << 16) | (0x92d0 >> 2),
509 0x00000000,
510 (0x0e00 << 16) | (0x8c00 >> 2),
511 0x00000000,
512 (0x0e00 << 16) | (0x8c04 >> 2),
513 0x00000000,
514 (0x0e00 << 16) | (0x8c20 >> 2),
515 0x00000000,
516 (0x0e00 << 16) | (0x8c38 >> 2),
517 0x00000000,
518 (0x0e00 << 16) | (0x8c3c >> 2),
519 0x00000000,
520 (0x0e00 << 16) | (0xae00 >> 2),
521 0x00000000,
522 (0x0e00 << 16) | (0x9604 >> 2),
523 0x00000000,
524 (0x0e00 << 16) | (0xac08 >> 2),
525 0x00000000,
526 (0x0e00 << 16) | (0xac0c >> 2),
527 0x00000000,
528 (0x0e00 << 16) | (0xac10 >> 2),
529 0x00000000,
530 (0x0e00 << 16) | (0xac14 >> 2),
531 0x00000000,
532 (0x0e00 << 16) | (0xac58 >> 2),
533 0x00000000,
534 (0x0e00 << 16) | (0xac68 >> 2),
535 0x00000000,
536 (0x0e00 << 16) | (0xac6c >> 2),
537 0x00000000,
538 (0x0e00 << 16) | (0xac70 >> 2),
539 0x00000000,
540 (0x0e00 << 16) | (0xac74 >> 2),
541 0x00000000,
542 (0x0e00 << 16) | (0xac78 >> 2),
543 0x00000000,
544 (0x0e00 << 16) | (0xac7c >> 2),
545 0x00000000,
546 (0x0e00 << 16) | (0xac80 >> 2),
547 0x00000000,
548 (0x0e00 << 16) | (0xac84 >> 2),
549 0x00000000,
550 (0x0e00 << 16) | (0xac88 >> 2),
551 0x00000000,
552 (0x0e00 << 16) | (0xac8c >> 2),
553 0x00000000,
554 (0x0e00 << 16) | (0x970c >> 2),
555 0x00000000,
556 (0x0e00 << 16) | (0x9714 >> 2),
557 0x00000000,
558 (0x0e00 << 16) | (0x9718 >> 2),
559 0x00000000,
560 (0x0e00 << 16) | (0x971c >> 2),
561 0x00000000,
562 (0x0e00 << 16) | (0x31068 >> 2),
563 0x00000000,
564 (0x4e00 << 16) | (0x31068 >> 2),
565 0x00000000,
566 (0x5e00 << 16) | (0x31068 >> 2),
567 0x00000000,
568 (0x6e00 << 16) | (0x31068 >> 2),
569 0x00000000,
570 (0x7e00 << 16) | (0x31068 >> 2),
571 0x00000000,
572 (0x8e00 << 16) | (0x31068 >> 2),
573 0x00000000,
574 (0x9e00 << 16) | (0x31068 >> 2),
575 0x00000000,
576 (0xae00 << 16) | (0x31068 >> 2),
577 0x00000000,
578 (0xbe00 << 16) | (0x31068 >> 2),
579 0x00000000,
580 (0x0e00 << 16) | (0xcd10 >> 2),
581 0x00000000,
582 (0x0e00 << 16) | (0xcd14 >> 2),
583 0x00000000,
584 (0x0e00 << 16) | (0x88b0 >> 2),
585 0x00000000,
586 (0x0e00 << 16) | (0x88b4 >> 2),
587 0x00000000,
588 (0x0e00 << 16) | (0x88b8 >> 2),
589 0x00000000,
590 (0x0e00 << 16) | (0x88bc >> 2),
591 0x00000000,
592 (0x0400 << 16) | (0x89c0 >> 2),
593 0x00000000,
594 (0x0e00 << 16) | (0x88c4 >> 2),
595 0x00000000,
596 (0x0e00 << 16) | (0x88c8 >> 2),
597 0x00000000,
598 (0x0e00 << 16) | (0x88d0 >> 2),
599 0x00000000,
600 (0x0e00 << 16) | (0x88d4 >> 2),
601 0x00000000,
602 (0x0e00 << 16) | (0x88d8 >> 2),
603 0x00000000,
604 (0x0e00 << 16) | (0x8980 >> 2),
605 0x00000000,
606 (0x0e00 << 16) | (0x30938 >> 2),
607 0x00000000,
608 (0x0e00 << 16) | (0x3093c >> 2),
609 0x00000000,
610 (0x0e00 << 16) | (0x30940 >> 2),
611 0x00000000,
612 (0x0e00 << 16) | (0x89a0 >> 2),
613 0x00000000,
614 (0x0e00 << 16) | (0x30900 >> 2),
615 0x00000000,
616 (0x0e00 << 16) | (0x30904 >> 2),
617 0x00000000,
618 (0x0e00 << 16) | (0x89b4 >> 2),
619 0x00000000,
620 (0x0e00 << 16) | (0x3c210 >> 2),
621 0x00000000,
622 (0x0e00 << 16) | (0x3c214 >> 2),
623 0x00000000,
624 (0x0e00 << 16) | (0x3c218 >> 2),
625 0x00000000,
626 (0x0e00 << 16) | (0x8904 >> 2),
627 0x00000000,
628 0x5,
629 (0x0e00 << 16) | (0x8c28 >> 2),
630 (0x0e00 << 16) | (0x8c2c >> 2),
631 (0x0e00 << 16) | (0x8c30 >> 2),
632 (0x0e00 << 16) | (0x8c34 >> 2),
633 (0x0e00 << 16) | (0x9600 >> 2),
634};
635
636static const u32 kalindi_rlc_save_restore_register_list[] =
637{
638 (0x0e00 << 16) | (0xc12c >> 2),
639 0x00000000,
640 (0x0e00 << 16) | (0xc140 >> 2),
641 0x00000000,
642 (0x0e00 << 16) | (0xc150 >> 2),
643 0x00000000,
644 (0x0e00 << 16) | (0xc15c >> 2),
645 0x00000000,
646 (0x0e00 << 16) | (0xc168 >> 2),
647 0x00000000,
648 (0x0e00 << 16) | (0xc170 >> 2),
649 0x00000000,
650 (0x0e00 << 16) | (0xc204 >> 2),
651 0x00000000,
652 (0x0e00 << 16) | (0xc2b4 >> 2),
653 0x00000000,
654 (0x0e00 << 16) | (0xc2b8 >> 2),
655 0x00000000,
656 (0x0e00 << 16) | (0xc2bc >> 2),
657 0x00000000,
658 (0x0e00 << 16) | (0xc2c0 >> 2),
659 0x00000000,
660 (0x0e00 << 16) | (0x8228 >> 2),
661 0x00000000,
662 (0x0e00 << 16) | (0x829c >> 2),
663 0x00000000,
664 (0x0e00 << 16) | (0x869c >> 2),
665 0x00000000,
666 (0x0600 << 16) | (0x98f4 >> 2),
667 0x00000000,
668 (0x0e00 << 16) | (0x98f8 >> 2),
669 0x00000000,
670 (0x0e00 << 16) | (0x9900 >> 2),
671 0x00000000,
672 (0x0e00 << 16) | (0xc260 >> 2),
673 0x00000000,
674 (0x0e00 << 16) | (0x90e8 >> 2),
675 0x00000000,
676 (0x0e00 << 16) | (0x3c000 >> 2),
677 0x00000000,
678 (0x0e00 << 16) | (0x3c00c >> 2),
679 0x00000000,
680 (0x0e00 << 16) | (0x8c1c >> 2),
681 0x00000000,
682 (0x0e00 << 16) | (0x9700 >> 2),
683 0x00000000,
684 (0x0e00 << 16) | (0xcd20 >> 2),
685 0x00000000,
686 (0x4e00 << 16) | (0xcd20 >> 2),
687 0x00000000,
688 (0x5e00 << 16) | (0xcd20 >> 2),
689 0x00000000,
690 (0x6e00 << 16) | (0xcd20 >> 2),
691 0x00000000,
692 (0x7e00 << 16) | (0xcd20 >> 2),
693 0x00000000,
694 (0x0e00 << 16) | (0x89bc >> 2),
695 0x00000000,
696 (0x0e00 << 16) | (0x8900 >> 2),
697 0x00000000,
698 0x3,
699 (0x0e00 << 16) | (0xc130 >> 2),
700 0x00000000,
701 (0x0e00 << 16) | (0xc134 >> 2),
702 0x00000000,
703 (0x0e00 << 16) | (0xc1fc >> 2),
704 0x00000000,
705 (0x0e00 << 16) | (0xc208 >> 2),
706 0x00000000,
707 (0x0e00 << 16) | (0xc264 >> 2),
708 0x00000000,
709 (0x0e00 << 16) | (0xc268 >> 2),
710 0x00000000,
711 (0x0e00 << 16) | (0xc26c >> 2),
712 0x00000000,
713 (0x0e00 << 16) | (0xc270 >> 2),
714 0x00000000,
715 (0x0e00 << 16) | (0xc274 >> 2),
716 0x00000000,
717 (0x0e00 << 16) | (0xc28c >> 2),
718 0x00000000,
719 (0x0e00 << 16) | (0xc290 >> 2),
720 0x00000000,
721 (0x0e00 << 16) | (0xc294 >> 2),
722 0x00000000,
723 (0x0e00 << 16) | (0xc298 >> 2),
724 0x00000000,
725 (0x0e00 << 16) | (0xc2a0 >> 2),
726 0x00000000,
727 (0x0e00 << 16) | (0xc2a4 >> 2),
728 0x00000000,
729 (0x0e00 << 16) | (0xc2a8 >> 2),
730 0x00000000,
731 (0x0e00 << 16) | (0xc2ac >> 2),
732 0x00000000,
733 (0x0e00 << 16) | (0x301d0 >> 2),
734 0x00000000,
735 (0x0e00 << 16) | (0x30238 >> 2),
736 0x00000000,
737 (0x0e00 << 16) | (0x30250 >> 2),
738 0x00000000,
739 (0x0e00 << 16) | (0x30254 >> 2),
740 0x00000000,
741 (0x0e00 << 16) | (0x30258 >> 2),
742 0x00000000,
743 (0x0e00 << 16) | (0x3025c >> 2),
744 0x00000000,
745 (0x4e00 << 16) | (0xc900 >> 2),
746 0x00000000,
747 (0x5e00 << 16) | (0xc900 >> 2),
748 0x00000000,
749 (0x6e00 << 16) | (0xc900 >> 2),
750 0x00000000,
751 (0x7e00 << 16) | (0xc900 >> 2),
752 0x00000000,
753 (0x4e00 << 16) | (0xc904 >> 2),
754 0x00000000,
755 (0x5e00 << 16) | (0xc904 >> 2),
756 0x00000000,
757 (0x6e00 << 16) | (0xc904 >> 2),
758 0x00000000,
759 (0x7e00 << 16) | (0xc904 >> 2),
760 0x00000000,
761 (0x4e00 << 16) | (0xc908 >> 2),
762 0x00000000,
763 (0x5e00 << 16) | (0xc908 >> 2),
764 0x00000000,
765 (0x6e00 << 16) | (0xc908 >> 2),
766 0x00000000,
767 (0x7e00 << 16) | (0xc908 >> 2),
768 0x00000000,
769 (0x4e00 << 16) | (0xc90c >> 2),
770 0x00000000,
771 (0x5e00 << 16) | (0xc90c >> 2),
772 0x00000000,
773 (0x6e00 << 16) | (0xc90c >> 2),
774 0x00000000,
775 (0x7e00 << 16) | (0xc90c >> 2),
776 0x00000000,
777 (0x4e00 << 16) | (0xc910 >> 2),
778 0x00000000,
779 (0x5e00 << 16) | (0xc910 >> 2),
780 0x00000000,
781 (0x6e00 << 16) | (0xc910 >> 2),
782 0x00000000,
783 (0x7e00 << 16) | (0xc910 >> 2),
784 0x00000000,
785 (0x0e00 << 16) | (0xc99c >> 2),
786 0x00000000,
787 (0x0e00 << 16) | (0x9834 >> 2),
788 0x00000000,
789 (0x0000 << 16) | (0x30f00 >> 2),
790 0x00000000,
791 (0x0000 << 16) | (0x30f04 >> 2),
792 0x00000000,
793 (0x0000 << 16) | (0x30f08 >> 2),
794 0x00000000,
795 (0x0000 << 16) | (0x30f0c >> 2),
796 0x00000000,
797 (0x0600 << 16) | (0x9b7c >> 2),
798 0x00000000,
799 (0x0e00 << 16) | (0x8a14 >> 2),
800 0x00000000,
801 (0x0e00 << 16) | (0x8a18 >> 2),
802 0x00000000,
803 (0x0600 << 16) | (0x30a00 >> 2),
804 0x00000000,
805 (0x0e00 << 16) | (0x8bf0 >> 2),
806 0x00000000,
807 (0x0e00 << 16) | (0x8bcc >> 2),
808 0x00000000,
809 (0x0e00 << 16) | (0x8b24 >> 2),
810 0x00000000,
811 (0x0e00 << 16) | (0x30a04 >> 2),
812 0x00000000,
813 (0x0600 << 16) | (0x30a10 >> 2),
814 0x00000000,
815 (0x0600 << 16) | (0x30a14 >> 2),
816 0x00000000,
817 (0x0600 << 16) | (0x30a18 >> 2),
818 0x00000000,
819 (0x0600 << 16) | (0x30a2c >> 2),
820 0x00000000,
821 (0x0e00 << 16) | (0xc700 >> 2),
822 0x00000000,
823 (0x0e00 << 16) | (0xc704 >> 2),
824 0x00000000,
825 (0x0e00 << 16) | (0xc708 >> 2),
826 0x00000000,
827 (0x0e00 << 16) | (0xc768 >> 2),
828 0x00000000,
829 (0x0400 << 16) | (0xc770 >> 2),
830 0x00000000,
831 (0x0400 << 16) | (0xc774 >> 2),
832 0x00000000,
833 (0x0400 << 16) | (0xc798 >> 2),
834 0x00000000,
835 (0x0400 << 16) | (0xc79c >> 2),
836 0x00000000,
837 (0x0e00 << 16) | (0x9100 >> 2),
838 0x00000000,
839 (0x0e00 << 16) | (0x3c010 >> 2),
840 0x00000000,
841 (0x0e00 << 16) | (0x8c00 >> 2),
842 0x00000000,
843 (0x0e00 << 16) | (0x8c04 >> 2),
844 0x00000000,
845 (0x0e00 << 16) | (0x8c20 >> 2),
846 0x00000000,
847 (0x0e00 << 16) | (0x8c38 >> 2),
848 0x00000000,
849 (0x0e00 << 16) | (0x8c3c >> 2),
850 0x00000000,
851 (0x0e00 << 16) | (0xae00 >> 2),
852 0x00000000,
853 (0x0e00 << 16) | (0x9604 >> 2),
854 0x00000000,
855 (0x0e00 << 16) | (0xac08 >> 2),
856 0x00000000,
857 (0x0e00 << 16) | (0xac0c >> 2),
858 0x00000000,
859 (0x0e00 << 16) | (0xac10 >> 2),
860 0x00000000,
861 (0x0e00 << 16) | (0xac14 >> 2),
862 0x00000000,
863 (0x0e00 << 16) | (0xac58 >> 2),
864 0x00000000,
865 (0x0e00 << 16) | (0xac68 >> 2),
866 0x00000000,
867 (0x0e00 << 16) | (0xac6c >> 2),
868 0x00000000,
869 (0x0e00 << 16) | (0xac70 >> 2),
870 0x00000000,
871 (0x0e00 << 16) | (0xac74 >> 2),
872 0x00000000,
873 (0x0e00 << 16) | (0xac78 >> 2),
874 0x00000000,
875 (0x0e00 << 16) | (0xac7c >> 2),
876 0x00000000,
877 (0x0e00 << 16) | (0xac80 >> 2),
878 0x00000000,
879 (0x0e00 << 16) | (0xac84 >> 2),
880 0x00000000,
881 (0x0e00 << 16) | (0xac88 >> 2),
882 0x00000000,
883 (0x0e00 << 16) | (0xac8c >> 2),
884 0x00000000,
885 (0x0e00 << 16) | (0x970c >> 2),
886 0x00000000,
887 (0x0e00 << 16) | (0x9714 >> 2),
888 0x00000000,
889 (0x0e00 << 16) | (0x9718 >> 2),
890 0x00000000,
891 (0x0e00 << 16) | (0x971c >> 2),
892 0x00000000,
893 (0x0e00 << 16) | (0x31068 >> 2),
894 0x00000000,
895 (0x4e00 << 16) | (0x31068 >> 2),
896 0x00000000,
897 (0x5e00 << 16) | (0x31068 >> 2),
898 0x00000000,
899 (0x6e00 << 16) | (0x31068 >> 2),
900 0x00000000,
901 (0x7e00 << 16) | (0x31068 >> 2),
902 0x00000000,
903 (0x0e00 << 16) | (0xcd10 >> 2),
904 0x00000000,
905 (0x0e00 << 16) | (0xcd14 >> 2),
906 0x00000000,
907 (0x0e00 << 16) | (0x88b0 >> 2),
908 0x00000000,
909 (0x0e00 << 16) | (0x88b4 >> 2),
910 0x00000000,
911 (0x0e00 << 16) | (0x88b8 >> 2),
912 0x00000000,
913 (0x0e00 << 16) | (0x88bc >> 2),
914 0x00000000,
915 (0x0400 << 16) | (0x89c0 >> 2),
916 0x00000000,
917 (0x0e00 << 16) | (0x88c4 >> 2),
918 0x00000000,
919 (0x0e00 << 16) | (0x88c8 >> 2),
920 0x00000000,
921 (0x0e00 << 16) | (0x88d0 >> 2),
922 0x00000000,
923 (0x0e00 << 16) | (0x88d4 >> 2),
924 0x00000000,
925 (0x0e00 << 16) | (0x88d8 >> 2),
926 0x00000000,
927 (0x0e00 << 16) | (0x8980 >> 2),
928 0x00000000,
929 (0x0e00 << 16) | (0x30938 >> 2),
930 0x00000000,
931 (0x0e00 << 16) | (0x3093c >> 2),
932 0x00000000,
933 (0x0e00 << 16) | (0x30940 >> 2),
934 0x00000000,
935 (0x0e00 << 16) | (0x89a0 >> 2),
936 0x00000000,
937 (0x0e00 << 16) | (0x30900 >> 2),
938 0x00000000,
939 (0x0e00 << 16) | (0x30904 >> 2),
940 0x00000000,
941 (0x0e00 << 16) | (0x89b4 >> 2),
942 0x00000000,
943 (0x0e00 << 16) | (0x3e1fc >> 2),
944 0x00000000,
945 (0x0e00 << 16) | (0x3c210 >> 2),
946 0x00000000,
947 (0x0e00 << 16) | (0x3c214 >> 2),
948 0x00000000,
949 (0x0e00 << 16) | (0x3c218 >> 2),
950 0x00000000,
951 (0x0e00 << 16) | (0x8904 >> 2),
952 0x00000000,
953 0x5,
954 (0x0e00 << 16) | (0x8c28 >> 2),
955 (0x0e00 << 16) | (0x8c2c >> 2),
956 (0x0e00 << 16) | (0x8c30 >> 2),
957 (0x0e00 << 16) | (0x8c34 >> 2),
958 (0x0e00 << 16) | (0x9600 >> 2),
959};
960
57e252bf
MN
961static const u32 bonaire_golden_spm_registers[] =
962{
963 0x30800, 0xe0ffffff, 0xe0000000
964};
965
966static const u32 bonaire_golden_common_registers[] =
967{
968 0xc770, 0xffffffff, 0x00000800,
969 0xc774, 0xffffffff, 0x00000800,
970 0xc798, 0xffffffff, 0x00007fbf,
971 0xc79c, 0xffffffff, 0x00007faf
972};
973
974static const u32 bonaire_golden_registers[] =
975{
976 0x3354, 0x00000333, 0x00000333,
977 0x3350, 0x000c0fc0, 0x00040200,
978 0x9a10, 0x00010000, 0x00058208,
979 0x3c000, 0xffff1fff, 0x00140000,
980 0x3c200, 0xfdfc0fff, 0x00000100,
981 0x3c234, 0x40000000, 0x40000200,
982 0x9830, 0xffffffff, 0x00000000,
983 0x9834, 0xf00fffff, 0x00000400,
984 0x9838, 0x0002021c, 0x00020200,
985 0xc78, 0x00000080, 0x00000000,
986 0x5bb0, 0x000000f0, 0x00000070,
987 0x5bc0, 0xf0311fff, 0x80300000,
988 0x98f8, 0x73773777, 0x12010001,
989 0x350c, 0x00810000, 0x408af000,
990 0x7030, 0x31000111, 0x00000011,
991 0x2f48, 0x73773777, 0x12010001,
992 0x220c, 0x00007fb6, 0x0021a1b1,
993 0x2210, 0x00007fb6, 0x002021b1,
994 0x2180, 0x00007fb6, 0x00002191,
995 0x2218, 0x00007fb6, 0x002121b1,
996 0x221c, 0x00007fb6, 0x002021b1,
997 0x21dc, 0x00007fb6, 0x00002191,
998 0x21e0, 0x00007fb6, 0x00002191,
999 0x3628, 0x0000003f, 0x0000000a,
1000 0x362c, 0x0000003f, 0x0000000a,
1001 0x2ae4, 0x00073ffe, 0x000022a2,
1002 0x240c, 0x000007ff, 0x00000000,
1003 0x8a14, 0xf000003f, 0x00000007,
1004 0x8bf0, 0x00002001, 0x00000001,
1005 0x8b24, 0xffffffff, 0x00ffffff,
1006 0x30a04, 0x0000ff0f, 0x00000000,
1007 0x28a4c, 0x07ffffff, 0x06000000,
1008 0x4d8, 0x00000fff, 0x00000100,
1009 0x3e78, 0x00000001, 0x00000002,
1010 0x9100, 0x03000000, 0x0362c688,
1011 0x8c00, 0x000000ff, 0x00000001,
1012 0xe40, 0x00001fff, 0x00001fff,
1013 0x9060, 0x0000007f, 0x00000020,
1014 0x9508, 0x00010000, 0x00010000,
1015 0xac14, 0x000003ff, 0x000000f3,
1016 0xac0c, 0xffffffff, 0x00001032
1017};
1018
1019static const u32 bonaire_mgcg_cgcg_init[] =
1020{
1021 0xc420, 0xffffffff, 0xfffffffc,
1022 0x30800, 0xffffffff, 0xe0000000,
1023 0x3c2a0, 0xffffffff, 0x00000100,
1024 0x3c208, 0xffffffff, 0x00000100,
1025 0x3c2c0, 0xffffffff, 0xc0000100,
1026 0x3c2c8, 0xffffffff, 0xc0000100,
1027 0x3c2c4, 0xffffffff, 0xc0000100,
1028 0x55e4, 0xffffffff, 0x00600100,
1029 0x3c280, 0xffffffff, 0x00000100,
1030 0x3c214, 0xffffffff, 0x06000100,
1031 0x3c220, 0xffffffff, 0x00000100,
1032 0x3c218, 0xffffffff, 0x06000100,
1033 0x3c204, 0xffffffff, 0x00000100,
1034 0x3c2e0, 0xffffffff, 0x00000100,
1035 0x3c224, 0xffffffff, 0x00000100,
1036 0x3c200, 0xffffffff, 0x00000100,
1037 0x3c230, 0xffffffff, 0x00000100,
1038 0x3c234, 0xffffffff, 0x00000100,
1039 0x3c250, 0xffffffff, 0x00000100,
1040 0x3c254, 0xffffffff, 0x00000100,
1041 0x3c258, 0xffffffff, 0x00000100,
1042 0x3c25c, 0xffffffff, 0x00000100,
1043 0x3c260, 0xffffffff, 0x00000100,
1044 0x3c27c, 0xffffffff, 0x00000100,
1045 0x3c278, 0xffffffff, 0x00000100,
1046 0x3c210, 0xffffffff, 0x06000100,
1047 0x3c290, 0xffffffff, 0x00000100,
1048 0x3c274, 0xffffffff, 0x00000100,
1049 0x3c2b4, 0xffffffff, 0x00000100,
1050 0x3c2b0, 0xffffffff, 0x00000100,
1051 0x3c270, 0xffffffff, 0x00000100,
1052 0x30800, 0xffffffff, 0xe0000000,
1053 0x3c020, 0xffffffff, 0x00010000,
1054 0x3c024, 0xffffffff, 0x00030002,
1055 0x3c028, 0xffffffff, 0x00040007,
1056 0x3c02c, 0xffffffff, 0x00060005,
1057 0x3c030, 0xffffffff, 0x00090008,
1058 0x3c034, 0xffffffff, 0x00010000,
1059 0x3c038, 0xffffffff, 0x00030002,
1060 0x3c03c, 0xffffffff, 0x00040007,
1061 0x3c040, 0xffffffff, 0x00060005,
1062 0x3c044, 0xffffffff, 0x00090008,
1063 0x3c048, 0xffffffff, 0x00010000,
1064 0x3c04c, 0xffffffff, 0x00030002,
1065 0x3c050, 0xffffffff, 0x00040007,
1066 0x3c054, 0xffffffff, 0x00060005,
1067 0x3c058, 0xffffffff, 0x00090008,
1068 0x3c05c, 0xffffffff, 0x00010000,
1069 0x3c060, 0xffffffff, 0x00030002,
1070 0x3c064, 0xffffffff, 0x00040007,
1071 0x3c068, 0xffffffff, 0x00060005,
1072 0x3c06c, 0xffffffff, 0x00090008,
1073 0x3c070, 0xffffffff, 0x00010000,
1074 0x3c074, 0xffffffff, 0x00030002,
1075 0x3c078, 0xffffffff, 0x00040007,
1076 0x3c07c, 0xffffffff, 0x00060005,
1077 0x3c080, 0xffffffff, 0x00090008,
1078 0x3c084, 0xffffffff, 0x00010000,
1079 0x3c088, 0xffffffff, 0x00030002,
1080 0x3c08c, 0xffffffff, 0x00040007,
1081 0x3c090, 0xffffffff, 0x00060005,
1082 0x3c094, 0xffffffff, 0x00090008,
1083 0x3c098, 0xffffffff, 0x00010000,
1084 0x3c09c, 0xffffffff, 0x00030002,
1085 0x3c0a0, 0xffffffff, 0x00040007,
1086 0x3c0a4, 0xffffffff, 0x00060005,
1087 0x3c0a8, 0xffffffff, 0x00090008,
1088 0x3c000, 0xffffffff, 0x96e00200,
1089 0x8708, 0xffffffff, 0x00900100,
1090 0xc424, 0xffffffff, 0x0020003f,
1091 0x38, 0xffffffff, 0x0140001c,
1092 0x3c, 0x000f0000, 0x000f0000,
1093 0x220, 0xffffffff, 0xC060000C,
1094 0x224, 0xc0000fff, 0x00000100,
1095 0xf90, 0xffffffff, 0x00000100,
1096 0xf98, 0x00000101, 0x00000000,
1097 0x20a8, 0xffffffff, 0x00000104,
1098 0x55e4, 0xff000fff, 0x00000100,
1099 0x30cc, 0xc0000fff, 0x00000104,
1100 0xc1e4, 0x00000001, 0x00000001,
1101 0xd00c, 0xff000ff0, 0x00000100,
1102 0xd80c, 0xff000ff0, 0x00000100
1103};
1104
1105static const u32 spectre_golden_spm_registers[] =
1106{
1107 0x30800, 0xe0ffffff, 0xe0000000
1108};
1109
1110static const u32 spectre_golden_common_registers[] =
1111{
1112 0xc770, 0xffffffff, 0x00000800,
1113 0xc774, 0xffffffff, 0x00000800,
1114 0xc798, 0xffffffff, 0x00007fbf,
1115 0xc79c, 0xffffffff, 0x00007faf
1116};
1117
1118static const u32 spectre_golden_registers[] =
1119{
1120 0x3c000, 0xffff1fff, 0x96940200,
1121 0x3c00c, 0xffff0001, 0xff000000,
1122 0x3c200, 0xfffc0fff, 0x00000100,
1123 0x6ed8, 0x00010101, 0x00010000,
1124 0x9834, 0xf00fffff, 0x00000400,
1125 0x9838, 0xfffffffc, 0x00020200,
1126 0x5bb0, 0x000000f0, 0x00000070,
1127 0x5bc0, 0xf0311fff, 0x80300000,
1128 0x98f8, 0x73773777, 0x12010001,
1129 0x9b7c, 0x00ff0000, 0x00fc0000,
1130 0x2f48, 0x73773777, 0x12010001,
1131 0x8a14, 0xf000003f, 0x00000007,
1132 0x8b24, 0xffffffff, 0x00ffffff,
1133 0x28350, 0x3f3f3fff, 0x00000082,
c6f73aab 1134 0x28354, 0x0000003f, 0x00000000,
57e252bf
MN
1135 0x3e78, 0x00000001, 0x00000002,
1136 0x913c, 0xffff03df, 0x00000004,
1137 0xc768, 0x00000008, 0x00000008,
1138 0x8c00, 0x000008ff, 0x00000800,
1139 0x9508, 0x00010000, 0x00010000,
1140 0xac0c, 0xffffffff, 0x54763210,
1141 0x214f8, 0x01ff01ff, 0x00000002,
1142 0x21498, 0x007ff800, 0x00200000,
1143 0x2015c, 0xffffffff, 0x00000f40,
1144 0x30934, 0xffffffff, 0x00000001
1145};
1146
1147static const u32 spectre_mgcg_cgcg_init[] =
1148{
1149 0xc420, 0xffffffff, 0xfffffffc,
1150 0x30800, 0xffffffff, 0xe0000000,
1151 0x3c2a0, 0xffffffff, 0x00000100,
1152 0x3c208, 0xffffffff, 0x00000100,
1153 0x3c2c0, 0xffffffff, 0x00000100,
1154 0x3c2c8, 0xffffffff, 0x00000100,
1155 0x3c2c4, 0xffffffff, 0x00000100,
1156 0x55e4, 0xffffffff, 0x00600100,
1157 0x3c280, 0xffffffff, 0x00000100,
1158 0x3c214, 0xffffffff, 0x06000100,
1159 0x3c220, 0xffffffff, 0x00000100,
1160 0x3c218, 0xffffffff, 0x06000100,
1161 0x3c204, 0xffffffff, 0x00000100,
1162 0x3c2e0, 0xffffffff, 0x00000100,
1163 0x3c224, 0xffffffff, 0x00000100,
1164 0x3c200, 0xffffffff, 0x00000100,
1165 0x3c230, 0xffffffff, 0x00000100,
1166 0x3c234, 0xffffffff, 0x00000100,
1167 0x3c250, 0xffffffff, 0x00000100,
1168 0x3c254, 0xffffffff, 0x00000100,
1169 0x3c258, 0xffffffff, 0x00000100,
1170 0x3c25c, 0xffffffff, 0x00000100,
1171 0x3c260, 0xffffffff, 0x00000100,
1172 0x3c27c, 0xffffffff, 0x00000100,
1173 0x3c278, 0xffffffff, 0x00000100,
1174 0x3c210, 0xffffffff, 0x06000100,
1175 0x3c290, 0xffffffff, 0x00000100,
1176 0x3c274, 0xffffffff, 0x00000100,
1177 0x3c2b4, 0xffffffff, 0x00000100,
1178 0x3c2b0, 0xffffffff, 0x00000100,
1179 0x3c270, 0xffffffff, 0x00000100,
1180 0x30800, 0xffffffff, 0xe0000000,
1181 0x3c020, 0xffffffff, 0x00010000,
1182 0x3c024, 0xffffffff, 0x00030002,
1183 0x3c028, 0xffffffff, 0x00040007,
1184 0x3c02c, 0xffffffff, 0x00060005,
1185 0x3c030, 0xffffffff, 0x00090008,
1186 0x3c034, 0xffffffff, 0x00010000,
1187 0x3c038, 0xffffffff, 0x00030002,
1188 0x3c03c, 0xffffffff, 0x00040007,
1189 0x3c040, 0xffffffff, 0x00060005,
1190 0x3c044, 0xffffffff, 0x00090008,
1191 0x3c048, 0xffffffff, 0x00010000,
1192 0x3c04c, 0xffffffff, 0x00030002,
1193 0x3c050, 0xffffffff, 0x00040007,
1194 0x3c054, 0xffffffff, 0x00060005,
1195 0x3c058, 0xffffffff, 0x00090008,
1196 0x3c05c, 0xffffffff, 0x00010000,
1197 0x3c060, 0xffffffff, 0x00030002,
1198 0x3c064, 0xffffffff, 0x00040007,
1199 0x3c068, 0xffffffff, 0x00060005,
1200 0x3c06c, 0xffffffff, 0x00090008,
1201 0x3c070, 0xffffffff, 0x00010000,
1202 0x3c074, 0xffffffff, 0x00030002,
1203 0x3c078, 0xffffffff, 0x00040007,
1204 0x3c07c, 0xffffffff, 0x00060005,
1205 0x3c080, 0xffffffff, 0x00090008,
1206 0x3c084, 0xffffffff, 0x00010000,
1207 0x3c088, 0xffffffff, 0x00030002,
1208 0x3c08c, 0xffffffff, 0x00040007,
1209 0x3c090, 0xffffffff, 0x00060005,
1210 0x3c094, 0xffffffff, 0x00090008,
1211 0x3c098, 0xffffffff, 0x00010000,
1212 0x3c09c, 0xffffffff, 0x00030002,
1213 0x3c0a0, 0xffffffff, 0x00040007,
1214 0x3c0a4, 0xffffffff, 0x00060005,
1215 0x3c0a8, 0xffffffff, 0x00090008,
1216 0x3c0ac, 0xffffffff, 0x00010000,
1217 0x3c0b0, 0xffffffff, 0x00030002,
1218 0x3c0b4, 0xffffffff, 0x00040007,
1219 0x3c0b8, 0xffffffff, 0x00060005,
1220 0x3c0bc, 0xffffffff, 0x00090008,
1221 0x3c000, 0xffffffff, 0x96e00200,
1222 0x8708, 0xffffffff, 0x00900100,
1223 0xc424, 0xffffffff, 0x0020003f,
1224 0x38, 0xffffffff, 0x0140001c,
1225 0x3c, 0x000f0000, 0x000f0000,
1226 0x220, 0xffffffff, 0xC060000C,
1227 0x224, 0xc0000fff, 0x00000100,
1228 0xf90, 0xffffffff, 0x00000100,
1229 0xf98, 0x00000101, 0x00000000,
1230 0x20a8, 0xffffffff, 0x00000104,
1231 0x55e4, 0xff000fff, 0x00000100,
1232 0x30cc, 0xc0000fff, 0x00000104,
1233 0xc1e4, 0x00000001, 0x00000001,
1234 0xd00c, 0xff000ff0, 0x00000100,
1235 0xd80c, 0xff000ff0, 0x00000100
1236};
1237
1238static const u32 kalindi_golden_spm_registers[] =
1239{
1240 0x30800, 0xe0ffffff, 0xe0000000
1241};
1242
1243static const u32 kalindi_golden_common_registers[] =
1244{
1245 0xc770, 0xffffffff, 0x00000800,
1246 0xc774, 0xffffffff, 0x00000800,
1247 0xc798, 0xffffffff, 0x00007fbf,
1248 0xc79c, 0xffffffff, 0x00007faf
1249};
1250
1251static const u32 kalindi_golden_registers[] =
1252{
1253 0x3c000, 0xffffdfff, 0x6e944040,
1254 0x55e4, 0xff607fff, 0xfc000100,
1255 0x3c220, 0xff000fff, 0x00000100,
1256 0x3c224, 0xff000fff, 0x00000100,
1257 0x3c200, 0xfffc0fff, 0x00000100,
1258 0x6ed8, 0x00010101, 0x00010000,
1259 0x9830, 0xffffffff, 0x00000000,
1260 0x9834, 0xf00fffff, 0x00000400,
1261 0x5bb0, 0x000000f0, 0x00000070,
1262 0x5bc0, 0xf0311fff, 0x80300000,
1263 0x98f8, 0x73773777, 0x12010001,
1264 0x98fc, 0xffffffff, 0x00000010,
1265 0x9b7c, 0x00ff0000, 0x00fc0000,
1266 0x8030, 0x00001f0f, 0x0000100a,
1267 0x2f48, 0x73773777, 0x12010001,
1268 0x2408, 0x000fffff, 0x000c007f,
1269 0x8a14, 0xf000003f, 0x00000007,
1270 0x8b24, 0x3fff3fff, 0x00ffcfff,
1271 0x30a04, 0x0000ff0f, 0x00000000,
1272 0x28a4c, 0x07ffffff, 0x06000000,
1273 0x4d8, 0x00000fff, 0x00000100,
1274 0x3e78, 0x00000001, 0x00000002,
1275 0xc768, 0x00000008, 0x00000008,
1276 0x8c00, 0x000000ff, 0x00000003,
1277 0x214f8, 0x01ff01ff, 0x00000002,
1278 0x21498, 0x007ff800, 0x00200000,
1279 0x2015c, 0xffffffff, 0x00000f40,
1280 0x88c4, 0x001f3ae3, 0x00000082,
1281 0x88d4, 0x0000001f, 0x00000010,
1282 0x30934, 0xffffffff, 0x00000000
1283};
1284
1285static const u32 kalindi_mgcg_cgcg_init[] =
1286{
1287 0xc420, 0xffffffff, 0xfffffffc,
1288 0x30800, 0xffffffff, 0xe0000000,
1289 0x3c2a0, 0xffffffff, 0x00000100,
1290 0x3c208, 0xffffffff, 0x00000100,
1291 0x3c2c0, 0xffffffff, 0x00000100,
1292 0x3c2c8, 0xffffffff, 0x00000100,
1293 0x3c2c4, 0xffffffff, 0x00000100,
1294 0x55e4, 0xffffffff, 0x00600100,
1295 0x3c280, 0xffffffff, 0x00000100,
1296 0x3c214, 0xffffffff, 0x06000100,
1297 0x3c220, 0xffffffff, 0x00000100,
1298 0x3c218, 0xffffffff, 0x06000100,
1299 0x3c204, 0xffffffff, 0x00000100,
1300 0x3c2e0, 0xffffffff, 0x00000100,
1301 0x3c224, 0xffffffff, 0x00000100,
1302 0x3c200, 0xffffffff, 0x00000100,
1303 0x3c230, 0xffffffff, 0x00000100,
1304 0x3c234, 0xffffffff, 0x00000100,
1305 0x3c250, 0xffffffff, 0x00000100,
1306 0x3c254, 0xffffffff, 0x00000100,
1307 0x3c258, 0xffffffff, 0x00000100,
1308 0x3c25c, 0xffffffff, 0x00000100,
1309 0x3c260, 0xffffffff, 0x00000100,
1310 0x3c27c, 0xffffffff, 0x00000100,
1311 0x3c278, 0xffffffff, 0x00000100,
1312 0x3c210, 0xffffffff, 0x06000100,
1313 0x3c290, 0xffffffff, 0x00000100,
1314 0x3c274, 0xffffffff, 0x00000100,
1315 0x3c2b4, 0xffffffff, 0x00000100,
1316 0x3c2b0, 0xffffffff, 0x00000100,
1317 0x3c270, 0xffffffff, 0x00000100,
1318 0x30800, 0xffffffff, 0xe0000000,
1319 0x3c020, 0xffffffff, 0x00010000,
1320 0x3c024, 0xffffffff, 0x00030002,
1321 0x3c028, 0xffffffff, 0x00040007,
1322 0x3c02c, 0xffffffff, 0x00060005,
1323 0x3c030, 0xffffffff, 0x00090008,
1324 0x3c034, 0xffffffff, 0x00010000,
1325 0x3c038, 0xffffffff, 0x00030002,
1326 0x3c03c, 0xffffffff, 0x00040007,
1327 0x3c040, 0xffffffff, 0x00060005,
1328 0x3c044, 0xffffffff, 0x00090008,
1329 0x3c000, 0xffffffff, 0x96e00200,
1330 0x8708, 0xffffffff, 0x00900100,
1331 0xc424, 0xffffffff, 0x0020003f,
1332 0x38, 0xffffffff, 0x0140001c,
1333 0x3c, 0x000f0000, 0x000f0000,
1334 0x220, 0xffffffff, 0xC060000C,
1335 0x224, 0xc0000fff, 0x00000100,
1336 0x20a8, 0xffffffff, 0x00000104,
1337 0x55e4, 0xff000fff, 0x00000100,
1338 0x30cc, 0xc0000fff, 0x00000104,
1339 0xc1e4, 0x00000001, 0x00000001,
1340 0xd00c, 0xff000ff0, 0x00000100,
1341 0xd80c, 0xff000ff0, 0x00000100
1342};
1343
c6f73aab
FT
1344static const u32 hawaii_golden_spm_registers[] =
1345{
1346 0x30800, 0xe0ffffff, 0xe0000000
1347};
1348
1349static const u32 hawaii_golden_common_registers[] =
1350{
1351 0x30800, 0xffffffff, 0xe0000000,
1352 0x28350, 0xffffffff, 0x3a00161a,
1353 0x28354, 0xffffffff, 0x0000002e,
1354 0x9a10, 0xffffffff, 0x00018208,
1355 0x98f8, 0xffffffff, 0x12011003
1356};
1357
1358static const u32 hawaii_golden_registers[] =
1359{
1360 0x3354, 0x00000333, 0x00000333,
1361 0x9a10, 0x00010000, 0x00058208,
1362 0x9830, 0xffffffff, 0x00000000,
1363 0x9834, 0xf00fffff, 0x00000400,
1364 0x9838, 0x0002021c, 0x00020200,
1365 0xc78, 0x00000080, 0x00000000,
1366 0x5bb0, 0x000000f0, 0x00000070,
1367 0x5bc0, 0xf0311fff, 0x80300000,
1368 0x350c, 0x00810000, 0x408af000,
1369 0x7030, 0x31000111, 0x00000011,
1370 0x2f48, 0x73773777, 0x12010001,
1371 0x2120, 0x0000007f, 0x0000001b,
1372 0x21dc, 0x00007fb6, 0x00002191,
1373 0x3628, 0x0000003f, 0x0000000a,
1374 0x362c, 0x0000003f, 0x0000000a,
1375 0x2ae4, 0x00073ffe, 0x000022a2,
1376 0x240c, 0x000007ff, 0x00000000,
1377 0x8bf0, 0x00002001, 0x00000001,
1378 0x8b24, 0xffffffff, 0x00ffffff,
1379 0x30a04, 0x0000ff0f, 0x00000000,
1380 0x28a4c, 0x07ffffff, 0x06000000,
1381 0x3e78, 0x00000001, 0x00000002,
1382 0xc768, 0x00000008, 0x00000008,
1383 0xc770, 0x00000f00, 0x00000800,
1384 0xc774, 0x00000f00, 0x00000800,
1385 0xc798, 0x00ffffff, 0x00ff7fbf,
1386 0xc79c, 0x00ffffff, 0x00ff7faf,
1387 0x8c00, 0x000000ff, 0x00000800,
1388 0xe40, 0x00001fff, 0x00001fff,
1389 0x9060, 0x0000007f, 0x00000020,
1390 0x9508, 0x00010000, 0x00010000,
1391 0xae00, 0x00100000, 0x000ff07c,
1392 0xac14, 0x000003ff, 0x0000000f,
1393 0xac10, 0xffffffff, 0x7564fdec,
1394 0xac0c, 0xffffffff, 0x3120b9a8,
1395 0xac08, 0x20000000, 0x0f9c0000
1396};
1397
1398static const u32 hawaii_mgcg_cgcg_init[] =
1399{
1400 0xc420, 0xffffffff, 0xfffffffd,
1401 0x30800, 0xffffffff, 0xe0000000,
1402 0x3c2a0, 0xffffffff, 0x00000100,
1403 0x3c208, 0xffffffff, 0x00000100,
1404 0x3c2c0, 0xffffffff, 0x00000100,
1405 0x3c2c8, 0xffffffff, 0x00000100,
1406 0x3c2c4, 0xffffffff, 0x00000100,
1407 0x55e4, 0xffffffff, 0x00200100,
1408 0x3c280, 0xffffffff, 0x00000100,
1409 0x3c214, 0xffffffff, 0x06000100,
1410 0x3c220, 0xffffffff, 0x00000100,
1411 0x3c218, 0xffffffff, 0x06000100,
1412 0x3c204, 0xffffffff, 0x00000100,
1413 0x3c2e0, 0xffffffff, 0x00000100,
1414 0x3c224, 0xffffffff, 0x00000100,
1415 0x3c200, 0xffffffff, 0x00000100,
1416 0x3c230, 0xffffffff, 0x00000100,
1417 0x3c234, 0xffffffff, 0x00000100,
1418 0x3c250, 0xffffffff, 0x00000100,
1419 0x3c254, 0xffffffff, 0x00000100,
1420 0x3c258, 0xffffffff, 0x00000100,
1421 0x3c25c, 0xffffffff, 0x00000100,
1422 0x3c260, 0xffffffff, 0x00000100,
1423 0x3c27c, 0xffffffff, 0x00000100,
1424 0x3c278, 0xffffffff, 0x00000100,
1425 0x3c210, 0xffffffff, 0x06000100,
1426 0x3c290, 0xffffffff, 0x00000100,
1427 0x3c274, 0xffffffff, 0x00000100,
1428 0x3c2b4, 0xffffffff, 0x00000100,
1429 0x3c2b0, 0xffffffff, 0x00000100,
1430 0x3c270, 0xffffffff, 0x00000100,
1431 0x30800, 0xffffffff, 0xe0000000,
1432 0x3c020, 0xffffffff, 0x00010000,
1433 0x3c024, 0xffffffff, 0x00030002,
1434 0x3c028, 0xffffffff, 0x00040007,
1435 0x3c02c, 0xffffffff, 0x00060005,
1436 0x3c030, 0xffffffff, 0x00090008,
1437 0x3c034, 0xffffffff, 0x00010000,
1438 0x3c038, 0xffffffff, 0x00030002,
1439 0x3c03c, 0xffffffff, 0x00040007,
1440 0x3c040, 0xffffffff, 0x00060005,
1441 0x3c044, 0xffffffff, 0x00090008,
1442 0x3c048, 0xffffffff, 0x00010000,
1443 0x3c04c, 0xffffffff, 0x00030002,
1444 0x3c050, 0xffffffff, 0x00040007,
1445 0x3c054, 0xffffffff, 0x00060005,
1446 0x3c058, 0xffffffff, 0x00090008,
1447 0x3c05c, 0xffffffff, 0x00010000,
1448 0x3c060, 0xffffffff, 0x00030002,
1449 0x3c064, 0xffffffff, 0x00040007,
1450 0x3c068, 0xffffffff, 0x00060005,
1451 0x3c06c, 0xffffffff, 0x00090008,
1452 0x3c070, 0xffffffff, 0x00010000,
1453 0x3c074, 0xffffffff, 0x00030002,
1454 0x3c078, 0xffffffff, 0x00040007,
1455 0x3c07c, 0xffffffff, 0x00060005,
1456 0x3c080, 0xffffffff, 0x00090008,
1457 0x3c084, 0xffffffff, 0x00010000,
1458 0x3c088, 0xffffffff, 0x00030002,
1459 0x3c08c, 0xffffffff, 0x00040007,
1460 0x3c090, 0xffffffff, 0x00060005,
1461 0x3c094, 0xffffffff, 0x00090008,
1462 0x3c098, 0xffffffff, 0x00010000,
1463 0x3c09c, 0xffffffff, 0x00030002,
1464 0x3c0a0, 0xffffffff, 0x00040007,
1465 0x3c0a4, 0xffffffff, 0x00060005,
1466 0x3c0a8, 0xffffffff, 0x00090008,
1467 0x3c0ac, 0xffffffff, 0x00010000,
1468 0x3c0b0, 0xffffffff, 0x00030002,
1469 0x3c0b4, 0xffffffff, 0x00040007,
1470 0x3c0b8, 0xffffffff, 0x00060005,
1471 0x3c0bc, 0xffffffff, 0x00090008,
1472 0x3c0c0, 0xffffffff, 0x00010000,
1473 0x3c0c4, 0xffffffff, 0x00030002,
1474 0x3c0c8, 0xffffffff, 0x00040007,
1475 0x3c0cc, 0xffffffff, 0x00060005,
1476 0x3c0d0, 0xffffffff, 0x00090008,
1477 0x3c0d4, 0xffffffff, 0x00010000,
1478 0x3c0d8, 0xffffffff, 0x00030002,
1479 0x3c0dc, 0xffffffff, 0x00040007,
1480 0x3c0e0, 0xffffffff, 0x00060005,
1481 0x3c0e4, 0xffffffff, 0x00090008,
1482 0x3c0e8, 0xffffffff, 0x00010000,
1483 0x3c0ec, 0xffffffff, 0x00030002,
1484 0x3c0f0, 0xffffffff, 0x00040007,
1485 0x3c0f4, 0xffffffff, 0x00060005,
1486 0x3c0f8, 0xffffffff, 0x00090008,
1487 0xc318, 0xffffffff, 0x00020200,
1488 0x3350, 0xffffffff, 0x00000200,
1489 0x15c0, 0xffffffff, 0x00000400,
1490 0x55e8, 0xffffffff, 0x00000000,
1491 0x2f50, 0xffffffff, 0x00000902,
1492 0x3c000, 0xffffffff, 0x96940200,
1493 0x8708, 0xffffffff, 0x00900100,
1494 0xc424, 0xffffffff, 0x0020003f,
1495 0x38, 0xffffffff, 0x0140001c,
1496 0x3c, 0x000f0000, 0x000f0000,
1497 0x220, 0xffffffff, 0xc060000c,
1498 0x224, 0xc0000fff, 0x00000100,
1499 0xf90, 0xffffffff, 0x00000100,
1500 0xf98, 0x00000101, 0x00000000,
1501 0x20a8, 0xffffffff, 0x00000104,
1502 0x55e4, 0xff000fff, 0x00000100,
1503 0x30cc, 0xc0000fff, 0x00000104,
1504 0xc1e4, 0x00000001, 0x00000001,
1505 0xd00c, 0xff000ff0, 0x00000100,
1506 0xd80c, 0xff000ff0, 0x00000100
1507};
1508
1509static const u32 godavari_golden_registers[] =
1510{
1511 0x55e4, 0xff607fff, 0xfc000100,
1512 0x6ed8, 0x00010101, 0x00010000,
1513 0x9830, 0xffffffff, 0x00000000,
1514 0x98302, 0xf00fffff, 0x00000400,
1515 0x6130, 0xffffffff, 0x00010000,
1516 0x5bb0, 0x000000f0, 0x00000070,
1517 0x5bc0, 0xf0311fff, 0x80300000,
1518 0x98f8, 0x73773777, 0x12010001,
1519 0x98fc, 0xffffffff, 0x00000010,
1520 0x8030, 0x00001f0f, 0x0000100a,
1521 0x2f48, 0x73773777, 0x12010001,
1522 0x2408, 0x000fffff, 0x000c007f,
1523 0x8a14, 0xf000003f, 0x00000007,
1524 0x8b24, 0xffffffff, 0x00ff0fff,
1525 0x30a04, 0x0000ff0f, 0x00000000,
1526 0x28a4c, 0x07ffffff, 0x06000000,
1527 0x4d8, 0x00000fff, 0x00000100,
1528 0xd014, 0x00010000, 0x00810001,
1529 0xd814, 0x00010000, 0x00810001,
1530 0x3e78, 0x00000001, 0x00000002,
1531 0xc768, 0x00000008, 0x00000008,
1532 0xc770, 0x00000f00, 0x00000800,
1533 0xc774, 0x00000f00, 0x00000800,
1534 0xc798, 0x00ffffff, 0x00ff7fbf,
1535 0xc79c, 0x00ffffff, 0x00ff7faf,
1536 0x8c00, 0x000000ff, 0x00000001,
1537 0x214f8, 0x01ff01ff, 0x00000002,
1538 0x21498, 0x007ff800, 0x00200000,
1539 0x2015c, 0xffffffff, 0x00000f40,
1540 0x88c4, 0x001f3ae3, 0x00000082,
1541 0x88d4, 0x0000001f, 0x00000010,
1542 0x30934, 0xffffffff, 0x00000000
1543};
1544
1545
57e252bf
MN
1546static void cik_init_golden_registers(struct radeon_device *rdev)
1547{
1548 switch (rdev->family) {
1549 case CHIP_BONAIRE:
1550 radeon_program_register_sequence(rdev,
1551 bonaire_mgcg_cgcg_init,
1552 (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));
1553 radeon_program_register_sequence(rdev,
1554 bonaire_golden_registers,
1555 (const u32)ARRAY_SIZE(bonaire_golden_registers));
1556 radeon_program_register_sequence(rdev,
1557 bonaire_golden_common_registers,
1558 (const u32)ARRAY_SIZE(bonaire_golden_common_registers));
1559 radeon_program_register_sequence(rdev,
1560 bonaire_golden_spm_registers,
1561 (const u32)ARRAY_SIZE(bonaire_golden_spm_registers));
1562 break;
1563 case CHIP_KABINI:
1564 radeon_program_register_sequence(rdev,
1565 kalindi_mgcg_cgcg_init,
1566 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
1567 radeon_program_register_sequence(rdev,
1568 kalindi_golden_registers,
1569 (const u32)ARRAY_SIZE(kalindi_golden_registers));
1570 radeon_program_register_sequence(rdev,
1571 kalindi_golden_common_registers,
1572 (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
1573 radeon_program_register_sequence(rdev,
1574 kalindi_golden_spm_registers,
1575 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
1576 break;
c6f73aab
FT
1577 case CHIP_MULLINS:
1578 radeon_program_register_sequence(rdev,
1579 kalindi_mgcg_cgcg_init,
1580 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
1581 radeon_program_register_sequence(rdev,
1582 godavari_golden_registers,
1583 (const u32)ARRAY_SIZE(godavari_golden_registers));
1584 radeon_program_register_sequence(rdev,
1585 kalindi_golden_common_registers,
1586 (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
1587 radeon_program_register_sequence(rdev,
1588 kalindi_golden_spm_registers,
1589 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
1590 break;
57e252bf
MN
1591 case CHIP_KAVERI:
1592 radeon_program_register_sequence(rdev,
1593 spectre_mgcg_cgcg_init,
1594 (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init));
1595 radeon_program_register_sequence(rdev,
1596 spectre_golden_registers,
1597 (const u32)ARRAY_SIZE(spectre_golden_registers));
1598 radeon_program_register_sequence(rdev,
1599 spectre_golden_common_registers,
1600 (const u32)ARRAY_SIZE(spectre_golden_common_registers));
1601 radeon_program_register_sequence(rdev,
1602 spectre_golden_spm_registers,
1603 (const u32)ARRAY_SIZE(spectre_golden_spm_registers));
1604 break;
c6f73aab
FT
1605 case CHIP_HAWAII:
1606 radeon_program_register_sequence(rdev,
1607 hawaii_mgcg_cgcg_init,
1608 (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init));
1609 radeon_program_register_sequence(rdev,
1610 hawaii_golden_registers,
1611 (const u32)ARRAY_SIZE(hawaii_golden_registers));
1612 radeon_program_register_sequence(rdev,
1613 hawaii_golden_common_registers,
1614 (const u32)ARRAY_SIZE(hawaii_golden_common_registers));
1615 radeon_program_register_sequence(rdev,
1616 hawaii_golden_spm_registers,
1617 (const u32)ARRAY_SIZE(hawaii_golden_spm_registers));
1618 break;
57e252bf
MN
1619 default:
1620 break;
1621 }
1622}
1623
1624/**
1625 * cik_get_xclk - get the xclk
1626 *
1627 * @rdev: radeon_device pointer
1628 *
1629 * Returns the reference clock used by the gfx engine
1630 * (CIK).
1631 */
1632u32 cik_get_xclk(struct radeon_device *rdev)
1633{
1634 u32 reference_clock = rdev->clock.spll.reference_freq;
1635
1636 if (rdev->flags & RADEON_IS_IGP) {
1637 if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK)
1638 return reference_clock / 2;
1639 } else {
1640 if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE)
1641 return reference_clock / 4;
1642 }
1643 return reference_clock;
1644}
1645
1646/**
1647 * cik_mm_rdoorbell - read a doorbell dword
1648 *
1649 * @rdev: radeon_device pointer
c6f73aab 1650 * @index: doorbell index
57e252bf
MN
1651 *
1652 * Returns the value in the doorbell aperture at the
c6f73aab 1653 * requested doorbell index (CIK).
57e252bf 1654 */
c6f73aab 1655u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index)
57e252bf 1656{
c6f73aab
FT
1657 if (index < rdev->doorbell.num_doorbells) {
1658 return readl(rdev->doorbell.ptr + index);
57e252bf 1659 } else {
c6f73aab 1660 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
57e252bf
MN
1661 return 0;
1662 }
1663}
1664
1665/**
1666 * cik_mm_wdoorbell - write a doorbell dword
1667 *
1668 * @rdev: radeon_device pointer
c6f73aab 1669 * @index: doorbell index
57e252bf
MN
1670 * @v: value to write
1671 *
1672 * Writes @v to the doorbell aperture at the
c6f73aab 1673 * requested doorbell index (CIK).
57e252bf 1674 */
c6f73aab 1675void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v)
57e252bf 1676{
c6f73aab
FT
1677 if (index < rdev->doorbell.num_doorbells) {
1678 writel(v, rdev->doorbell.ptr + index);
57e252bf 1679 } else {
c6f73aab 1680 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
57e252bf
MN
1681 }
1682}
1683
1684#define BONAIRE_IO_MC_REGS_SIZE 36
1685
1686static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] =
1687{
1688 {0x00000070, 0x04400000},
1689 {0x00000071, 0x80c01803},
1690 {0x00000072, 0x00004004},
1691 {0x00000073, 0x00000100},
1692 {0x00000074, 0x00ff0000},
1693 {0x00000075, 0x34000000},
1694 {0x00000076, 0x08000014},
1695 {0x00000077, 0x00cc08ec},
1696 {0x00000078, 0x00000400},
1697 {0x00000079, 0x00000000},
1698 {0x0000007a, 0x04090000},
1699 {0x0000007c, 0x00000000},
1700 {0x0000007e, 0x4408a8e8},
1701 {0x0000007f, 0x00000304},
1702 {0x00000080, 0x00000000},
1703 {0x00000082, 0x00000001},
1704 {0x00000083, 0x00000002},
1705 {0x00000084, 0xf3e4f400},
1706 {0x00000085, 0x052024e3},
1707 {0x00000087, 0x00000000},
1708 {0x00000088, 0x01000000},
1709 {0x0000008a, 0x1c0a0000},
1710 {0x0000008b, 0xff010000},
1711 {0x0000008d, 0xffffefff},
1712 {0x0000008e, 0xfff3efff},
1713 {0x0000008f, 0xfff3efbf},
1714 {0x00000092, 0xf7ffffff},
1715 {0x00000093, 0xffffff7f},
1716 {0x00000095, 0x00101101},
1717 {0x00000096, 0x00000fff},
1718 {0x00000097, 0x00116fff},
1719 {0x00000098, 0x60010000},
1720 {0x00000099, 0x10010000},
1721 {0x0000009a, 0x00006000},
1722 {0x0000009b, 0x00001000},
1723 {0x0000009f, 0x00b48000}
1724};
1725
c6f73aab
FT
1726#define HAWAII_IO_MC_REGS_SIZE 22
1727
1728static const u32 hawaii_io_mc_regs[HAWAII_IO_MC_REGS_SIZE][2] =
1729{
1730 {0x0000007d, 0x40000000},
1731 {0x0000007e, 0x40180304},
1732 {0x0000007f, 0x0000ff00},
1733 {0x00000081, 0x00000000},
1734 {0x00000083, 0x00000800},
1735 {0x00000086, 0x00000000},
1736 {0x00000087, 0x00000100},
1737 {0x00000088, 0x00020100},
1738 {0x00000089, 0x00000000},
1739 {0x0000008b, 0x00040000},
1740 {0x0000008c, 0x00000100},
1741 {0x0000008e, 0xff010000},
1742 {0x00000090, 0xffffefff},
1743 {0x00000091, 0xfff3efff},
1744 {0x00000092, 0xfff3efbf},
1745 {0x00000093, 0xf7ffffff},
1746 {0x00000094, 0xffffff7f},
1747 {0x00000095, 0x00000fff},
1748 {0x00000096, 0x00116fff},
1749 {0x00000097, 0x60010000},
1750 {0x00000098, 0x10010000},
1751 {0x0000009f, 0x00c79000}
1752};
1753
1754
57e252bf
MN
1755/**
1756 * cik_srbm_select - select specific register instances
1757 *
1758 * @rdev: radeon_device pointer
1759 * @me: selected ME (micro engine)
1760 * @pipe: pipe
1761 * @queue: queue
1762 * @vmid: VMID
1763 *
1764 * Switches the currently active registers instances. Some
1765 * registers are instanced per VMID, others are instanced per
1766 * me/pipe/queue combination.
1767 */
1768static void cik_srbm_select(struct radeon_device *rdev,
1769 u32 me, u32 pipe, u32 queue, u32 vmid)
1770{
1771 u32 srbm_gfx_cntl = (PIPEID(pipe & 0x3) |
1772 MEID(me & 0x3) |
1773 VMID(vmid & 0xf) |
1774 QUEUEID(queue & 0x7));
1775 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl);
1776}
1777
1778/* ucode loading */
1779/**
1780 * ci_mc_load_microcode - load MC ucode into the hw
1781 *
1782 * @rdev: radeon_device pointer
1783 *
1784 * Load the GDDR MC ucode into the hw (CIK).
1785 * Returns 0 on success, error on failure.
1786 */
c6f73aab 1787int ci_mc_load_microcode(struct radeon_device *rdev)
57e252bf 1788{
cb754608
IV
1789 const __be32 *fw_data = NULL;
1790 const __le32 *new_fw_data = NULL;
57e252bf 1791 u32 running, blackout = 0;
cb754608
IV
1792 u32 *io_mc_regs = NULL;
1793 const __le32 *new_io_mc_regs = NULL;
c6f73aab 1794 int i, regs_size, ucode_size;
57e252bf
MN
1795
1796 if (!rdev->mc_fw)
1797 return -EINVAL;
1798
cb754608
IV
1799 if (rdev->new_fw) {
1800 const struct mc_firmware_header_v1_0 *hdr =
1801 (const struct mc_firmware_header_v1_0 *)rdev->mc_fw->data;
c6f73aab 1802
cb754608
IV
1803 radeon_ucode_print_mc_hdr(&hdr->header);
1804
1805 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
1806 new_io_mc_regs = (const __le32 *)
1807 ((const char *)rdev->mc_fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
1808 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1809 new_fw_data = (const __le32 *)
1810 ((const char *)rdev->mc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1811 } else {
1812 ucode_size = rdev->mc_fw->datasize / 4;
1813
1814 switch (rdev->family) {
1815 case CHIP_BONAIRE:
1816 io_mc_regs = (u32 *)&bonaire_io_mc_regs;
1817 regs_size = BONAIRE_IO_MC_REGS_SIZE;
1818 break;
1819 case CHIP_HAWAII:
1820 io_mc_regs = (u32 *)&hawaii_io_mc_regs;
1821 regs_size = HAWAII_IO_MC_REGS_SIZE;
1822 break;
1823 default:
1824 return -EINVAL;
1825 }
1826 fw_data = (const __be32 *)rdev->mc_fw->data;
57e252bf
MN
1827 }
1828
1829 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
1830
1831 if (running == 0) {
1832 if (running) {
1833 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
1834 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
1835 }
1836
1837 /* reset the engine and set to writable */
1838 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1839 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
1840
1841 /* load mc io regs */
1842 for (i = 0; i < regs_size; i++) {
cb754608
IV
1843 if (rdev->new_fw) {
1844 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
1845 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
1846 } else {
1847 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
1848 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
1849 }
57e252bf
MN
1850 }
1851 /* load the MC ucode */
cb754608
IV
1852 for (i = 0; i < ucode_size; i++) {
1853 if (rdev->new_fw)
1854 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
1855 else
1856 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
1857 }
57e252bf
MN
1858
1859 /* put the engine back into the active state */
1860 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1861 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
1862 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
1863
1864 /* wait for training to complete */
1865 for (i = 0; i < rdev->usec_timeout; i++) {
1866 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
1867 break;
c4ef309b 1868 udelay(1);
57e252bf
MN
1869 }
1870 for (i = 0; i < rdev->usec_timeout; i++) {
1871 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
1872 break;
c4ef309b 1873 udelay(1);
57e252bf
MN
1874 }
1875
1876 if (running)
1877 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
1878 }
1879
1880 return 0;
1881}
1882
1883/**
1884 * cik_init_microcode - load ucode images from disk
1885 *
1886 * @rdev: radeon_device pointer
1887 *
1888 * Use the firmware interface to load the ucode images into
1889 * the driver (not loaded into hw).
1890 * Returns 0 on success, error on failure.
1891 */
1892static int cik_init_microcode(struct radeon_device *rdev)
1893{
1894 const char *chip_name;
cb754608 1895 const char *new_chip_name;
57e252bf 1896 size_t pfp_req_size, me_req_size, ce_req_size,
c6f73aab
FT
1897 mec_req_size, rlc_req_size, mc_req_size = 0,
1898 sdma_req_size, smc_req_size = 0, mc2_req_size = 0;
57e252bf 1899 char fw_name[30];
cb754608 1900 int new_fw = 0;
57e252bf 1901 int err;
cb754608 1902 int num_fw;
57e252bf
MN
1903
1904 DRM_DEBUG("\n");
1905
1906 switch (rdev->family) {
1907 case CHIP_BONAIRE:
1908 chip_name = "BONAIRE";
cb754608 1909 new_chip_name = "bonaire";
57e252bf
MN
1910 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1911 me_req_size = CIK_ME_UCODE_SIZE * 4;
1912 ce_req_size = CIK_CE_UCODE_SIZE * 4;
1913 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
1914 rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
c6f73aab
FT
1915 mc_req_size = BONAIRE_MC_UCODE_SIZE * 4;
1916 mc2_req_size = BONAIRE_MC2_UCODE_SIZE * 4;
57e252bf 1917 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
4cd92098 1918 smc_req_size = ALIGN(BONAIRE_SMC_UCODE_SIZE, 4);
cb754608 1919 num_fw = 8;
57e252bf 1920 break;
c6f73aab
FT
1921 case CHIP_HAWAII:
1922 chip_name = "HAWAII";
cb754608 1923 new_chip_name = "hawaii";
c6f73aab
FT
1924 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1925 me_req_size = CIK_ME_UCODE_SIZE * 4;
1926 ce_req_size = CIK_CE_UCODE_SIZE * 4;
1927 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
1928 rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
1929 mc_req_size = HAWAII_MC_UCODE_SIZE * 4;
1930 mc2_req_size = HAWAII_MC2_UCODE_SIZE * 4;
1931 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
1932 smc_req_size = ALIGN(HAWAII_SMC_UCODE_SIZE, 4);
cb754608 1933 num_fw = 8;
c6f73aab 1934 break;
57e252bf
MN
1935 case CHIP_KAVERI:
1936 chip_name = "KAVERI";
cb754608 1937 new_chip_name = "kaveri";
57e252bf
MN
1938 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1939 me_req_size = CIK_ME_UCODE_SIZE * 4;
1940 ce_req_size = CIK_CE_UCODE_SIZE * 4;
1941 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
1942 rlc_req_size = KV_RLC_UCODE_SIZE * 4;
1943 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
cb754608 1944 num_fw = 7;
57e252bf
MN
1945 break;
1946 case CHIP_KABINI:
1947 chip_name = "KABINI";
cb754608 1948 new_chip_name = "kabini";
57e252bf
MN
1949 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1950 me_req_size = CIK_ME_UCODE_SIZE * 4;
1951 ce_req_size = CIK_CE_UCODE_SIZE * 4;
1952 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
1953 rlc_req_size = KB_RLC_UCODE_SIZE * 4;
1954 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
cb754608 1955 num_fw = 6;
57e252bf 1956 break;
c6f73aab
FT
1957 case CHIP_MULLINS:
1958 chip_name = "MULLINS";
cb754608 1959 new_chip_name = "mullins";
c6f73aab
FT
1960 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1961 me_req_size = CIK_ME_UCODE_SIZE * 4;
1962 ce_req_size = CIK_CE_UCODE_SIZE * 4;
1963 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
1964 rlc_req_size = ML_RLC_UCODE_SIZE * 4;
1965 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
cb754608 1966 num_fw = 6;
c6f73aab 1967 break;
57e252bf
MN
1968 default: BUG();
1969 }
1970
cb754608 1971 DRM_INFO("Loading %s Microcode\n", new_chip_name);
57e252bf 1972
cb754608 1973 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", new_chip_name);
71187b16 1974 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
cb754608
IV
1975 if (err) {
1976 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", chip_name);
71187b16 1977 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
cb754608
IV
1978 if (err)
1979 goto out;
1980 if (rdev->pfp_fw->datasize != pfp_req_size) {
1981 printk(KERN_ERR
1982 "cik_cp: Bogus length %zu in firmware \"%s\"\n",
1983 rdev->pfp_fw->datasize, fw_name);
1984 err = -EINVAL;
1985 goto out;
1986 }
1987 } else {
1988 err = radeon_ucode_validate(rdev->pfp_fw);
1989 if (err) {
1990 printk(KERN_ERR
1991 "cik_fw: validation failed for firmware \"%s\"\n",
1992 fw_name);
1993 goto out;
1994 } else {
1995 new_fw++;
1996 }
57e252bf
MN
1997 }
1998
cb754608 1999 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", new_chip_name);
71187b16 2000 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
cb754608
IV
2001 if (err) {
2002 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", chip_name);
71187b16 2003 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
cb754608
IV
2004 if (err)
2005 goto out;
2006 if (rdev->me_fw->datasize != me_req_size) {
2007 printk(KERN_ERR
2008 "cik_cp: Bogus length %zu in firmware \"%s\"\n",
2009 rdev->me_fw->datasize, fw_name);
2010 err = -EINVAL;
2011 }
2012 } else {
2013 err = radeon_ucode_validate(rdev->me_fw);
2014 if (err) {
2015 printk(KERN_ERR
2016 "cik_fw: validation failed for firmware \"%s\"\n",
2017 fw_name);
2018 goto out;
2019 } else {
2020 new_fw++;
2021 }
57e252bf
MN
2022 }
2023
cb754608 2024 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_ce", new_chip_name);
71187b16 2025 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
cb754608
IV
2026 if (err) {
2027 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_ce", chip_name);
71187b16 2028 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
cb754608
IV
2029 if (err)
2030 goto out;
2031 if (rdev->ce_fw->datasize != ce_req_size) {
2032 printk(KERN_ERR
2033 "cik_cp: Bogus length %zu in firmware \"%s\"\n",
2034 rdev->ce_fw->datasize, fw_name);
2035 err = -EINVAL;
2036 }
2037 } else {
2038 err = radeon_ucode_validate(rdev->ce_fw);
2039 if (err) {
2040 printk(KERN_ERR
2041 "cik_fw: validation failed for firmware \"%s\"\n",
2042 fw_name);
2043 goto out;
2044 } else {
2045 new_fw++;
2046 }
57e252bf
MN
2047 }
2048
cb754608 2049 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_mec", new_chip_name);
71187b16 2050 err = request_firmware(&rdev->mec_fw, fw_name, rdev->dev);
cb754608
IV
2051 if (err) {
2052 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_mec", chip_name);
71187b16 2053 err = request_firmware(&rdev->mec_fw, fw_name, rdev->dev);
cb754608
IV
2054 if (err)
2055 goto out;
2056 if (rdev->mec_fw->datasize != mec_req_size) {
2057 printk(KERN_ERR
2058 "cik_cp: Bogus length %zu in firmware \"%s\"\n",
2059 rdev->mec_fw->datasize, fw_name);
2060 err = -EINVAL;
2061 }
2062 } else {
2063 err = radeon_ucode_validate(rdev->mec_fw);
2064 if (err) {
2065 printk(KERN_ERR
2066 "cik_fw: validation failed for firmware \"%s\"\n",
2067 fw_name);
2068 goto out;
2069 } else {
2070 new_fw++;
2071 }
2072 }
2073
2074 if (rdev->family == CHIP_KAVERI) {
2075 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_mec2", new_chip_name);
71187b16 2076 err = request_firmware(&rdev->mec2_fw, fw_name, rdev->dev);
cb754608
IV
2077 if (err) {
2078 goto out;
2079 } else {
2080 err = radeon_ucode_validate(rdev->mec2_fw);
2081 if (err) {
2082 goto out;
2083 } else {
2084 new_fw++;
2085 }
2086 }
57e252bf
MN
2087 }
2088
cb754608 2089 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_rlc", new_chip_name);
71187b16 2090 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
cb754608
IV
2091 if (err) {
2092 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_rlc", chip_name);
71187b16 2093 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
cb754608
IV
2094 if (err)
2095 goto out;
2096 if (rdev->rlc_fw->datasize != rlc_req_size) {
2097 printk(KERN_ERR
2098 "cik_rlc: Bogus length %zu in firmware \"%s\"\n",
2099 rdev->rlc_fw->datasize, fw_name);
2100 err = -EINVAL;
2101 }
2102 } else {
2103 err = radeon_ucode_validate(rdev->rlc_fw);
2104 if (err) {
2105 printk(KERN_ERR
2106 "cik_fw: validation failed for firmware \"%s\"\n",
2107 fw_name);
2108 goto out;
2109 } else {
2110 new_fw++;
2111 }
57e252bf
MN
2112 }
2113
cb754608 2114 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_sdma", new_chip_name);
71187b16 2115 err = request_firmware(&rdev->sdma_fw, fw_name, rdev->dev);
cb754608
IV
2116 if (err) {
2117 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_sdma", chip_name);
71187b16 2118 err = request_firmware(&rdev->sdma_fw, fw_name, rdev->dev);
cb754608
IV
2119 if (err)
2120 goto out;
2121 if (rdev->sdma_fw->datasize != sdma_req_size) {
2122 printk(KERN_ERR
2123 "cik_sdma: Bogus length %zu in firmware \"%s\"\n",
2124 rdev->sdma_fw->datasize, fw_name);
2125 err = -EINVAL;
2126 }
2127 } else {
2128 err = radeon_ucode_validate(rdev->sdma_fw);
2129 if (err) {
2130 printk(KERN_ERR
2131 "cik_fw: validation failed for firmware \"%s\"\n",
2132 fw_name);
2133 goto out;
2134 } else {
2135 new_fw++;
2136 }
57e252bf
MN
2137 }
2138
4cd92098 2139 /* No SMC, MC ucode on APUs */
57e252bf 2140 if (!(rdev->flags & RADEON_IS_IGP)) {
cb754608 2141 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_mc", new_chip_name);
71187b16 2142 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
c6f73aab 2143 if (err) {
cb754608 2144 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_mc2", chip_name);
71187b16 2145 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
cb754608
IV
2146 if (err) {
2147 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_mc", chip_name);
71187b16 2148 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
cb754608
IV
2149 if (err)
2150 goto out;
2151 }
2152 if ((rdev->mc_fw->datasize != mc_req_size) &&
2153 (rdev->mc_fw->datasize != mc2_req_size)){
2154 printk(KERN_ERR
2155 "cik_mc: Bogus length %zu in firmware \"%s\"\n",
2156 rdev->mc_fw->datasize, fw_name);
2157 err = -EINVAL;
2158 }
2159 DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->datasize);
2160 } else {
2161 err = radeon_ucode_validate(rdev->mc_fw);
2162 if (err) {
2163 printk(KERN_ERR
2164 "cik_fw: validation failed for firmware \"%s\"\n",
2165 fw_name);
c6f73aab 2166 goto out;
cb754608
IV
2167 } else {
2168 new_fw++;
2169 }
c6f73aab 2170 }
4cd92098 2171
cb754608 2172 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_smc", new_chip_name);
71187b16 2173 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
4cd92098 2174 if (err) {
cb754608 2175 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_smc", chip_name);
71187b16 2176 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
cb754608
IV
2177 if (err) {
2178 printk(KERN_ERR
2179 "smc: error loading firmware \"%s\"\n",
2180 fw_name);
2181 release_firmware(rdev->smc_fw);
2182 rdev->smc_fw = NULL;
2183 err = 0;
2184 } else if (rdev->smc_fw->datasize != smc_req_size) {
2185 printk(KERN_ERR
2186 "cik_smc: Bogus length %zu in firmware \"%s\"\n",
2187 rdev->smc_fw->datasize, fw_name);
2188 err = -EINVAL;
2189 }
2190 } else {
2191 err = radeon_ucode_validate(rdev->smc_fw);
2192 if (err) {
2193 printk(KERN_ERR
2194 "cik_fw: validation failed for firmware \"%s\"\n",
2195 fw_name);
2196 goto out;
2197 } else {
2198 new_fw++;
2199 }
4cd92098 2200 }
57e252bf
MN
2201 }
2202
cb754608
IV
2203 if (new_fw == 0) {
2204 rdev->new_fw = false;
2205 } else if (new_fw < num_fw) {
2206 printk(KERN_ERR "ci_fw: mixing new and old firmware!\n");
2207 err = -EINVAL;
2208 } else {
2209 rdev->new_fw = true;
2210 }
2211
57e252bf
MN
2212out:
2213 if (err) {
2214 if (err != -EINVAL)
2215 printk(KERN_ERR
2216 "cik_cp: Failed to load firmware \"%s\"\n",
2217 fw_name);
fcd4983f 2218 release_firmware(rdev->pfp_fw);
2219 rdev->pfp_fw = NULL;
2220 release_firmware(rdev->me_fw);
2221 rdev->me_fw = NULL;
2222 release_firmware(rdev->ce_fw);
2223 rdev->ce_fw = NULL;
2224 release_firmware(rdev->mec_fw);
2225 rdev->mec_fw = NULL;
cb754608
IV
2226 release_firmware(rdev->mec2_fw);
2227 rdev->mec2_fw = NULL;
fcd4983f 2228 release_firmware(rdev->rlc_fw);
2229 rdev->rlc_fw = NULL;
2230 release_firmware(rdev->sdma_fw);
2231 rdev->sdma_fw = NULL;
2232 release_firmware(rdev->mc_fw);
2233 rdev->mc_fw = NULL;
4cd92098 2234 release_firmware(rdev->smc_fw);
2235 rdev->smc_fw = NULL;
57e252bf
MN
2236 }
2237 return err;
2238}
2239
63a766bf 2240/**
2241 * cik_fini_microcode - drop the firmwares image references
2242 *
2243 * @rdev: radeon_device pointer
2244 *
2245 * Drop the pfp, me, mec, mec2, rlc, sdma, mc, smc and ce firmware image references.
2246 * Called at driver shutdown.
2247 */
2248static void cik_fini_microcode(struct radeon_device *rdev)
2249{
2250 release_firmware(rdev->pfp_fw);
2251 rdev->pfp_fw = NULL;
2252 release_firmware(rdev->me_fw);
2253 rdev->me_fw = NULL;
2254 release_firmware(rdev->ce_fw);
2255 rdev->ce_fw = NULL;
2256 release_firmware(rdev->mec_fw);
2257 rdev->mec_fw = NULL;
2258 release_firmware(rdev->mec2_fw);
2259 rdev->mec2_fw = NULL;
2260 release_firmware(rdev->rlc_fw);
2261 rdev->rlc_fw = NULL;
2262 release_firmware(rdev->sdma_fw);
2263 rdev->sdma_fw = NULL;
2264 release_firmware(rdev->mc_fw);
2265 rdev->mc_fw = NULL;
2266 release_firmware(rdev->smc_fw);
2267 rdev->smc_fw = NULL;
2268}
2269
57e252bf
MN
2270/*
2271 * Core functions
2272 */
2273/**
2274 * cik_tiling_mode_table_init - init the hw tiling table
2275 *
2276 * @rdev: radeon_device pointer
2277 *
2278 * Starting with SI, the tiling setup is done globally in a
2279 * set of 32 tiling modes. Rather than selecting each set of
2280 * parameters per surface as on older asics, we just select
2281 * which index in the tiling table we want to use, and the
2282 * surface uses those parameters (CIK).
2283 */
2284static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2285{
2286 const u32 num_tile_mode_states = 32;
2287 const u32 num_secondary_tile_mode_states = 16;
2288 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
2289 u32 num_pipe_configs;
2290 u32 num_rbs = rdev->config.cik.max_backends_per_se *
2291 rdev->config.cik.max_shader_engines;
2292
2293 switch (rdev->config.cik.mem_row_size_in_kb) {
2294 case 1:
2295 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
2296 break;
2297 case 2:
2298 default:
2299 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
2300 break;
2301 case 4:
2302 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
2303 break;
2304 }
2305
2306 num_pipe_configs = rdev->config.cik.max_tile_pipes;
2307 if (num_pipe_configs > 8)
c6f73aab 2308 num_pipe_configs = 16;
57e252bf 2309
c6f73aab 2310 if (num_pipe_configs == 16) {
57e252bf
MN
2311 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2312 switch (reg_offset) {
2313 case 0:
2314 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2315 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
c6f73aab 2316 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
57e252bf
MN
2317 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2318 break;
2319 case 1:
2320 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2321 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
c6f73aab 2322 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
57e252bf
MN
2323 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2324 break;
2325 case 2:
2326 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2327 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
c6f73aab 2328 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
57e252bf
MN
2329 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2330 break;
2331 case 3:
2332 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2333 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
c6f73aab 2334 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
57e252bf
MN
2335 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2336 break;
2337 case 4:
2338 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2339 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
c6f73aab 2340 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
57e252bf
MN
2341 TILE_SPLIT(split_equal_to_row_size));
2342 break;
2343 case 5:
2344 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
c6f73aab 2345 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
57e252bf
MN
2346 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2347 break;
2348 case 6:
2349 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2350 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
c6f73aab 2351 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
57e252bf
MN
2352 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2353 break;
2354 case 7:
2355 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2356 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
c6f73aab 2357 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
57e252bf
MN
2358 TILE_SPLIT(split_equal_to_row_size));
2359 break;
2360 case 8:
2361 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
c6f73aab 2362 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
57e252bf
MN
2363 break;
2364 case 9:
2365 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
c6f73aab 2366 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
57e252bf
MN
2367 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2368 break;
2369 case 10:
2370 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2371 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
c6f73aab 2372 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
57e252bf
MN
2373 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2374 break;
2375 case 11:
2376 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2377 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
c6f73aab 2378 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
57e252bf
MN
2379 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2380 break;
2381 case 12:
2382 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2383 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
c6f73aab 2384 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
57e252bf
MN
2385 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2386 break;
2387 case 13:
2388 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
c6f73aab 2389 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
57e252bf
MN
2390 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2391 break;
2392 case 14:
2393 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2394 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
c6f73aab 2395 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
57e252bf
MN
2396 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2397 break;
2398 case 16:
2399 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2400 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
c6f73aab 2401 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
57e252bf
MN
2402 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2403 break;
2404 case 17:
2405 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2406 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
c6f73aab 2407 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
57e252bf
MN
2408 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2409 break;
2410 case 27:
2411 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
c6f73aab 2412 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
57e252bf
MN
2413 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2414 break;
2415 case 28:
2416 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2417 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
c6f73aab 2418 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
57e252bf
MN
2419 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2420 break;
2421 case 29:
2422 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2423 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
c6f73aab 2424 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
57e252bf
MN
2425 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2426 break;
2427 case 30:
2428 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2429 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
c6f73aab 2430 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
57e252bf
MN
2431 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2432 break;
2433 default:
2434 gb_tile_moden = 0;
2435 break;
2436 }
2437 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
2438 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2439 }
2440 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
2441 switch (reg_offset) {
2442 case 0:
2443 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2444 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
c6f73aab 2445 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
57e252bf
MN
2446 NUM_BANKS(ADDR_SURF_16_BANK));
2447 break;
2448 case 1:
2449 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2450 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2451 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2452 NUM_BANKS(ADDR_SURF_16_BANK));
2453 break;
2454 case 2:
2455 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2456 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
c6f73aab 2457 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
57e252bf
MN
2458 NUM_BANKS(ADDR_SURF_16_BANK));
2459 break;
2460 case 3:
2461 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2462 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
c6f73aab 2463 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
57e252bf
MN
2464 NUM_BANKS(ADDR_SURF_16_BANK));
2465 break;
2466 case 4:
2467 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2468 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2469 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2470 NUM_BANKS(ADDR_SURF_8_BANK));
2471 break;
2472 case 5:
2473 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2474 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2475 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2476 NUM_BANKS(ADDR_SURF_4_BANK));
2477 break;
2478 case 6:
2479 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2480 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2481 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2482 NUM_BANKS(ADDR_SURF_2_BANK));
2483 break;
2484 case 8:
2485 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
c6f73aab
FT
2486 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2487 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
57e252bf
MN
2488 NUM_BANKS(ADDR_SURF_16_BANK));
2489 break;
2490 case 9:
2491 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
c6f73aab
FT
2492 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2493 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
57e252bf
MN
2494 NUM_BANKS(ADDR_SURF_16_BANK));
2495 break;
2496 case 10:
2497 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
c6f73aab
FT
2498 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2499 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
57e252bf
MN
2500 NUM_BANKS(ADDR_SURF_16_BANK));
2501 break;
2502 case 11:
2503 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2504 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
c6f73aab
FT
2505 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2506 NUM_BANKS(ADDR_SURF_8_BANK));
57e252bf
MN
2507 break;
2508 case 12:
2509 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2510 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2511 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
c6f73aab 2512 NUM_BANKS(ADDR_SURF_4_BANK));
57e252bf
MN
2513 break;
2514 case 13:
2515 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2516 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2517 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
c6f73aab 2518 NUM_BANKS(ADDR_SURF_2_BANK));
57e252bf
MN
2519 break;
2520 case 14:
2521 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2524 NUM_BANKS(ADDR_SURF_2_BANK));
2525 break;
2526 default:
2527 gb_tile_moden = 0;
2528 break;
2529 }
c6f73aab 2530 rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
57e252bf
MN
2531 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2532 }
c6f73aab
FT
2533 } else if (num_pipe_configs == 8) {
2534 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2535 switch (reg_offset) {
2536 case 0:
2537 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2538 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2539 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2540 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2541 break;
2542 case 1:
2543 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2544 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2545 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2546 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2547 break;
2548 case 2:
2549 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2550 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2551 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2552 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2553 break;
2554 case 3:
2555 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2556 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2557 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2558 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2559 break;
2560 case 4:
2561 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2562 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2563 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2564 TILE_SPLIT(split_equal_to_row_size));
2565 break;
2566 case 5:
2567 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2568 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2569 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2570 break;
2571 case 6:
2572 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2573 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2574 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2575 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2576 break;
2577 case 7:
2578 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2579 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2580 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2581 TILE_SPLIT(split_equal_to_row_size));
2582 break;
2583 case 8:
2584 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2585 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2586 break;
2587 case 9:
2588 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2589 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2590 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2591 break;
2592 case 10:
2593 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2594 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2595 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2596 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2597 break;
2598 case 11:
2599 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2600 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2601 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2602 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2603 break;
2604 case 12:
2605 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2606 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2607 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2608 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2609 break;
2610 case 13:
2611 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2612 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2613 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2614 break;
2615 case 14:
2616 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2617 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2618 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2619 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2620 break;
2621 case 16:
2622 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2623 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2624 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2625 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2626 break;
2627 case 17:
2628 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2629 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2630 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2631 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2632 break;
2633 case 27:
2634 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2635 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2636 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2637 break;
2638 case 28:
2639 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2640 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2641 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2642 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2643 break;
2644 case 29:
2645 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2646 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2647 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2648 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2649 break;
2650 case 30:
2651 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2652 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2653 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2654 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2655 break;
2656 default:
2657 gb_tile_moden = 0;
2658 break;
2659 }
2660 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
2661 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2662 }
2663 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
2664 switch (reg_offset) {
2665 case 0:
2666 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2667 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2668 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2669 NUM_BANKS(ADDR_SURF_16_BANK));
2670 break;
2671 case 1:
2672 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2673 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2674 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2675 NUM_BANKS(ADDR_SURF_16_BANK));
2676 break;
2677 case 2:
2678 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2679 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2680 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2681 NUM_BANKS(ADDR_SURF_16_BANK));
2682 break;
2683 case 3:
2684 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2685 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2686 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2687 NUM_BANKS(ADDR_SURF_16_BANK));
2688 break;
2689 case 4:
2690 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2691 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2692 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2693 NUM_BANKS(ADDR_SURF_8_BANK));
2694 break;
2695 case 5:
2696 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2697 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2698 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2699 NUM_BANKS(ADDR_SURF_4_BANK));
2700 break;
2701 case 6:
2702 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2703 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2704 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2705 NUM_BANKS(ADDR_SURF_2_BANK));
2706 break;
2707 case 8:
2708 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2709 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2710 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2711 NUM_BANKS(ADDR_SURF_16_BANK));
2712 break;
2713 case 9:
2714 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2715 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2716 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2717 NUM_BANKS(ADDR_SURF_16_BANK));
2718 break;
2719 case 10:
2720 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2721 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2722 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2723 NUM_BANKS(ADDR_SURF_16_BANK));
2724 break;
2725 case 11:
2726 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2727 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2728 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2729 NUM_BANKS(ADDR_SURF_16_BANK));
2730 break;
2731 case 12:
2732 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2733 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2734 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2735 NUM_BANKS(ADDR_SURF_8_BANK));
2736 break;
2737 case 13:
2738 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2739 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2740 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2741 NUM_BANKS(ADDR_SURF_4_BANK));
2742 break;
2743 case 14:
2744 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2745 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2746 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2747 NUM_BANKS(ADDR_SURF_2_BANK));
2748 break;
2749 default:
2750 gb_tile_moden = 0;
2751 break;
2752 }
2753 rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
2754 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2755 }
2756 } else if (num_pipe_configs == 4) {
2757 if (num_rbs == 4) {
2758 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2759 switch (reg_offset) {
2760 case 0:
2761 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2762 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2763 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2764 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2765 break;
2766 case 1:
2767 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2768 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2769 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2770 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2771 break;
2772 case 2:
2773 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2774 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2775 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2776 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2777 break;
2778 case 3:
57e252bf
MN
2779 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2780 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2781 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2782 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2783 break;
2784 case 4:
2785 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2786 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2787 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2788 TILE_SPLIT(split_equal_to_row_size));
2789 break;
2790 case 5:
2791 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
c6f73aab 2792 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
57e252bf
MN
2793 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2794 break;
2795 case 6:
2796 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2797 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2798 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2799 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2800 break;
2801 case 7:
2802 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2803 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2804 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2805 TILE_SPLIT(split_equal_to_row_size));
2806 break;
2807 case 8:
2808 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2809 PIPE_CONFIG(ADDR_SURF_P4_16x16));
2810 break;
2811 case 9:
2812 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
c6f73aab 2813 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
57e252bf
MN
2814 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2815 break;
2816 case 10:
2817 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2818 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2819 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2820 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2821 break;
2822 case 11:
2823 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2824 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2825 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2826 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2827 break;
2828 case 12:
2829 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2830 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2831 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2832 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2833 break;
2834 case 13:
2835 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
c6f73aab 2836 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
57e252bf
MN
2837 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2838 break;
2839 case 14:
2840 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2841 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2842 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2843 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2844 break;
2845 case 16:
2846 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2847 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2848 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2849 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2850 break;
2851 case 17:
2852 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2853 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2854 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2855 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2856 break;
2857 case 27:
2858 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
c6f73aab 2859 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
57e252bf
MN
2860 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2861 break;
2862 case 28:
2863 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2864 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2865 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2866 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2867 break;
2868 case 29:
2869 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2870 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2871 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2872 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2873 break;
2874 case 30:
2875 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2876 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2877 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2878 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2879 break;
2880 default:
2881 gb_tile_moden = 0;
2882 break;
2883 }
2884 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
2885 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2886 }
2887 } else if (num_rbs < 4) {
2888 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2889 switch (reg_offset) {
2890 case 0:
2891 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2892 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2893 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2894 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2895 break;
2896 case 1:
2897 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2898 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2899 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2900 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2901 break;
2902 case 2:
2903 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2904 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2905 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2906 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2907 break;
2908 case 3:
2909 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2910 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2911 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2912 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2913 break;
2914 case 4:
2915 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2916 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2917 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2918 TILE_SPLIT(split_equal_to_row_size));
2919 break;
2920 case 5:
2921 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
c6f73aab 2922 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
57e252bf
MN
2923 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2924 break;
2925 case 6:
2926 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2927 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2928 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2929 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2930 break;
2931 case 7:
2932 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2933 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2934 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2935 TILE_SPLIT(split_equal_to_row_size));
2936 break;
2937 case 8:
2938 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2939 PIPE_CONFIG(ADDR_SURF_P4_8x16));
2940 break;
2941 case 9:
2942 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
c6f73aab 2943 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
57e252bf
MN
2944 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2945 break;
2946 case 10:
2947 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2948 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2949 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2950 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2951 break;
2952 case 11:
2953 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2954 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2955 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2956 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2957 break;
2958 case 12:
2959 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2960 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2961 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2962 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2963 break;
2964 case 13:
2965 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
c6f73aab 2966 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
57e252bf
MN
2967 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2968 break;
2969 case 14:
2970 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2971 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2972 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2973 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2974 break;
2975 case 16:
2976 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
c4ef309b 2977 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2978 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2979 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
57e252bf
MN
2980 break;
2981 case 17:
2982 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
c4ef309b 2983 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2984 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2985 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
57e252bf
MN
2986 break;
2987 case 27:
2988 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
c6f73aab 2989 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
c4ef309b 2990 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
57e252bf
MN
2991 break;
2992 case 28:
2993 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
c4ef309b 2994 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2995 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2996 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
57e252bf
MN
2997 break;
2998 case 29:
2999 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
c4ef309b 3000 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3001 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3002 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
57e252bf
MN
3003 break;
3004 case 30:
3005 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
c4ef309b 3006 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3007 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3008 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
57e252bf
MN
3009 break;
3010 default:
3011 gb_tile_moden = 0;
3012 break;
3013 }
3014 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
3015 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
3016 }
3017 }
3018 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
3019 switch (reg_offset) {
c4ef309b 3020 case 0:
3021 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3022 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3023 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3024 NUM_BANKS(ADDR_SURF_16_BANK));
3025 break;
3026 case 1:
3027 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3028 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3029 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3030 NUM_BANKS(ADDR_SURF_16_BANK));
3031 break;
3032 case 2:
3033 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3034 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3035 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3036 NUM_BANKS(ADDR_SURF_16_BANK));
3037 break;
3038 case 3:
3039 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3040 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3041 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3042 NUM_BANKS(ADDR_SURF_16_BANK));
3043 break;
3044 case 4:
3045 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3046 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3047 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3048 NUM_BANKS(ADDR_SURF_16_BANK));
3049 break;
3050 case 5:
3051 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3052 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3053 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3054 NUM_BANKS(ADDR_SURF_8_BANK));
3055 break;
3056 case 6:
3057 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3058 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3059 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3060 NUM_BANKS(ADDR_SURF_4_BANK));
3061 break;
3062 case 8:
3063 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3064 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3065 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3066 NUM_BANKS(ADDR_SURF_16_BANK));
3067 break;
3068 case 9:
3069 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3070 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3071 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3072 NUM_BANKS(ADDR_SURF_16_BANK));
3073 break;
3074 case 10:
3075 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3076 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3077 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3078 NUM_BANKS(ADDR_SURF_16_BANK));
3079 break;
3080 case 11:
3081 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3082 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3083 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3084 NUM_BANKS(ADDR_SURF_16_BANK));
3085 break;
3086 case 12:
3087 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3088 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3089 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3090 NUM_BANKS(ADDR_SURF_16_BANK));
3091 break;
3092 case 13:
3093 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3094 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3095 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3096 NUM_BANKS(ADDR_SURF_8_BANK));
3097 break;
3098 case 14:
3099 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3100 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3101 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3102 NUM_BANKS(ADDR_SURF_4_BANK));
3103 break;
3104 default:
3105 gb_tile_moden = 0;
3106 break;
57e252bf 3107 }
c6f73aab 3108 rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
57e252bf
MN
3109 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
3110 }
3111 } else if (num_pipe_configs == 2) {
3112 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
3113 switch (reg_offset) {
c4ef309b 3114 case 0:
3115 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3116 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
3117 PIPE_CONFIG(ADDR_SURF_P2) |
3118 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
3119 break;
3120 case 1:
3121 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3122 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
3123 PIPE_CONFIG(ADDR_SURF_P2) |
3124 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
3125 break;
3126 case 2:
3127 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3128 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
3129 PIPE_CONFIG(ADDR_SURF_P2) |
3130 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
3131 break;
3132 case 3:
3133 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3134 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
3135 PIPE_CONFIG(ADDR_SURF_P2) |
3136 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
3137 break;
3138 case 4:
3139 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3140 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
3141 PIPE_CONFIG(ADDR_SURF_P2) |
3142 TILE_SPLIT(split_equal_to_row_size));
3143 break;
3144 case 5:
3145 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
c6f73aab 3146 PIPE_CONFIG(ADDR_SURF_P2) |
c4ef309b 3147 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3148 break;
3149 case 6:
3150 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3151 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
3152 PIPE_CONFIG(ADDR_SURF_P2) |
3153 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
3154 break;
3155 case 7:
3156 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3157 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
3158 PIPE_CONFIG(ADDR_SURF_P2) |
3159 TILE_SPLIT(split_equal_to_row_size));
3160 break;
3161 case 8:
c6f73aab
FT
3162 gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3163 PIPE_CONFIG(ADDR_SURF_P2);
c4ef309b 3164 break;
3165 case 9:
3166 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
c6f73aab
FT
3167 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3168 PIPE_CONFIG(ADDR_SURF_P2));
c4ef309b 3169 break;
3170 case 10:
3171 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3172 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3173 PIPE_CONFIG(ADDR_SURF_P2) |
3174 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3175 break;
3176 case 11:
3177 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3178 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3179 PIPE_CONFIG(ADDR_SURF_P2) |
3180 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3181 break;
3182 case 12:
3183 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3184 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3185 PIPE_CONFIG(ADDR_SURF_P2) |
3186 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3187 break;
3188 case 13:
3189 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
c6f73aab 3190 PIPE_CONFIG(ADDR_SURF_P2) |
c4ef309b 3191 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
3192 break;
3193 case 14:
3194 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3195 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3196 PIPE_CONFIG(ADDR_SURF_P2) |
3197 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3198 break;
3199 case 16:
3200 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3201 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3202 PIPE_CONFIG(ADDR_SURF_P2) |
3203 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3204 break;
3205 case 17:
3206 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3207 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3208 PIPE_CONFIG(ADDR_SURF_P2) |
3209 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3210 break;
3211 case 27:
3212 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
c6f73aab
FT
3213 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3214 PIPE_CONFIG(ADDR_SURF_P2));
c4ef309b 3215 break;
3216 case 28:
3217 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3218 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3219 PIPE_CONFIG(ADDR_SURF_P2) |
3220 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3221 break;
3222 case 29:
3223 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3224 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3225 PIPE_CONFIG(ADDR_SURF_P2) |
3226 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3227 break;
3228 case 30:
3229 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3230 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3231 PIPE_CONFIG(ADDR_SURF_P2) |
3232 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3233 break;
3234 default:
3235 gb_tile_moden = 0;
3236 break;
57e252bf
MN
3237 }
3238 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
3239 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
3240 }
3241 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
3242 switch (reg_offset) {
c4ef309b 3243 case 0:
3244 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3245 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3246 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3247 NUM_BANKS(ADDR_SURF_16_BANK));
3248 break;
3249 case 1:
3250 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3251 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3252 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3253 NUM_BANKS(ADDR_SURF_16_BANK));
3254 break;
3255 case 2:
3256 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3257 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3258 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3259 NUM_BANKS(ADDR_SURF_16_BANK));
3260 break;
3261 case 3:
3262 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3263 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3264 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3265 NUM_BANKS(ADDR_SURF_16_BANK));
3266 break;
3267 case 4:
3268 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3269 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3270 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3271 NUM_BANKS(ADDR_SURF_16_BANK));
3272 break;
3273 case 5:
3274 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3275 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3276 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3277 NUM_BANKS(ADDR_SURF_16_BANK));
3278 break;
3279 case 6:
3280 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3281 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3282 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3283 NUM_BANKS(ADDR_SURF_8_BANK));
3284 break;
3285 case 8:
3286 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3287 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3288 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3289 NUM_BANKS(ADDR_SURF_16_BANK));
3290 break;
3291 case 9:
3292 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3293 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3294 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3295 NUM_BANKS(ADDR_SURF_16_BANK));
3296 break;
3297 case 10:
3298 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3299 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3300 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3301 NUM_BANKS(ADDR_SURF_16_BANK));
3302 break;
3303 case 11:
3304 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3305 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3306 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3307 NUM_BANKS(ADDR_SURF_16_BANK));
3308 break;
3309 case 12:
3310 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3311 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3312 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3313 NUM_BANKS(ADDR_SURF_16_BANK));
3314 break;
3315 case 13:
3316 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3317 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3318 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3319 NUM_BANKS(ADDR_SURF_16_BANK));
3320 break;
3321 case 14:
3322 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3323 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3324 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3325 NUM_BANKS(ADDR_SURF_8_BANK));
3326 break;
3327 default:
3328 gb_tile_moden = 0;
3329 break;
57e252bf 3330 }
c6f73aab 3331 rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
57e252bf
MN
3332 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
3333 }
3334 } else
3335 DRM_ERROR("unknown num pipe config: 0x%x\n", num_pipe_configs);
3336}
3337
3338/**
3339 * cik_select_se_sh - select which SE, SH to address
3340 *
3341 * @rdev: radeon_device pointer
3342 * @se_num: shader engine to address
3343 * @sh_num: sh block to address
3344 *
3345 * Select which SE, SH combinations to address. Certain
3346 * registers are instanced per SE or SH. 0xffffffff means
3347 * broadcast to all SEs or SHs (CIK).
3348 */
3349static void cik_select_se_sh(struct radeon_device *rdev,
c4ef309b 3350 u32 se_num, u32 sh_num)
57e252bf
MN
3351{
3352 u32 data = INSTANCE_BROADCAST_WRITES;
3353
3354 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
3355 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
3356 else if (se_num == 0xffffffff)
3357 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
3358 else if (sh_num == 0xffffffff)
3359 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
3360 else
3361 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
3362 WREG32(GRBM_GFX_INDEX, data);
3363}
3364
3365/**
3366 * cik_create_bitmask - create a bitmask
3367 *
3368 * @bit_width: length of the mask
3369 *
3370 * create a variable length bit mask (CIK).
3371 * Returns the bitmask.
3372 */
3373static u32 cik_create_bitmask(u32 bit_width)
3374{
3375 u32 i, mask = 0;
3376
3377 for (i = 0; i < bit_width; i++) {
3378 mask <<= 1;
3379 mask |= 1;
3380 }
3381 return mask;
3382}
3383
3384/**
c6f73aab 3385 * cik_get_rb_disabled - computes the mask of disabled RBs
57e252bf
MN
3386 *
3387 * @rdev: radeon_device pointer
3388 * @max_rb_num: max RBs (render backends) for the asic
3389 * @se_num: number of SEs (shader engines) for the asic
3390 * @sh_per_se: number of SH blocks per SE for the asic
3391 *
3392 * Calculates the bitmask of disabled RBs (CIK).
3393 * Returns the disabled RB bitmask.
3394 */
3395static u32 cik_get_rb_disabled(struct radeon_device *rdev,
c6f73aab 3396 u32 max_rb_num_per_se,
c4ef309b 3397 u32 sh_per_se)
57e252bf
MN
3398{
3399 u32 data, mask;
3400
3401 data = RREG32(CC_RB_BACKEND_DISABLE);
3402 if (data & 1)
3403 data &= BACKEND_DISABLE_MASK;
3404 else
3405 data = 0;
3406 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
3407
3408 data >>= BACKEND_DISABLE_SHIFT;
3409
c6f73aab 3410 mask = cik_create_bitmask(max_rb_num_per_se / sh_per_se);
57e252bf
MN
3411
3412 return data & mask;
3413}
3414
3415/**
3416 * cik_setup_rb - setup the RBs on the asic
3417 *
3418 * @rdev: radeon_device pointer
3419 * @se_num: number of SEs (shader engines) for the asic
3420 * @sh_per_se: number of SH blocks per SE for the asic
3421 * @max_rb_num: max RBs (render backends) for the asic
3422 *
3423 * Configures per-SE/SH RB registers (CIK).
3424 */
3425static void cik_setup_rb(struct radeon_device *rdev,
c4ef309b 3426 u32 se_num, u32 sh_per_se,
c6f73aab 3427 u32 max_rb_num_per_se)
57e252bf
MN
3428{
3429 int i, j;
3430 u32 data, mask;
3431 u32 disabled_rbs = 0;
3432 u32 enabled_rbs = 0;
3433
3434 for (i = 0; i < se_num; i++) {
3435 for (j = 0; j < sh_per_se; j++) {
3436 cik_select_se_sh(rdev, i, j);
c6f73aab
FT
3437 data = cik_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
3438 if (rdev->family == CHIP_HAWAII)
3439 disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);
3440 else
3441 disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH);
57e252bf
MN
3442 }
3443 }
3444 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3445
3446 mask = 1;
c6f73aab 3447 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
57e252bf
MN
3448 if (!(disabled_rbs & mask))
3449 enabled_rbs |= mask;
3450 mask <<= 1;
3451 }
3452
c6f73aab
FT
3453 rdev->config.cik.backend_enable_mask = enabled_rbs;
3454
57e252bf
MN
3455 for (i = 0; i < se_num; i++) {
3456 cik_select_se_sh(rdev, i, 0xffffffff);
3457 data = 0;
3458 for (j = 0; j < sh_per_se; j++) {
3459 switch (enabled_rbs & 3) {
c6f73aab
FT
3460 case 0:
3461 if (j == 0)
3462 data |= PKR_MAP(RASTER_CONFIG_RB_MAP_3);
3463 else
3464 data |= PKR_MAP(RASTER_CONFIG_RB_MAP_0);
3465 break;
c4ef309b 3466 case 1:
3467 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
3468 break;
3469 case 2:
3470 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
3471 break;
3472 case 3:
3473 default:
3474 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
3475 break;
57e252bf
MN
3476 }
3477 enabled_rbs >>= 2;
3478 }
3479 WREG32(PA_SC_RASTER_CONFIG, data);
3480 }
3481 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3482}
3483
3484/**
3485 * cik_gpu_init - setup the 3D engine
3486 *
3487 * @rdev: radeon_device pointer
3488 *
3489 * Configures the 3D engine and tiling configuration
3490 * registers so that the 3D engine is usable.
3491 */
4cd92098 3492static void cik_gpu_init(struct radeon_device *rdev)
57e252bf
MN
3493{
3494 u32 gb_addr_config = RREG32(GB_ADDR_CONFIG);
3495 u32 mc_shared_chmap, mc_arb_ramcfg;
3496 u32 hdp_host_path_cntl;
3497 u32 tmp;
3498 int i, j;
3499
3500 switch (rdev->family) {
c4ef309b 3501 case CHIP_BONAIRE:
3502 rdev->config.cik.max_shader_engines = 2;
3503 rdev->config.cik.max_tile_pipes = 4;
3504 rdev->config.cik.max_cu_per_sh = 7;
3505 rdev->config.cik.max_sh_per_se = 1;
3506 rdev->config.cik.max_backends_per_se = 2;
3507 rdev->config.cik.max_texture_channel_caches = 4;
3508 rdev->config.cik.max_gprs = 256;
3509 rdev->config.cik.max_gs_threads = 32;
3510 rdev->config.cik.max_hw_contexts = 8;
3511
3512 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3513 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3514 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3515 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3516 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
3517 break;
c6f73aab
FT
3518 case CHIP_HAWAII:
3519 rdev->config.cik.max_shader_engines = 4;
3520 rdev->config.cik.max_tile_pipes = 16;
3521 rdev->config.cik.max_cu_per_sh = 11;
3522 rdev->config.cik.max_sh_per_se = 1;
3523 rdev->config.cik.max_backends_per_se = 4;
3524 rdev->config.cik.max_texture_channel_caches = 16;
3525 rdev->config.cik.max_gprs = 256;
3526 rdev->config.cik.max_gs_threads = 32;
3527 rdev->config.cik.max_hw_contexts = 8;
3528
3529 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3530 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3531 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3532 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3533 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
3534 break;
c4ef309b 3535 case CHIP_KAVERI:
4cd92098 3536 rdev->config.cik.max_shader_engines = 1;
3537 rdev->config.cik.max_tile_pipes = 4;
c6f73aab
FT
3538 if ((rdev->pdev->device == 0x1304) ||
3539 (rdev->pdev->device == 0x1305) ||
3540 (rdev->pdev->device == 0x130C) ||
3541 (rdev->pdev->device == 0x130F) ||
3542 (rdev->pdev->device == 0x1310) ||
3543 (rdev->pdev->device == 0x1311) ||
3544 (rdev->pdev->device == 0x131C)) {
4cd92098 3545 rdev->config.cik.max_cu_per_sh = 8;
3546 rdev->config.cik.max_backends_per_se = 2;
c6f73aab
FT
3547 } else if ((rdev->pdev->device == 0x1309) ||
3548 (rdev->pdev->device == 0x130A) ||
3549 (rdev->pdev->device == 0x130D) ||
3550 (rdev->pdev->device == 0x1313) ||
3551 (rdev->pdev->device == 0x131D)) {
4cd92098 3552 rdev->config.cik.max_cu_per_sh = 6;
3553 rdev->config.cik.max_backends_per_se = 2;
c6f73aab
FT
3554 } else if ((rdev->pdev->device == 0x1306) ||
3555 (rdev->pdev->device == 0x1307) ||
3556 (rdev->pdev->device == 0x130B) ||
3557 (rdev->pdev->device == 0x130E) ||
3558 (rdev->pdev->device == 0x1315) ||
3559 (rdev->pdev->device == 0x1318) ||
3560 (rdev->pdev->device == 0x131B)) {
4cd92098 3561 rdev->config.cik.max_cu_per_sh = 4;
3562 rdev->config.cik.max_backends_per_se = 1;
3563 } else {
3564 rdev->config.cik.max_cu_per_sh = 3;
3565 rdev->config.cik.max_backends_per_se = 1;
3566 }
3567 rdev->config.cik.max_sh_per_se = 1;
3568 rdev->config.cik.max_texture_channel_caches = 4;
3569 rdev->config.cik.max_gprs = 256;
3570 rdev->config.cik.max_gs_threads = 16;
3571 rdev->config.cik.max_hw_contexts = 8;
3572
3573 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3574 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3575 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3576 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3577 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
c4ef309b 3578 break;
3579 case CHIP_KABINI:
c6f73aab 3580 case CHIP_MULLINS:
c4ef309b 3581 default:
3582 rdev->config.cik.max_shader_engines = 1;
3583 rdev->config.cik.max_tile_pipes = 2;
3584 rdev->config.cik.max_cu_per_sh = 2;
3585 rdev->config.cik.max_sh_per_se = 1;
3586 rdev->config.cik.max_backends_per_se = 1;
3587 rdev->config.cik.max_texture_channel_caches = 2;
3588 rdev->config.cik.max_gprs = 256;
3589 rdev->config.cik.max_gs_threads = 16;
3590 rdev->config.cik.max_hw_contexts = 8;
3591
3592 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3593 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3594 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3595 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3596 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
3597 break;
57e252bf
MN
3598 }
3599
3600 /* Initialize HDP */
3601 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
3602 WREG32((0x2c14 + j), 0x00000000);
3603 WREG32((0x2c18 + j), 0x00000000);
3604 WREG32((0x2c1c + j), 0x00000000);
3605 WREG32((0x2c20 + j), 0x00000000);
3606 WREG32((0x2c24 + j), 0x00000000);
3607 }
3608
3609 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
3610
3611 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
3612
3613 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
3614 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
3615
3616 rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes;
3617 rdev->config.cik.mem_max_burst_length_bytes = 256;
3618 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
3619 rdev->config.cik.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
3620 if (rdev->config.cik.mem_row_size_in_kb > 4)
3621 rdev->config.cik.mem_row_size_in_kb = 4;
3622 /* XXX use MC settings? */
3623 rdev->config.cik.shader_engine_tile_size = 32;
3624 rdev->config.cik.num_gpus = 1;
3625 rdev->config.cik.multi_gpu_tile_size = 64;
3626
3627 /* fix up row size */
3628 gb_addr_config &= ~ROW_SIZE_MASK;
3629 switch (rdev->config.cik.mem_row_size_in_kb) {
c4ef309b 3630 case 1:
3631 default:
3632 gb_addr_config |= ROW_SIZE(0);
3633 break;
3634 case 2:
3635 gb_addr_config |= ROW_SIZE(1);
3636 break;
3637 case 4:
3638 gb_addr_config |= ROW_SIZE(2);
3639 break;
57e252bf
MN
3640 }
3641
3642 /* setup tiling info dword. gb_addr_config is not adequate since it does
3643 * not have bank info, so create a custom tiling dword.
3644 * bits 3:0 num_pipes
3645 * bits 7:4 num_banks
3646 * bits 11:8 group_size
3647 * bits 15:12 row_size
3648 */
3649 rdev->config.cik.tile_config = 0;
3650 switch (rdev->config.cik.num_tile_pipes) {
c4ef309b 3651 case 1:
3652 rdev->config.cik.tile_config |= (0 << 0);
3653 break;
3654 case 2:
3655 rdev->config.cik.tile_config |= (1 << 0);
3656 break;
3657 case 4:
3658 rdev->config.cik.tile_config |= (2 << 0);
3659 break;
3660 case 8:
3661 default:
3662 /* XXX what about 12? */
3663 rdev->config.cik.tile_config |= (3 << 0);
3664 break;
57e252bf 3665 }
4cd92098 3666 rdev->config.cik.tile_config |=
3667 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
57e252bf
MN
3668 rdev->config.cik.tile_config |=
3669 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
3670 rdev->config.cik.tile_config |=
3671 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
3672
3673 WREG32(GB_ADDR_CONFIG, gb_addr_config);
3674 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
3675 WREG32(DMIF_ADDR_CALC, gb_addr_config);
3676 WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70);
3677 WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70);
3678 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
3679 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
3680 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
3681
3682 cik_tiling_mode_table_init(rdev);
3683
3684 cik_setup_rb(rdev, rdev->config.cik.max_shader_engines,
c4ef309b 3685 rdev->config.cik.max_sh_per_se,
3686 rdev->config.cik.max_backends_per_se);
57e252bf 3687
c6f73aab
FT
3688 rdev->config.cik.active_cus = 0;
3689 for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
3690 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
3691 rdev->config.cik.active_cus +=
3692 hweight32(cik_get_cu_active_bitmap(rdev, i, j));
3693 }
3694 }
3695
57e252bf
MN
3696 /* set HW defaults for 3D engine */
3697 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
3698
3699 WREG32(SX_DEBUG_1, 0x20);
3700
3701 WREG32(TA_CNTL_AUX, 0x00010000);
3702
3703 tmp = RREG32(SPI_CONFIG_CNTL);
3704 tmp |= 0x03000000;
3705 WREG32(SPI_CONFIG_CNTL, tmp);
3706
3707 WREG32(SQ_CONFIG, 1);
3708
3709 WREG32(DB_DEBUG, 0);
3710
3711 tmp = RREG32(DB_DEBUG2) & ~0xf00fffff;
3712 tmp |= 0x00000400;
3713 WREG32(DB_DEBUG2, tmp);
3714
3715 tmp = RREG32(DB_DEBUG3) & ~0x0002021c;
3716 tmp |= 0x00020200;
3717 WREG32(DB_DEBUG3, tmp);
3718
3719 tmp = RREG32(CB_HW_CONTROL) & ~0x00010000;
3720 tmp |= 0x00018208;
3721 WREG32(CB_HW_CONTROL, tmp);
3722
3723 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
3724
3725 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) |
c4ef309b 3726 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_backend) |
3727 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cik.sc_hiz_tile_fifo_size) |
3728 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cik.sc_earlyz_tile_fifo_size)));
57e252bf
MN
3729
3730 WREG32(VGT_NUM_INSTANCES, 1);
3731
3732 WREG32(CP_PERFMON_CNTL, 0);
3733
3734 WREG32(SQ_CONFIG, 0);
3735
3736 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
c4ef309b 3737 FORCE_EOV_MAX_REZ_CNT(255)));
57e252bf
MN
3738
3739 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
c4ef309b 3740 AUTO_INVLD_EN(ES_AND_GS_AUTO));
57e252bf
MN
3741
3742 WREG32(VGT_GS_VERTEX_REUSE, 16);
3743 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
3744
3745 tmp = RREG32(HDP_MISC_CNTL);
3746 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
3747 WREG32(HDP_MISC_CNTL, tmp);
3748
3749 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
3750 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
3751
3752 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
3753 WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER);
3754
c4ef309b 3755 udelay(50);
57e252bf
MN
3756}
3757
3758/*
3759 * GPU scratch registers helpers function.
3760 */
3761/**
3762 * cik_scratch_init - setup driver info for CP scratch regs
3763 *
3764 * @rdev: radeon_device pointer
3765 *
3766 * Set up the number and offset of the CP scratch registers.
3767 * NOTE: use of CP scratch registers is a legacy inferface and
3768 * is not used by default on newer asics (r6xx+). On newer asics,
3769 * memory buffers are used for fences rather than scratch regs.
3770 */
4cd92098 3771static void cik_scratch_init(struct radeon_device *rdev)
57e252bf
MN
3772{
3773 int i;
3774
3775 rdev->scratch.num_reg = 7;
3776 rdev->scratch.reg_base = SCRATCH_REG0;
3777 for (i = 0; i < rdev->scratch.num_reg; i++) {
3778 rdev->scratch.free[i] = true;
3779 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3780 }
3781}
3782
3783/**
3784 * cik_ring_test - basic gfx ring test
3785 *
3786 * @rdev: radeon_device pointer
3787 * @ring: radeon_ring structure holding ring information
3788 *
3789 * Allocate a scratch register and write to it using the gfx ring (CIK).
3790 * Provides a basic gfx ring test to verify that the ring is working.
3791 * Used by cik_cp_gfx_resume();
3792 * Returns 0 on success, error on failure.
3793 */
3794int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3795{
3796 uint32_t scratch;
3797 uint32_t tmp = 0;
3798 unsigned i;
3799 int r;
3800
3801 r = radeon_scratch_get(rdev, &scratch);
3802 if (r) {
3803 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3804 return r;
3805 }
3806 WREG32(scratch, 0xCAFEDEAD);
3807 r = radeon_ring_lock(rdev, ring, 3);
3808 if (r) {
3809 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
3810 radeon_scratch_free(rdev, scratch);
3811 return r;
3812 }
3813 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3814 radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2));
3815 radeon_ring_write(ring, 0xDEADBEEF);
c6f73aab 3816 radeon_ring_unlock_commit(rdev, ring, false);
57e252bf
MN
3817
3818 for (i = 0; i < rdev->usec_timeout; i++) {
3819 tmp = RREG32(scratch);
3820 if (tmp == 0xDEADBEEF)
3821 break;
3822 DRM_UDELAY(1);
3823 }
3824 if (i < rdev->usec_timeout) {
3825 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
3826 } else {
3827 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
3828 ring->idx, scratch, tmp);
3829 r = -EINVAL;
3830 }
3831 radeon_scratch_free(rdev, scratch);
3832 return r;
3833}
3834
c6f73aab
FT
3835/**
3836 * cik_hdp_flush_cp_ring_emit - emit an hdp flush on the cp
3837 *
3838 * @rdev: radeon_device pointer
3839 * @ridx: radeon ring index
3840 *
3841 * Emits an hdp flush on the cp.
3842 */
3843static void cik_hdp_flush_cp_ring_emit(struct radeon_device *rdev,
3844 int ridx)
3845{
3846 struct radeon_ring *ring = &rdev->ring[ridx];
3847 u32 ref_and_mask;
3848
3849 switch (ring->idx) {
3850 case CAYMAN_RING_TYPE_CP1_INDEX:
3851 case CAYMAN_RING_TYPE_CP2_INDEX:
3852 default:
3853 switch (ring->me) {
3854 case 0:
3855 ref_and_mask = CP2 << ring->pipe;
3856 break;
3857 case 1:
3858 ref_and_mask = CP6 << ring->pipe;
3859 break;
3860 default:
3861 return;
3862 }
3863 break;
3864 case RADEON_RING_TYPE_GFX_INDEX:
3865 ref_and_mask = CP0;
3866 break;
3867 }
3868
3869 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3870 radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
3871 WAIT_REG_MEM_FUNCTION(3) | /* == */
3872 WAIT_REG_MEM_ENGINE(1))); /* pfp */
3873 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ >> 2);
3874 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE >> 2);
3875 radeon_ring_write(ring, ref_and_mask);
3876 radeon_ring_write(ring, ref_and_mask);
3877 radeon_ring_write(ring, 0x20); /* poll interval */
3878}
3879
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MN
3880/**
3881 * cik_fence_gfx_ring_emit - emit a fence on the gfx ring
3882 *
3883 * @rdev: radeon_device pointer
3884 * @fence: radeon fence object
3885 *
3886 * Emits a fence sequnce number on the gfx ring and flushes
3887 * GPU caches.
3888 */
3889void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
3890 struct radeon_fence *fence)
3891{
3892 struct radeon_ring *ring = &rdev->ring[fence->ring];
3893 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3894
3895 /* EVENT_WRITE_EOP - flush caches, send int */
3896 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3897 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
3898 EOP_TC_ACTION_EN |
3899 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3900 EVENT_INDEX(5)));
3901 radeon_ring_write(ring, addr & 0xfffffffc);
3902 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2));
3903 radeon_ring_write(ring, fence->seq);
3904 radeon_ring_write(ring, 0);
57e252bf
MN
3905}
3906
3907/**
3908 * cik_fence_compute_ring_emit - emit a fence on the compute ring
3909 *
3910 * @rdev: radeon_device pointer
3911 * @fence: radeon fence object
3912 *
3913 * Emits a fence sequnce number on the compute ring and flushes
3914 * GPU caches.
3915 */
3916void cik_fence_compute_ring_emit(struct radeon_device *rdev,
3917 struct radeon_fence *fence)
3918{
3919 struct radeon_ring *ring = &rdev->ring[fence->ring];
3920 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3921
3922 /* RELEASE_MEM - flush caches, send int */
3923 radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
3924 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
3925 EOP_TC_ACTION_EN |
3926 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3927 EVENT_INDEX(5)));
3928 radeon_ring_write(ring, DATA_SEL(1) | INT_SEL(2));
3929 radeon_ring_write(ring, addr & 0xfffffffc);
3930 radeon_ring_write(ring, upper_32_bits(addr));
3931 radeon_ring_write(ring, fence->seq);
3932 radeon_ring_write(ring, 0);
57e252bf
MN
3933}
3934
c6f73aab
FT
3935/**
3936 * cik_semaphore_ring_emit - emit a semaphore on the CP ring
3937 *
3938 * @rdev: radeon_device pointer
3939 * @ring: radeon ring buffer object
3940 * @semaphore: radeon semaphore object
3941 * @emit_wait: Is this a sempahore wait?
3942 *
3943 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
3944 * from running ahead of semaphore waits.
3945 */
3946bool cik_semaphore_ring_emit(struct radeon_device *rdev,
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MN
3947 struct radeon_ring *ring,
3948 struct radeon_semaphore *semaphore,
3949 bool emit_wait)
3950{
3951 uint64_t addr = semaphore->gpu_addr;
3952 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
3953
3954 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
c6f73aab 3955 radeon_ring_write(ring, lower_32_bits(addr));
57e252bf 3956 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
c6f73aab
FT
3957
3958 if (emit_wait && ring->idx == RADEON_RING_TYPE_GFX_INDEX) {
3959 /* Prevent the PFP from running ahead of the semaphore wait */
3960 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3961 radeon_ring_write(ring, 0x0);
3962 }
3963
3964 return true;
3965}
3966
3967/**
3968 * cik_copy_cpdma - copy pages using the CP DMA engine
3969 *
3970 * @rdev: radeon_device pointer
3971 * @src_offset: src GPU address
3972 * @dst_offset: dst GPU address
3973 * @num_gpu_pages: number of GPU pages to xfer
3974 * @fence: radeon fence object
3975 *
3976 * Copy GPU paging using the CP DMA engine (CIK+).
3977 * Used by the radeon ttm implementation to move pages if
3978 * registered as the asic copy callback.
3979 */
3980int cik_copy_cpdma(struct radeon_device *rdev,
3981 uint64_t src_offset, uint64_t dst_offset,
3982 unsigned num_gpu_pages,
3983 struct radeon_fence **fence)
3984{
3985 struct radeon_semaphore *sem = NULL;
3986 int ring_index = rdev->asic->copy.blit_ring_index;
3987 struct radeon_ring *ring = &rdev->ring[ring_index];
3988 u32 size_in_bytes, cur_size_in_bytes, control;
3989 int i, num_loops;