drm/i915: Disable few unused const structs and functions.
[dragonfly.git] / sys / dev / drm / i915 / intel_audio.c
CommitLineData
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1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/kernel.h>
25#include <drm/i915_component.h>
26#include "intel_drv.h"
27
28#include <drm/drmP.h>
29#include <drm/drm_edid.h>
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30#include "i915_drv.h"
31
32/**
33 * DOC: High Definition Audio over HDMI and Display Port
34 *
35 * The graphics and audio drivers together support High Definition Audio over
36 * HDMI and Display Port. The audio programming sequences are divided into audio
37 * codec and controller enable and disable sequences. The graphics driver
38 * handles the audio codec sequences, while the audio driver handles the audio
39 * controller sequences.
40 *
41 * The disable sequences must be performed before disabling the transcoder or
42 * port. The enable sequences may only be performed after enabling the
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43 * transcoder and port, and after completed link training. Therefore the audio
44 * enable/disable sequences are part of the modeset sequence.
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45 *
46 * The codec and controller sequences could be done either parallel or serial,
47 * but generally the ELDV/PD change in the codec sequence indicates to the audio
48 * driver that the controller sequence should start. Indeed, most of the
49 * co-operation between the graphics and audio drivers is handled via audio
50 * related registers. (The notable exception is the power management, not
51 * covered here.)
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52 *
53 * The struct i915_audio_component is used to interact between the graphics
54 * and audio drivers. The struct i915_audio_component_ops *ops in it is
55 * defined in graphics driver and called in audio driver. The
56 * struct i915_audio_component_audio_ops *audio_ops is called from i915 driver.
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57 */
58
59static const struct {
60 int clock;
61 u32 config;
62} hdmi_audio_clock[] = {
352ff8bd 63 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
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64 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
65 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
352ff8bd 66 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
2c9916cd 67 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
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68 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
69 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
2c9916cd 70 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
352ff8bd 71 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
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72 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
73};
74
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75/* HDMI N/CTS table */
76#define TMDS_297M 297000
77#define TMDS_296M 296703
78static const struct {
79 int sample_rate;
80 int clock;
81 int n;
82 int cts;
83} aud_ncts[] = {
84 { 44100, TMDS_296M, 4459, 234375 },
85 { 44100, TMDS_297M, 4704, 247500 },
86 { 48000, TMDS_296M, 5824, 281250 },
87 { 48000, TMDS_297M, 5120, 247500 },
88 { 32000, TMDS_296M, 5824, 421875 },
89 { 32000, TMDS_297M, 3072, 222750 },
90 { 88200, TMDS_296M, 8918, 234375 },
91 { 88200, TMDS_297M, 9408, 247500 },
92 { 96000, TMDS_296M, 11648, 281250 },
93 { 96000, TMDS_297M, 10240, 247500 },
94 { 176400, TMDS_296M, 17836, 234375 },
95 { 176400, TMDS_297M, 18816, 247500 },
96 { 192000, TMDS_296M, 23296, 281250 },
97 { 192000, TMDS_297M, 20480, 247500 },
98};
99
2c9916cd 100/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
352ff8bd 101static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted_mode)
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102{
103 int i;
104
105 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
352ff8bd 106 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
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107 break;
108 }
109
110 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
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111 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
112 adjusted_mode->crtc_clock);
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113 i = 1;
114 }
115
116 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
117 hdmi_audio_clock[i].clock,
118 hdmi_audio_clock[i].config);
119
120 return hdmi_audio_clock[i].config;
121}
122
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123static int audio_config_get_n(const struct drm_display_mode *mode, int rate)
124{
125 int i;
126
127 for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
128 if ((rate == aud_ncts[i].sample_rate) &&
129 (mode->clock == aud_ncts[i].clock)) {
130 return aud_ncts[i].n;
131 }
132 }
133 return 0;
134}
135
136static uint32_t audio_config_setup_n_reg(int n, uint32_t val)
137{
138 int n_low, n_up;
139 uint32_t tmp = val;
140
141 n_low = n & 0xfff;
142 n_up = (n >> 12) & 0xff;
143 tmp &= ~(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK);
144 tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) |
145 (n_low << AUD_CONFIG_LOWER_N_SHIFT) |
146 AUD_CONFIG_N_PROG_ENABLE);
147 return tmp;
148}
149
150/* check whether N/CTS/M need be set manually */
151static bool audio_rate_need_prog(struct intel_crtc *crtc,
152 const struct drm_display_mode *mode)
153{
154 if (((mode->clock == TMDS_297M) ||
155 (mode->clock == TMDS_296M)) &&
156 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
157 return true;
158 else
159 return false;
160}
161
2c9916cd 162static bool intel_eld_uptodate(struct drm_connector *connector,
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163 i915_reg_t reg_eldv, uint32_t bits_eldv,
164 i915_reg_t reg_elda, uint32_t bits_elda,
165 i915_reg_t reg_edid)
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166{
167 struct drm_i915_private *dev_priv = connector->dev->dev_private;
168 uint8_t *eld = connector->eld;
169 uint32_t tmp;
170 int i;
171
172 tmp = I915_READ(reg_eldv);
173 tmp &= bits_eldv;
174
175 if (!tmp)
176 return false;
177
178 tmp = I915_READ(reg_elda);
179 tmp &= ~bits_elda;
180 I915_WRITE(reg_elda, tmp);
181
182 for (i = 0; i < drm_eld_size(eld) / 4; i++)
183 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
184 return false;
185
186 return true;
187}
188
189static void g4x_audio_codec_disable(struct intel_encoder *encoder)
190{
191 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
192 uint32_t eldv, tmp;
193
194 DRM_DEBUG_KMS("Disable audio codec\n");
195
196 tmp = I915_READ(G4X_AUD_VID_DID);
197 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
198 eldv = G4X_ELDV_DEVCL_DEVBLC;
199 else
200 eldv = G4X_ELDV_DEVCTG;
201
202 /* Invalidate ELD */
203 tmp = I915_READ(G4X_AUD_CNTL_ST);
204 tmp &= ~eldv;
205 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
206}
207
208static void g4x_audio_codec_enable(struct drm_connector *connector,
209 struct intel_encoder *encoder,
352ff8bd 210 const struct drm_display_mode *adjusted_mode)
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211{
212 struct drm_i915_private *dev_priv = connector->dev->dev_private;
213 uint8_t *eld = connector->eld;
214 uint32_t eldv;
215 uint32_t tmp;
216 int len, i;
217
218 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);
219
220 tmp = I915_READ(G4X_AUD_VID_DID);
221 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
222 eldv = G4X_ELDV_DEVCL_DEVBLC;
223 else
224 eldv = G4X_ELDV_DEVCTG;
225
226 if (intel_eld_uptodate(connector,
227 G4X_AUD_CNTL_ST, eldv,
228 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
229 G4X_HDMIW_HDMIEDID))
230 return;
231
232 tmp = I915_READ(G4X_AUD_CNTL_ST);
233 tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
234 len = (tmp >> 9) & 0x1f; /* ELD buffer size */
235 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
236
237 len = min(drm_eld_size(eld) / 4, len);
238 DRM_DEBUG_DRIVER("ELD size %d\n", len);
239 for (i = 0; i < len; i++)
240 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
241
242 tmp = I915_READ(G4X_AUD_CNTL_ST);
243 tmp |= eldv;
244 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
245}
246
247static void hsw_audio_codec_disable(struct intel_encoder *encoder)
248{
249 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
250 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
251 enum i915_pipe pipe = intel_crtc->pipe;
252 uint32_t tmp;
253
254 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
255
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256 mutex_lock(&dev_priv->av_mutex);
257
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258 /* Disable timestamps */
259 tmp = I915_READ(HSW_AUD_CFG(pipe));
260 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
261 tmp |= AUD_CONFIG_N_PROG_ENABLE;
262 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
263 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
c0e85e96 264 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
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265 tmp |= AUD_CONFIG_N_VALUE_INDEX;
266 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
267
268 /* Invalidate ELD */
269 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
270 tmp &= ~AUDIO_ELD_VALID(pipe);
271 tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
272 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
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273
274 mutex_unlock(&dev_priv->av_mutex);
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275}
276
277static void hsw_audio_codec_enable(struct drm_connector *connector,
278 struct intel_encoder *encoder,
352ff8bd 279 const struct drm_display_mode *adjusted_mode)
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280{
281 struct drm_i915_private *dev_priv = connector->dev->dev_private;
282 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
283 enum i915_pipe pipe = intel_crtc->pipe;
352ff8bd 284 struct i915_audio_component *acomp = dev_priv->audio_component;
2c9916cd 285 const uint8_t *eld = connector->eld;
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286 struct intel_digital_port *intel_dig_port =
287 enc_to_dig_port(&encoder->base);
288 enum port port = intel_dig_port->port;
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289 uint32_t tmp;
290 int len, i;
352ff8bd 291 int n, rate;
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292
293 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
294 pipe_name(pipe), drm_eld_size(eld));
295
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296 mutex_lock(&dev_priv->av_mutex);
297
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298 /* Enable audio presence detect, invalidate ELD */
299 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
300 tmp |= AUDIO_OUTPUT_ENABLE(pipe);
301 tmp &= ~AUDIO_ELD_VALID(pipe);
302 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
303
304 /*
305 * FIXME: We're supposed to wait for vblank here, but we have vblanks
306 * disabled during the mode set. The proper fix would be to push the
307 * rest of the setup into a vblank work item, queued here, but the
308 * infrastructure is not there yet.
309 */
310
311 /* Reset ELD write address */
312 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
313 tmp &= ~IBX_ELD_ADDRESS_MASK;
314 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
315
316 /* Up to 84 bytes of hw ELD buffer */
317 len = min(drm_eld_size(eld), 84);
318 for (i = 0; i < len / 4; i++)
319 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((const uint32_t *)eld + i));
320
321 /* ELD valid */
322 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
323 tmp |= AUDIO_ELD_VALID(pipe);
324 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
325
326 /* Enable timestamps */
327 tmp = I915_READ(HSW_AUD_CFG(pipe));
328 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
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329 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
330 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
331 tmp |= AUD_CONFIG_N_VALUE_INDEX;
332 else
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333 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
334
335 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
336 if (audio_rate_need_prog(intel_crtc, adjusted_mode)) {
337 if (!acomp)
338 rate = 0;
339 else if (port >= PORT_A && port <= PORT_E)
340 rate = acomp->aud_sample_rate[port];
341 else {
342 DRM_ERROR("invalid port: %d\n", port);
343 rate = 0;
344 }
345 n = audio_config_get_n(adjusted_mode, rate);
346 if (n != 0)
347 tmp = audio_config_setup_n_reg(n, tmp);
348 else
349 DRM_DEBUG_KMS("no suitable N value is found\n");
350 }
351
2c9916cd 352 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
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353
354 mutex_unlock(&dev_priv->av_mutex);
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355}
356
357static void ilk_audio_codec_disable(struct intel_encoder *encoder)
358{
359 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
360 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
361 struct intel_digital_port *intel_dig_port =
362 enc_to_dig_port(&encoder->base);
363 enum port port = intel_dig_port->port;
364 enum i915_pipe pipe = intel_crtc->pipe;
365 uint32_t tmp, eldv;
aee94f86 366 i915_reg_t aud_config, aud_cntrl_st2;
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367
368 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
369 port_name(port), pipe_name(pipe));
370
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371 if (WARN_ON(port == PORT_A))
372 return;
373
8621f407 374 if (HAS_PCH_IBX(dev_priv)) {
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375 aud_config = IBX_AUD_CFG(pipe);
376 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
aee94f86 377 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
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378 aud_config = VLV_AUD_CFG(pipe);
379 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
380 } else {
381 aud_config = CPT_AUD_CFG(pipe);
382 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
383 }
384
385 /* Disable timestamps */
386 tmp = I915_READ(aud_config);
387 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
388 tmp |= AUD_CONFIG_N_PROG_ENABLE;
389 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
390 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
391 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
392 tmp |= AUD_CONFIG_N_VALUE_INDEX;
393 I915_WRITE(aud_config, tmp);
394
19c468b4 395 eldv = IBX_ELD_VALID(port);
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396
397 /* Invalidate ELD */
398 tmp = I915_READ(aud_cntrl_st2);
399 tmp &= ~eldv;
400 I915_WRITE(aud_cntrl_st2, tmp);
401}
402
403static void ilk_audio_codec_enable(struct drm_connector *connector,
404 struct intel_encoder *encoder,
352ff8bd 405 const struct drm_display_mode *adjusted_mode)
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406{
407 struct drm_i915_private *dev_priv = connector->dev->dev_private;
408 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
409 struct intel_digital_port *intel_dig_port =
410 enc_to_dig_port(&encoder->base);
411 enum port port = intel_dig_port->port;
412 enum i915_pipe pipe = intel_crtc->pipe;
413 uint8_t *eld = connector->eld;
414 uint32_t eldv;
415 uint32_t tmp;
416 int len, i;
aee94f86 417 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
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418
419 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
420 port_name(port), pipe_name(pipe), drm_eld_size(eld));
421
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422 if (WARN_ON(port == PORT_A))
423 return;
424
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425 /*
426 * FIXME: We're supposed to wait for vblank here, but we have vblanks
427 * disabled during the mode set. The proper fix would be to push the
428 * rest of the setup into a vblank work item, queued here, but the
429 * infrastructure is not there yet.
430 */
431
432 if (HAS_PCH_IBX(connector->dev)) {
433 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
434 aud_config = IBX_AUD_CFG(pipe);
435 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
436 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
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437 } else if (IS_VALLEYVIEW(connector->dev) ||
438 IS_CHERRYVIEW(connector->dev)) {
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439 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
440 aud_config = VLV_AUD_CFG(pipe);
441 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
442 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
443 } else {
444 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
445 aud_config = CPT_AUD_CFG(pipe);
446 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
447 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
448 }
449
19c468b4 450 eldv = IBX_ELD_VALID(port);
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451
452 /* Invalidate ELD */
453 tmp = I915_READ(aud_cntrl_st2);
454 tmp &= ~eldv;
455 I915_WRITE(aud_cntrl_st2, tmp);
456
457 /* Reset ELD write address */
458 tmp = I915_READ(aud_cntl_st);
459 tmp &= ~IBX_ELD_ADDRESS_MASK;
460 I915_WRITE(aud_cntl_st, tmp);
461
462 /* Up to 84 bytes of hw ELD buffer */
463 len = min(drm_eld_size(eld), 84);
464 for (i = 0; i < len / 4; i++)
465 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
466
467 /* ELD valid */
468 tmp = I915_READ(aud_cntrl_st2);
469 tmp |= eldv;
470 I915_WRITE(aud_cntrl_st2, tmp);
471
472 /* Enable timestamps */
473 tmp = I915_READ(aud_config);
474 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
475 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
476 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
c0e85e96 477 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
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478 tmp |= AUD_CONFIG_N_VALUE_INDEX;
479 else
352ff8bd 480 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
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481 I915_WRITE(aud_config, tmp);
482}
483
484/**
485 * intel_audio_codec_enable - Enable the audio codec for HD audio
486 * @intel_encoder: encoder on which to enable audio
487 *
488 * The enable sequences may only be performed after enabling the transcoder and
489 * port, and after completed link training.
490 */
491void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
492{
493 struct drm_encoder *encoder = &intel_encoder->base;
494 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
352ff8bd 495 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
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496 struct drm_connector *connector;
497 struct drm_device *dev = encoder->dev;
498 struct drm_i915_private *dev_priv = dev->dev_private;
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499 struct i915_audio_component *acomp = dev_priv->audio_component;
500 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
501 enum port port = intel_dig_port->port;
2c9916cd 502
352ff8bd 503 connector = drm_select_eld(encoder);
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504 if (!connector)
505 return;
506
507 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
508 connector->base.id,
509 connector->name,
510 connector->encoder->base.id,
511 connector->encoder->name);
512
513 /* ELD Conn_Type */
514 connector->eld[5] &= ~(3 << 2);
c0e85e96 515 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
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516 connector->eld[5] |= (1 << 2);
517
352ff8bd 518 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
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519
520 if (dev_priv->display.audio_codec_enable)
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521 dev_priv->display.audio_codec_enable(connector, intel_encoder,
522 adjusted_mode);
a05eeebf 523
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524 mutex_lock(&dev_priv->av_mutex);
525 intel_dig_port->audio_connector = connector;
526 /* referred in audio callbacks */
527 dev_priv->dig_port_map[port] = intel_encoder;
528 mutex_unlock(&dev_priv->av_mutex);
529
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530 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
531 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
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532}
533
534/**
535 * intel_audio_codec_disable - Disable the audio codec for HD audio
a05eeebf 536 * @intel_encoder: encoder on which to disable audio
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537 *
538 * The disable sequences must be performed before disabling the transcoder or
539 * port.
540 */
a05eeebf 541void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
2c9916cd 542{
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543 struct drm_encoder *encoder = &intel_encoder->base;
544 struct drm_device *dev = encoder->dev;
2c9916cd 545 struct drm_i915_private *dev_priv = dev->dev_private;
a05eeebf
FT
546 struct i915_audio_component *acomp = dev_priv->audio_component;
547 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
548 enum port port = intel_dig_port->port;
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549
550 if (dev_priv->display.audio_codec_disable)
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FT
551 dev_priv->display.audio_codec_disable(intel_encoder);
552
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FT
553 mutex_lock(&dev_priv->av_mutex);
554 intel_dig_port->audio_connector = NULL;
555 dev_priv->dig_port_map[port] = NULL;
556 mutex_unlock(&dev_priv->av_mutex);
557
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FT
558 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
559 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
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560}
561
562/**
8621f407
FT
563 * intel_init_audio_hooks - Set up chip specific audio hooks
564 * @dev_priv: device private
2c9916cd 565 */
8621f407 566void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
2c9916cd 567{
8621f407 568 if (IS_G4X(dev_priv)) {
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FT
569 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
570 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
8621f407 571 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
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572 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
573 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
8621f407 574 } else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) {
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FT
575 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
576 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
8621f407 577 } else if (HAS_PCH_SPLIT(dev_priv)) {
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578 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
579 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
580 }
581}
582
76594197 583#if 0 /* unused */
2c9916cd
FT
584static void i915_audio_component_get_power(struct device *dev)
585{
586 intel_display_power_get(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
587}
588
589static void i915_audio_component_put_power(struct device *dev)
590{
591 intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
592}
593
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FT
594static void i915_audio_component_codec_wake_override(struct device *dev,
595 bool enable)
596{
597 struct drm_i915_private *dev_priv = dev_to_i915(dev);
598 u32 tmp;
599
aee94f86 600 if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
19c468b4
FT
601 return;
602
8621f407
FT
603 i915_audio_component_get_power(dev);
604
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FT
605 /*
606 * Enable/disable generating the codec wake signal, overriding the
607 * internal logic to generate the codec wake to controller.
608 */
609 tmp = I915_READ(HSW_AUD_CHICKENBIT);
610 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
611 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
612 usleep_range(1000, 1500);
613
614 if (enable) {
615 tmp = I915_READ(HSW_AUD_CHICKENBIT);
616 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
617 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
618 usleep_range(1000, 1500);
619 }
8621f407
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620
621 i915_audio_component_put_power(dev);
19c468b4
FT
622}
623
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FT
624/* Get CDCLK in kHz */
625static int i915_audio_component_get_cdclk_freq(struct device *dev)
626{
627 struct drm_i915_private *dev_priv = dev_to_i915(dev);
628 int ret;
629
630 if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
631 return -ENODEV;
632
633 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
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FT
634 ret = dev_priv->display.get_display_clock_speed(dev_priv->dev);
635
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FT
636 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
637
638 return ret;
639}
640
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FT
641static int i915_audio_component_sync_audio_rate(struct device *dev,
642 int port, int rate)
643{
644 struct drm_i915_private *dev_priv = dev_to_i915(dev);
352ff8bd 645 struct intel_encoder *intel_encoder;
352ff8bd
FT
646 struct intel_crtc *crtc;
647 struct drm_display_mode *mode;
648 struct i915_audio_component *acomp = dev_priv->audio_component;
aee94f86 649 enum i915_pipe pipe = INVALID_PIPE;
352ff8bd
FT
650 u32 tmp;
651 int n;
aee94f86 652 int err = 0;
352ff8bd 653
aee94f86 654 /* HSW, BDW, SKL, KBL need this fix */
352ff8bd 655 if (!IS_SKYLAKE(dev_priv) &&
aee94f86
FT
656 !IS_KABYLAKE(dev_priv) &&
657 !IS_BROADWELL(dev_priv) &&
658 !IS_HASWELL(dev_priv))
352ff8bd
FT
659 return 0;
660
8621f407 661 i915_audio_component_get_power(dev);
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FT
662 mutex_lock(&dev_priv->av_mutex);
663 /* 1. get the pipe */
aee94f86
FT
664 intel_encoder = dev_priv->dig_port_map[port];
665 /* intel_encoder might be NULL for DP MST */
666 if (!intel_encoder || !intel_encoder->base.crtc ||
667 intel_encoder->type != INTEL_OUTPUT_HDMI) {
668 DRM_DEBUG_KMS("no valid port %c\n", port_name(port));
669 err = -ENODEV;
670 goto unlock;
352ff8bd 671 }
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FT
672 crtc = to_intel_crtc(intel_encoder->base.crtc);
673 pipe = crtc->pipe;
352ff8bd
FT
674 if (pipe == INVALID_PIPE) {
675 DRM_DEBUG_KMS("no pipe for the port %c\n", port_name(port));
aee94f86
FT
676 err = -ENODEV;
677 goto unlock;
352ff8bd 678 }
aee94f86 679
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FT
680 DRM_DEBUG_KMS("pipe %c connects port %c\n",
681 pipe_name(pipe), port_name(port));
682 mode = &crtc->config->base.adjusted_mode;
683
684 /* port must be valid now, otherwise the pipe will be invalid */
685 acomp->aud_sample_rate[port] = rate;
686
687 /* 2. check whether to set the N/CTS/M manually or not */
688 if (!audio_rate_need_prog(crtc, mode)) {
689 tmp = I915_READ(HSW_AUD_CFG(pipe));
690 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
691 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
aee94f86 692 goto unlock;
352ff8bd
FT
693 }
694
695 n = audio_config_get_n(mode, rate);
696 if (n == 0) {
697 DRM_DEBUG_KMS("Using automatic mode for N value on port %c\n",
698 port_name(port));
699 tmp = I915_READ(HSW_AUD_CFG(pipe));
700 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
701 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
aee94f86 702 goto unlock;
352ff8bd
FT
703 }
704
705 /* 3. set the N/CTS/M */
706 tmp = I915_READ(HSW_AUD_CFG(pipe));
707 tmp = audio_config_setup_n_reg(n, tmp);
708 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
709
aee94f86 710 unlock:
352ff8bd 711 mutex_unlock(&dev_priv->av_mutex);
8621f407 712 i915_audio_component_put_power(dev);
aee94f86
FT
713 return err;
714}
715
716static int i915_audio_component_get_eld(struct device *dev, int port,
717 bool *enabled,
718 unsigned char *buf, int max_bytes)
719{
720 struct drm_i915_private *dev_priv = dev_to_i915(dev);
721 struct intel_encoder *intel_encoder;
722 struct intel_digital_port *intel_dig_port;
723 const u8 *eld;
724 int ret = -EINVAL;
725
726 mutex_lock(&dev_priv->av_mutex);
727 intel_encoder = dev_priv->dig_port_map[port];
728 /* intel_encoder might be NULL for DP MST */
729 if (intel_encoder) {
730 ret = 0;
731 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
732 *enabled = intel_dig_port->audio_connector != NULL;
733 if (*enabled) {
734 eld = intel_dig_port->audio_connector->eld;
735 ret = drm_eld_size(eld);
736 memcpy(buf, eld, min(max_bytes, ret));
737 }
738 }
739
740 mutex_unlock(&dev_priv->av_mutex);
741 return ret;
352ff8bd 742}
76594197 743#endif
352ff8bd 744
76594197 745#if 0 /* unused */
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FT
746static const struct i915_audio_component_ops i915_audio_component_ops = {
747 .owner = THIS_MODULE,
748 .get_power = i915_audio_component_get_power,
749 .put_power = i915_audio_component_put_power,
19c468b4 750 .codec_wake_override = i915_audio_component_codec_wake_override,
2c9916cd 751 .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
352ff8bd 752 .sync_audio_rate = i915_audio_component_sync_audio_rate,
aee94f86 753 .get_eld = i915_audio_component_get_eld,
2c9916cd
FT
754};
755
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FT
756static int i915_audio_component_bind(struct device *i915_dev,
757 struct device *hda_dev, void *data)
758{
759 struct i915_audio_component *acomp = data;
a05eeebf 760 struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
352ff8bd 761 int i;
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FT
762
763 if (WARN_ON(acomp->ops || acomp->dev))
764 return -EEXIST;
765
a05eeebf 766 drm_modeset_lock_all(dev_priv->dev);
2c9916cd
FT
767 acomp->ops = &i915_audio_component_ops;
768 acomp->dev = i915_dev;
352ff8bd
FT
769 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
770 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
771 acomp->aud_sample_rate[i] = 0;
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FT
772 dev_priv->audio_component = acomp;
773 drm_modeset_unlock_all(dev_priv->dev);
2c9916cd
FT
774
775 return 0;
776}
777
778static void i915_audio_component_unbind(struct device *i915_dev,
779 struct device *hda_dev, void *data)
780{
781 struct i915_audio_component *acomp = data;
a05eeebf 782 struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
2c9916cd 783
a05eeebf 784 drm_modeset_lock_all(dev_priv->dev);
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FT
785 acomp->ops = NULL;
786 acomp->dev = NULL;
a05eeebf
FT
787 dev_priv->audio_component = NULL;
788 drm_modeset_unlock_all(dev_priv->dev);
2c9916cd
FT
789}
790
791static const struct component_ops i915_audio_component_bind_ops = {
792 .bind = i915_audio_component_bind,
793 .unbind = i915_audio_component_unbind,
794};
795#endif
796
797/**
798 * i915_audio_component_init - initialize and register the audio component
799 * @dev_priv: i915 device instance
800 *
801 * This will register with the component framework a child component which
802 * will bind dynamically to the snd_hda_intel driver's corresponding master
803 * component when the latter is registered. During binding the child
804 * initializes an instance of struct i915_audio_component which it receives
805 * from the master. The master can then start to use the interface defined by
806 * this struct. Each side can break the binding at any point by deregistering
807 * its own component after which each side's component unbind callback is
808 * called.
809 *
810 * We ignore any error during registration and continue with reduced
811 * functionality (i.e. without HDMI audio).
812 */
813void i915_audio_component_init(struct drm_i915_private *dev_priv)
814{
815#if 0
816 int ret;
817
818 ret = component_add(dev_priv->dev->dev, &i915_audio_component_bind_ops);
819 if (ret < 0) {
820 DRM_ERROR("failed to add audio component (%d)\n", ret);
821 /* continue with reduced functionality */
822 return;
823 }
824#endif
825
826 dev_priv->audio_component_registered = true;
827}
828
829/**
830 * i915_audio_component_cleanup - deregister the audio component
831 * @dev_priv: i915 device instance
832 *
833 * Deregisters the audio component, breaking any existing binding to the
834 * corresponding snd_hda_intel driver's master component.
835 */
836void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
837{
838 if (!dev_priv->audio_component_registered)
839 return;
840
841#if 0
842 component_del(dev_priv->dev->dev, &i915_audio_component_bind_ops);
843#endif
844 dev_priv->audio_component_registered = false;
845}