machintr/i386: Function renaming; no functional changes
[dragonfly.git] / sys / platform / pc32 / apic / ioapic_abi.c
CommitLineData
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1/*
2 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
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3 * Copyright (c) 1996, by Steve Passe. All rights reserved.
4 * Copyright (c) 1991 The Regents of the University of California.
5 * All rights reserved.
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6 *
7 * This code is derived from software contributed to The DragonFly Project
8 * by Matthew Dillon <dillon@backplane.com>
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9 *
10 * This code is derived from software contributed to Berkeley by
11 * William Jolitz.
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12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 * 3. Neither the name of The DragonFly Project nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific, prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
31 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
32 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
35 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
37 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
37e7efec 39 *
0b692e79 40 * $DragonFly: src/sys/platform/pc32/apic/apic_abi.c,v 1.12 2007/04/30 16:45:55 dillon Exp $
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41 */
42
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/kernel.h>
46#include <sys/machintr.h>
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47#include <sys/interrupt.h>
48#include <sys/bus.h>
0b692e79 49
37e7efec 50#include <machine/smp.h>
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51#include <machine/segments.h>
52#include <machine/md_var.h>
87cf6827 53#include <machine/intr_machdep.h>
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54#include <machine/globaldata.h>
55
56#include <sys/thread2.h>
57
58587c23 58#include <machine_base/isa/isa_intr.h>
4298586a 59#include <machine_base/icu/icu.h>
6b809ec7 60#include <machine_base/icu/icu_var.h>
4298586a 61#include <machine_base/apic/ioapic.h>
929c940f 62#include <machine_base/apic/ioapic_abi.h>
77f86d14 63#include <machine_base/apic/ioapic_ipl.h>
1e7aaefa 64#include <machine_base/apic/apicreg.h>
37e7efec 65
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66#define IOAPIC_HWI_VECTORS IDT_HWI_VECTORS
67
10ff1029 68extern inthand_t
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69 IDTVEC(ioapic_intr0),
70 IDTVEC(ioapic_intr1),
71 IDTVEC(ioapic_intr2),
72 IDTVEC(ioapic_intr3),
73 IDTVEC(ioapic_intr4),
74 IDTVEC(ioapic_intr5),
75 IDTVEC(ioapic_intr6),
76 IDTVEC(ioapic_intr7),
77 IDTVEC(ioapic_intr8),
78 IDTVEC(ioapic_intr9),
79 IDTVEC(ioapic_intr10),
80 IDTVEC(ioapic_intr11),
81 IDTVEC(ioapic_intr12),
82 IDTVEC(ioapic_intr13),
83 IDTVEC(ioapic_intr14),
84 IDTVEC(ioapic_intr15),
85 IDTVEC(ioapic_intr16),
86 IDTVEC(ioapic_intr17),
87 IDTVEC(ioapic_intr18),
88 IDTVEC(ioapic_intr19),
89 IDTVEC(ioapic_intr20),
90 IDTVEC(ioapic_intr21),
91 IDTVEC(ioapic_intr22),
92 IDTVEC(ioapic_intr23),
93 IDTVEC(ioapic_intr24),
94 IDTVEC(ioapic_intr25),
95 IDTVEC(ioapic_intr26),
96 IDTVEC(ioapic_intr27),
97 IDTVEC(ioapic_intr28),
98 IDTVEC(ioapic_intr29),
99 IDTVEC(ioapic_intr30),
100 IDTVEC(ioapic_intr31),
101 IDTVEC(ioapic_intr32),
102 IDTVEC(ioapic_intr33),
103 IDTVEC(ioapic_intr34),
104 IDTVEC(ioapic_intr35),
105 IDTVEC(ioapic_intr36),
106 IDTVEC(ioapic_intr37),
107 IDTVEC(ioapic_intr38),
108 IDTVEC(ioapic_intr39),
109 IDTVEC(ioapic_intr40),
110 IDTVEC(ioapic_intr41),
111 IDTVEC(ioapic_intr42),
112 IDTVEC(ioapic_intr43),
113 IDTVEC(ioapic_intr44),
114 IDTVEC(ioapic_intr45),
115 IDTVEC(ioapic_intr46),
116 IDTVEC(ioapic_intr47),
117 IDTVEC(ioapic_intr48),
118 IDTVEC(ioapic_intr49),
119 IDTVEC(ioapic_intr50),
120 IDTVEC(ioapic_intr51),
121 IDTVEC(ioapic_intr52),
122 IDTVEC(ioapic_intr53),
123 IDTVEC(ioapic_intr54),
124 IDTVEC(ioapic_intr55),
125 IDTVEC(ioapic_intr56),
126 IDTVEC(ioapic_intr57),
127 IDTVEC(ioapic_intr58),
128 IDTVEC(ioapic_intr59),
129 IDTVEC(ioapic_intr60),
130 IDTVEC(ioapic_intr61),
131 IDTVEC(ioapic_intr62),
132 IDTVEC(ioapic_intr63),
133 IDTVEC(ioapic_intr64),
134 IDTVEC(ioapic_intr65),
135 IDTVEC(ioapic_intr66),
136 IDTVEC(ioapic_intr67),
137 IDTVEC(ioapic_intr68),
138 IDTVEC(ioapic_intr69),
139 IDTVEC(ioapic_intr70),
140 IDTVEC(ioapic_intr71),
141 IDTVEC(ioapic_intr72),
142 IDTVEC(ioapic_intr73),
143 IDTVEC(ioapic_intr74),
144 IDTVEC(ioapic_intr75),
145 IDTVEC(ioapic_intr76),
146 IDTVEC(ioapic_intr77),
147 IDTVEC(ioapic_intr78),
148 IDTVEC(ioapic_intr79),
149 IDTVEC(ioapic_intr80),
150 IDTVEC(ioapic_intr81),
151 IDTVEC(ioapic_intr82),
152 IDTVEC(ioapic_intr83),
153 IDTVEC(ioapic_intr84),
154 IDTVEC(ioapic_intr85),
155 IDTVEC(ioapic_intr86),
156 IDTVEC(ioapic_intr87),
157 IDTVEC(ioapic_intr88),
158 IDTVEC(ioapic_intr89),
159 IDTVEC(ioapic_intr90),
160 IDTVEC(ioapic_intr91),
161 IDTVEC(ioapic_intr92),
162 IDTVEC(ioapic_intr93),
163 IDTVEC(ioapic_intr94),
164 IDTVEC(ioapic_intr95),
165 IDTVEC(ioapic_intr96),
166 IDTVEC(ioapic_intr97),
167 IDTVEC(ioapic_intr98),
168 IDTVEC(ioapic_intr99),
169 IDTVEC(ioapic_intr100),
170 IDTVEC(ioapic_intr101),
171 IDTVEC(ioapic_intr102),
172 IDTVEC(ioapic_intr103),
173 IDTVEC(ioapic_intr104),
174 IDTVEC(ioapic_intr105),
175 IDTVEC(ioapic_intr106),
176 IDTVEC(ioapic_intr107),
177 IDTVEC(ioapic_intr108),
178 IDTVEC(ioapic_intr109),
179 IDTVEC(ioapic_intr110),
180 IDTVEC(ioapic_intr111),
181 IDTVEC(ioapic_intr112),
182 IDTVEC(ioapic_intr113),
183 IDTVEC(ioapic_intr114),
184 IDTVEC(ioapic_intr115),
185 IDTVEC(ioapic_intr116),
186 IDTVEC(ioapic_intr117),
187 IDTVEC(ioapic_intr118),
188 IDTVEC(ioapic_intr119),
189 IDTVEC(ioapic_intr120),
190 IDTVEC(ioapic_intr121),
191 IDTVEC(ioapic_intr122),
192 IDTVEC(ioapic_intr123),
193 IDTVEC(ioapic_intr124),
194 IDTVEC(ioapic_intr125),
195 IDTVEC(ioapic_intr126),
196 IDTVEC(ioapic_intr127),
197 IDTVEC(ioapic_intr128),
198 IDTVEC(ioapic_intr129),
199 IDTVEC(ioapic_intr130),
200 IDTVEC(ioapic_intr131),
201 IDTVEC(ioapic_intr132),
202 IDTVEC(ioapic_intr133),
203 IDTVEC(ioapic_intr134),
204 IDTVEC(ioapic_intr135),
205 IDTVEC(ioapic_intr136),
206 IDTVEC(ioapic_intr137),
207 IDTVEC(ioapic_intr138),
208 IDTVEC(ioapic_intr139),
209 IDTVEC(ioapic_intr140),
210 IDTVEC(ioapic_intr141),
211 IDTVEC(ioapic_intr142),
212 IDTVEC(ioapic_intr143),
213 IDTVEC(ioapic_intr144),
214 IDTVEC(ioapic_intr145),
215 IDTVEC(ioapic_intr146),
216 IDTVEC(ioapic_intr147),
217 IDTVEC(ioapic_intr148),
218 IDTVEC(ioapic_intr149),
219 IDTVEC(ioapic_intr150),
220 IDTVEC(ioapic_intr151),
221 IDTVEC(ioapic_intr152),
222 IDTVEC(ioapic_intr153),
223 IDTVEC(ioapic_intr154),
224 IDTVEC(ioapic_intr155),
225 IDTVEC(ioapic_intr156),
226 IDTVEC(ioapic_intr157),
227 IDTVEC(ioapic_intr158),
228 IDTVEC(ioapic_intr159),
229 IDTVEC(ioapic_intr160),
230 IDTVEC(ioapic_intr161),
231 IDTVEC(ioapic_intr162),
232 IDTVEC(ioapic_intr163),
233 IDTVEC(ioapic_intr164),
234 IDTVEC(ioapic_intr165),
235 IDTVEC(ioapic_intr166),
236 IDTVEC(ioapic_intr167),
237 IDTVEC(ioapic_intr168),
238 IDTVEC(ioapic_intr169),
239 IDTVEC(ioapic_intr170),
240 IDTVEC(ioapic_intr171),
241 IDTVEC(ioapic_intr172),
242 IDTVEC(ioapic_intr173),
243 IDTVEC(ioapic_intr174),
244 IDTVEC(ioapic_intr175),
245 IDTVEC(ioapic_intr176),
246 IDTVEC(ioapic_intr177),
247 IDTVEC(ioapic_intr178),
248 IDTVEC(ioapic_intr179),
249 IDTVEC(ioapic_intr180),
250 IDTVEC(ioapic_intr181),
251 IDTVEC(ioapic_intr182),
252 IDTVEC(ioapic_intr183),
253 IDTVEC(ioapic_intr184),
254 IDTVEC(ioapic_intr185),
255 IDTVEC(ioapic_intr186),
256 IDTVEC(ioapic_intr187),
257 IDTVEC(ioapic_intr188),
258 IDTVEC(ioapic_intr189),
259 IDTVEC(ioapic_intr190),
260 IDTVEC(ioapic_intr191);
261
262static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
263 &IDTVEC(ioapic_intr0),
264 &IDTVEC(ioapic_intr1),
265 &IDTVEC(ioapic_intr2),
266 &IDTVEC(ioapic_intr3),
267 &IDTVEC(ioapic_intr4),
268 &IDTVEC(ioapic_intr5),
269 &IDTVEC(ioapic_intr6),
270 &IDTVEC(ioapic_intr7),
271 &IDTVEC(ioapic_intr8),
272 &IDTVEC(ioapic_intr9),
273 &IDTVEC(ioapic_intr10),
274 &IDTVEC(ioapic_intr11),
275 &IDTVEC(ioapic_intr12),
276 &IDTVEC(ioapic_intr13),
277 &IDTVEC(ioapic_intr14),
278 &IDTVEC(ioapic_intr15),
279 &IDTVEC(ioapic_intr16),
280 &IDTVEC(ioapic_intr17),
281 &IDTVEC(ioapic_intr18),
282 &IDTVEC(ioapic_intr19),
283 &IDTVEC(ioapic_intr20),
284 &IDTVEC(ioapic_intr21),
285 &IDTVEC(ioapic_intr22),
286 &IDTVEC(ioapic_intr23),
287 &IDTVEC(ioapic_intr24),
288 &IDTVEC(ioapic_intr25),
289 &IDTVEC(ioapic_intr26),
290 &IDTVEC(ioapic_intr27),
291 &IDTVEC(ioapic_intr28),
292 &IDTVEC(ioapic_intr29),
293 &IDTVEC(ioapic_intr30),
294 &IDTVEC(ioapic_intr31),
295 &IDTVEC(ioapic_intr32),
296 &IDTVEC(ioapic_intr33),
297 &IDTVEC(ioapic_intr34),
298 &IDTVEC(ioapic_intr35),
299 &IDTVEC(ioapic_intr36),
300 &IDTVEC(ioapic_intr37),
301 &IDTVEC(ioapic_intr38),
302 &IDTVEC(ioapic_intr39),
303 &IDTVEC(ioapic_intr40),
304 &IDTVEC(ioapic_intr41),
305 &IDTVEC(ioapic_intr42),
306 &IDTVEC(ioapic_intr43),
307 &IDTVEC(ioapic_intr44),
308 &IDTVEC(ioapic_intr45),
309 &IDTVEC(ioapic_intr46),
310 &IDTVEC(ioapic_intr47),
311 &IDTVEC(ioapic_intr48),
312 &IDTVEC(ioapic_intr49),
313 &IDTVEC(ioapic_intr50),
314 &IDTVEC(ioapic_intr51),
315 &IDTVEC(ioapic_intr52),
316 &IDTVEC(ioapic_intr53),
317 &IDTVEC(ioapic_intr54),
318 &IDTVEC(ioapic_intr55),
319 &IDTVEC(ioapic_intr56),
320 &IDTVEC(ioapic_intr57),
321 &IDTVEC(ioapic_intr58),
322 &IDTVEC(ioapic_intr59),
323 &IDTVEC(ioapic_intr60),
324 &IDTVEC(ioapic_intr61),
325 &IDTVEC(ioapic_intr62),
326 &IDTVEC(ioapic_intr63),
327 &IDTVEC(ioapic_intr64),
328 &IDTVEC(ioapic_intr65),
329 &IDTVEC(ioapic_intr66),
330 &IDTVEC(ioapic_intr67),
331 &IDTVEC(ioapic_intr68),
332 &IDTVEC(ioapic_intr69),
333 &IDTVEC(ioapic_intr70),
334 &IDTVEC(ioapic_intr71),
335 &IDTVEC(ioapic_intr72),
336 &IDTVEC(ioapic_intr73),
337 &IDTVEC(ioapic_intr74),
338 &IDTVEC(ioapic_intr75),
339 &IDTVEC(ioapic_intr76),
340 &IDTVEC(ioapic_intr77),
341 &IDTVEC(ioapic_intr78),
342 &IDTVEC(ioapic_intr79),
343 &IDTVEC(ioapic_intr80),
344 &IDTVEC(ioapic_intr81),
345 &IDTVEC(ioapic_intr82),
346 &IDTVEC(ioapic_intr83),
347 &IDTVEC(ioapic_intr84),
348 &IDTVEC(ioapic_intr85),
349 &IDTVEC(ioapic_intr86),
350 &IDTVEC(ioapic_intr87),
351 &IDTVEC(ioapic_intr88),
352 &IDTVEC(ioapic_intr89),
353 &IDTVEC(ioapic_intr90),
354 &IDTVEC(ioapic_intr91),
355 &IDTVEC(ioapic_intr92),
356 &IDTVEC(ioapic_intr93),
357 &IDTVEC(ioapic_intr94),
358 &IDTVEC(ioapic_intr95),
359 &IDTVEC(ioapic_intr96),
360 &IDTVEC(ioapic_intr97),
361 &IDTVEC(ioapic_intr98),
362 &IDTVEC(ioapic_intr99),
363 &IDTVEC(ioapic_intr100),
364 &IDTVEC(ioapic_intr101),
365 &IDTVEC(ioapic_intr102),
366 &IDTVEC(ioapic_intr103),
367 &IDTVEC(ioapic_intr104),
368 &IDTVEC(ioapic_intr105),
369 &IDTVEC(ioapic_intr106),
370 &IDTVEC(ioapic_intr107),
371 &IDTVEC(ioapic_intr108),
372 &IDTVEC(ioapic_intr109),
373 &IDTVEC(ioapic_intr110),
374 &IDTVEC(ioapic_intr111),
375 &IDTVEC(ioapic_intr112),
376 &IDTVEC(ioapic_intr113),
377 &IDTVEC(ioapic_intr114),
378 &IDTVEC(ioapic_intr115),
379 &IDTVEC(ioapic_intr116),
380 &IDTVEC(ioapic_intr117),
381 &IDTVEC(ioapic_intr118),
382 &IDTVEC(ioapic_intr119),
383 &IDTVEC(ioapic_intr120),
384 &IDTVEC(ioapic_intr121),
385 &IDTVEC(ioapic_intr122),
386 &IDTVEC(ioapic_intr123),
387 &IDTVEC(ioapic_intr124),
388 &IDTVEC(ioapic_intr125),
389 &IDTVEC(ioapic_intr126),
390 &IDTVEC(ioapic_intr127),
391 &IDTVEC(ioapic_intr128),
392 &IDTVEC(ioapic_intr129),
393 &IDTVEC(ioapic_intr130),
394 &IDTVEC(ioapic_intr131),
395 &IDTVEC(ioapic_intr132),
396 &IDTVEC(ioapic_intr133),
397 &IDTVEC(ioapic_intr134),
398 &IDTVEC(ioapic_intr135),
399 &IDTVEC(ioapic_intr136),
400 &IDTVEC(ioapic_intr137),
401 &IDTVEC(ioapic_intr138),
402 &IDTVEC(ioapic_intr139),
403 &IDTVEC(ioapic_intr140),
404 &IDTVEC(ioapic_intr141),
405 &IDTVEC(ioapic_intr142),
406 &IDTVEC(ioapic_intr143),
407 &IDTVEC(ioapic_intr144),
408 &IDTVEC(ioapic_intr145),
409 &IDTVEC(ioapic_intr146),
410 &IDTVEC(ioapic_intr147),
411 &IDTVEC(ioapic_intr148),
412 &IDTVEC(ioapic_intr149),
413 &IDTVEC(ioapic_intr150),
414 &IDTVEC(ioapic_intr151),
415 &IDTVEC(ioapic_intr152),
416 &IDTVEC(ioapic_intr153),
417 &IDTVEC(ioapic_intr154),
418 &IDTVEC(ioapic_intr155),
419 &IDTVEC(ioapic_intr156),
420 &IDTVEC(ioapic_intr157),
421 &IDTVEC(ioapic_intr158),
422 &IDTVEC(ioapic_intr159),
423 &IDTVEC(ioapic_intr160),
424 &IDTVEC(ioapic_intr161),
425 &IDTVEC(ioapic_intr162),
426 &IDTVEC(ioapic_intr163),
427 &IDTVEC(ioapic_intr164),
428 &IDTVEC(ioapic_intr165),
429 &IDTVEC(ioapic_intr166),
430 &IDTVEC(ioapic_intr167),
431 &IDTVEC(ioapic_intr168),
432 &IDTVEC(ioapic_intr169),
433 &IDTVEC(ioapic_intr170),
434 &IDTVEC(ioapic_intr171),
435 &IDTVEC(ioapic_intr172),
436 &IDTVEC(ioapic_intr173),
437 &IDTVEC(ioapic_intr174),
438 &IDTVEC(ioapic_intr175),
439 &IDTVEC(ioapic_intr176),
440 &IDTVEC(ioapic_intr177),
441 &IDTVEC(ioapic_intr178),
442 &IDTVEC(ioapic_intr179),
443 &IDTVEC(ioapic_intr180),
444 &IDTVEC(ioapic_intr181),
445 &IDTVEC(ioapic_intr182),
446 &IDTVEC(ioapic_intr183),
447 &IDTVEC(ioapic_intr184),
448 &IDTVEC(ioapic_intr185),
449 &IDTVEC(ioapic_intr186),
450 &IDTVEC(ioapic_intr187),
451 &IDTVEC(ioapic_intr188),
452 &IDTVEC(ioapic_intr189),
453 &IDTVEC(ioapic_intr190),
454 &IDTVEC(ioapic_intr191)
c571da4a 455};
10ff1029 456
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457#define IOAPIC_HWI_SYSCALL (IDT_OFFSET_SYSCALL - IDT_OFFSET)
458
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459static struct ioapic_irqmap {
460 int im_type; /* IOAPIC_IMT_ */
461 enum intr_trigger im_trig;
f6915355 462 enum intr_polarity im_pola;
a3dd9120 463 int im_gsi;
d1ae7328 464 uint32_t im_flags; /* IOAPIC_IMF_ */
b2150df1 465} ioapic_irqmaps[IOAPIC_HWI_VECTORS];
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466
467#define IOAPIC_IMT_UNUSED 0
468#define IOAPIC_IMT_RESERVED 1
469#define IOAPIC_IMT_LINE 2
474ba684 470#define IOAPIC_IMT_SYSCALL 3
a3dd9120 471
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472#define IOAPIC_IMF_CONF 0x1
473
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474extern void IOAPIC_INTREN(int);
475extern void IOAPIC_INTRDIS(int);
476
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477extern int imcr_present;
478
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479static void ioapic_abi_intr_enable(int);
480static void ioapic_abi_intr_disable(int);
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481static void ioapic_abi_intr_setup(int, int);
482static void ioapic_abi_intr_teardown(int);
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483static void ioapic_abi_intr_config(int,
484 enum intr_trigger, enum intr_polarity);
35b2edcb 485
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486static void ioapic_abi_finalize(void);
487static void ioapic_abi_cleanup(void);
488static void ioapic_abi_setdefault(void);
489static void ioapic_abi_stabilize(void);
490static void ioapic_abi_initmap(void);
9e0e3f85 491
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492struct machintr_abi MachIntrABI_IOAPIC = {
493 MACHINTR_IOAPIC,
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494
495 .intr_disable = ioapic_abi_intr_disable,
496 .intr_enable = ioapic_abi_intr_enable,
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497 .intr_setup = ioapic_abi_intr_setup,
498 .intr_teardown = ioapic_abi_intr_teardown,
780a6eec 499 .intr_config = ioapic_abi_intr_config,
35b2edcb 500
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501 .finalize = ioapic_abi_finalize,
502 .cleanup = ioapic_abi_cleanup,
503 .setdefault = ioapic_abi_setdefault,
504 .stabilize = ioapic_abi_stabilize,
505 .initmap = ioapic_abi_initmap
37e7efec
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506};
507
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508static int ioapic_abi_extint_irq = -1;
509
7a54dec9 510struct ioapic_irqinfo ioapic_irqs[IOAPIC_HWI_VECTORS];
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511
512static void
35b2edcb 513ioapic_abi_intr_enable(int irq)
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514{
515 if (irq < 0 || irq >= IOAPIC_HWI_VECTORS) {
35b2edcb 516 kprintf("ioapic_abi_intr_enable invalid irq %d\n", irq);
fa6eddaf
SZ
517 return;
518 }
519 IOAPIC_INTREN(irq);
520}
521
522static void
35b2edcb 523ioapic_abi_intr_disable(int irq)
fa6eddaf
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524{
525 if (irq < 0 || irq >= IOAPIC_HWI_VECTORS) {
35b2edcb 526 kprintf("ioapic_abi_intr_disable invalid irq %d\n", irq);
fa6eddaf
SZ
527 return;
528 }
529 IOAPIC_INTRDIS(irq);
530}
531
37e7efec 532static void
780a6eec 533ioapic_abi_finalize(void)
37e7efec 534{
e0918665 535 KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
f45bfca0 536 KKASSERT(ioapic_enable);
10db3cc6 537
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538 /*
539 * If an IMCR is present, program bit 0 to disconnect the 8259
e0918665 540 * from the BSP.
54e1df6b 541 */
9d758cc4 542 if (imcr_present) {
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SZ
543 outb(0x22, 0x70); /* select IMCR */
544 outb(0x23, 0x01); /* disconnect 8259 */
545 }
37e7efec
MD
546}
547
0b692e79
MD
548/*
549 * This routine is called after physical interrupts are enabled but before
550 * the critical section is released. We need to clean out any interrupts
551 * that had already been posted to the cpu.
552 */
553static void
780a6eec 554ioapic_abi_cleanup(void)
0b692e79 555{
c263294b 556 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
0b692e79
MD
557}
558
7bf5fa56
SZ
559/* Must never be called */
560static void
780a6eec 561ioapic_abi_stabilize(void)
7bf5fa56
SZ
562{
563 panic("ioapic_stabilize() is called\n");
564}
565
f416026e
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566static void
567ioapic_abi_intr_setup(int intr, int flags)
10ff1029 568{
f416026e 569 int vector, select;
54e1df6b
SZ
570 uint32_t value;
571 u_long ef;
10ff1029 572
f416026e
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573 KKASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS &&
574 intr != IOAPIC_HWI_SYSCALL);
575 KKASSERT(ioapic_irqs[intr].io_addr != NULL);
576
577 ef = read_eflags();
578 cpu_disable_intr();
579
580 vector = IDT_OFFSET + intr;
581 setidt(vector, ioapic_intr[intr], SDT_SYS386IGT,
582 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
583
584 /*
585 * Now reprogram the vector in the IO APIC. In order to avoid
586 * losing an EOI for a level interrupt, which is vector based,
587 * make sure that the IO APIC is programmed for edge-triggering
588 * first, then reprogrammed with the new vector. This should
589 * clear the IRR bit.
590 */
591 imen_lock();
592
593 select = ioapic_irqs[intr].io_idx;
594 value = ioapic_read(ioapic_irqs[intr].io_addr, select);
595 value |= IOART_INTMSET;
596
597 ioapic_write(ioapic_irqs[intr].io_addr, select,
598 (value & ~APIC_TRIGMOD_MASK));
599 ioapic_write(ioapic_irqs[intr].io_addr, select,
600 (value & ~IOART_INTVEC) | vector);
601
602 imen_unlock();
603
35b2edcb 604 machintr_intr_enable(intr);
f416026e
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605
606 write_eflags(ef);
607}
608
609static void
610ioapic_abi_intr_teardown(int intr)
611{
612 int vector, select;
613 uint32_t value;
614 u_long ef;
10ff1029 615
f416026e
SZ
616 KKASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS &&
617 intr != IOAPIC_HWI_SYSCALL);
618 KKASSERT(ioapic_irqs[intr].io_addr != NULL);
7a54dec9 619
54e1df6b
SZ
620 ef = read_eflags();
621 cpu_disable_intr();
10ff1029 622
f416026e
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623 /*
624 * Teardown an interrupt vector. The vector should already be
625 * installed in the cpu's IDT, but make sure.
626 */
35b2edcb 627 machintr_intr_disable(intr);
35408d22 628
f416026e
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629 vector = IDT_OFFSET + intr;
630 setidt(vector, ioapic_intr[intr], SDT_SYS386IGT, SEL_KPL,
631 GSEL(GCODE_SEL, SEL_KPL));
632
633 /*
634 * In order to avoid losing an EOI for a level interrupt, which
635 * is vector based, make sure that the IO APIC is programmed for
636 * edge-triggering first, then reprogrammed with the new vector.
637 * This should clear the IRR bit.
638 */
639 imen_lock();
640
641 select = ioapic_irqs[intr].io_idx;
642 value = ioapic_read(ioapic_irqs[intr].io_addr, select);
643
644 ioapic_write(ioapic_irqs[intr].io_addr, select,
645 (value & ~APIC_TRIGMOD_MASK));
646 ioapic_write(ioapic_irqs[intr].io_addr, select,
647 (value & ~IOART_INTVEC) | vector);
648
649 imen_unlock();
10ff1029 650
54e1df6b 651 write_eflags(ef);
54e1df6b 652}
06f5be02 653
10db3cc6 654static void
780a6eec 655ioapic_abi_setdefault(void)
10db3cc6
SZ
656{
657 int intr;
658
9e0e3f85 659 for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
474ba684 660 if (intr == IOAPIC_HWI_SYSCALL)
10db3cc6 661 continue;
9e0e3f85 662 setidt(IDT_OFFSET + intr, ioapic_intr[intr], SDT_SYS386IGT,
10db3cc6
SZ
663 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
664 }
665}
666
a3dd9120 667static void
780a6eec 668ioapic_abi_initmap(void)
a3dd9120
SZ
669{
670 int i;
671
c36b581c
SZ
672 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i)
673 ioapic_irqmaps[i].im_gsi = -1;
474ba684 674 ioapic_irqmaps[IOAPIC_HWI_SYSCALL].im_type = IOAPIC_IMT_SYSCALL;
a3dd9120
SZ
675}
676
929c940f
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677void
678ioapic_abi_set_irqmap(int irq, int gsi, enum intr_trigger trig,
679 enum intr_polarity pola)
680{
7a54dec9 681 struct ioapic_irqinfo *info;
929c940f
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682 struct ioapic_irqmap *map;
683 void *ioaddr;
684 int pin;
685
686 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
687 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
929c940f
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688
689 KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
690 map = &ioapic_irqmaps[irq];
691
692 KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
693 map->im_type = IOAPIC_IMT_LINE;
694
695 map->im_gsi = gsi;
696 map->im_trig = trig;
697 map->im_pola = pola;
698
699 if (bootverbose) {
4ecd5d4d
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700 kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n",
701 irq, map->im_gsi,
702 intr_str_trigger(map->im_trig),
703 intr_str_polarity(map->im_pola));
929c940f
SZ
704 }
705
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706 pin = ioapic_gsi_pin(map->im_gsi);
707 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
929c940f 708
7a54dec9 709 info = &ioapic_irqs[irq];
929c940f 710
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711 imen_lock();
712
7a54dec9
SZ
713 info->io_addr = ioaddr;
714 info->io_idx = IOAPIC_REDTBL + (2 * pin);
715 info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
d1ae7328 716 if (map->im_trig == INTR_TRIGGER_LEVEL)
7a54dec9 717 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
d1ae7328
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718
719 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
720 map->im_trig, map->im_pola);
7bceaa10
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721
722 imen_unlock();
d1ae7328
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723}
724
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725void
726ioapic_abi_fixup_irqmap(void)
727{
728 int i;
729
58587c23 730 for (i = 0; i < ISA_IRQ_CNT; ++i) {
4a913811
SZ
731 struct ioapic_irqmap *map = &ioapic_irqmaps[i];
732
733 if (map->im_type == IOAPIC_IMT_UNUSED) {
734 map->im_type = IOAPIC_IMT_RESERVED;
735 if (bootverbose)
736 kprintf("IOAPIC: irq %d reserved\n", i);
737 }
738 }
739}
740
e90e7ac4
SZ
741int
742ioapic_abi_find_gsi(int gsi, enum intr_trigger trig, enum intr_polarity pola)
743{
744 int irq;
745
746 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
747 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
e90e7ac4
SZ
748
749 for (irq = 0; irq < IOAPIC_HWI_VECTORS; ++irq) {
750 const struct ioapic_irqmap *map = &ioapic_irqmaps[irq];
751
752 if (map->im_gsi == gsi) {
753 KKASSERT(map->im_type == IOAPIC_IMT_LINE);
754
755 if (map->im_flags & IOAPIC_IMF_CONF) {
756 if (map->im_trig != trig ||
757 map->im_pola != pola)
758 return -1;
759 }
760 return irq;
761 }
762 }
763 return -1;
764}
765
766int
767ioapic_abi_find_irq(int irq, enum intr_trigger trig, enum intr_polarity pola)
768{
769 const struct ioapic_irqmap *map;
770
771 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
772 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
e90e7ac4
SZ
773
774 if (irq < 0 || irq >= IOAPIC_HWI_VECTORS)
775 return -1;
776 map = &ioapic_irqmaps[irq];
777
778 if (map->im_type != IOAPIC_IMT_LINE)
779 return -1;
780
781 if (map->im_flags & IOAPIC_IMF_CONF) {
782 if (map->im_trig != trig || map->im_pola != pola)
783 return -1;
784 }
785 return irq;
786}
787
d1ae7328 788static void
780a6eec 789ioapic_abi_intr_config(int irq, enum intr_trigger trig, enum intr_polarity pola)
d1ae7328 790{
7a54dec9 791 struct ioapic_irqinfo *info;
d1ae7328
SZ
792 struct ioapic_irqmap *map;
793 void *ioaddr;
794 int pin;
795
d1ae7328
SZ
796 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
797 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
d1ae7328
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798
799 KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
800 map = &ioapic_irqmaps[irq];
801
802 KKASSERT(map->im_type == IOAPIC_IMT_LINE);
803
7962296e 804#ifdef notyet
d1ae7328
SZ
805 if (map->im_flags & IOAPIC_IMF_CONF) {
806 if (trig != map->im_trig) {
4ecd5d4d
SZ
807 panic("ioapic_intr_config: trig %s -> %s\n",
808 intr_str_trigger(map->im_trig),
809 intr_str_trigger(trig));
d1ae7328
SZ
810 }
811 if (pola != map->im_pola) {
812 panic("ioapic_intr_config: pola %s -> %s\n",
4ecd5d4d
SZ
813 intr_str_polarity(map->im_pola),
814 intr_str_polarity(pola));
d1ae7328
SZ
815 }
816 return;
817 }
7962296e 818#endif
d1ae7328
SZ
819 map->im_flags |= IOAPIC_IMF_CONF;
820
821 if (trig == map->im_trig && pola == map->im_pola)
822 return;
823
824 if (bootverbose) {
4ecd5d4d
SZ
825 kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n",
826 irq, map->im_gsi,
827 intr_str_trigger(map->im_trig),
828 intr_str_polarity(map->im_pola),
829 intr_str_trigger(trig),
830 intr_str_polarity(pola));
d1ae7328 831 }
d1ae7328
SZ
832 map->im_trig = trig;
833 map->im_pola = pola;
834
835 pin = ioapic_gsi_pin(map->im_gsi);
836 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
837
7a54dec9 838 info = &ioapic_irqs[irq];
d1ae7328 839
7bceaa10
SZ
840 imen_lock();
841
7a54dec9 842 info->io_flags &= ~IOAPIC_IRQI_FLAG_LEVEL;
d1ae7328 843 if (map->im_trig == INTR_TRIGGER_LEVEL)
7a54dec9 844 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
929c940f 845
ecec8ddc
SZ
846 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
847 map->im_trig, map->im_pola);
7bceaa10
SZ
848
849 imen_unlock();
929c940f
SZ
850}
851
6b809ec7
SZ
852int
853ioapic_abi_extint_irqmap(int irq)
854{
7a54dec9 855 struct ioapic_irqinfo *info;
6b809ec7
SZ
856 struct ioapic_irqmap *map;
857 void *ioaddr;
858 int pin, error, vec;
859
860 vec = IDT_OFFSET + irq;
861
862 if (ioapic_abi_extint_irq == irq)
863 return 0;
864 else if (ioapic_abi_extint_irq >= 0)
865 return EEXIST;
866
867 error = icu_ioapic_extint(irq, vec);
868 if (error)
869 return error;
870
871 map = &ioapic_irqmaps[irq];
872
873 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED ||
874 map->im_type == IOAPIC_IMT_LINE);
875 if (map->im_type == IOAPIC_IMT_LINE) {
876 if (map->im_flags & IOAPIC_IMF_CONF)
877 return EEXIST;
878 }
879 ioapic_abi_extint_irq = irq;
880
881 map->im_type = IOAPIC_IMT_LINE;
882 map->im_trig = INTR_TRIGGER_EDGE;
883 map->im_pola = INTR_POLARITY_HIGH;
884 map->im_flags = IOAPIC_IMF_CONF;
885
886 map->im_gsi = ioapic_extpin_gsi();
887 KKASSERT(map->im_gsi >= 0);
888
889 if (bootverbose) {
4ecd5d4d
SZ
890 kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n",
891 irq, map->im_gsi,
892 intr_str_trigger(map->im_trig),
893 intr_str_polarity(map->im_pola));
6b809ec7
SZ
894 }
895
896 pin = ioapic_gsi_pin(map->im_gsi);
897 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
898
7a54dec9 899 info = &ioapic_irqs[irq];
6b809ec7
SZ
900
901 imen_lock();
902
7a54dec9
SZ
903 info->io_addr = ioaddr;
904 info->io_idx = IOAPIC_REDTBL + (2 * pin);
905 info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
6b809ec7
SZ
906
907 ioapic_extpin_setup(ioaddr, pin, vec);
908
909 imen_unlock();
910
911 return 0;
912}