machintr/i386: Function renaming; no functional changes
[dragonfly.git] / sys / platform / pc32 / icu / icu_abi.c
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1/*
2 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
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3 * Copyright (c) 1991 The Regents of the University of California.
4 * All rights reserved.
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5 *
6 * This code is derived from software contributed to The DragonFly Project
7 * by Matthew Dillon <dillon@backplane.com>
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8 *
9 * This code is derived from software contributed to Berkeley by
10 * William Jolitz.
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11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in
20 * the documentation and/or other materials provided with the
21 * distribution.
22 * 3. Neither the name of The DragonFly Project nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific, prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
29 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
30 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
32 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
34 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
36 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
d916dbc1 39 * $DragonFly: src/sys/platform/pc32/icu/icu_abi.c,v 1.14 2007/07/07 12:13:47 sephe Exp $
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40 */
41
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42#include <sys/param.h>
43#include <sys/systm.h>
44#include <sys/kernel.h>
45#include <sys/machintr.h>
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46#include <sys/interrupt.h>
47#include <sys/bus.h>
48
49#include <machine/segments.h>
50#include <machine/md_var.h>
87cf6827 51#include <machine/intr_machdep.h>
0b692e79 52#include <machine/globaldata.h>
10db3cc6 53#include <machine/smp.h>
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54
55#include <sys/thread2.h>
5f456c40 56
7265a4fe 57#include <machine_base/icu/elcr_var.h>
9e0e3f85 58
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59#include <machine_base/icu/icu.h>
60#include <machine_base/icu/icu_ipl.h>
ed4d621d 61#include <machine_base/apic/ioapic.h>
37e7efec 62
10ff1029 63extern inthand_t
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64 IDTVEC(icu_intr0), IDTVEC(icu_intr1),
65 IDTVEC(icu_intr2), IDTVEC(icu_intr3),
66 IDTVEC(icu_intr4), IDTVEC(icu_intr5),
67 IDTVEC(icu_intr6), IDTVEC(icu_intr7),
68 IDTVEC(icu_intr8), IDTVEC(icu_intr9),
69 IDTVEC(icu_intr10), IDTVEC(icu_intr11),
70 IDTVEC(icu_intr12), IDTVEC(icu_intr13),
71 IDTVEC(icu_intr14), IDTVEC(icu_intr15);
10ff1029 72
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73static inthand_t *icu_intr[ICU_HWI_VECTORS] = {
74 &IDTVEC(icu_intr0), &IDTVEC(icu_intr1),
75 &IDTVEC(icu_intr2), &IDTVEC(icu_intr3),
76 &IDTVEC(icu_intr4), &IDTVEC(icu_intr5),
77 &IDTVEC(icu_intr6), &IDTVEC(icu_intr7),
78 &IDTVEC(icu_intr8), &IDTVEC(icu_intr9),
79 &IDTVEC(icu_intr10), &IDTVEC(icu_intr11),
80 &IDTVEC(icu_intr12), &IDTVEC(icu_intr13),
81 &IDTVEC(icu_intr14), &IDTVEC(icu_intr15)
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82};
83
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84static struct icu_irqmap {
85 int im_type; /* ICU_IMT_ */
86 enum intr_trigger im_trig;
b2150df1 87} icu_irqmaps[IDT_HWI_VECTORS];
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88
89#define ICU_IMT_UNUSED 0 /* KEEP THIS */
90#define ICU_IMT_RESERVED 1
91#define ICU_IMT_LINE 2
474ba684 92#define ICU_IMT_SYSCALL 3
a3dd9120 93
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94extern void ICU_INTREN(int);
95extern void ICU_INTRDIS(int);
96
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97extern int imcr_present;
98
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99static void icu_abi_intr_setup(int, int);
100static void icu_abi_intr_teardown(int);
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101static void icu_abi_intr_config(int, enum intr_trigger, enum intr_polarity);
102
103static void icu_abi_finalize(void);
104static void icu_abi_cleanup(void);
105static void icu_abi_setdefault(void);
106static void icu_abi_stabilize(void);
107static void icu_abi_initmap(void);
10db3cc6 108
30c5f287 109struct machintr_abi MachIntrABI_ICU = {
54e1df6b 110 MACHINTR_ICU,
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111
112 .intr_disable = ICU_INTRDIS,
113 .intr_enable = ICU_INTREN,
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114 .intr_setup = icu_abi_intr_setup,
115 .intr_teardown = icu_abi_intr_teardown,
780a6eec 116 .intr_config = icu_abi_intr_config,
35b2edcb 117
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118 .finalize = icu_abi_finalize,
119 .cleanup = icu_abi_cleanup,
120 .setdefault = icu_abi_setdefault,
121 .stabilize = icu_abi_stabilize,
122 .initmap = icu_abi_initmap
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123};
124
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125/*
126 * WARNING! SMP builds can use the ICU now so this code must be MP safe.
127 */
37e7efec 128
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129/*
130 * Called before interrupts are physically enabled
131 */
37e7efec 132static void
780a6eec 133icu_abi_stabilize(void)
37e7efec 134{
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135 int intr;
136
7bf5fa56 137 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr)
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138 machintr_intr_disable(intr);
139 machintr_intr_enable(ICU_IRQ_SLAVE);
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140}
141
142/*
143 * Called after interrupts physically enabled but before the
144 * critical section is released.
145 */
146static void
780a6eec 147icu_abi_cleanup(void)
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148{
149 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
150}
151
152/*
153 * Called after stablize and cleanup; critical section is not
154 * held and interrupts are not physically disabled.
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155 */
156static void
780a6eec 157icu_abi_finalize(void)
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158{
159 KKASSERT(MachIntrABI.type == MACHINTR_ICU);
f45bfca0 160 KKASSERT(!ioapic_enable);
54e1df6b 161
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162 /*
163 * If an IMCR is present, programming bit 0 disconnects the 8259
164 * from the BSP. The 8259 may still be connected to LINT0 on the
165 * BSP's LAPIC.
166 *
167 * If we are running SMP the LAPIC is active, try to use virtual
168 * wire mode so we can use other interrupt sources within the LAPIC
169 * in addition to the 8259.
170 */
9d758cc4 171 if (imcr_present) {
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172 outb(0x22, 0x70);
173 outb(0x23, 0x01);
7bf5fa56 174 }
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175}
176
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177static void
178icu_abi_intr_setup(int intr, int flags __unused)
10ff1029 179{
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180 u_long ef;
181
f416026e 182 KKASSERT(intr >= 0 && intr < ICU_HWI_VECTORS && intr != ICU_IRQ_SLAVE);
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183
184 ef = read_eflags();
185 cpu_disable_intr();
54e1df6b 186
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187 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
188 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
35b2edcb 189 machintr_intr_enable(intr);
54e1df6b 190
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191 write_eflags(ef);
192}
193
194static void
195icu_abi_intr_teardown(int intr)
196{
197 u_long ef;
198
199 KKASSERT(intr >= 0 && intr < ICU_HWI_VECTORS && intr != ICU_IRQ_SLAVE);
200
201 ef = read_eflags();
202 cpu_disable_intr();
203
35b2edcb 204 machintr_intr_disable(intr);
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205 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
206 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
54e1df6b 207
54e1df6b 208 write_eflags(ef);
10ff1029 209}
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210
211static void
780a6eec 212icu_abi_setdefault(void)
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213{
214 int intr;
215
216 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) {
217 if (intr == ICU_IRQ_SLAVE)
218 continue;
219 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
220 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
221 }
222}
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223
224static void
780a6eec 225icu_abi_initmap(void)
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226{
227 int i;
228
229 for (i = 0; i < ICU_HWI_VECTORS; ++i)
230 icu_irqmaps[i].im_type = ICU_IMT_LINE;
231 icu_irqmaps[ICU_IRQ_SLAVE].im_type = ICU_IMT_RESERVED;
232
233 if (elcr_found) {
234 for (i = 0; i < ICU_HWI_VECTORS; ++i)
235 icu_irqmaps[i].im_trig = elcr_read_trigger(i);
236 } else {
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237 /*
238 * NOTE: Trigger mode does not matter at all
239 */
240 for (i = 0; i < ICU_HWI_VECTORS; ++i)
241 icu_irqmaps[i].im_trig = INTR_TRIGGER_EDGE;
a3dd9120 242 }
474ba684 243 icu_irqmaps[IDT_OFFSET_SYSCALL - IDT_OFFSET].im_type = ICU_IMT_SYSCALL;
a3dd9120 244}
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245
246static void
780a6eec 247icu_abi_intr_config(int irq, enum intr_trigger trig,
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248 enum intr_polarity pola __unused)
249{
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250 struct icu_irqmap *map;
251
252 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
253
b2150df1 254 KKASSERT(irq >= 0 && irq < IDT_HWI_VECTORS);
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255 map = &icu_irqmaps[irq];
256
257 KKASSERT(map->im_type == ICU_IMT_LINE);
258
259 /* TODO: Check whether it is configured or not */
260
261 if (trig == map->im_trig)
262 return;
263
264 if (bootverbose) {
265 kprintf("ICU: irq %d, %s -> %s\n", irq,
266 intr_str_trigger(map->im_trig),
267 intr_str_trigger(trig));
268 }
269 map->im_trig = trig;
270
271 if (!elcr_found) {
272 if (bootverbose)
273 kprintf("ICU: no ELCR, skip irq %d config\n", irq);
274 return;
275 }
276 elcr_write_trigger(irq, map->im_trig);
d1ae7328 277}