timeout/untimeout ==> callout_*
[dragonfly.git] / sys / dev / atm / hfa / fore_var.h
CommitLineData
984263bc
MD
1/*
2 *
3 * ===================================
4 * HARP | Host ATM Research Platform
5 * ===================================
6 *
7 *
8 * This Host ATM Research Platform ("HARP") file (the "Software") is
9 * made available by Network Computing Services, Inc. ("NetworkCS")
10 * "AS IS". NetworkCS does not provide maintenance, improvements or
11 * support of any kind.
12 *
13 * NETWORKCS MAKES NO WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED,
14 * INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY
15 * AND FITNESS FOR A PARTICULAR PURPOSE, AS TO ANY ELEMENT OF THE
16 * SOFTWARE OR ANY SUPPORT PROVIDED IN CONNECTION WITH THIS SOFTWARE.
17 * In no event shall NetworkCS be responsible for any damages, including
18 * but not limited to consequential damages, arising from or relating to
19 * any use of the Software or related support.
20 *
21 * Copyright 1994-1998 Network Computing Services, Inc.
22 *
23 * Copies of this Software may be made, however, the above copyright
24 * notice must be reproduced on all copies.
25 *
26 * @(#) $FreeBSD: src/sys/dev/hfa/fore_var.h,v 1.2 1999/08/28 00:41:53 peter Exp $
7a651277 27 * @(#) $DragonFly: src/sys/dev/atm/hfa/fore_var.h,v 1.3 2004/09/15 01:51:55 joerg Exp $
984263bc
MD
28 *
29 */
30
31/*
32 * FORE Systems 200-Series Adapter Support
33 * ---------------------------------------
34 *
35 * Host protocol control blocks
36 *
37 */
38
39#ifndef _FORE_VAR_H
40#define _FORE_VAR_H
41
42/*
43 * Device VCC Entry
44 *
45 * Contains the common and Fore-specific information for each VCC
46 * which is opened through a Fore device.
47 */
48struct fore_vcc {
49 struct cmn_vcc fv_cmn; /* Common VCC stuff */
50 Fore_aal fv_aal; /* CP version of AAL */
51};
52typedef struct fore_vcc Fore_vcc;
53
54#define fv_next fv_cmn.cv_next
55#define fv_toku fv_cmn.cv_toku
56#define fv_upper fv_cmn.cv_upper
57#define fv_connvc fv_cmn.cv_connvc
58#define fv_state fv_cmn.cv_state
59#define fv_flags fv_cmn.cv_flags
60
61/*
62 * VCC Flags
63 */
64#define FVF_ACTCMD 0x01 /* Activate command issued */
65
66
67/*
68 * Host Transmit Queue Element
69 *
70 * Defines the host's view of the CP PDU Transmit Queue
71 */
72struct h_xmit_queue {
73 struct h_xmit_queue *hxq_next; /* Next element in queue */
74 Xmit_queue *hxq_cpelem; /* CP queue element */
75 Q_status *hxq_status; /* Element status word */
76 Xmit_descr *hxq_descr; /* Element's transmit descriptor */
77 Xmit_descr *hxq_descr_dma; /* Element's transmit descriptor */
78 Fore_vcc *hxq_vcc; /* Data's VCC */
79 KBuffer *hxq_buf; /* Data's buffer chain head */
80 H_dma hxq_dma[XMIT_MAX_SEGS]; /* DMA addresses for segments */
81};
82typedef struct h_xmit_queue H_xmit_queue;
83
84
85
86/*
87 * Host Receive Queue Element
88 *
89 * Defines the host's view of the CP PDU Receive Queue
90 */
91struct h_recv_queue {
92 struct h_recv_queue *hrq_next; /* Next element in queue */
93 Recv_queue *hrq_cpelem; /* CP queue element */
94 Q_status *hrq_status; /* Element status word */
95 Recv_descr *hrq_descr; /* Element's receive descriptor */
96 Recv_descr *hrq_descr_dma; /* Element's receive descriptor */
97};
98typedef struct h_recv_queue H_recv_queue;
99
100
101
102/*
103 * Host Buffer Supply Queue Element
104 *
105 * Defines the host's view of the CP Buffer Supply Queue
106 */
107struct h_buf_queue {
108 struct h_buf_queue *hbq_next; /* Next element in queue */
109 Buf_queue *hbq_cpelem; /* CP queue element */
110 Q_status *hbq_status; /* Element status word */
111 Buf_descr *hbq_descr; /* Element's buffer descriptor array */
112 Buf_descr *hbq_descr_dma; /* Element's buffer descriptor array */
113};
114typedef struct h_buf_queue H_buf_queue;
115
116
117
118/*
119 * Host Command Queue Element
120 *
121 * Defines the host's view of the CP Command Queue
122 */
123struct h_cmd_queue {
124 struct h_cmd_queue *hcq_next; /* Next element in queue */
125 Cmd_queue *hcq_cpelem; /* CP queue element */
126 Q_status *hcq_status; /* Element status word */
127 Cmd_code hcq_code; /* Command code */
128 void *hcq_arg; /* Command-specific argument */
129};
130typedef struct h_cmd_queue H_cmd_queue;
131
132
133
134/*
135 * Host Buffer Handle
136 *
137 * For each buffer supplied to the CP, there will be one of these structures
138 * embedded into the non-data portion of the buffer. This will allow us to
139 * track which buffers are currently "controlled" by the CP. The address of
140 * this structure will supplied to/returned from the CP as the buffer handle.
141 */
142struct buf_handle {
143 Qelem_t bh_qelem; /* Queuing element */
144 u_int bh_type; /* Buffer type (see below) */
145 H_dma bh_dma; /* Buffer DMA address */
146};
147typedef struct buf_handle Buf_handle;
148#define SIZEOF_Buf_handle 16
149
150/*
151 * Buffer Types
152 */
153#define BHT_S1_SMALL 1 /* Buffer strategy 1, small */
154#define BHT_S1_LARGE 2 /* Buffer strategy 1, large */
155#define BHT_S2_SMALL 3 /* Buffer strategy 2, small */
156#define BHT_S2_LARGE 4 /* Buffer strategy 2, large */
157
158
159
160/*
161 * Device Unit Structure
162 *
163 * Contains all the information for a single device (adapter).
164 */
165struct fore_unit {
166 Cmn_unit fu_cmn; /* Common unit stuff */
167#ifdef sun
168 struct dev_info *fu_devinfo; /* Device node for this unit */
169#endif
170 Fore_reg *fu_ctlreg; /* Device control register */
171#ifdef FORE_SBUS
172 Fore_reg *fu_intlvl; /* Interrupt level register */
173#endif
174#ifdef FORE_PCI
175 Fore_reg *fu_imask; /* Interrupt mask register */
176 Fore_reg *fu_psr; /* PCI specific register */
177 pcici_t fu_pcitag; /* PCI tag */
178#endif
179 Fore_mem *fu_ram; /* Device RAM */
180 u_int fu_ramsize; /* Size of device RAM */
181 Mon960 *fu_mon; /* Monitor program interface */
182 Aali *fu_aali; /* Microcode program interface */
183 u_int fu_timer; /* Watchdog timer value */
184
185 /* Transmit Queue */
186 H_xmit_queue fu_xmit_q[XMIT_QUELEN]; /* Host queue */
187 H_xmit_queue *fu_xmit_head; /* Queue head */
188 H_xmit_queue *fu_xmit_tail; /* Queue tail */
189 Q_status *fu_xmit_stat; /* Status array (host) */
190 Q_status *fu_xmit_statd; /* Status array (DMA) */
191
192 /* Receive Queue */
193 H_recv_queue fu_recv_q[RECV_QUELEN]; /* Host queue */
194 H_recv_queue *fu_recv_head; /* Queue head */
195 Q_status *fu_recv_stat; /* Status array (host) */
196 Q_status *fu_recv_statd; /* Status array (DMA) */
197 Recv_descr *fu_recv_desc; /* Descriptor array (host) */
198 Recv_descr *fu_recv_descd; /* Descriptor array (DMA) */
199
200 /* Buffer Supply Queue - Strategy 1 Small */
201 H_buf_queue fu_buf1s_q[BUF1_SM_QUELEN]; /* Host queue */
202 H_buf_queue *fu_buf1s_head; /* Queue head */
203 H_buf_queue *fu_buf1s_tail; /* Queue tail */
204 Q_status *fu_buf1s_stat; /* Status array (host) */
205 Q_status *fu_buf1s_statd;/* Status array (DMA) */
206 Buf_descr *fu_buf1s_desc; /* Descriptor array (host) */
207 Buf_descr *fu_buf1s_descd;/* Descriptor array (DMA) */
208 Queue_t fu_buf1s_bq; /* Queue of supplied buffers */
209 u_int fu_buf1s_cnt; /* Count of supplied buffers */
210
211 /* Buffer Supply Queue - Strategy 1 Large */
212 H_buf_queue fu_buf1l_q[BUF1_LG_QUELEN]; /* Host queue */
213 H_buf_queue *fu_buf1l_head; /* Queue head */
214 H_buf_queue *fu_buf1l_tail; /* Queue tail */
215 Q_status *fu_buf1l_stat; /* Status array (host) */
216 Q_status *fu_buf1l_statd;/* Status array (DMA) */
217 Buf_descr *fu_buf1l_desc; /* Descriptor array (host) */
218 Buf_descr *fu_buf1l_descd;/* Descriptor array (DMA) */
219 Queue_t fu_buf1l_bq; /* Queue of supplied buffers */
220 u_int fu_buf1l_cnt; /* Count of supplied buffers */
221
222 /* Command Queue */
223 H_cmd_queue fu_cmd_q[CMD_QUELEN]; /* Host queue */
224 H_cmd_queue *fu_cmd_head; /* Queue head */
225 H_cmd_queue *fu_cmd_tail; /* Queue tail */
226 Q_status *fu_cmd_stat; /* Status array (host) */
227 Q_status *fu_cmd_statd; /* Status array (DMA) */
228
229 Fore_stats *fu_stats; /* Device statistics buffer */
230 Fore_stats *fu_statsd; /* Device statistics buffer (DMA) */
231 time_t fu_stats_time; /* Last stats request timestamp */
232 int fu_stats_ret; /* Stats request return code */
233#ifdef FORE_PCI
234 Fore_prom *fu_prom; /* Device PROM buffer */
235 Fore_prom *fu_promd; /* Device PROM buffer (DMA) */
236#endif
7a651277 237 struct callout fu_init_timer;
984263bc
MD
238};
239typedef struct fore_unit Fore_unit;
240
241#define fu_pif fu_cmn.cu_pif
242#define fu_unit fu_cmn.cu_unit
243#define fu_flags fu_cmn.cu_flags
244#define fu_mtu fu_cmn.cu_mtu
245#define fu_open_vcc fu_cmn.cu_open_vcc
246#define fu_vcc fu_cmn.cu_vcc
247#define fu_intrpri fu_cmn.cu_intrpri
248#define fu_savepri fu_cmn.cu_savepri
249#define fu_vcc_pool fu_cmn.cu_vcc_pool
250#define fu_nif_pool fu_cmn.cu_nif_pool
251#define fu_ioctl fu_cmn.cu_ioctl
252#define fu_instvcc fu_cmn.cu_instvcc
253#define fu_openvcc fu_cmn.cu_openvcc
254#define fu_closevcc fu_cmn.cu_closevcc
255#define fu_output fu_cmn.cu_output
256#define fu_config fu_cmn.cu_config
257
258/*
259 * Device flags (in addition to CUF_* flags)
260 */
261#define FUF_STATCMD 0x80 /* Statistics request in progress */
262
263
264/*
265 * Macros to access CP memory
266 */
267#define CP_READ(x) ntohl((u_long)(x))
268#define CP_WRITE(x) htonl((u_long)(x))
269
270#endif /* _FORE_VAR_H */