Add __DragonFly__
[dragonfly.git] / sys / dev / atm / en / midwayreg.h
CommitLineData
984263bc 1/* $NetBSD: midwayreg.h,v 1.6 1997/03/20 21:34:47 chuck Exp $ */
8021d602 2/* $DragonFly: src/sys/dev/atm/en/midwayreg.h,v 1.2 2004/02/13 19:06:15 joerg Exp $ */
984263bc
MD
3
4/*
5 * m i d w a y r e g . h
6 *
7 * this file contains the description of the ENI ATM midway chip
8 * data structures. see midway.c for more details.
9 *
10 */
11
8021d602 12#if defined(__DragonFly__) || defined(sparc) || defined(__FreeBSD__)
984263bc
MD
13/* XXX: gross. netbsd/sparc doesn't have machine/bus.h yet. */
14typedef void * bus_space_tag_t;
15typedef u_int32_t pci_chipset_tag_t;
16typedef caddr_t bus_space_handle_t;
17typedef u_int32_t bus_size_t;
18typedef caddr_t bus_addr_t;
19
20#define bus_space_read_4(t, h, o) ((void) t, \
21 (*(volatile u_int32_t *)((h) + (o))))
22#define bus_space_write_4(t, h, o, v) \
23 ((void) t, ((void)(*(volatile u_int32_t *)((h) + (o)) = (v))))
24
25#if defined(sparc)
26#define vtophys(x) ((u_int32_t)(x)) /* sun4c dvma */
27#endif
28
29#endif
30
31
32#define MID_SZTOB(X) ((X) * 256 * 4) /* size to bytes */
33#define MID_BTOSZ(X) ((X) / 256 / 4) /* bytes to "size" */
34
35#define MID_N_VC 1024 /* # of VCs we can use */
36#define MID_NTX_CH 8 /* 8 transmit channels (shared) */
37#define MID_ATMDATASZ 48 /* need data in 48 byte blocks */
38
39/*
40 * card data structures, top down
41 *
42 * in order to have a portable driver, the netbsd guys will not let us
43 * use structs. we have a bus_space_handle_t which is the en_base address.
44 * everything else is an offset from that base. all card data must be
45 * accessed with bus_space_read_4()/bus_space_write_4():
46 *
47 * rv = bus_space_read_4(sc->en_memt, sc->en_base, BYTE_OFFSET);
48 * bus_space_write_4(sc->en_memt, sc->en_base, BYTE_OFFSET, VALUE);
49 *
50 * en_card: the whole card (prom + phy + midway + obmem)
51 * obmem contains: vci tab + dma queues (rx & tx) + service list + bufs
52 */
53
54/* byte offsets from en_base of various items */
55#define MID_PHYOFF 0x030000 /* PHY offset */
56#define MID_MIDOFF 0x040000 /* midway regs offset */
57#define MID_RAMOFF 0x200000 /* RAM offset */
58#define MID_DRQOFF 0x204000 /* DRQ offset */
59#define MID_DRQEND MID_DTQOFF /* DRQ end */
60#define MID_DTQOFF 0x205000 /* DTQ offset */
61#define MID_DTQEND MID_SLOFF /* DTQ end */
62#define MID_SLOFF 0x206000 /* service list */
63#define MID_SLEND MID_BUFOFF /* service list end */
64#define MID_BUFOFF 0x207000 /* buffer area */
65#define MID_PROBEOFF 0x21fffc /* start probe here */
66#define MID_PROBSIZE 0x020000 /* 128 KB */
67#define MID_MAXOFF 0x3ffffc /* max offset */
68
69/*
70 * prom & phy: not defined here
71 */
72#define MID_ADPMACOFF 0xffc0 /* mac address offset (adaptec only) */
73
74/*
75 * midway regs (byte offsets from en_base)
76 */
77
78#define MID_RESID 0x40000 /* write=reset reg, read=ID reg */
79
80#define MID_VER(X) (((X) & 0xf0000000) >> 28) /* midway version # */
81#define MID_MID(X) (((X) & 0x700) >> 8) /* motherboard ID */
82#define MID_IS_SABRE(X) ((X) & 0x80) /* sabre controller? */
83#define MID_IS_SUNI(X) ((X) & 0x40) /* SUNI? vs utopia */
84#define MID_IS_UPIPE(X) ((X) & 0x20) /* utopia pipeline? */
85#define MID_DID(X) ((X) & 0x1f) /* daughterboard ID */
86
87#define MID_INTACK 0x40004 /* interrupt ACK */
88#define MID_INTSTAT 0x40008 /* interrupt status */
89#define MID_INTENA 0x4000c /* interrupt enable */
90
91#define MID_TXCHAN(N) (1 << ((N) + 9)) /* ack/status/enable xmit channel bit*/
92#define MID_INT_TX 0x1fe00 /* mask for any xmit interrupt */
93#define MID_INT_DMA_OVR 0x00100 /* DMA overflow interrupt */
94#define MID_INT_IDENT 0x00080 /* ident match error interrupt */
95#define MID_INT_LERR 0x00040 /* LERR interrupt (sbus?) */
96#define MID_INT_DMA_ERR 0x00020 /* DMA error interrupt */
97#define MID_INT_DMA_RX 0x00010 /* DMA recv interrupt */
98#define MID_INT_DMA_TX 0x00008 /* DMA xmit interrupt */
99#define MID_INT_SERVICE 0x00004 /* service list interrupt */
100#define MID_INT_SUNI 0x00002 /* SUNI interrupt */
101#define MID_INT_STATS 0x00001 /* stats overflow interrupt */
102
103#define MID_INT_ANY 0x1ffff /* any interrupt? */
104
105#define MID_INTBITS "\20\21T7\20T6\17T5\16T4\15T3\14T2\13T1\12T0\11DMAOVR\10ID\7LERR\6DMAERR\5RXDMA\4TXDMA\3SERV\2SUNI\1STAT"
106
107#define MID_MAST_CSR 0x40010 /* master CSR */
108
109#define MID_IPL(X) (((X) & 0x1c0) >> 6) /* IPL */
110#define MID_SETIPL(I) ((I) << 6)
111#define MID_MCSR_TXLOCK 0x20 /* lock on xmit overflow mode */
112/* NOTE: next 5 bits: write 1 means enable, write 0 means no change */
113#define MID_MCSR_ENDMA 0x10 /* DMA enable */
114#define MID_MCSR_ENTX 0x08 /* TX enable */
115#define MID_MCSR_ENRX 0x04 /* RX enable */
116#define MID_MCSR_W1MS 0x02 /* wait 1 msec */
117#define MID_MCSR_W500US 0x01 /* wait 500 usec */
118
119#define MID_MCSRBITS "\20\6LCK\5DMAON\4TXON\3RXON\2W1MS\1W500US"
120
121#define MID_STAT 0x40014 /* stat register, clear on read */
122
123#define MID_VTRASH(X) (((X) >> 16) & 0xffff)
124 /* # cells trashed due to VCI's mode */
125#define MID_OTRASH(X) ((X) & 0xffff) /* # cells trashed due to overflow */
126
127#define MID_SERV_WRITE 0x40018 /* 10 bit service write pointer (r/o) */
128#define MID_DMA_ADDR 0x4001c /* VA of DMA (r/o) */
129
130 /* DMA queue pointers (bits 0 to 8) */
131#define MID_DMA_WRRX 0x40020 /* write ptr. for DMA recv queue */
132 /* (for adaptor -> host xfers) */
133#define MID_DMA_RDRX 0x40024 /* read ptr for DMA recv queue (r/o) */
134 /* (i.e. current adaptor->host xfer) */
135#define MID_DMA_WRTX 0x40028 /* write ptr for DMA xmit queue */
136 /* (for host -> adaptor xfers) */
137#define MID_DMA_RDTX 0x4002c /* read ptr for DMA xmit queue (r/o) */
138 /* (i.e. current host->adaptor xfer) */
139
140 /* xmit channel regs (1 per channel, MID_NTX_CH max channels) */
141
142#define MIDX_PLACE(N) (0x40040+((N)*0x10)) /* xmit place */
143
144#define MIDX_MKPLACE(SZ,LOC) ( ((SZ) << 11) | (LOC) )
145#define MIDX_LOC(X) ((X) & 0x7ff) /* location in obmem */
146#define MIDX_SZ(X) ((X) >> 11) /* (size of block / 256) in int32_t's*/
147#define MIDX_BASE(X) \
148 (((MIDX_LOC(X) << MIDV_LOCTOPSHFT) * sizeof(u_int32_t)) + MID_RAMOFF)
149
150 /* the following two regs are word offsets in the block */
151#define MIDX_READPTR(N) (0x40044+((N)*0x10)) /* xmit read pointer (r/o) */
152#define MIDX_DESCSTART(N) (0x40048+((N)*0x10)) /* seg currently in DMA (r/o) */
153
154
155/*
156 * obmem items
157 */
158
159/*
160 * vci table in obmem (offset from MID_VCTOFF)
161 */
162
163#define MID_VC(N) (MID_RAMOFF+((N)*0x10))
164
165#define MIDV_TRASH 0x00000000 /* ignore VC */
166#define MIDV_AAL5 0x80000000 /* do AAL5 on it */
167#define MIDV_NOAAL 0x40000000 /* do per-cell stuff on it */
168#define MIDV_MASK 0xc0000000 /* mode mask */
169#define MIDV_SETMODE(VC,M) (((VC) & ~(MIDV_MASK)) | (M)) /* new mode */
170#define MIDV_PTI 0x20000000 /* save PTI cells? */
171#define MIDV_LOCTOPSHFT 8 /* shift to get top 11 bits of 19 */
172#define MIDV_LOCSHIFT 18
173#define MIDV_LOCMASK 0x7ff
174#define MIDV_LOC(X) (((X) >> MIDV_LOCSHIFT) & MIDV_LOCMASK)
175 /* 11 most sig bits of addr */
176#define MIDV_SZSHIFT 15
177#define MIDV_SZ(X) (((X) >> MIDV_SZSHIFT) & 7)
178 /* size encoded the usual way */
179#define MIDV_INSERVICE 0x1 /* in service list */
180
181#define MID_DST_RP(N) (MID_VC(N)|0x4)
182
183#define MIDV_DSTART_SHIFT 16 /* shift */
184#define MIDV_DSTART(X) (((X) >> MIDV_DSTART_SHIFT) & 0x7fff)
185#define MIDV_READP_MASK 0x7fff /* valid bits, (shift = 0) */
186
187#define MID_WP_ST_CNT(N) (MID_VC(N)|0x8) /* write pointer/state/count */
188
189#define MIDV_WRITEP_MASK 0x7fff0000 /* mask for write ptr. */
190#define MIDV_WRITEP_SHIFT 16
191#define MIDV_ST_IDLE 0x0000
192#define MIDV_ST_TRASH 0xc000
193#define MIDV_ST_REASS 0x4000
194#define MIDV_CCOUNT 0x7ff /* cell count */
195
196#define MID_CRC(N) (MID_VC(N)|0xc) /* CRC */
197
198/*
199 * dma recv q.
200 */
201
202#define MID_DMA_END (1 << 5) /* for both tx and rx */
203#define MID_DMA_CNT(X) (((X) >> 16) & 0xffff)
204#define MID_DMA_TXCHAN(X) (((X) >> 6) & 0x7)
205#define MID_DMA_RXVCI(X) (((X) >> 6) & 0x3ff)
206#define MID_DMA_TYPE(X) ((X) & 0xf)
207
208#define MID_DRQ_N 512 /* # of descriptors */
209#define MID_DRQ_A2REG(N) (((N) - MID_DRQOFF) >> 3)
210 /* convert byte offset to reg value */
211#define MID_DRQ_REG2A(N) (((N) << 3) + MID_DRQOFF) /* and back */
212
213/* note: format of word 1 of RXQ is different beween ENI and ADP cards */
214#define MID_MK_RXQ_ENI(CNT,VC,END,TYPE) \
215 ( ((CNT) << 16)|((VC) << 6)|(END)|(TYPE) )
216
217#define MID_MK_RXQ_ADP(CNT,VC,END,JK) \
218 ( ((CNT) << 12)|((VC) << 2)|((END) >> 4)|(((JK) != 0) ? 1 : 0))
219/*
220 * dma xmit q.
221 */
222
223#define MID_DTQ_N 512 /* # of descriptors */
224#define MID_DTQ_A2REG(N) (((N) - MID_DTQOFF) >> 3)
225 /* convert byte offset to reg value */
226#define MID_DTQ_REG2A(N) (((N) << 3) + MID_DTQOFF) /* and back */
227
228
229/* note: format of word 1 of TXQ is different beween ENI and ADP cards */
230#define MID_MK_TXQ_ENI(CNT,CHN,END,TYPE) \
231 ( ((CNT) << 16)|((CHN) << 6)|(END)|(TYPE) )
232
233#define MID_MK_TXQ_ADP(CNT,CHN,END,JK) \
234 ( ((CNT) << 12)|((CHN) << 2)|((END) >> 4)|(((JK) != 0) ? 1 : 0) )
235
236/*
237 * dma types
238 */
239
240#define MIDDMA_JK 0x3 /* just kidding */
241#define MIDDMA_BYTE 0x1 /* byte */
242#define MIDDMA_2BYTE 0x2 /* 2 bytes */
243#define MIDDMA_WORD 0x0 /* word */
244#define MIDDMA_2WORD 0x7 /* 2 words */
245#define MIDDMA_4WORD 0x4 /* 4 words */
246#define MIDDMA_8WORD 0x5 /* 8 words */
247#define MIDDMA_16WORD 0x6 /* 16 words!!! */
248#define MIDDMA_2WMAYBE 0xf /* 2 words, maybe */
249#define MIDDMA_4WMAYBE 0xc /* 4 words, maybe */
250#define MIDDMA_8WMAYBE 0xd /* 8 words, maybe */
251#define MIDDMA_16WMAYBE 0xe /* 16 words, maybe */
252
253#define MIDDMA_MAYBE 0xc /* mask to detect WMAYBE dma code */
254#define MIDDMA_MAXBURST (16 * sizeof(u_int32_t)) /* largest burst */
255
256/*
257 * service list
258 */
259
260#define MID_SL_N 1024 /* max # entries on slist */
261#define MID_SL_A2REG(N) (((N) - MID_SLOFF) >> 2)
262 /* convert byte offset to reg value */
263#define MID_SL_REG2A(N) (((N) << 2) + MID_SLOFF) /* and back */
264
265/*
266 * data in the buffer area of obmem
267 */
268
269/*
270 * recv buffer desc. (1 u_int32_t at start of buffer)
271 */
272
273#define MID_RBD_SIZE 4 /* RBD size */
274#define MID_CHDR_SIZE 4 /* on aal0, cell header size */
275#define MID_RBD_ID(X) ((X) & 0xfe000000) /* get ID */
276#define MID_RBD_STDID 0x36000000 /* standard ID */
277#define MID_RBD_CLP 0x01000000 /* CLP: cell loss priority */
278#define MID_RBD_CE 0x00010000 /* CE: congestion experienced */
279#define MID_RBD_T 0x00001000 /* T: trashed due to overflow */
280#define MID_RBD_CRCERR 0x00000800 /* CRC error */
281#define MID_RBD_CNT(X) ((X) & 0x7ff) /* cell count */
282
283/*
284 * xmit buffer desc. (2 u_int32_t's at start of buffer)
285 * (note we treat the PR & RATE as a single u_int8_t)
286 */
287
288#define MID_TBD_SIZE 8
289#define MID_TBD_MK1(AAL,PR_RATE,CNT) \
290 (MID_TBD_STDID|(AAL)|((PR_RATE) << 19)|(CNT))
291#define MID_TBD_STDID 0xb0000000 /* standard ID */
292#define MID_TBD_AAL5 0x08000000 /* AAL 5 */
293#define MID_TBD_NOAAL5 0x00000000 /* not AAL 5 */
294
295#define MID_TBD_MK2(VCI,PTI,CLP) \
296 (((VCI) << 4)|((PTI) << 1)|(CLP))
297
298/*
299 * aal5 pdu tail, last 2 words of last cell of AAL5 frame
300 * (word 2 is CRC .. handled by hw)
301 */
302
303#define MID_PDU_SIZE 8
304#define MID_PDU_MK1(UU,CPI,LEN) \
305 (((UU) << 24)|((CPI) << 16)|(LEN))
306#define MID_PDU_LEN(X) ((X) & 0xffff)