Add __DragonFly__
[dragonfly.git] / sys / dev / atm / en / midwayvar.h
CommitLineData
984263bc 1/* $NetBSD: midwayvar.h,v 1.10 1997/03/20 21:34:46 chuck Exp $ */
8021d602 2/* $DragonFly: src/sys/dev/atm/en/midwayvar.h,v 1.4 2004/02/13 19:06:15 joerg Exp $*/
984263bc
MD
3
4/*
5 *
6 * Copyright (c) 1996 Charles D. Cranor and Washington University.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Charles D. Cranor and
20 * Washington University.
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36/*
37 * m i d w a y v a r . h
38 *
39 * we define the en_softc here so that bus specific modules can allocate
40 * it as the first item in their softc. note that BSD-required
41 * "struct device" is in the mid_softc!
42 *
43 * author: Chuck Cranor <chuck@ccrc.wustl.edu>
44 */
45
46/*
47 * params needed to determine softc size
48 */
49
50#ifndef EN_NTX
51#define EN_NTX 8 /* number of tx bufs to use */
52#endif
53#ifndef EN_TXSZ
54#define EN_TXSZ 32 /* trasmit buf size in KB */
55#endif
56#ifndef EN_RXSZ
57#define EN_RXSZ 32 /* recv buf size in KB */
58#endif
59#define EN_MAXNRX ((2048-(EN_NTX*EN_TXSZ))/EN_RXSZ)
60 /* largest possible NRX (depends on RAM size) */
61
62
63#if defined(__NetBSD__) || defined(__OpenBSD__) || defined(__bsdi__)
64#define EN_INTR_TYPE int
65#define EN_INTR_RET(X) return(X)
66#if defined(__NetBSD__) || defined(__OpenBSD__)
67#define EN_IOCTL_CMDT u_long
68#elif defined(__bsdi__)
69#define EN_IOCTL_CMDT int
70#endif
71
8021d602 72#elif defined(__DragonFly__) || defined(__FreeBSD__)
984263bc
MD
73
74#define EN_INTR_TYPE void
75#define EN_INTR_RET(X) return
76#define EN_IOCTL_CMDT u_long
77
78struct device {
79 char dv_xname[IFNAMSIZ];
80};
81
82#define DV_IFNET 1
83
84struct cfdriver {
85 int zero;
86 char *name;
87 int one;
88 int cd_ndevs;
89 void *cd_devs[NEN];
90};
91
92#endif
93
94/*
95 * softc
96 */
97
98struct en_softc {
99 /* bsd glue */
100 struct device sc_dev; /* system device */
101 struct ifnet enif; /* network ifnet handle */
102
103 /* bus glue */
104 bus_space_tag_t en_memt; /* for EN_READ/EN_WRITE */
105 bus_space_handle_t en_base; /* base of en card */
106 bus_size_t en_obmemsz; /* size of en card (bytes) */
38e94a25 107 void (*en_busreset) (void *);
984263bc
MD
108 /* bus specific reset function */
109
110 /* serv list */
111 u_int32_t hwslistp; /* hw pointer to service list (byte offset) */
112 u_int16_t swslist[MID_SL_N]; /* software service list (see en_service()) */
113 u_int16_t swsl_head, /* ends of swslist (index into swslist) */
114 swsl_tail;
115 u_int32_t swsl_size; /* # of items in swsl */
116
117
118 /* xmit dma */
119 u_int32_t dtq[MID_DTQ_N]; /* sw copy of dma q (see ENIDQ macros) */
120 u_int32_t dtq_free; /* # of dtq's free */
121 u_int32_t dtq_us; /* software copy of our pointer (byte offset) */
122 u_int32_t dtq_chip; /* chip's pointer (byte offset) */
123 u_int32_t need_dtqs; /* true if we ran out of DTQs */
124
125 /* recv dma */
126 u_int32_t drq[MID_DRQ_N]; /* sw copy of dma q (see ENIDQ macros) */
127 u_int32_t drq_free; /* # of drq's free */
128 u_int32_t drq_us; /* software copy of our pointer (byte offset) */
129 u_int32_t drq_chip; /* chip's pointer (byte offset) */
130 u_int32_t need_drqs; /* true if we ran out of DRQs */
131
132 /* xmit buf ctrl. (per channel) */
133 struct {
134 u_int32_t mbsize; /* # mbuf bytes we are using (max=TXHIWAT) */
135 u_int32_t bfree; /* # free bytes in buffer (not dma or xmit) */
136 u_int32_t start, stop; /* ends of buffer area (byte offset) */
137 u_int32_t cur; /* next free area (byte offset) */
138 u_int32_t nref; /* # of VCs using this channel */
139 struct ifqueue indma; /* mbufs being dma'd now */
140 struct ifqueue q; /* mbufs waiting for dma now */
141 } txslot[MID_NTX_CH];
142
143 /* xmit vc ctrl. (per vc) */
144 u_int8_t txspeed[MID_N_VC]; /* speed of tx on a VC */
145 u_int8_t txvc2slot[MID_N_VC]; /* map VC to slot */
146
147 /* recv vc ctrl. (per vc). maps VC number to recv slot */
148 u_int16_t rxvc2slot[MID_N_VC];
149 int en_nrx; /* # of active rx slots */
150
151 /* recv buf ctrl. (per recv slot) */
152 struct {
153 void *rxhand; /* recv. handle if doing direct delivery */
154 u_int32_t mode; /* saved copy of mode info */
155 u_int32_t start, stop; /* ends of my buffer area */
156 u_int32_t cur; /* where I am at */
157 u_int16_t atm_vci; /* backpointer to VCI */
158 u_int8_t atm_flags; /* copy of atm_flags from atm_ph */
159 u_int8_t oth_flags; /* other flags */
160 u_int32_t raw_threshold; /* for raw mode */
161 struct ifqueue indma; /* mbufs being dma'd now */
162 struct ifqueue q; /* mbufs waiting for dma now */
163 } rxslot[EN_MAXNRX]; /* recv info */
164
165 u_int8_t macaddr[6]; /* card unique mac address */
166
167 /* stats */
168 u_int32_t vtrash; /* sw copy of counter */
169 u_int32_t otrash; /* sw copy of counter */
170 u_int32_t ttrash; /* # of RBD's with T bit set */
171 u_int32_t mfix; /* # of times we had to call mfix */
172 u_int32_t mfixfail; /* # of times mfix failed */
173 u_int32_t headbyte; /* # of times we used BYTE DMA at front */
174 u_int32_t tailbyte; /* # of times we used BYTE DMA at end */
175 u_int32_t tailflush; /* # of times we had to FLUSH out DMA bytes */
176 u_int32_t txmbovr; /* # of times we dropped due to mbsize */
177 u_int32_t dmaovr; /* tx dma overflow count */
178 u_int32_t txoutspace; /* out of space in xmit buffer */
179 u_int32_t txdtqout; /* out of DTQs */
180 u_int32_t launch; /* total # of launches */
181 u_int32_t lheader; /* # of launches without OB header */
182 u_int32_t ltail; /* # of launches without OB tail */
183 u_int32_t hwpull; /* # of pulls off hardware service list */
184 u_int32_t swadd; /* # of pushes on sw service list */
185 u_int32_t rxqnotus; /* # of times we pull from rx q, but fail */
186 u_int32_t rxqus; /* # of good pulls from rx q */
187 u_int32_t rxoutboth; /* # of times out of mbufs and DRQs */
188 u_int32_t rxdrqout; /* # of times out of DRQs */
189 u_int32_t rxmbufout; /* # of time out of mbufs */
190
191 /* random stuff */
192 u_int32_t ipl; /* sbus interrupt lvl (1 on pci?) */
193 u_int8_t bestburstcode; /* code of best burst we can use */
194 u_int8_t bestburstlen; /* length of best burst (bytes) */
195 u_int8_t bestburstshift; /* (x >> shift) == (x / bestburstlen) */
196 u_int8_t bestburstmask; /* bits to check if not multiple of burst */
197 u_int8_t alburst; /* align dma bursts? */
198 u_int8_t is_adaptec; /* adaptec version of midway? */
199};
200
201/*
202 * exported functions
203 */
204
38e94a25
RG
205void en_attach (struct en_softc *);
206EN_INTR_TYPE en_intr (void *);
207void en_reset (struct en_softc *);