Remove duplicate FreeBSD tag.
[dragonfly.git] / sys / dev / netif / lge / if_lge.c
CommitLineData
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1/*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <william.paul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $
81b9b122 34 * $DragonFly: src/sys/dev/netif/lge/if_lge.c,v 1.19 2005/02/19 15:16:39 swildner Exp $
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35 */
36
37/*
38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
39 * documentation not available, but ask me nicely.
40 *
41 * Written by Bill Paul <william.paul@windriver.com>
42 * Wind River Systems
43 */
44
45/*
46 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
47 * It's a 64-bit PCI part that supports TCP/IP checksum offload,
48 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
49 * are three supported methods for data transfer between host and
50 * NIC: programmed I/O, traditional scatter/gather DMA and Packet
51 * Propulsion Technology (tm) DMA. The latter mechanism is a form
52 * of double buffer DMA where the packet data is copied to a
53 * pre-allocated DMA buffer who's physical address has been loaded
54 * into a table at device initialization time. The rationale is that
55 * the virtual to physical address translation needed for normal
56 * scatter/gather DMA is more expensive than the data copy needed
57 * for double buffering. This may be true in Windows NT and the like,
58 * but it isn't true for us, at least on the x86 arch. This driver
59 * uses the scatter/gather I/O method for both TX and RX.
60 *
61 * The LXT1001 only supports TCP/IP checksum offload on receive.
62 * Also, the VLAN tagging is done using a 16-entry table which allows
63 * the chip to perform hardware filtering based on VLAN tags. Sadly,
64 * our vlan support doesn't currently play well with this kind of
65 * hardware support.
66 *
67 * Special thanks to:
68 * - Jeff James at Intel, for arranging to have the LXT1001 manual
69 * released (at long last)
70 * - Beny Chen at D-Link, for actually sending it to me
71 * - Brad Short and Keith Alexis at SMC, for sending me sample
72 * SMC9462SX and SMC9462TX adapters for testing
73 * - Paul Saab at Y!, for not killing me (though it remains to be seen
74 * if in fact he did me much of a favor)
75 */
76
77#include <sys/param.h>
78#include <sys/systm.h>
79#include <sys/sockio.h>
80#include <sys/mbuf.h>
81#include <sys/malloc.h>
82#include <sys/kernel.h>
83#include <sys/socket.h>
84
85#include <net/if.h>
d1f483a6 86#include <net/ifq_var.h>
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87#include <net/if_arp.h>
88#include <net/ethernet.h>
89#include <net/if_dl.h>
90#include <net/if_media.h>
91
92#include <net/bpf.h>
93
94#include <vm/vm.h> /* for vtophys */
95#include <vm/pmap.h> /* for vtophys */
96#include <machine/clock.h> /* for DELAY */
97#include <machine/bus_pio.h>
98#include <machine/bus_memio.h>
99#include <machine/bus.h>
100#include <machine/resource.h>
101#include <sys/bus.h>
102#include <sys/rman.h>
103
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104#include "../mii_layer/mii.h"
105#include "../mii_layer/miivar.h"
984263bc 106
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107#include <bus/pci/pcireg.h>
108#include <bus/pci/pcivar.h>
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109
110#define LGE_USEIOSPACE
111
1f2de5d4 112#include "if_lgereg.h"
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113
114/* "controller miibus0" required. See GENERIC if you get errors here. */
115#include "miibus_if.h"
116
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117/*
118 * Various supported device vendors/types and their names.
119 */
120static struct lge_type lge_devs[] = {
121 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" },
122 { 0, 0, NULL }
123};
124
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125static int lge_probe (device_t);
126static int lge_attach (device_t);
127static int lge_detach (device_t);
984263bc 128
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129static int lge_alloc_jumbo_mem (struct lge_softc *);
130static void lge_free_jumbo_mem (struct lge_softc *);
131static void *lge_jalloc (struct lge_softc *);
132static void lge_jfree (caddr_t, u_int);
133static void lge_jref (caddr_t, u_int);
984263bc 134
b5101a88 135static int lge_newbuf (struct lge_softc *,
984263bc 136 struct lge_rx_desc *,
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137 struct mbuf *);
138static int lge_encap (struct lge_softc *,
139 struct mbuf *, u_int32_t *);
140static void lge_rxeof (struct lge_softc *, int);
141static void lge_rxeoc (struct lge_softc *);
142static void lge_txeof (struct lge_softc *);
143static void lge_intr (void *);
144static void lge_tick (void *);
145static void lge_start (struct ifnet *);
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146static int lge_ioctl (struct ifnet *, u_long, caddr_t,
147 struct ucred *);
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148static void lge_init (void *);
149static void lge_stop (struct lge_softc *);
150static void lge_watchdog (struct ifnet *);
151static void lge_shutdown (device_t);
152static int lge_ifmedia_upd (struct ifnet *);
153static void lge_ifmedia_sts (struct ifnet *, struct ifmediareq *);
154
155static void lge_eeprom_getword (struct lge_softc *, int, u_int16_t *);
156static void lge_read_eeprom (struct lge_softc *, caddr_t, int,
157 int, int);
158
159static int lge_miibus_readreg (device_t, int, int);
160static int lge_miibus_writereg (device_t, int, int, int);
161static void lge_miibus_statchg (device_t);
162
163static void lge_setmulti (struct lge_softc *);
164static u_int32_t lge_crc (struct lge_softc *, caddr_t);
165static void lge_reset (struct lge_softc *);
166static int lge_list_rx_init (struct lge_softc *);
167static int lge_list_tx_init (struct lge_softc *);
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168
169#ifdef LGE_USEIOSPACE
170#define LGE_RES SYS_RES_IOPORT
171#define LGE_RID LGE_PCI_LOIO
172#else
173#define LGE_RES SYS_RES_MEMORY
174#define LGE_RID LGE_PCI_LOMEM
175#endif
176
177static device_method_t lge_methods[] = {
178 /* Device interface */
179 DEVMETHOD(device_probe, lge_probe),
180 DEVMETHOD(device_attach, lge_attach),
181 DEVMETHOD(device_detach, lge_detach),
182 DEVMETHOD(device_shutdown, lge_shutdown),
183
184 /* bus interface */
185 DEVMETHOD(bus_print_child, bus_generic_print_child),
186 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
187
188 /* MII interface */
189 DEVMETHOD(miibus_readreg, lge_miibus_readreg),
190 DEVMETHOD(miibus_writereg, lge_miibus_writereg),
191 DEVMETHOD(miibus_statchg, lge_miibus_statchg),
192
193 { 0, 0 }
194};
195
196static driver_t lge_driver = {
197 "lge",
198 lge_methods,
199 sizeof(struct lge_softc)
200};
201
202static devclass_t lge_devclass;
203
32832096 204DECLARE_DUMMY_MODULE(if_lge);
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205DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, 0, 0);
206DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0);
207
208#define LGE_SETBIT(sc, reg, x) \
209 CSR_WRITE_4(sc, reg, \
210 CSR_READ_4(sc, reg) | (x))
211
212#define LGE_CLRBIT(sc, reg, x) \
213 CSR_WRITE_4(sc, reg, \
214 CSR_READ_4(sc, reg) & ~(x))
215
216#define SIO_SET(x) \
217 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
218
219#define SIO_CLR(x) \
220 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
221
222/*
223 * Read a word of data stored in the EEPROM at address 'addr.'
224 */
225static void lge_eeprom_getword(sc, addr, dest)
226 struct lge_softc *sc;
227 int addr;
228 u_int16_t *dest;
229{
f96d6c88 230 int i;
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231 u_int32_t val;
232
233 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
234 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8));
235
236 for (i = 0; i < LGE_TIMEOUT; i++)
237 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))
238 break;
239
240 if (i == LGE_TIMEOUT) {
241 printf("lge%d: EEPROM read timed out\n", sc->lge_unit);
242 return;
243 }
244
245 val = CSR_READ_4(sc, LGE_EEDATA);
246
247 if (addr & 1)
248 *dest = (val >> 16) & 0xFFFF;
249 else
250 *dest = val & 0xFFFF;
251
252 return;
253}
254
255/*
256 * Read a sequence of words from the EEPROM.
257 */
258static void lge_read_eeprom(sc, dest, off, cnt, swap)
259 struct lge_softc *sc;
260 caddr_t dest;
261 int off;
262 int cnt;
263 int swap;
264{
265 int i;
266 u_int16_t word = 0, *ptr;
267
268 for (i = 0; i < cnt; i++) {
269 lge_eeprom_getword(sc, off + i, &word);
270 ptr = (u_int16_t *)(dest + (i * 2));
271 if (swap)
272 *ptr = ntohs(word);
273 else
274 *ptr = word;
275 }
276
277 return;
278}
279
280static int lge_miibus_readreg(dev, phy, reg)
281 device_t dev;
282 int phy, reg;
283{
284 struct lge_softc *sc;
285 int i;
286
287 sc = device_get_softc(dev);
288
289 /*
290 * If we have a non-PCS PHY, pretend that the internal
291 * autoneg stuff at PHY address 0 isn't there so that
292 * the miibus code will find only the GMII PHY.
293 */
294 if (sc->lge_pcs == 0 && phy == 0)
295 return(0);
296
297 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
298
299 for (i = 0; i < LGE_TIMEOUT; i++)
300 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
301 break;
302
303 if (i == LGE_TIMEOUT) {
304 printf("lge%d: PHY read timed out\n", sc->lge_unit);
305 return(0);
306 }
307
308 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
309}
310
311static int lge_miibus_writereg(dev, phy, reg, data)
312 device_t dev;
313 int phy, reg, data;
314{
315 struct lge_softc *sc;
316 int i;
317
318 sc = device_get_softc(dev);
319
320 CSR_WRITE_4(sc, LGE_GMIICTL,
321 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
322
323 for (i = 0; i < LGE_TIMEOUT; i++)
324 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
325 break;
326
327 if (i == LGE_TIMEOUT) {
328 printf("lge%d: PHY write timed out\n", sc->lge_unit);
329 return(0);
330 }
331
332 return(0);
333}
334
335static void lge_miibus_statchg(dev)
336 device_t dev;
337{
338 struct lge_softc *sc;
339 struct mii_data *mii;
340
341 sc = device_get_softc(dev);
342 mii = device_get_softc(sc->lge_miibus);
343
344 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
345 switch (IFM_SUBTYPE(mii->mii_media_active)) {
7f259627 346 case IFM_1000_T:
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347 case IFM_1000_SX:
348 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
349 break;
350 case IFM_100_TX:
351 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
352 break;
353 case IFM_10_T:
354 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
355 break;
356 default:
357 /*
358 * Choose something, even if it's wrong. Clearing
359 * all the bits will hose autoneg on the internal
360 * PHY.
361 */
362 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
363 break;
364 }
365
366 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
367 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
368 } else {
369 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
370 }
371
372 return;
373}
374
375static u_int32_t lge_crc(sc, addr)
376 struct lge_softc *sc;
377 caddr_t addr;
378{
379 u_int32_t crc, carry;
380 int i, j;
381 u_int8_t c;
382
383 /* Compute CRC for the address value. */
384 crc = 0xFFFFFFFF; /* initial value */
385
386 for (i = 0; i < 6; i++) {
387 c = *(addr + i);
388 for (j = 0; j < 8; j++) {
389 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
390 crc <<= 1;
391 c >>= 1;
392 if (carry)
393 crc = (crc ^ 0x04c11db6) | carry;
394 }
395 }
396
397 /*
398 * return the filter bit position
399 */
400 return((crc >> 26) & 0x0000003F);
401}
402
403static void lge_setmulti(sc)
404 struct lge_softc *sc;
405{
406 struct ifnet *ifp;
407 struct ifmultiaddr *ifma;
408 u_int32_t h = 0, hashes[2] = { 0, 0 };
409
410 ifp = &sc->arpcom.ac_if;
411
412 /* Make sure multicast hash table is enabled. */
413 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST);
414
415 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
416 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
417 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
418 return;
419 }
420
421 /* first, zot all the existing hash bits */
422 CSR_WRITE_4(sc, LGE_MAR0, 0);
423 CSR_WRITE_4(sc, LGE_MAR1, 0);
424
425 /* now program new ones */
426 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
427 ifma = ifma->ifma_link.le_next) {
428 if (ifma->ifma_addr->sa_family != AF_LINK)
429 continue;
430 h = lge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
431 if (h < 32)
432 hashes[0] |= (1 << h);
433 else
434 hashes[1] |= (1 << (h - 32));
435 }
436
437 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
438 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
439
440 return;
441}
442
443static void lge_reset(sc)
444 struct lge_softc *sc;
445{
f96d6c88 446 int i;
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447
448 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST);
449
450 for (i = 0; i < LGE_TIMEOUT; i++) {
451 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))
452 break;
453 }
454
455 if (i == LGE_TIMEOUT)
456 printf("lge%d: reset never completed\n", sc->lge_unit);
457
458 /* Wait a little while for the chip to get its brains in order. */
459 DELAY(1000);
460
461 return;
462}
463
464/*
465 * Probe for a Level 1 chip. Check the PCI vendor and device
466 * IDs against our list and return a device name if we find a match.
467 */
468static int lge_probe(dev)
469 device_t dev;
470{
471 struct lge_type *t;
472
473 t = lge_devs;
474
475 while(t->lge_name != NULL) {
476 if ((pci_get_vendor(dev) == t->lge_vid) &&
477 (pci_get_device(dev) == t->lge_did)) {
478 device_set_desc(dev, t->lge_name);
479 return(0);
480 }
481 t++;
482 }
483
484 return(ENXIO);
485}
486
487/*
488 * Attach the interface. Allocate softc structures, do ifmedia
489 * setup and ethernet/BPF attach.
490 */
491static int lge_attach(dev)
492 device_t dev;
493{
494 int s;
495 u_char eaddr[ETHER_ADDR_LEN];
496 u_int32_t command;
497 struct lge_softc *sc;
498 struct ifnet *ifp;
499 int unit, error = 0, rid;
500
501 s = splimp();
502
503 sc = device_get_softc(dev);
504 unit = device_get_unit(dev);
505 bzero(sc, sizeof(struct lge_softc));
29744ced 506 callout_init(&sc->lge_stat_timer);
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507
508 /*
509 * Handle power management nonsense.
510 */
511 command = pci_read_config(dev, LGE_PCI_CAPID, 4) & 0x000000FF;
512 if (command == 0x01) {
513
514 command = pci_read_config(dev, LGE_PCI_PWRMGMTCTRL, 4);
515 if (command & LGE_PSTATE_MASK) {
516 u_int32_t iobase, membase, irq;
517
518 /* Save important PCI config data. */
519 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4);
520 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4);
521 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4);
522
523 /* Reset the power state. */
524 printf("lge%d: chip is in D%d power mode "
525 "-- setting to D0\n", unit, command & LGE_PSTATE_MASK);
526 command &= 0xFFFFFFFC;
527 pci_write_config(dev, LGE_PCI_PWRMGMTCTRL, command, 4);
528
529 /* Restore PCI config data. */
530 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4);
531 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4);
532 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4);
533 }
534 }
535
536 /*
537 * Map control/status registers.
538 */
539 command = pci_read_config(dev, PCIR_COMMAND, 4);
540 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
541 pci_write_config(dev, PCIR_COMMAND, command, 4);
542 command = pci_read_config(dev, PCIR_COMMAND, 4);
543
544#ifdef LGE_USEIOSPACE
545 if (!(command & PCIM_CMD_PORTEN)) {
546 printf("lge%d: failed to enable I/O ports!\n", unit);
547 error = ENXIO;;
548 goto fail;
549 }
550#else
551 if (!(command & PCIM_CMD_MEMEN)) {
552 printf("lge%d: failed to enable memory mapping!\n", unit);
553 error = ENXIO;;
554 goto fail;
555 }
556#endif
557
558 rid = LGE_RID;
559 sc->lge_res = bus_alloc_resource(dev, LGE_RES, &rid,
560 0, ~0, 1, RF_ACTIVE);
561
562 if (sc->lge_res == NULL) {
563 printf("lge%d: couldn't map ports/memory\n", unit);
564 error = ENXIO;
565 goto fail;
566 }
567
568 sc->lge_btag = rman_get_bustag(sc->lge_res);
569 sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
570
571 /* Allocate interrupt */
572 rid = 0;
573 sc->lge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
574 RF_SHAREABLE | RF_ACTIVE);
575
576 if (sc->lge_irq == NULL) {
577 printf("lge%d: couldn't map interrupt\n", unit);
578 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
579 error = ENXIO;
580 goto fail;
581 }
582
583 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET,
584 lge_intr, sc, &sc->lge_intrhand);
585
586 if (error) {
587 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
588 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
589 printf("lge%d: couldn't set up irq\n", unit);
590 goto fail;
591 }
592
593 /* Reset the adapter. */
594 lge_reset(sc);
595
596 /*
597 * Get station address from the EEPROM.
598 */
599 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0);
600 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0);
601 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0);
602
984263bc 603 sc->lge_unit = unit;
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604
605 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
606 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
607
608 if (sc->lge_ldata == NULL) {
609 printf("lge%d: no memory for list buffers!\n", unit);
610 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
611 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
612 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
613 error = ENXIO;
614 goto fail;
615 }
616 bzero(sc->lge_ldata, sizeof(struct lge_list_data));
617
618 /* Try to allocate memory for jumbo buffers. */
619 if (lge_alloc_jumbo_mem(sc)) {
620 printf("lge%d: jumbo buffer allocation failed\n",
621 sc->lge_unit);
622 contigfree(sc->lge_ldata,
623 sizeof(struct lge_list_data), M_DEVBUF);
624 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
625 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
626 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
627 error = ENXIO;
628 goto fail;
629 }
630
631 ifp = &sc->arpcom.ac_if;
632 ifp->if_softc = sc;
cdb7d804 633 if_initname(ifp, "lge", unit);
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MD
634 ifp->if_mtu = ETHERMTU;
635 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
636 ifp->if_ioctl = lge_ioctl;
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637 ifp->if_start = lge_start;
638 ifp->if_watchdog = lge_watchdog;
639 ifp->if_init = lge_init;
640 ifp->if_baudrate = 1000000000;
d1f483a6
JS
641 ifq_set_maxlen(&ifp->if_snd, LGE_TX_LIST_CNT - 1);
642 ifq_set_ready(&ifp->if_snd);
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643 ifp->if_capabilities = IFCAP_RXCSUM;
644 ifp->if_capenable = ifp->if_capabilities;
645
646 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
647 sc->lge_pcs = 1;
648 else
649 sc->lge_pcs = 0;
650
651 /*
652 * Do MII setup.
653 */
654 if (mii_phy_probe(dev, &sc->lge_miibus,
655 lge_ifmedia_upd, lge_ifmedia_sts)) {
656 printf("lge%d: MII without any PHY!\n", sc->lge_unit);
657 contigfree(sc->lge_ldata,
658 sizeof(struct lge_list_data), M_DEVBUF);
659 lge_free_jumbo_mem(sc);
660 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
661 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
662 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
663 error = ENXIO;
664 goto fail;
665 }
666
667 /*
668 * Call MI attach routine.
669 */
0a8b5977 670 ether_ifattach(ifp, eaddr);
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671
672fail:
673 splx(s);
674 return(error);
675}
676
677static int lge_detach(dev)
678 device_t dev;
679{
680 struct lge_softc *sc;
681 struct ifnet *ifp;
682 int s;
683
684 s = splimp();
685
686 sc = device_get_softc(dev);
687 ifp = &sc->arpcom.ac_if;
688
689 lge_reset(sc);
690 lge_stop(sc);
0a8b5977 691 ether_ifdetach(ifp);
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692
693 bus_generic_detach(dev);
694 device_delete_child(dev, sc->lge_miibus);
695
696 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
697 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
698 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
699
700 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF);
701 lge_free_jumbo_mem(sc);
702
703 splx(s);
704
705 return(0);
706}
707
708/*
709 * Initialize the transmit descriptors.
710 */
711static int lge_list_tx_init(sc)
712 struct lge_softc *sc;
713{
714 struct lge_list_data *ld;
715 struct lge_ring_data *cd;
716 int i;
717
718 cd = &sc->lge_cdata;
719 ld = sc->lge_ldata;
720 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
721 ld->lge_tx_list[i].lge_mbuf = NULL;
722 ld->lge_tx_list[i].lge_ctl = 0;
723 }
724
725 cd->lge_tx_prod = cd->lge_tx_cons = 0;
726
727 return(0);
728}
729
730
731/*
732 * Initialize the RX descriptors and allocate mbufs for them. Note that
733 * we arralge the descriptors in a closed ring, so that the last descriptor
734 * points back to the first.
735 */
736static int lge_list_rx_init(sc)
737 struct lge_softc *sc;
738{
739 struct lge_list_data *ld;
740 struct lge_ring_data *cd;
741 int i;
742
743 ld = sc->lge_ldata;
744 cd = &sc->lge_cdata;
745
746 cd->lge_rx_prod = cd->lge_rx_cons = 0;
747
748 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
749
750 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
751 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
752 break;
753 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
754 return(ENOBUFS);
755 }
756
757 /* Clear possible 'rx command queue empty' interrupt. */
758 CSR_READ_4(sc, LGE_ISR);
759
760 return(0);
761}
762
763/*
764 * Initialize an RX descriptor and attach an MBUF cluster.
765 */
766static int lge_newbuf(sc, c, m)
767 struct lge_softc *sc;
768 struct lge_rx_desc *c;
769 struct mbuf *m;
770{
771 struct mbuf *m_new = NULL;
772 caddr_t *buf = NULL;
773
774 if (m == NULL) {
74f1caca 775 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
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776 if (m_new == NULL) {
777 printf("lge%d: no memory for rx list "
778 "-- packet dropped!\n", sc->lge_unit);
779 return(ENOBUFS);
780 }
781
782 /* Allocate the jumbo buffer */
783 buf = lge_jalloc(sc);
784 if (buf == NULL) {
785#ifdef LGE_VERBOSE
786 printf("lge%d: jumbo allocation failed "
787 "-- packet dropped!\n", sc->lge_unit);
788#endif
789 m_freem(m_new);
790 return(ENOBUFS);
791 }
792 /* Attach the buffer to the mbuf */
793 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
7eccf245 794 m_new->m_flags |= M_EXT | M_EXT_OLD;
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795 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
796 m_new->m_len = LGE_MCLBYTES;
7eccf245
MD
797 m_new->m_ext.ext_nfree.old = lge_jfree;
798 m_new->m_ext.ext_nref.old = lge_jref;
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799 } else {
800 m_new = m;
801 m_new->m_len = m_new->m_pkthdr.len = LGE_MCLBYTES;
802 m_new->m_data = m_new->m_ext.ext_buf;
803 }
804
805 /*
806 * Adjust alignment so packet payload begins on a
807 * longword boundary. Mandatory for Alpha, useful on
808 * x86 too.
809 */
810 m_adj(m_new, ETHER_ALIGN);
811
812 c->lge_mbuf = m_new;
813 c->lge_fragptr_hi = 0;
814 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
815 c->lge_fraglen = m_new->m_len;
816 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
817 c->lge_sts = 0;
818
819 /*
820 * Put this buffer in the RX command FIFO. To do this,
821 * we just write the physical address of the descriptor
822 * into the RX descriptor address registers. Note that
823 * there are two registers, one high DWORD and one low
824 * DWORD, which lets us specify a 64-bit address if
825 * desired. We only use a 32-bit address for now.
826 * Writing to the low DWORD register is what actually
827 * causes the command to be issued, so we do that
828 * last.
829 */
830 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
831 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
832
833 return(0);
834}
835
836static int lge_alloc_jumbo_mem(sc)
837 struct lge_softc *sc;
838{
839 caddr_t ptr;
f96d6c88 840 int i;
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841 struct lge_jpool_entry *entry;
842
843 /* Grab a big chunk o' storage. */
844 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
845 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
846
847 if (sc->lge_cdata.lge_jumbo_buf == NULL) {
848 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit);
849 return(ENOBUFS);
850 }
851
852 SLIST_INIT(&sc->lge_jfree_listhead);
853 SLIST_INIT(&sc->lge_jinuse_listhead);
854
855 /*
856 * Now divide it up into 9K pieces and save the addresses
857 * in an array.
858 */
859 ptr = sc->lge_cdata.lge_jumbo_buf;
860 for (i = 0; i < LGE_JSLOTS; i++) {
861 u_int64_t **aptr;
862 aptr = (u_int64_t **)ptr;
863 aptr[0] = (u_int64_t *)sc;
864 ptr += sizeof(u_int64_t);
865 sc->lge_cdata.lge_jslots[i].lge_buf = ptr;
866 sc->lge_cdata.lge_jslots[i].lge_inuse = 0;
867 ptr += LGE_MCLBYTES;
868 entry = malloc(sizeof(struct lge_jpool_entry),
c5541aee 869 M_DEVBUF, M_WAITOK);
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870 entry->slot = i;
871 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
872 entry, jpool_entries);
873 }
874
875 return(0);
876}
877
878static void lge_free_jumbo_mem(sc)
879 struct lge_softc *sc;
880{
881 int i;
882 struct lge_jpool_entry *entry;
883
884 for (i = 0; i < LGE_JSLOTS; i++) {
885 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
886 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
887 free(entry, M_DEVBUF);
888 }
889
890 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF);
891
892 return;
893}
894
895/*
896 * Allocate a jumbo buffer.
897 */
898static void *lge_jalloc(sc)
899 struct lge_softc *sc;
900{
901 struct lge_jpool_entry *entry;
902
903 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
904
905 if (entry == NULL) {
906#ifdef LGE_VERBOSE
907 printf("lge%d: no free jumbo buffers\n", sc->lge_unit);
908#endif
909 return(NULL);
910 }
911
912 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
913 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries);
914 sc->lge_cdata.lge_jslots[entry->slot].lge_inuse = 1;
915 return(sc->lge_cdata.lge_jslots[entry->slot].lge_buf);
916}
917
918/*
919 * Adjust usage count on a jumbo buffer. In general this doesn't
920 * get used much because our jumbo buffers don't get passed around
921 * a lot, but it's implemented for correctness.
922 */
923static void lge_jref(buf, size)
924 caddr_t buf;
925 u_int size;
926{
927 struct lge_softc *sc;
928 u_int64_t **aptr;
f96d6c88 929 int i;
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930
931 /* Extract the softc struct pointer. */
932 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
933 sc = (struct lge_softc *)(aptr[0]);
934
935 if (sc == NULL)
936 panic("lge_jref: can't find softc pointer!");
937
938 if (size != LGE_MCLBYTES)
939 panic("lge_jref: adjusting refcount of buf of wrong size!");
940
941 /* calculate the slot this buffer belongs to */
942
943 i = ((vm_offset_t)aptr
944 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
945
946 if ((i < 0) || (i >= LGE_JSLOTS))
947 panic("lge_jref: asked to reference buffer "
948 "that we don't manage!");
949 else if (sc->lge_cdata.lge_jslots[i].lge_inuse == 0)
950 panic("lge_jref: buffer already free!");
951 else
952 sc->lge_cdata.lge_jslots[i].lge_inuse++;
953
954 return;
955}
956
957/*
958 * Release a jumbo buffer.
959 */
960static void lge_jfree(buf, size)
961 caddr_t buf;
962 u_int size;
963{
964 struct lge_softc *sc;
965 u_int64_t **aptr;
966 int i;
967 struct lge_jpool_entry *entry;
968
969 /* Extract the softc struct pointer. */
970 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
971 sc = (struct lge_softc *)(aptr[0]);
972
973 if (sc == NULL)
974 panic("lge_jfree: can't find softc pointer!");
975
976 if (size != LGE_MCLBYTES)
977 panic("lge_jfree: freeing buffer of wrong size!");
978
979 /* calculate the slot this buffer belongs to */
980 i = ((vm_offset_t)aptr
981 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
982
983 if ((i < 0) || (i >= LGE_JSLOTS))
984 panic("lge_jfree: asked to free buffer that we don't manage!");
985 else if (sc->lge_cdata.lge_jslots[i].lge_inuse == 0)
986 panic("lge_jfree: buffer already free!");
987 else {
988 sc->lge_cdata.lge_jslots[i].lge_inuse--;
989 if(sc->lge_cdata.lge_jslots[i].lge_inuse == 0) {
990 entry = SLIST_FIRST(&sc->lge_jinuse_listhead);
991 if (entry == NULL)
992 panic("lge_jfree: buffer not in use!");
993 entry->slot = i;
994 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead,
995 jpool_entries);
996 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
997 entry, jpool_entries);
998 }
999 }
1000
1001 return;
1002}
1003
1004/*
1005 * A frame has been uploaded: pass the resulting mbuf chain up to
1006 * the higher level protocols.
1007 */
1008static void lge_rxeof(sc, cnt)
1009 struct lge_softc *sc;
1010 int cnt;
1011{
984263bc
MD
1012 struct mbuf *m;
1013 struct ifnet *ifp;
1014 struct lge_rx_desc *cur_rx;
1015 int c, i, total_len = 0;
1016 u_int32_t rxsts, rxctl;
1017
1018 ifp = &sc->arpcom.ac_if;
1019
1020 /* Find out how many frames were processed. */
1021 c = cnt;
1022 i = sc->lge_cdata.lge_rx_cons;
1023
1024 /* Suck them in. */
1025 while(c) {
1026 struct mbuf *m0 = NULL;
1027
1028 cur_rx = &sc->lge_ldata->lge_rx_list[i];
1029 rxctl = cur_rx->lge_ctl;
1030 rxsts = cur_rx->lge_sts;
1031 m = cur_rx->lge_mbuf;
1032 cur_rx->lge_mbuf = NULL;
1033 total_len = LGE_RXBYTES(cur_rx);
1034 LGE_INC(i, LGE_RX_LIST_CNT);
1035 c--;
1036
1037 /*
1038 * If an error occurs, update stats, clear the
1039 * status word and leave the mbuf cluster in place:
1040 * it should simply get re-used next time this descriptor
1041 * comes up in the ring.
1042 */
1043 if (rxctl & LGE_RXCTL_ERRMASK) {
1044 ifp->if_ierrors++;
1045 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
1046 continue;
1047 }
1048
1049 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
1050 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1051 total_len + ETHER_ALIGN, 0, ifp, NULL);
1052 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
1053 if (m0 == NULL) {
1054 printf("lge%d: no receive buffers "
1055 "available -- packet dropped!\n",
1056 sc->lge_unit);
1057 ifp->if_ierrors++;
1058 continue;
1059 }
1060 m_adj(m0, ETHER_ALIGN);
1061 m = m0;
1062 } else {
1063 m->m_pkthdr.rcvif = ifp;
1064 m->m_pkthdr.len = m->m_len = total_len;
1065 }
1066
1067 ifp->if_ipackets++;
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1068
1069 /* Do IP checksum checking. */
1070 if (rxsts & LGE_RXSTS_ISIP)
1071 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1072 if (!(rxsts & LGE_RXSTS_IPCSUMERR))
1073 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1074 if ((rxsts & LGE_RXSTS_ISTCP &&
1075 !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
1076 (rxsts & LGE_RXSTS_ISUDP &&
1077 !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
1078 m->m_pkthdr.csum_flags |=
1079 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1080 m->m_pkthdr.csum_data = 0xffff;
1081 }
1082
3013ac0e 1083 (*ifp->if_input)(ifp, m);
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1084 }
1085
1086 sc->lge_cdata.lge_rx_cons = i;
1087
1088 return;
1089}
1090
1091void lge_rxeoc(sc)
1092 struct lge_softc *sc;
1093{
1094 struct ifnet *ifp;
1095
1096 ifp = &sc->arpcom.ac_if;
1097 ifp->if_flags &= ~IFF_RUNNING;
1098 lge_init(sc);
1099 return;
1100}
1101
1102/*
1103 * A frame was downloaded to the chip. It's safe for us to clean up
1104 * the list buffers.
1105 */
1106
1107static void lge_txeof(sc)
1108 struct lge_softc *sc;
1109{
1110 struct lge_tx_desc *cur_tx = NULL;
1111 struct ifnet *ifp;
1112 u_int32_t idx, txdone;
1113
1114 ifp = &sc->arpcom.ac_if;
1115
1116 /* Clear the timeout timer. */
1117 ifp->if_timer = 0;
1118
1119 /*
1120 * Go through our tx list and free mbufs for those
1121 * frames that have been transmitted.
1122 */
1123 idx = sc->lge_cdata.lge_tx_cons;
1124 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
1125
1126 while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
1127 cur_tx = &sc->lge_ldata->lge_tx_list[idx];
1128
1129 ifp->if_opackets++;
1130 if (cur_tx->lge_mbuf != NULL) {
1131 m_freem(cur_tx->lge_mbuf);
1132 cur_tx->lge_mbuf = NULL;
1133 }
1134 cur_tx->lge_ctl = 0;
1135
1136 txdone--;
1137 LGE_INC(idx, LGE_TX_LIST_CNT);
1138 ifp->if_timer = 0;
1139 }
1140
1141 sc->lge_cdata.lge_tx_cons = idx;
1142
1143 if (cur_tx != NULL)
1144 ifp->if_flags &= ~IFF_OACTIVE;
1145
1146 return;
1147}
1148
1149static void lge_tick(xsc)
1150 void *xsc;
1151{
1152 struct lge_softc *sc;
1153 struct mii_data *mii;
1154 struct ifnet *ifp;
1155 int s;
1156
1157 s = splimp();
1158
1159 sc = xsc;
1160 ifp = &sc->arpcom.ac_if;
1161
1162 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
1163 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1164 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1165 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1166
1167 if (!sc->lge_link) {
1168 mii = device_get_softc(sc->lge_miibus);
1169 mii_tick(mii);
1170 mii_pollstat(mii);
1171 if (mii->mii_media_status & IFM_ACTIVE &&
1172 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1173 sc->lge_link++;
1174 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
7f259627 1175 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
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1176 printf("lge%d: gigabit link up\n",
1177 sc->lge_unit);
d1f483a6 1178 if (!ifq_is_empty(&ifp->if_snd))
984263bc
MD
1179 lge_start(ifp);
1180 }
1181 }
1182
29744ced 1183 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc);
984263bc
MD
1184
1185 splx(s);
1186
1187 return;
1188}
1189
1190static void lge_intr(arg)
1191 void *arg;
1192{
1193 struct lge_softc *sc;
1194 struct ifnet *ifp;
1195 u_int32_t status;
1196
1197 sc = arg;
1198 ifp = &sc->arpcom.ac_if;
1199
1200 /* Supress unwanted interrupts */
1201 if (!(ifp->if_flags & IFF_UP)) {
1202 lge_stop(sc);
1203 return;
1204 }
1205
1206 for (;;) {
1207 /*
1208 * Reading the ISR register clears all interrupts, and
1209 * clears the 'interrupts enabled' bit in the IMR
1210 * register.
1211 */
1212 status = CSR_READ_4(sc, LGE_ISR);
1213
1214 if ((status & LGE_INTRS) == 0)
1215 break;
1216
1217 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1218 lge_txeof(sc);
1219
1220 if (status & LGE_ISR_RXDMA_DONE)
1221 lge_rxeof(sc, LGE_RX_DMACNT(status));
1222
1223 if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1224 lge_rxeoc(sc);
1225
1226 if (status & LGE_ISR_PHY_INTR) {
1227 sc->lge_link = 0;
29744ced 1228 callout_stop(&sc->lge_stat_timer);
984263bc
MD
1229 lge_tick(sc);
1230 }
1231 }
1232
1233 /* Re-enable interrupts. */
1234 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1235
d1f483a6 1236 if (!ifq_is_empty(&ifp->if_snd))
984263bc
MD
1237 lge_start(ifp);
1238
1239 return;
1240}
1241
1242/*
1243 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1244 * pointers to the fragment pointers.
1245 */
1246static int lge_encap(sc, m_head, txidx)
1247 struct lge_softc *sc;
1248 struct mbuf *m_head;
1249 u_int32_t *txidx;
1250{
1251 struct lge_frag *f = NULL;
1252 struct lge_tx_desc *cur_tx;
1253 struct mbuf *m;
1254 int frag = 0, tot_len = 0;
1255
1256 /*
1257 * Start packing the mbufs in this chain into
1258 * the fragment pointers. Stop when we run out
1259 * of fragments or hit the end of the mbuf chain.
1260 */
1261 m = m_head;
1262 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1263 frag = 0;
1264
1265 for (m = m_head; m != NULL; m = m->m_next) {
1266 if (m->m_len != 0) {
1267 tot_len += m->m_len;
1268 f = &cur_tx->lge_frags[frag];
1269 f->lge_fraglen = m->m_len;
1270 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1271 f->lge_fragptr_hi = 0;
1272 frag++;
1273 }
1274 }
1275
1276 if (m != NULL)
1277 return(ENOBUFS);
1278
1279 cur_tx->lge_mbuf = m_head;
1280 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1281 LGE_INC((*txidx), LGE_TX_LIST_CNT);
1282
1283 /* Queue for transmit */
1284 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1285
1286 return(0);
1287}
1288
1289/*
1290 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1291 * to the mbuf data regions directly in the transmit lists. We also save a
1292 * copy of the pointers since the transmit list fragment pointers are
1293 * physical addresses.
1294 */
1295
1296static void lge_start(ifp)
1297 struct ifnet *ifp;
1298{
1299 struct lge_softc *sc;
1300 struct mbuf *m_head = NULL;
1301 u_int32_t idx;
1302
1303 sc = ifp->if_softc;
1304
1305 if (!sc->lge_link)
1306 return;
1307
1308 idx = sc->lge_cdata.lge_tx_prod;
1309
1310 if (ifp->if_flags & IFF_OACTIVE)
1311 return;
1312
1313 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1314 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
1315 break;
1316
d1f483a6 1317 m_head = ifq_poll(&ifp->if_snd);
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1318 if (m_head == NULL)
1319 break;
1320
1321 if (lge_encap(sc, m_head, &idx)) {
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1322 ifp->if_flags |= IFF_OACTIVE;
1323 break;
1324 }
d1f483a6 1325 m_head = ifq_dequeue(&ifp->if_snd);
984263bc 1326
7600679e 1327 BPF_MTAP(ifp, m_head);
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1328 }
1329
1330 sc->lge_cdata.lge_tx_prod = idx;
1331
1332 /*
1333 * Set a timeout in case the chip goes out to lunch.
1334 */
1335 ifp->if_timer = 5;
1336
1337 return;
1338}
1339
1340static void lge_init(xsc)
1341 void *xsc;
1342{
1343 struct lge_softc *sc = xsc;
1344 struct ifnet *ifp = &sc->arpcom.ac_if;
1345 struct mii_data *mii;
1346 int s;
1347
1348 if (ifp->if_flags & IFF_RUNNING)
1349 return;
1350
1351 s = splimp();
1352
1353 /*
1354 * Cancel pending I/O and free all RX/TX buffers.
1355 */
1356 lge_stop(sc);
1357 lge_reset(sc);
1358
1359 mii = device_get_softc(sc->lge_miibus);
1360
1361 /* Set MAC address */
1362 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1363 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1364
1365 /* Init circular RX list. */
1366 if (lge_list_rx_init(sc) == ENOBUFS) {
1367 printf("lge%d: initialization failed: no "
1368 "memory for rx buffers\n", sc->lge_unit);
1369 lge_stop(sc);
1370 (void)splx(s);
1371 return;
1372 }
1373
1374 /*
1375 * Init tx descriptors.
1376 */
1377 lge_list_tx_init(sc);
1378
1379 /* Set initial value for MODE1 register. */
1380 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST|
1381 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD|
1382 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0|
1383 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2);
1384
1385 /* If we want promiscuous mode, set the allframes bit. */
1386 if (ifp->if_flags & IFF_PROMISC) {
1387 CSR_WRITE_4(sc, LGE_MODE1,
1388 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC);
1389 } else {
1390 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1391 }
1392
1393 /*
1394 * Set the capture broadcast bit to capture broadcast frames.
1395 */
1396 if (ifp->if_flags & IFF_BROADCAST) {
1397 CSR_WRITE_4(sc, LGE_MODE1,
1398 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST);
1399 } else {
1400 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1401 }
1402
1403 /* Packet padding workaround? */
1404 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1405
1406 /* No error frames */
1407 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1408
1409 /* Receive large frames */
1410 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS);
1411
1412 /* Workaround: disable RX/TX flow control */
1413 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1414 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1415
1416 /* Make sure to strip CRC from received frames */
1417 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1418
1419 /* Turn off magic packet mode */
1420 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1421
1422 /* Turn off all VLAN stuff */
1423 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX|
1424 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT);
1425
1426 /* Workarond: FIFO overflow */
1427 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1428 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1429
1430 /*
1431 * Load the multicast filter.
1432 */
1433 lge_setmulti(sc);
1434
1435 /*
1436 * Enable hardware checksum validation for all received IPv4
1437 * packets, do not reject packets with bad checksums.
1438 */
1439 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM|
1440 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM|
1441 LGE_MODE2_RX_ERRCSUM);
1442
1443 /*
1444 * Enable the delivery of PHY interrupts based on
1445 * link/speed/duplex status chalges.
1446 */
1447 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL);
1448
1449 /* Enable receiver and transmitter. */
1450 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1451 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB);
1452
1453 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1454 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB);
1455
1456 /*
1457 * Enable interrupts.
1458 */
1459 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|
1460 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS);
1461
1462 lge_ifmedia_upd(ifp);
1463
1464 ifp->if_flags |= IFF_RUNNING;
1465 ifp->if_flags &= ~IFF_OACTIVE;
1466
1467 (void)splx(s);
1468
29744ced 1469 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc);
984263bc
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1470
1471 return;
1472}
1473
1474/*
1475 * Set media options.
1476 */
1477static int lge_ifmedia_upd(ifp)
1478 struct ifnet *ifp;
1479{
1480 struct lge_softc *sc;
1481 struct mii_data *mii;
1482
1483 sc = ifp->if_softc;
1484
1485 mii = device_get_softc(sc->lge_miibus);
1486 sc->lge_link = 0;
1487 if (mii->mii_instance) {
1488 struct mii_softc *miisc;
1489 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1490 miisc = LIST_NEXT(miisc, mii_list))
1491 mii_phy_reset(miisc);
1492 }
1493 mii_mediachg(mii);
1494
1495 return(0);
1496}
1497
1498/*
1499 * Report current media status.
1500 */
1501static void lge_ifmedia_sts(ifp, ifmr)
1502 struct ifnet *ifp;
1503 struct ifmediareq *ifmr;
1504{
1505 struct lge_softc *sc;
1506 struct mii_data *mii;
1507
1508 sc = ifp->if_softc;
1509
1510 mii = device_get_softc(sc->lge_miibus);
1511 mii_pollstat(mii);
1512 ifmr->ifm_active = mii->mii_media_active;
1513 ifmr->ifm_status = mii->mii_media_status;
1514
1515 return;
1516}
1517
bd4539cc 1518static int lge_ioctl(ifp, command, data, cr)
984263bc
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1519 struct ifnet *ifp;
1520 u_long command;
1521 caddr_t data;
bd4539cc 1522 struct ucred *cr;
984263bc
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1523{
1524 struct lge_softc *sc = ifp->if_softc;
1525 struct ifreq *ifr = (struct ifreq *) data;
1526 struct mii_data *mii;
1527 int s, error = 0;
1528
1529 s = splimp();
1530
1531 switch(command) {
1532 case SIOCSIFADDR:
1533 case SIOCGIFADDR:
1534 error = ether_ioctl(ifp, command, data);
1535 break;
1536 case SIOCSIFMTU:
1537 if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1538 error = EINVAL;
1539 else
1540 ifp->if_mtu = ifr->ifr_mtu;
1541 break;
1542 case SIOCSIFFLAGS:
1543 if (ifp->if_flags & IFF_UP) {
1544 if (ifp->if_flags & IFF_RUNNING &&
1545 ifp->if_flags & IFF_PROMISC &&
1546 !(sc->lge_if_flags & IFF_PROMISC)) {
1547 CSR_WRITE_4(sc, LGE_MODE1,
1548 LGE_MODE1_SETRST_CTL1|
1549 LGE_MODE1_RX_PROMISC);
1550 } else if (ifp->if_flags & IFF_RUNNING &&
1551 !(ifp->if_flags & IFF_PROMISC) &&
1552 sc->lge_if_flags & IFF_PROMISC) {
1553 CSR_WRITE_4(sc, LGE_MODE1,
1554 LGE_MODE1_RX_PROMISC);
1555 } else {
1556 ifp->if_flags &= ~IFF_RUNNING;
1557 lge_init(sc);
1558 }
1559 } else {
1560 if (ifp->if_flags & IFF_RUNNING)
1561 lge_stop(sc);
1562 }
1563 sc->lge_if_flags = ifp->if_flags;
1564 error = 0;
1565 break;
1566 case SIOCADDMULTI:
1567 case SIOCDELMULTI:
1568 lge_setmulti(sc);
1569 error = 0;
1570 break;
1571 case SIOCGIFMEDIA:
1572 case SIOCSIFMEDIA:
1573 mii = device_get_softc(sc->lge_miibus);
1574 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1575 break;
1576 default:
1577 error = EINVAL;
1578 break;
1579 }
1580
1581 (void)splx(s);
1582
1583 return(error);
1584}
1585
1586static void lge_watchdog(ifp)
1587 struct ifnet *ifp;
1588{
1589 struct lge_softc *sc;
1590
1591 sc = ifp->if_softc;
1592
1593 ifp->if_oerrors++;
1594 printf("lge%d: watchdog timeout\n", sc->lge_unit);
1595
1596 lge_stop(sc);
1597 lge_reset(sc);
1598 ifp->if_flags &= ~IFF_RUNNING;
1599 lge_init(sc);
1600
d1f483a6 1601 if (!ifq_is_empty(&ifp->if_snd))
984263bc
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1602 lge_start(ifp);
1603
1604 return;
1605}
1606
1607/*
1608 * Stop the adapter and free any mbufs allocated to the
1609 * RX and TX lists.
1610 */
1611static void lge_stop(sc)
1612 struct lge_softc *sc;
1613{
f96d6c88 1614 int i;
984263bc
MD
1615 struct ifnet *ifp;
1616
1617 ifp = &sc->arpcom.ac_if;
1618 ifp->if_timer = 0;
29744ced 1619 callout_stop(&sc->lge_stat_timer);
984263bc
MD
1620 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1621
1622 /* Disable receiver and transmitter. */
1623 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1624 sc->lge_link = 0;
1625
1626 /*
1627 * Free data in the RX lists.
1628 */
1629 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1630 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1631 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1632 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1633 }
1634 }
1635 bzero((char *)&sc->lge_ldata->lge_rx_list,
1636 sizeof(sc->lge_ldata->lge_rx_list));
1637
1638 /*
1639 * Free the TX list buffers.
1640 */
1641 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1642 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1643 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1644 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1645 }
1646 }
1647
1648 bzero((char *)&sc->lge_ldata->lge_tx_list,
1649 sizeof(sc->lge_ldata->lge_tx_list));
1650
1651 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1652
1653 return;
1654}
1655
1656/*
1657 * Stop all chip I/O so that the kernel's probe routines don't
1658 * get confused by errant DMAs when rebooting.
1659 */
1660static void lge_shutdown(dev)
1661 device_t dev;
1662{
1663 struct lge_softc *sc;
1664
1665 sc = device_get_softc(dev);
1666
1667 lge_reset(sc);
1668 lge_stop(sc);
1669
1670 return;
1671}