drm/i915: Add Coffee Lake support
[dragonfly.git] / sys / dev / drm / include / drm / i915_pciids.h
CommitLineData
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1/*
2 * Copyright 2013 Intel Corporation
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25#ifndef _I915_PCIIDS_H
26#define _I915_PCIIDS_H
27
28/*
29 * A pci_device_id struct {
30 * __u32 vendor, device;
31 * __u32 subvendor, subdevice;
32 * __u32 class, class_mask;
33 * kernel_ulong_t driver_data;
34 * };
35 * Don't use C99 here because "class" is reserved and we want to
36 * give userspace flexibility.
37 */
38#define INTEL_VGA_DEVICE(id, info) { \
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39 0x8086, id, \
40 ~0, ~0, \
41 0x030000, 0xff0000, \
42 (unsigned long) info }
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43
44#define INTEL_QUANTA_VGA_DEVICE(info) { \
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45 0x8086, 0x16a, \
46 0x152d, 0x8990, \
47 0x030000, 0xff0000, \
48 (unsigned long) info }
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49
50#define INTEL_I830_IDS(info) \
51 INTEL_VGA_DEVICE(0x3577, info)
52
53#define INTEL_I845G_IDS(info) \
54 INTEL_VGA_DEVICE(0x2562, info)
55
56#define INTEL_I85X_IDS(info) \
57 INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
58 INTEL_VGA_DEVICE(0x358e, info)
59
60#define INTEL_I865G_IDS(info) \
61 INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
62
63#define INTEL_I915G_IDS(info) \
64 INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
65 INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */
66
67#define INTEL_I915GM_IDS(info) \
68 INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
69
70#define INTEL_I945G_IDS(info) \
71 INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
72
73#define INTEL_I945GM_IDS(info) \
74 INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
75 INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */
76
77#define INTEL_I965G_IDS(info) \
78 INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \
79 INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \
80 INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \
81 INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */
82
83#define INTEL_G33_IDS(info) \
84 INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
85 INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \
86 INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */
87
88#define INTEL_I965GM_IDS(info) \
89 INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \
90 INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */
91
92#define INTEL_GM45_IDS(info) \
93 INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
94
95#define INTEL_G45_IDS(info) \
96 INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
97 INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
98 INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
99 INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
100 INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
101 INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
102
103#define INTEL_PINEVIEW_IDS(info) \
104 INTEL_VGA_DEVICE(0xa001, info), \
105 INTEL_VGA_DEVICE(0xa011, info)
106
107#define INTEL_IRONLAKE_D_IDS(info) \
108 INTEL_VGA_DEVICE(0x0042, info)
109
110#define INTEL_IRONLAKE_M_IDS(info) \
111 INTEL_VGA_DEVICE(0x0046, info)
112
113#define INTEL_SNB_D_IDS(info) \
114 INTEL_VGA_DEVICE(0x0102, info), \
115 INTEL_VGA_DEVICE(0x0112, info), \
116 INTEL_VGA_DEVICE(0x0122, info), \
117 INTEL_VGA_DEVICE(0x010A, info)
118
119#define INTEL_SNB_M_IDS(info) \
120 INTEL_VGA_DEVICE(0x0106, info), \
121 INTEL_VGA_DEVICE(0x0116, info), \
122 INTEL_VGA_DEVICE(0x0126, info)
123
124#define INTEL_IVB_M_IDS(info) \
125 INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \
126 INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
127
128#define INTEL_IVB_D_IDS(info) \
129 INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
130 INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
131 INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \
132 INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */
133
134#define INTEL_IVB_Q_IDS(info) \
135 INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
136
137#define INTEL_HSW_D_IDS(info) \
138 INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
139 INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
140 INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
141 INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
142 INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
143 INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
144 INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
145 INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
146 INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
147 INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
148 INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
149 INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
150 INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
151 INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
152 INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
153 INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
154 INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
155 INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
156 INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
157 INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
158 INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
159 INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
160 INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
161 INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
162 INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
163 INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
164 INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
165 INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
166 INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
167 INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
168 INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
169 INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
170 INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
171 INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
172 INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
173 INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
174 INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
175 INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
176 INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
177 INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
178 INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
179 INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
180 INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
181 INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
182 INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */ \
183
184#define INTEL_HSW_M_IDS(info) \
185 INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
186 INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
187 INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
188 INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
189 INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
190 INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
191 INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
192 INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
193 INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
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194 INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
195 INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
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196 INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
197 INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
198 INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
199 INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
200
201#define INTEL_VLV_M_IDS(info) \
202 INTEL_VGA_DEVICE(0x0f30, info), \
203 INTEL_VGA_DEVICE(0x0f31, info), \
204 INTEL_VGA_DEVICE(0x0f32, info), \
205 INTEL_VGA_DEVICE(0x0f33, info), \
206 INTEL_VGA_DEVICE(0x0157, info)
207
208#define INTEL_VLV_D_IDS(info) \
209 INTEL_VGA_DEVICE(0x0155, info)
210
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211#define INTEL_BDW_GT12M_IDS(info) \
212 INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
213 INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
214 INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
215 INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
216 INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
217 INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
218 INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
219 INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */
9edbd4a0 220
ba55f2f5 221#define INTEL_BDW_GT12D_IDS(info) \
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222 INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
223 INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \
224 INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
225 INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */
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226
227#define INTEL_BDW_GT3M_IDS(info) \
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228 INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
229 INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
230 INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
231 INTEL_VGA_DEVICE(0x162E, info) /* ULX */
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232
233#define INTEL_BDW_GT3D_IDS(info) \
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234 INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
235 INTEL_VGA_DEVICE(0x162D, info) /* Workstation */
9edbd4a0 236
ba55f2f5 237#define INTEL_BDW_RSVDM_IDS(info) \
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238 INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
239 INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
240 INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \
241 INTEL_VGA_DEVICE(0x163E, info) /* ULX */
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242
243#define INTEL_BDW_RSVDD_IDS(info) \
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244 INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
245 INTEL_VGA_DEVICE(0x163D, info) /* Workstation */
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246
247#define INTEL_BDW_M_IDS(info) \
248 INTEL_BDW_GT12M_IDS(info), \
249 INTEL_BDW_GT3M_IDS(info), \
250 INTEL_BDW_RSVDM_IDS(info)
251
252#define INTEL_BDW_D_IDS(info) \
253 INTEL_BDW_GT12D_IDS(info), \
254 INTEL_BDW_GT3D_IDS(info), \
255 INTEL_BDW_RSVDD_IDS(info)
256
257#define INTEL_CHV_IDS(info) \
258 INTEL_VGA_DEVICE(0x22b0, info), \
259 INTEL_VGA_DEVICE(0x22b1, info), \
260 INTEL_VGA_DEVICE(0x22b2, info), \
261 INTEL_VGA_DEVICE(0x22b3, info)
262
477eb7f9 263#define INTEL_SKL_GT1_IDS(info) \
2c9916cd 264 INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
2c9916cd 265 INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
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266 INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
267 INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
268 INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
269
270#define INTEL_SKL_GT2_IDS(info) \
271 INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
272 INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
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273 INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
274 INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \
2c9916cd 275 INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
2c9916cd 276 INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
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277 INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */
278
477eb7f9 279#define INTEL_SKL_GT3_IDS(info) \
c0e85e96 280 INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
477eb7f9 281 INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
c0e85e96 282 INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
477eb7f9 283 INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
aee94f86 284 INTEL_VGA_DEVICE(0x192A, info) /* SRV GT3 */
477eb7f9 285
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286#define INTEL_SKL_GT4_IDS(info) \
287 INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
288 INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
289 INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
290 INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4 */
291
292#define INTEL_SKL_IDS(info) \
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293 INTEL_SKL_GT1_IDS(info), \
294 INTEL_SKL_GT2_IDS(info), \
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295 INTEL_SKL_GT3_IDS(info), \
296 INTEL_SKL_GT4_IDS(info)
477eb7f9 297
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298#define INTEL_BXT_IDS(info) \
299 INTEL_VGA_DEVICE(0x0A84, info), \
352ff8bd 300 INTEL_VGA_DEVICE(0x1A84, info), \
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301 INTEL_VGA_DEVICE(0x1A85, info), \
302 INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
303 INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */
477eb7f9 304
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305#define INTEL_KBL_GT1_IDS(info) \
306 INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
307 INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
308 INTEL_VGA_DEVICE(0x5917, info), /* DT GT1.5 */ \
309 INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
310 INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
311 INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
312 INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
313 INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
314
315#define INTEL_KBL_GT2_IDS(info) \
316 INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
317 INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
318 INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
319 INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
320 INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
321 INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
322 INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
323
324#define INTEL_KBL_GT3_IDS(info) \
325 INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
326 INTEL_VGA_DEVICE(0x592B, info), /* Halo GT3 */ \
327 INTEL_VGA_DEVICE(0x592A, info) /* SRV GT3 */
328
329#define INTEL_KBL_GT4_IDS(info) \
330 INTEL_VGA_DEVICE(0x5932, info), /* DT GT4 */ \
331 INTEL_VGA_DEVICE(0x593B, info), /* Halo GT4 */ \
332 INTEL_VGA_DEVICE(0x593A, info), /* SRV GT4 */ \
333 INTEL_VGA_DEVICE(0x593D, info) /* WKS GT4 */
334
335#define INTEL_KBL_IDS(info) \
336 INTEL_KBL_GT1_IDS(info), \
337 INTEL_KBL_GT2_IDS(info), \
338 INTEL_KBL_GT3_IDS(info), \
339 INTEL_KBL_GT4_IDS(info)
340
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341/* CFL S */
342#define INTEL_CFL_S_IDS(info) \
343 INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \
344 INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \
345 INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \
346 INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \
347 INTEL_VGA_DEVICE(0x3E96, info) /* SRV GT2 */
348
349/* CFL H */
350#define INTEL_CFL_H_IDS(info) \
351 INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
352 INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */
353
354/* CFL U */
355#define INTEL_CFL_U_IDS(info) \
356 INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \
357 INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \
358 INTEL_VGA_DEVICE(0x3EA8, info), /* ULT GT3 */ \
359 INTEL_VGA_DEVICE(0x3EA5, info) /* ULT GT3 */
360
9edbd4a0 361#endif /* _I915_PCIIDS_H */