ALTQ support. Remove bogus check of ifq max len.
[dragonfly.git] / sys / dev / netif / bge / if_bge.c
CommitLineData
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1/*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
7e40b8c5 33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.29 2003/12/01 21:06:59 ambrisko Exp $
936ff230 34 * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.27 2005/02/14 17:45:08 joerg Exp $
1de703da 35 *
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36 */
37
38/*
39 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
40 *
41 * Written by Bill Paul <wpaul@windriver.com>
42 * Senior Engineer, Wind River Systems
43 */
44
45/*
46 * The Broadcom BCM5700 is based on technology originally developed by
47 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
48 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
49 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
50 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
51 * frames, highly configurable RX filtering, and 16 RX and TX queues
52 * (which, along with RX filter rules, can be used for QOS applications).
53 * Other features, such as TCP segmentation, may be available as part
54 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
55 * firmware images can be stored in hardware and need not be compiled
56 * into the driver.
57 *
58 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
59 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
60 *
61 * The BCM5701 is a single-chip solution incorporating both the BCM5700
62 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
63 * does not support external SSRAM.
64 *
65 * Broadcom also produces a variation of the BCM5700 under the "Altima"
66 * brand name, which is functionally similar but lacks PCI-X support.
67 *
68 * Without external SSRAM, you can only have at most 4 TX rings,
69 * and the use of the mini RX ring is disabled. This seems to imply
70 * that these features are simply not available on the BCM5701. As a
71 * result, this driver does not implement any support for the mini RX
72 * ring.
73 */
74
75#include <sys/param.h>
76#include <sys/systm.h>
77#include <sys/sockio.h>
78#include <sys/mbuf.h>
79#include <sys/malloc.h>
80#include <sys/kernel.h>
81#include <sys/socket.h>
82#include <sys/queue.h>
83
84#include <net/if.h>
936ff230 85#include <net/ifq_var.h>
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86#include <net/if_arp.h>
87#include <net/ethernet.h>
88#include <net/if_dl.h>
89#include <net/if_media.h>
90
91#include <net/bpf.h>
92
93#include <net/if_types.h>
1f2de5d4 94#include <net/vlan/if_vlan_var.h>
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95
96#include <netinet/in_systm.h>
97#include <netinet/in.h>
98#include <netinet/ip.h>
99
100#include <vm/vm.h> /* for vtophys */
101#include <vm/pmap.h> /* for vtophys */
102#include <machine/clock.h> /* for DELAY */
103#include <machine/bus_memio.h>
104#include <machine/bus.h>
105#include <machine/resource.h>
106#include <sys/bus.h>
107#include <sys/rman.h>
108
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109#include <dev/netif/mii_layer/mii.h>
110#include <dev/netif/mii_layer/miivar.h>
111#include <dev/netif/mii_layer/miidevs.h>
112#include <dev/netif/mii_layer/brgphyreg.h>
984263bc 113
f952ab63 114#include <bus/pci/pcidevs.h>
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115#include <bus/pci/pcireg.h>
116#include <bus/pci/pcivar.h>
984263bc 117
1f2de5d4 118#include "if_bgereg.h"
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119
120#define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
121
122/* "controller miibus0" required. See GENERIC if you get errors here. */
123#include "miibus_if.h"
124
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125/*
126 * Various supported device vendors/types and their names. Note: the
127 * spec seems to indicate that the hardware still has Alteon's vendor
128 * ID burned into it, though it will always be overriden by the vendor
129 * ID in the EEPROM. Just to be safe, we cover all possibilities.
130 */
131#define BGE_DEVDESC_MAX 64 /* Maximum device description length */
132
133static struct bge_type bge_devs[] = {
f952ab63 134 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
984263bc 135 "Broadcom BCM5700 Gigabit Ethernet" },
f952ab63 136 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
984263bc 137 "Broadcom BCM5701 Gigabit Ethernet" },
f952ab63 138 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
984263bc 139 "Broadcom BCM5700 Gigabit Ethernet" },
f952ab63 140 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
984263bc 141 "Broadcom BCM5701 Gigabit Ethernet" },
f952ab63 142 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
984263bc 143 "Broadcom BCM5702X Gigabit Ethernet" },
f952ab63
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144 { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5702X,
145 "Broadcom BCM5702X Gigabit Ethernet" },
146 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
147 "Broadcom BCM5703X Gigabit Ethernet" },
148 { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5703X,
984263bc 149 "Broadcom BCM5703X Gigabit Ethernet" },
f952ab63 150 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
984263bc 151 "Broadcom BCM5704C Dual Gigabit Ethernet" },
f952ab63 152 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
984263bc 153 "Broadcom BCM5704S Dual Gigabit Ethernet" },
f952ab63 154 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
7e40b8c5 155 "Broadcom BCM5705 Gigabit Ethernet" },
f952ab63 156 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
7e40b8c5 157 "Broadcom BCM5705M Gigabit Ethernet" },
f952ab63 158 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705_ALT,
7e40b8c5 159 "Broadcom BCM5705M Gigabit Ethernet" },
f952ab63 160 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
7e40b8c5 161 "Broadcom BCM5782 Gigabit Ethernet" },
f952ab63
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162 { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5788,
163 "Broadcom BCM5788 Gigabit Ethernet" },
164 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
165 "Broadcom BCM5901 Fast Ethernet" },
166 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
167 "Broadcom BCM5901A2 Fast Ethernet" },
168 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
984263bc 169 "SysKonnect Gigabit Ethernet" },
f952ab63 170 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
984263bc 171 "Altima AC1000 Gigabit Ethernet" },
f952ab63 172 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
7e40b8c5 173 "Altima AC1002 Gigabit Ethernet" },
f952ab63 174 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
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175 "Altima AC9100 Gigabit Ethernet" },
176 { 0, 0, NULL }
177};
178
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179static int bge_probe (device_t);
180static int bge_attach (device_t);
181static int bge_detach (device_t);
984263bc 182static void bge_release_resources
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183 (struct bge_softc *);
184static void bge_txeof (struct bge_softc *);
185static void bge_rxeof (struct bge_softc *);
186
187static void bge_tick (void *);
188static void bge_stats_update (struct bge_softc *);
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189static void bge_stats_update_regs
190 (struct bge_softc *);
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191static int bge_encap (struct bge_softc *, struct mbuf *,
192 u_int32_t *);
193
194static void bge_intr (void *);
195static void bge_start (struct ifnet *);
bd4539cc
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196static int bge_ioctl (struct ifnet *, u_long, caddr_t,
197 struct ucred *);
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198static void bge_init (void *);
199static void bge_stop (struct bge_softc *);
200static void bge_watchdog (struct ifnet *);
201static void bge_shutdown (device_t);
202static int bge_ifmedia_upd (struct ifnet *);
203static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *);
204
205static u_int8_t bge_eeprom_getbyte (struct bge_softc *,
206 int, u_int8_t *);
207static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int);
208
209static u_int32_t bge_crc (caddr_t);
210static void bge_setmulti (struct bge_softc *);
211
212static void bge_handle_events (struct bge_softc *);
213static int bge_alloc_jumbo_mem (struct bge_softc *);
214static void bge_free_jumbo_mem (struct bge_softc *);
215static void *bge_jalloc (struct bge_softc *);
216static void bge_jfree (caddr_t, u_int);
217static void bge_jref (caddr_t, u_int);
218static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *);
219static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *);
220static int bge_init_rx_ring_std (struct bge_softc *);
221static void bge_free_rx_ring_std (struct bge_softc *);
222static int bge_init_rx_ring_jumbo (struct bge_softc *);
223static void bge_free_rx_ring_jumbo (struct bge_softc *);
224static void bge_free_tx_ring (struct bge_softc *);
225static int bge_init_tx_ring (struct bge_softc *);
226
227static int bge_chipinit (struct bge_softc *);
228static int bge_blockinit (struct bge_softc *);
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229
230#ifdef notdef
b5101a88
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231static u_int8_t bge_vpd_readbyte (struct bge_softc *, int);
232static void bge_vpd_read_res (struct bge_softc *,
233 struct vpd_res *, int);
234static void bge_vpd_read (struct bge_softc *);
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235#endif
236
237static u_int32_t bge_readmem_ind
b5101a88
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238 (struct bge_softc *, int);
239static void bge_writemem_ind (struct bge_softc *, int, int);
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240#ifdef notdef
241static u_int32_t bge_readreg_ind
b5101a88 242 (struct bge_softc *, int);
984263bc 243#endif
b5101a88 244static void bge_writereg_ind (struct bge_softc *, int, int);
984263bc 245
b5101a88
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246static int bge_miibus_readreg (device_t, int, int);
247static int bge_miibus_writereg (device_t, int, int, int);
248static void bge_miibus_statchg (device_t);
984263bc 249
b5101a88 250static void bge_reset (struct bge_softc *);
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251
252static device_method_t bge_methods[] = {
253 /* Device interface */
254 DEVMETHOD(device_probe, bge_probe),
255 DEVMETHOD(device_attach, bge_attach),
256 DEVMETHOD(device_detach, bge_detach),
257 DEVMETHOD(device_shutdown, bge_shutdown),
258
259 /* bus interface */
260 DEVMETHOD(bus_print_child, bus_generic_print_child),
261 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
262
263 /* MII interface */
264 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
265 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
266 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
267
268 { 0, 0 }
269};
270
271static driver_t bge_driver = {
272 "bge",
273 bge_methods,
274 sizeof(struct bge_softc)
275};
276
277static devclass_t bge_devclass;
278
32832096 279DECLARE_DUMMY_MODULE(if_bge);
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280DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
281DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
282
283static u_int32_t
284bge_readmem_ind(sc, off)
285 struct bge_softc *sc;
286 int off;
287{
288 device_t dev;
289
290 dev = sc->bge_dev;
291
292 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
293 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4));
294}
295
296static void
297bge_writemem_ind(sc, off, val)
298 struct bge_softc *sc;
299 int off, val;
300{
301 device_t dev;
302
303 dev = sc->bge_dev;
304
305 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
306 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
307
308 return;
309}
310
311#ifdef notdef
312static u_int32_t
313bge_readreg_ind(sc, off)
314 struct bge_softc *sc;
315 int off;
316{
317 device_t dev;
318
319 dev = sc->bge_dev;
320
321 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
322 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
323}
324#endif
325
326static void
327bge_writereg_ind(sc, off, val)
328 struct bge_softc *sc;
329 int off, val;
330{
331 device_t dev;
332
333 dev = sc->bge_dev;
334
335 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
336 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
337
338 return;
339}
340
341#ifdef notdef
342static u_int8_t
343bge_vpd_readbyte(sc, addr)
344 struct bge_softc *sc;
345 int addr;
346{
347 int i;
348 device_t dev;
349 u_int32_t val;
350
351 dev = sc->bge_dev;
352 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2);
353 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
354 DELAY(10);
355 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG)
356 break;
357 }
358
359 if (i == BGE_TIMEOUT) {
360 printf("bge%d: VPD read timed out\n", sc->bge_unit);
361 return(0);
362 }
363
364 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4);
365
366 return((val >> ((addr % 4) * 8)) & 0xFF);
367}
368
369static void
370bge_vpd_read_res(sc, res, addr)
371 struct bge_softc *sc;
372 struct vpd_res *res;
373 int addr;
374{
375 int i;
376 u_int8_t *ptr;
377
378 ptr = (u_int8_t *)res;
379 for (i = 0; i < sizeof(struct vpd_res); i++)
380 ptr[i] = bge_vpd_readbyte(sc, i + addr);
381
382 return;
383}
384
385static void
386bge_vpd_read(sc)
387 struct bge_softc *sc;
388{
389 int pos = 0, i;
390 struct vpd_res res;
391
392 if (sc->bge_vpd_prodname != NULL)
393 free(sc->bge_vpd_prodname, M_DEVBUF);
394 if (sc->bge_vpd_readonly != NULL)
395 free(sc->bge_vpd_readonly, M_DEVBUF);
396 sc->bge_vpd_prodname = NULL;
397 sc->bge_vpd_readonly = NULL;
398
399 bge_vpd_read_res(sc, &res, pos);
400
401 if (res.vr_id != VPD_RES_ID) {
402 printf("bge%d: bad VPD resource id: expected %x got %x\n",
403 sc->bge_unit, VPD_RES_ID, res.vr_id);
404 return;
405 }
406
407 pos += sizeof(res);
c5541aee 408 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT);
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409 for (i = 0; i < res.vr_len; i++)
410 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos);
411 sc->bge_vpd_prodname[i] = '\0';
412 pos += i;
413
414 bge_vpd_read_res(sc, &res, pos);
415
416 if (res.vr_id != VPD_RES_READ) {
417 printf("bge%d: bad VPD resource id: expected %x got %x\n",
418 sc->bge_unit, VPD_RES_READ, res.vr_id);
419 return;
420 }
421
422 pos += sizeof(res);
c5541aee 423 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT);
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MD
424 for (i = 0; i < res.vr_len + 1; i++)
425 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos);
426
427 return;
428}
429#endif
430
431/*
432 * Read a byte of data stored in the EEPROM at address 'addr.' The
433 * BCM570x supports both the traditional bitbang interface and an
434 * auto access interface for reading the EEPROM. We use the auto
435 * access method.
436 */
437static u_int8_t
438bge_eeprom_getbyte(sc, addr, dest)
439 struct bge_softc *sc;
440 int addr;
441 u_int8_t *dest;
442{
443 int i;
444 u_int32_t byte = 0;
445
446 /*
447 * Enable use of auto EEPROM access so we can avoid
448 * having to use the bitbang method.
449 */
450 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
451
452 /* Reset the EEPROM, load the clock period. */
453 CSR_WRITE_4(sc, BGE_EE_ADDR,
454 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
455 DELAY(20);
456
457 /* Issue the read EEPROM command. */
458 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
459
460 /* Wait for completion */
461 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
462 DELAY(10);
463 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
464 break;
465 }
466
467 if (i == BGE_TIMEOUT) {
468 printf("bge%d: eeprom read timed out\n", sc->bge_unit);
469 return(0);
470 }
471
472 /* Get result. */
473 byte = CSR_READ_4(sc, BGE_EE_DATA);
474
475 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
476
477 return(0);
478}
479
480/*
481 * Read a sequence of bytes from the EEPROM.
482 */
483static int
484bge_read_eeprom(sc, dest, off, cnt)
485 struct bge_softc *sc;
486 caddr_t dest;
487 int off;
488 int cnt;
489{
490 int err = 0, i;
491 u_int8_t byte = 0;
492
493 for (i = 0; i < cnt; i++) {
494 err = bge_eeprom_getbyte(sc, off + i, &byte);
495 if (err)
496 break;
497 *(dest + i) = byte;
498 }
499
500 return(err ? 1 : 0);
501}
502
503static int
504bge_miibus_readreg(dev, phy, reg)
505 device_t dev;
506 int phy, reg;
507{
508 struct bge_softc *sc;
509 struct ifnet *ifp;
510 u_int32_t val, autopoll;
511 int i;
512
513 sc = device_get_softc(dev);
514 ifp = &sc->arpcom.ac_if;
515
7e40b8c5
HP
516 /*
517 * Broadcom's own driver always assumes the internal
518 * PHY is at GMII address 1. On some chips, the PHY responds
519 * to accesses at all addresses, which could cause us to
520 * bogusly attach the PHY 32 times at probe type. Always
521 * restricting the lookup to address 1 is simpler than
522 * trying to figure out which chips revisions should be
523 * special-cased.
524 */
984263bc 525 if (phy != 1)
7e40b8c5 526 return(0);
984263bc
MD
527
528 /* Reading with autopolling on may trigger PCI errors */
529 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
530 if (autopoll & BGE_MIMODE_AUTOPOLL) {
531 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
532 DELAY(40);
533 }
534
535 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
536 BGE_MIPHY(phy)|BGE_MIREG(reg));
537
538 for (i = 0; i < BGE_TIMEOUT; i++) {
539 val = CSR_READ_4(sc, BGE_MI_COMM);
540 if (!(val & BGE_MICOMM_BUSY))
541 break;
542 }
543
544 if (i == BGE_TIMEOUT) {
545 printf("bge%d: PHY read timed out\n", sc->bge_unit);
546 val = 0;
547 goto done;
548 }
549
550 val = CSR_READ_4(sc, BGE_MI_COMM);
551
552done:
553 if (autopoll & BGE_MIMODE_AUTOPOLL) {
554 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
555 DELAY(40);
556 }
557
558 if (val & BGE_MICOMM_READFAIL)
559 return(0);
560
561 return(val & 0xFFFF);
562}
563
564static int
565bge_miibus_writereg(dev, phy, reg, val)
566 device_t dev;
567 int phy, reg, val;
568{
569 struct bge_softc *sc;
570 u_int32_t autopoll;
571 int i;
572
573 sc = device_get_softc(dev);
574
575 /* Reading with autopolling on may trigger PCI errors */
576 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
577 if (autopoll & BGE_MIMODE_AUTOPOLL) {
578 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
579 DELAY(40);
580 }
581
582 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
583 BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
584
585 for (i = 0; i < BGE_TIMEOUT; i++) {
586 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
587 break;
588 }
589
590 if (autopoll & BGE_MIMODE_AUTOPOLL) {
591 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
592 DELAY(40);
593 }
594
595 if (i == BGE_TIMEOUT) {
596 printf("bge%d: PHY read timed out\n", sc->bge_unit);
597 return(0);
598 }
599
600 return(0);
601}
602
603static void
604bge_miibus_statchg(dev)
605 device_t dev;
606{
607 struct bge_softc *sc;
608 struct mii_data *mii;
609
610 sc = device_get_softc(dev);
611 mii = device_get_softc(sc->bge_miibus);
612
613 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
7f259627 614 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
984263bc
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615 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
616 } else {
617 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
618 }
619
620 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
621 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
622 } else {
623 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
624 }
625
626 return;
627}
628
629/*
630 * Handle events that have triggered interrupts.
631 */
632static void
633bge_handle_events(sc)
634 struct bge_softc *sc;
635{
636
637 return;
638}
639
640/*
641 * Memory management for jumbo frames.
642 */
643
644static int
645bge_alloc_jumbo_mem(sc)
646 struct bge_softc *sc;
647{
648 caddr_t ptr;
f96d6c88 649 int i;
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650 struct bge_jpool_entry *entry;
651
652 /* Grab a big chunk o' storage. */
653 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF,
654 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
655
656 if (sc->bge_cdata.bge_jumbo_buf == NULL) {
657 printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit);
658 return(ENOBUFS);
659 }
660
661 SLIST_INIT(&sc->bge_jfree_listhead);
662 SLIST_INIT(&sc->bge_jinuse_listhead);
663
664 /*
665 * Now divide it up into 9K pieces and save the addresses
666 * in an array. Note that we play an evil trick here by using
667 * the first few bytes in the buffer to hold the the address
668 * of the softc structure for this interface. This is because
669 * bge_jfree() needs it, but it is called by the mbuf management
670 * code which will not pass it to us explicitly.
671 */
672 ptr = sc->bge_cdata.bge_jumbo_buf;
673 for (i = 0; i < BGE_JSLOTS; i++) {
674 u_int64_t **aptr;
675 aptr = (u_int64_t **)ptr;
676 aptr[0] = (u_int64_t *)sc;
677 ptr += sizeof(u_int64_t);
678 sc->bge_cdata.bge_jslots[i].bge_buf = ptr;
679 sc->bge_cdata.bge_jslots[i].bge_inuse = 0;
680 ptr += (BGE_JLEN - sizeof(u_int64_t));
681 entry = malloc(sizeof(struct bge_jpool_entry),
c5541aee 682 M_DEVBUF, M_INTWAIT);
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683 entry->slot = i;
684 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
685 entry, jpool_entries);
686 }
687
688 return(0);
689}
690
691static void
692bge_free_jumbo_mem(sc)
693 struct bge_softc *sc;
694{
695 int i;
696 struct bge_jpool_entry *entry;
697
698 for (i = 0; i < BGE_JSLOTS; i++) {
699 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
700 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
701 free(entry, M_DEVBUF);
702 }
703
704 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF);
705
706 return;
707}
708
709/*
710 * Allocate a jumbo buffer.
711 */
712static void *
713bge_jalloc(sc)
714 struct bge_softc *sc;
715{
716 struct bge_jpool_entry *entry;
717
718 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
719
720 if (entry == NULL) {
721 printf("bge%d: no free jumbo buffers\n", sc->bge_unit);
722 return(NULL);
723 }
724
725 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
726 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries);
727 sc->bge_cdata.bge_jslots[entry->slot].bge_inuse = 1;
728 return(sc->bge_cdata.bge_jslots[entry->slot].bge_buf);
729}
730
731/*
732 * Adjust usage count on a jumbo buffer.
733 */
734static void
735bge_jref(buf, size)
736 caddr_t buf;
737 u_int size;
738{
739 struct bge_softc *sc;
740 u_int64_t **aptr;
f96d6c88 741 int i;
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742
743 /* Extract the softc struct pointer. */
744 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
745 sc = (struct bge_softc *)(aptr[0]);
746
747 if (sc == NULL)
748 panic("bge_jref: can't find softc pointer!");
749
750 if (size != BGE_JUMBO_FRAMELEN)
751 panic("bge_jref: adjusting refcount of buf of wrong size!");
752
753 /* calculate the slot this buffer belongs to */
754
755 i = ((vm_offset_t)aptr
756 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN;
757
758 if ((i < 0) || (i >= BGE_JSLOTS))
759 panic("bge_jref: asked to reference buffer "
760 "that we don't manage!");
761 else if (sc->bge_cdata.bge_jslots[i].bge_inuse == 0)
762 panic("bge_jref: buffer already free!");
763 else
764 sc->bge_cdata.bge_jslots[i].bge_inuse++;
765
766 return;
767}
768
769/*
770 * Release a jumbo buffer.
771 */
772static void
773bge_jfree(buf, size)
774 caddr_t buf;
775 u_int size;
776{
777 struct bge_softc *sc;
778 u_int64_t **aptr;
779 int i;
780 struct bge_jpool_entry *entry;
781
782 /* Extract the softc struct pointer. */
783 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
784 sc = (struct bge_softc *)(aptr[0]);
785
786 if (sc == NULL)
787 panic("bge_jfree: can't find softc pointer!");
788
789 if (size != BGE_JUMBO_FRAMELEN)
790 panic("bge_jfree: freeing buffer of wrong size!");
791
792 /* calculate the slot this buffer belongs to */
793
794 i = ((vm_offset_t)aptr
795 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN;
796
797 if ((i < 0) || (i >= BGE_JSLOTS))
798 panic("bge_jfree: asked to free buffer that we don't manage!");
799 else if (sc->bge_cdata.bge_jslots[i].bge_inuse == 0)
800 panic("bge_jfree: buffer already free!");
801 else {
802 sc->bge_cdata.bge_jslots[i].bge_inuse--;
803 if(sc->bge_cdata.bge_jslots[i].bge_inuse == 0) {
804 entry = SLIST_FIRST(&sc->bge_jinuse_listhead);
805 if (entry == NULL)
806 panic("bge_jfree: buffer not in use!");
807 entry->slot = i;
808 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead,
809 jpool_entries);
810 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
811 entry, jpool_entries);
812 }
813 }
814
815 return;
816}
817
818
819/*
820 * Intialize a standard receive ring descriptor.
821 */
822static int
823bge_newbuf_std(sc, i, m)
824 struct bge_softc *sc;
825 int i;
826 struct mbuf *m;
827{
828 struct mbuf *m_new = NULL;
829 struct bge_rx_bd *r;
830
831 if (m == NULL) {
74f1caca 832 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
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833 if (m_new == NULL) {
834 return(ENOBUFS);
835 }
836
74f1caca 837 MCLGET(m_new, MB_DONTWAIT);
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838 if (!(m_new->m_flags & M_EXT)) {
839 m_freem(m_new);
840 return(ENOBUFS);
841 }
842 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
843 } else {
844 m_new = m;
845 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
846 m_new->m_data = m_new->m_ext.ext_buf;
847 }
848
849 if (!sc->bge_rx_alignment_bug)
850 m_adj(m_new, ETHER_ALIGN);
851 sc->bge_cdata.bge_rx_std_chain[i] = m_new;
852 r = &sc->bge_rdata->bge_rx_std_ring[i];
7e40b8c5 853 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
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854 r->bge_flags = BGE_RXBDFLAG_END;
855 r->bge_len = m_new->m_len;
856 r->bge_idx = i;
857
858 return(0);
859}
860
861/*
862 * Initialize a jumbo receive ring descriptor. This allocates
863 * a jumbo buffer from the pool managed internally by the driver.
864 */
865static int
866bge_newbuf_jumbo(sc, i, m)
867 struct bge_softc *sc;
868 int i;
869 struct mbuf *m;
870{
871 struct mbuf *m_new = NULL;
872 struct bge_rx_bd *r;
873
874 if (m == NULL) {
875 caddr_t *buf = NULL;
876
877 /* Allocate the mbuf. */
74f1caca 878 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
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879 if (m_new == NULL) {
880 return(ENOBUFS);
881 }
882
883 /* Allocate the jumbo buffer */
884 buf = bge_jalloc(sc);
885 if (buf == NULL) {
886 m_freem(m_new);
887 printf("bge%d: jumbo allocation failed "
888 "-- packet dropped!\n", sc->bge_unit);
889 return(ENOBUFS);
890 }
891
892 /* Attach the buffer to the mbuf. */
893 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
7eccf245 894 m_new->m_flags |= M_EXT | M_EXT_OLD;
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895 m_new->m_len = m_new->m_pkthdr.len =
896 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
7eccf245
MD
897 m_new->m_ext.ext_nfree.old = bge_jfree;
898 m_new->m_ext.ext_nref.old = bge_jref;
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899 } else {
900 m_new = m;
901 m_new->m_data = m_new->m_ext.ext_buf;
902 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
903 }
904
905 if (!sc->bge_rx_alignment_bug)
906 m_adj(m_new, ETHER_ALIGN);
907 /* Set up the descriptor. */
908 r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
909 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
7e40b8c5 910 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
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911 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
912 r->bge_len = m_new->m_len;
913 r->bge_idx = i;
914
915 return(0);
916}
917
918/*
919 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
920 * that's 1MB or memory, which is a lot. For now, we fill only the first
921 * 256 ring entries and hope that our CPU is fast enough to keep up with
922 * the NIC.
923 */
924static int
925bge_init_rx_ring_std(sc)
926 struct bge_softc *sc;
927{
928 int i;
929
930 for (i = 0; i < BGE_SSLOTS; i++) {
931 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
932 return(ENOBUFS);
933 };
934
935 sc->bge_std = i - 1;
936 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
937
938 return(0);
939}
940
941static void
942bge_free_rx_ring_std(sc)
943 struct bge_softc *sc;
944{
945 int i;
946
947 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
948 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
949 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
950 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
951 }
952 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i],
953 sizeof(struct bge_rx_bd));
954 }
955
956 return;
957}
958
959static int
960bge_init_rx_ring_jumbo(sc)
961 struct bge_softc *sc;
962{
963 int i;
964 struct bge_rcb *rcb;
965
966 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
967 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
968 return(ENOBUFS);
969 };
970
971 sc->bge_jumbo = i - 1;
972
973 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
974 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
975 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
976
977 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
978
979 return(0);
980}
981
982static void
983bge_free_rx_ring_jumbo(sc)
984 struct bge_softc *sc;
985{
986 int i;
987
988 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
989 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
990 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
991 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
992 }
993 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i],
994 sizeof(struct bge_rx_bd));
995 }
996
997 return;
998}
999
1000static void
1001bge_free_tx_ring(sc)
1002 struct bge_softc *sc;
1003{
1004 int i;
1005
1006 if (sc->bge_rdata->bge_tx_ring == NULL)
1007 return;
1008
1009 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1010 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1011 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1012 sc->bge_cdata.bge_tx_chain[i] = NULL;
1013 }
1014 bzero((char *)&sc->bge_rdata->bge_tx_ring[i],
1015 sizeof(struct bge_tx_bd));
1016 }
1017
1018 return;
1019}
1020
1021static int
1022bge_init_tx_ring(sc)
1023 struct bge_softc *sc;
1024{
1025 sc->bge_txcnt = 0;
1026 sc->bge_tx_saved_considx = 0;
1027
1028 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
1029 /* 5700 b2 errata */
1030 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1031 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
1032
1033 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1034 /* 5700 b2 errata */
1035 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1036 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1037
1038 return(0);
1039}
1040
1041#define BGE_POLY 0xEDB88320
1042
1043static u_int32_t
1044bge_crc(addr)
1045 caddr_t addr;
1046{
1047 u_int32_t idx, bit, data, crc;
1048
1049 /* Compute CRC for the address value. */
1050 crc = 0xFFFFFFFF; /* initial value */
1051
1052 for (idx = 0; idx < 6; idx++) {
1053 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
1054 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0);
1055 }
1056
1057 return(crc & 0x7F);
1058}
1059
1060static void
1061bge_setmulti(sc)
1062 struct bge_softc *sc;
1063{
1064 struct ifnet *ifp;
1065 struct ifmultiaddr *ifma;
1066 u_int32_t hashes[4] = { 0, 0, 0, 0 };
1067 int h, i;
1068
1069 ifp = &sc->arpcom.ac_if;
1070
1071 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1072 for (i = 0; i < 4; i++)
1073 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1074 return;
1075 }
1076
1077 /* First, zot all the existing filters. */
1078 for (i = 0; i < 4; i++)
1079 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1080
1081 /* Now program new ones. */
1082 for (ifma = ifp->if_multiaddrs.lh_first;
1083 ifma != NULL; ifma = ifma->ifma_link.le_next) {
1084 if (ifma->ifma_addr->sa_family != AF_LINK)
1085 continue;
1086 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1087 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1088 }
1089
1090 for (i = 0; i < 4; i++)
1091 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1092
1093 return;
1094}
1095
1096/*
1097 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1098 * self-test results.
1099 */
1100static int
1101bge_chipinit(sc)
1102 struct bge_softc *sc;
1103{
1104 int i;
1105 u_int32_t dma_rw_ctl;
1106
1107 /* Set endianness before we access any non-PCI registers. */
1108#if BYTE_ORDER == BIG_ENDIAN
1109 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
1110 BGE_BIGENDIAN_INIT, 4);
1111#else
1112 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
1113 BGE_LITTLEENDIAN_INIT, 4);
1114#endif
1115
1116 /*
1117 * Check the 'ROM failed' bit on the RX CPU to see if
1118 * self-tests passed.
1119 */
1120 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1121 printf("bge%d: RX CPU self-diagnostics failed!\n",
1122 sc->bge_unit);
1123 return(ENODEV);
1124 }
1125
1126 /* Clear the MAC control register */
1127 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1128
1129 /*
1130 * Clear the MAC statistics block in the NIC's
1131 * internal memory.
1132 */
1133 for (i = BGE_STATS_BLOCK;
1134 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t))
1135 BGE_MEMWIN_WRITE(sc, i, 0);
1136
1137 for (i = BGE_STATUS_BLOCK;
1138 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t))
1139 BGE_MEMWIN_WRITE(sc, i, 0);
1140
1141 /* Set up the PCI DMA control register. */
1142 if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1143 BGE_PCISTATE_PCI_BUSMODE) {
1144 /* Conventional PCI bus */
1145 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1146 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1147 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1148 (0x0F);
1149 } else {
1150 /* PCI-X bus */
1151 /*
1152 * The 5704 uses a different encoding of read/write
1153 * watermarks.
1154 */
1155 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1156 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1157 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1158 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1159 else
1160 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1161 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1162 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1163 (0x0F);
1164
1165 /*
1166 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1167 * for hardware bugs.
1168 */
1169 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1170 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1171 u_int32_t tmp;
1172
1173 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1174 if (tmp == 0x6 || tmp == 0x7)
1175 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1176 }
1177 }
1178
1179 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
7e40b8c5
HP
1180 sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1181 sc->bge_asicrev == BGE_ASICREV_BCM5705)
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1182 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1183 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1184
1185 /*
1186 * Set up general mode register.
1187 */
1188 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|
1189 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1190 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
b4fdf56d 1191 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM);
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1192
1193 /*
1194 * Disable memory write invalidate. Apparently it is not supported
1195 * properly by these devices.
1196 */
1197 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1198
1199#ifdef __brokenalpha__
1200 /*
1201 * Must insure that we do not cross an 8K (bytes) boundary
1202 * for DMA reads. Our highest limit is 1K bytes. This is a
1203 * restriction on some ALPHA platforms with early revision
1204 * 21174 PCI chipsets, such as the AlphaPC 164lx
1205 */
1206 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1207 BGE_PCI_READ_BNDRY_1024BYTES, 4);
1208#endif
1209
1210 /* Set the timer prescaler (always 66Mhz) */
1211 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1212
1213 return(0);
1214}
1215
1216static int
1217bge_blockinit(sc)
1218 struct bge_softc *sc;
1219{
1220 struct bge_rcb *rcb;
1221 volatile struct bge_rcb *vrcb;
1222 int i;
1223
1224 /*
1225 * Initialize the memory window pointer register so that
1226 * we can access the first 32K of internal NIC RAM. This will
1227 * allow us to set up the TX send ring RCBs and the RX return
1228 * ring RCBs, plus other things which live in NIC memory.
1229 */
1230 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1231
7e40b8c5
HP
1232 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1233
1234 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1235 /* Configure mbuf memory pool */
1236 if (sc->bge_extram) {
1237 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1238 BGE_EXT_SSRAM);
1239 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1240 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1241 else
1242 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1243 } else {
1244 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1245 BGE_BUFFPOOL_1);
1246 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1247 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1248 else
1249 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1250 }
984263bc 1251
7e40b8c5
HP
1252 /* Configure DMA resource pool */
1253 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1254 BGE_DMA_DESCRIPTORS);
1255 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1256 }
984263bc
MD
1257
1258 /* Configure mbuf pool watermarks */
7e40b8c5
HP
1259 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
1260 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1261 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1262 } else {
1263 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1264 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1265 }
984263bc
MD
1266 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1267
1268 /* Configure DMA resource watermarks */
1269 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1270 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1271
1272 /* Enable buffer manager */
7e40b8c5
HP
1273 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1274 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1275 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
984263bc 1276
7e40b8c5
HP
1277 /* Poll for buffer manager start indication */
1278 for (i = 0; i < BGE_TIMEOUT; i++) {
1279 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1280 break;
1281 DELAY(10);
1282 }
984263bc 1283
7e40b8c5
HP
1284 if (i == BGE_TIMEOUT) {
1285 printf("bge%d: buffer manager failed to start\n",
1286 sc->bge_unit);
1287 return(ENXIO);
1288 }
984263bc
MD
1289 }
1290
1291 /* Enable flow-through queues */
1292 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1293 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1294
1295 /* Wait until queue initialization is complete */
1296 for (i = 0; i < BGE_TIMEOUT; i++) {
1297 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1298 break;
1299 DELAY(10);
1300 }
1301
1302 if (i == BGE_TIMEOUT) {
1303 printf("bge%d: flow-through queue init failed\n",
1304 sc->bge_unit);
1305 return(ENXIO);
1306 }
1307
1308 /* Initialize the standard RX ring control block */
1309 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
7e40b8c5
HP
1310 BGE_HOSTADDR(rcb->bge_hostaddr,
1311 vtophys(&sc->bge_rdata->bge_rx_std_ring));
1312 if (sc->bge_asicrev == BGE_ASICREV_BCM5705)
1313 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1314 else
1315 rcb->bge_maxlen_flags =
1316 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
984263bc
MD
1317 if (sc->bge_extram)
1318 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
1319 else
1320 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1321 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1322 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1323 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1324 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1325
1326 /*
1327 * Initialize the jumbo RX ring control block
1328 * We set the 'ring disabled' bit in the flags
1329 * field until we're actually ready to start
1330 * using this ring (i.e. once we set the MTU
1331 * high enough to require it).
1332 */
7e40b8c5
HP
1333 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1334 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
1335 BGE_HOSTADDR(rcb->bge_hostaddr,
1336 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring));
1337 rcb->bge_maxlen_flags =
1338 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1339 BGE_RCB_FLAG_RING_DISABLED);
1340 if (sc->bge_extram)
1341 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
1342 else
1343 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1344 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1345 rcb->bge_hostaddr.bge_addr_hi);
1346 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1347 rcb->bge_hostaddr.bge_addr_lo);
1348 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1349 rcb->bge_maxlen_flags);
1350 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1351
1352 /* Set up dummy disabled mini ring RCB */
1353 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
1354 rcb->bge_maxlen_flags =
1355 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1356 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1357 rcb->bge_maxlen_flags);
1358 }
984263bc
MD
1359
1360 /*
1361 * Set the BD ring replentish thresholds. The recommended
1362 * values are 1/8th the number of descriptors allocated to
1363 * each ring.
1364 */
1365 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
1366 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1367
1368 /*
1369 * Disable all unused send rings by setting the 'ring disabled'
1370 * bit in the flags field of all the TX send ring control blocks.
1371 * These are located in NIC memory.
1372 */
1373 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1374 BGE_SEND_RING_RCB);
1375 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1376 vrcb->bge_maxlen_flags =
1377 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1378 vrcb->bge_nicaddr = 0;
1379 vrcb++;
1380 }
1381
1382 /* Configure TX RCB 0 (we use only the first ring) */
1383 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1384 BGE_SEND_RING_RCB);
1385 vrcb->bge_hostaddr.bge_addr_hi = 0;
7e40b8c5 1386 BGE_HOSTADDR(vrcb->bge_hostaddr, vtophys(&sc->bge_rdata->bge_tx_ring));
984263bc 1387 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT);
7e40b8c5
HP
1388 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1389 vrcb->bge_maxlen_flags =
1390 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0);
984263bc
MD
1391
1392 /* Disable all unused RX return rings */
1393 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1394 BGE_RX_RETURN_RING_RCB);
1395 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1396 vrcb->bge_hostaddr.bge_addr_hi = 0;
1397 vrcb->bge_hostaddr.bge_addr_lo = 0;
1398 vrcb->bge_maxlen_flags =
7e40b8c5 1399 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
984263bc
MD
1400 BGE_RCB_FLAG_RING_DISABLED);
1401 vrcb->bge_nicaddr = 0;
1402 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1403 (i * (sizeof(u_int64_t))), 0);
1404 vrcb++;
1405 }
1406
1407 /* Initialize RX ring indexes */
1408 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1409 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1410 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1411
1412 /*
1413 * Set up RX return ring 0
1414 * Note that the NIC address for RX return rings is 0x00000000.
1415 * The return rings live entirely within the host, so the
1416 * nicaddr field in the RCB isn't used.
1417 */
1418 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1419 BGE_RX_RETURN_RING_RCB);
1420 vrcb->bge_hostaddr.bge_addr_hi = 0;
7e40b8c5
HP
1421 BGE_HOSTADDR(vrcb->bge_hostaddr,
1422 vtophys(&sc->bge_rdata->bge_rx_return_ring));
984263bc 1423 vrcb->bge_nicaddr = 0x00000000;
7e40b8c5
HP
1424 vrcb->bge_maxlen_flags =
1425 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0);
984263bc
MD
1426
1427 /* Set random backoff seed for TX */
1428 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1429 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1430 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1431 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1432 BGE_TX_BACKOFF_SEED_MASK);
1433
1434 /* Set inter-packet gap */
1435 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1436
1437 /*
1438 * Specify which ring to use for packets that don't match
1439 * any RX rules.
1440 */
1441 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1442
1443 /*
1444 * Configure number of RX lists. One interrupt distribution
1445 * list, sixteen active lists, one bad frames class.
1446 */
1447 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1448
1449 /* Inialize RX list placement stats mask. */
1450 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1451 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1452
1453 /* Disable host coalescing until we get it set up */
1454 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1455
1456 /* Poll to make sure it's shut down. */
1457 for (i = 0; i < BGE_TIMEOUT; i++) {
1458 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1459 break;
1460 DELAY(10);
1461 }
1462
1463 if (i == BGE_TIMEOUT) {
1464 printf("bge%d: host coalescing engine failed to idle\n",
1465 sc->bge_unit);
1466 return(ENXIO);
1467 }
1468
1469 /* Set up host coalescing defaults */
1470 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1471 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1472 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1473 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
7e40b8c5
HP
1474 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1475 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1476 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1477 }
984263bc
MD
1478 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1479 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
984263bc
MD
1480
1481 /* Set up address of statistics block */
7e40b8c5
HP
1482 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1483 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0);
1484 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1485 vtophys(&sc->bge_rdata->bge_info.bge_stats));
1486
1487 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1488 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1489 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1490 }
984263bc
MD
1491
1492 /* Set up address of status block */
984263bc
MD
1493 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0);
1494 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1495 vtophys(&sc->bge_rdata->bge_status_block));
7e40b8c5 1496
984263bc
MD
1497 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
1498 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
1499
1500 /* Turn on host coalescing state machine */
1501 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1502
1503 /* Turn on RX BD completion state machine and enable attentions */
1504 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1505 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1506
1507 /* Turn on RX list placement state machine */
1508 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1509
1510 /* Turn on RX list selector state machine. */
7e40b8c5
HP
1511 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1512 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
984263bc
MD
1513
1514 /* Turn on DMA, clear stats */
1515 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1516 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1517 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1518 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1519 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1520
1521 /* Set misc. local control, enable interrupts on attentions */
1522 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1523
1524#ifdef notdef
1525 /* Assert GPIO pins for PHY reset */
1526 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1527 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1528 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1529 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1530#endif
1531
1532 /* Turn on DMA completion state machine */
7e40b8c5
HP
1533 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1534 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
984263bc
MD
1535
1536 /* Turn on write DMA state machine */
1537 CSR_WRITE_4(sc, BGE_WDMA_MODE,
1538 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
1539
1540 /* Turn on read DMA state machine */
1541 CSR_WRITE_4(sc, BGE_RDMA_MODE,
1542 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1543
1544 /* Turn on RX data completion state machine */
1545 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1546
1547 /* Turn on RX BD initiator state machine */
1548 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1549
1550 /* Turn on RX data and RX BD initiator state machine */
1551 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1552
1553 /* Turn on Mbuf cluster free state machine */
7e40b8c5
HP
1554 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1555 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
984263bc
MD
1556
1557 /* Turn on send BD completion state machine */
1558 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1559
1560 /* Turn on send data completion state machine */
1561 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1562
1563 /* Turn on send data initiator state machine */
1564 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1565
1566 /* Turn on send BD initiator state machine */
1567 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1568
1569 /* Turn on send BD selector state machine */
1570 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1571
1572 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1573 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1574 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1575
1576 /* ack/clear link change events */
1577 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
7e40b8c5
HP
1578 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1579 BGE_MACSTAT_LINK_CHANGED);
984263bc
MD
1580
1581 /* Enable PHY auto polling (for MII/GMII only) */
1582 if (sc->bge_tbi) {
1583 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1584 } else {
1585 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1586 if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1587 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1588 BGE_EVTENB_MI_INTERRUPT);
1589 }
1590
1591 /* Enable link state change attentions. */
1592 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1593
1594 return(0);
1595}
1596
1597/*
1598 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1599 * against our list and return its name if we find a match. Note
1600 * that since the Broadcom controller contains VPD support, we
1601 * can get the device name string from the controller itself instead
1602 * of the compiled-in string. This is a little slow, but it guarantees
1603 * we'll always announce the right product name.
1604 */
1605static int
1606bge_probe(dev)
1607 device_t dev;
1608{
1609 struct bge_type *t;
1610 struct bge_softc *sc;
1611 char *descbuf;
1612
1613 t = bge_devs;
1614
1615 sc = device_get_softc(dev);
1616 bzero(sc, sizeof(struct bge_softc));
1617 sc->bge_unit = device_get_unit(dev);
1618 sc->bge_dev = dev;
1619
1620 while(t->bge_name != NULL) {
1621 if ((pci_get_vendor(dev) == t->bge_vid) &&
1622 (pci_get_device(dev) == t->bge_did)) {
1623#ifdef notdef
1624 bge_vpd_read(sc);
1625 device_set_desc(dev, sc->bge_vpd_prodname);
1626#endif
c5541aee 1627 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_INTWAIT);
984263bc
MD
1628 snprintf(descbuf, BGE_DEVDESC_MAX,
1629 "%s, ASIC rev. %#04x", t->bge_name,
1630 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
1631 device_set_desc_copy(dev, descbuf);
7fc47c8f 1632 if (pci_get_subvendor(dev) == PCI_VENDOR_DELL)
7e40b8c5 1633 sc->bge_no_3_led = 1;
984263bc
MD
1634 free(descbuf, M_TEMP);
1635 return(0);
1636 }
1637 t++;
1638 }
1639
1640 return(ENXIO);
1641}
1642
1643static int
1644bge_attach(dev)
1645 device_t dev;
1646{
1647 int s;
1648 u_int32_t command;
1649 struct ifnet *ifp;
1650 struct bge_softc *sc;
1651 u_int32_t hwcfg = 0;
1652 u_int32_t mac_addr = 0;
1653 int unit, error = 0, rid;
0a8b5977 1654 uint8_t ether_addr[ETHER_ADDR_LEN];
984263bc
MD
1655
1656 s = splimp();
1657
1658 sc = device_get_softc(dev);
1659 unit = device_get_unit(dev);
1660 sc->bge_dev = dev;
1661 sc->bge_unit = unit;
263489fb 1662 callout_init(&sc->bge_stat_timer);
984263bc
MD
1663
1664 /*
1665 * Map control/status registers.
1666 */
1667 command = pci_read_config(dev, PCIR_COMMAND, 4);
1668 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1669 pci_write_config(dev, PCIR_COMMAND, command, 4);
1670 command = pci_read_config(dev, PCIR_COMMAND, 4);
1671
1672 if (!(command & PCIM_CMD_MEMEN)) {
1673 printf("bge%d: failed to enable memory mapping!\n", unit);
1674 error = ENXIO;
1675 goto fail;
1676 }
1677
1678 rid = BGE_PCI_BAR0;
1679 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1680 0, ~0, 1, RF_ACTIVE);
1681
1682 if (sc->bge_res == NULL) {
1683 printf ("bge%d: couldn't map memory\n", unit);
1684 error = ENXIO;
1685 goto fail;
1686 }
1687
1688 sc->bge_btag = rman_get_bustag(sc->bge_res);
1689 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1690 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res);
1691
1692 /*
1693 * XXX FIXME: rman_get_virtual() on the alpha is currently
1694 * broken and returns a physical address instead of a kernel
1695 * virtual address. Consequently, we need to do a little
1696 * extra mangling of the vhandle on the alpha. This should
1697 * eventually be fixed! The whole idea here is to get rid
1698 * of platform dependencies.
1699 */
1700#ifdef __alpha__
1701 if (pci_cvt_to_bwx(sc->bge_vhandle))
1702 sc->bge_vhandle = pci_cvt_to_bwx(sc->bge_vhandle);
1703 else
1704 sc->bge_vhandle = pci_cvt_to_dense(sc->bge_vhandle);
1705 sc->bge_vhandle = ALPHA_PHYS_TO_K0SEG(sc->bge_vhandle);
1706#endif
1707
1708 /* Allocate interrupt */
1709 rid = 0;
1710
1711 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1712 RF_SHAREABLE | RF_ACTIVE);
1713
1714 if (sc->bge_irq == NULL) {
1715 printf("bge%d: couldn't map interrupt\n", unit);
1716 error = ENXIO;
1717 goto fail;
1718 }
1719
1720 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET,
1721 bge_intr, sc, &sc->bge_intrhand);
1722
1723 if (error) {
1724 bge_release_resources(sc);
1725 printf("bge%d: couldn't set up irq\n", unit);
1726 goto fail;
1727 }
1728
1729 sc->bge_unit = unit;
1730
1731 /* Try to reset the chip. */
1732 bge_reset(sc);
1733
1734 if (bge_chipinit(sc)) {
1735 printf("bge%d: chip initialization failed\n", sc->bge_unit);
1736 bge_release_resources(sc);
1737 error = ENXIO;
1738 goto fail;
1739 }
1740
1741 /*
1742 * Get station address from the EEPROM.
1743 */
1744 mac_addr = bge_readmem_ind(sc, 0x0c14);
1745 if ((mac_addr >> 16) == 0x484b) {
0a8b5977
JS
1746 ether_addr[0] = (uint8_t)(mac_addr >> 8);
1747 ether_addr[1] = (uint8_t)mac_addr;
984263bc 1748 mac_addr = bge_readmem_ind(sc, 0x0c18);
0a8b5977
JS
1749 ether_addr[2] = (uint8_t)(mac_addr >> 24);
1750 ether_addr[3] = (uint8_t)(mac_addr >> 16);
1751 ether_addr[4] = (uint8_t)(mac_addr >> 8);
1752 ether_addr[5] = (uint8_t)mac_addr;
1753 } else if (bge_read_eeprom(sc, ether_addr,
984263bc
MD
1754 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1755 printf("bge%d: failed to read station address\n", unit);
1756 bge_release_resources(sc);
1757 error = ENXIO;
1758 goto fail;
1759 }
1760
984263bc
MD
1761 /* Allocate the general information block and ring buffers. */
1762 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF,
1763 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1764
1765 if (sc->bge_rdata == NULL) {
1766 bge_release_resources(sc);
1767 error = ENXIO;
1768 printf("bge%d: no memory for list buffers!\n", sc->bge_unit);
1769 goto fail;
1770 }
1771
1772 bzero(sc->bge_rdata, sizeof(struct bge_ring_data));
1773
7e40b8c5
HP
1774 /* Save ASIC rev. */
1775
1776 sc->bge_chipid =
1777 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1778 BGE_PCIMISCCTL_ASICREV;
1779 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1780 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1781
1782 /*
1783 * Try to allocate memory for jumbo buffers.
1784 * The 5705 does not appear to support jumbo frames.
1785 */
1786 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1787 if (bge_alloc_jumbo_mem(sc)) {
1788 printf("bge%d: jumbo buffer allocation "
1789 "failed\n", sc->bge_unit);
1790 bge_release_resources(sc);
1791 error = ENXIO;
1792 goto fail;
1793 }
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MD
1794 }
1795
1796 /* Set default tuneable values. */
1797 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1798 sc->bge_rx_coal_ticks = 150;
1799 sc->bge_tx_coal_ticks = 150;
1800 sc->bge_rx_max_coal_bds = 64;
1801 sc->bge_tx_max_coal_bds = 128;
1802
7e40b8c5
HP
1803 /* 5705 limits RX return ring to 512 entries. */
1804 if (sc->bge_asicrev == BGE_ASICREV_BCM5705)
1805 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1806 else
1807 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1808
984263bc
MD
1809 /* Set up ifnet structure */
1810 ifp = &sc->arpcom.ac_if;
1811 ifp->if_softc = sc;
cdb7d804 1812 if_initname(ifp, "bge", sc->bge_unit);
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MD
1813 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1814 ifp->if_ioctl = bge_ioctl;
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MD
1815 ifp->if_start = bge_start;
1816 ifp->if_watchdog = bge_watchdog;
1817 ifp->if_init = bge_init;
1818 ifp->if_mtu = ETHERMTU;
936ff230
JS
1819 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1820 ifq_set_ready(&ifp->if_snd);
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MD
1821 ifp->if_hwassist = BGE_CSUM_FEATURES;
1822 ifp->if_capabilities = IFCAP_HWCSUM;
1823 ifp->if_capenable = ifp->if_capabilities;
1824
984263bc
MD
1825 /*
1826 * Figure out what sort of media we have by checking the
1827 * hardware config word in the first 32k of NIC internal memory,
1828 * or fall back to examining the EEPROM if necessary.
1829 * Note: on some BCM5700 cards, this value appears to be unset.
1830 * If that's the case, we have to rely on identifying the NIC
1831 * by its PCI subsystem ID, as we do below for the SysKonnect
1832 * SK-9D41.
1833 */
1834 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1835 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1836 else {
1837 bge_read_eeprom(sc, (caddr_t)&hwcfg,
1838 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));
1839 hwcfg = ntohl(hwcfg);
1840 }
1841
1842 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1843 sc->bge_tbi = 1;
1844
1845 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
f952ab63
JS
1846 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
1847 PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
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MD
1848 sc->bge_tbi = 1;
1849
1850 if (sc->bge_tbi) {
1851 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1852 bge_ifmedia_upd, bge_ifmedia_sts);
1853 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1854 ifmedia_add(&sc->bge_ifmedia,
1855 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1856 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1857 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1858 } else {
1859 /*
1860 * Do transceiver setup.
1861 */
1862 if (mii_phy_probe(dev, &sc->bge_miibus,
1863 bge_ifmedia_upd, bge_ifmedia_sts)) {
1864 printf("bge%d: MII without any PHY!\n", sc->bge_unit);
1865 bge_release_resources(sc);
1866 bge_free_jumbo_mem(sc);
1867 error = ENXIO;
1868 goto fail;
1869 }
1870 }
1871
1872 /*
1873 * When using the BCM5701 in PCI-X mode, data corruption has
1874 * been observed in the first few bytes of some received packets.
1875 * Aligning the packet buffer in memory eliminates the corruption.
1876 * Unfortunately, this misaligns the packet payloads. On platforms
1877 * which do not support unaligned accesses, we will realign the
1878 * payloads by copying the received packets.
1879 */
1880 switch (sc->bge_chipid) {
1881 case BGE_CHIPID_BCM5701_A0:
1882 case BGE_CHIPID_BCM5701_B0:
1883 case BGE_CHIPID_BCM5701_B2:
1884 case BGE_CHIPID_BCM5701_B5:
1885 /* If in PCI-X mode, work around the alignment bug. */
1886 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
1887 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) ==
1888 BGE_PCISTATE_PCI_BUSSPEED)
1889 sc->bge_rx_alignment_bug = 1;
1890 break;
1891 }
1892
1893 /*
1894 * Call MI attach routine.
1895 */
0a8b5977 1896 ether_ifattach(ifp, ether_addr);
984263bc
MD
1897
1898fail:
1899 splx(s);
1900
1901 return(error);
1902}
1903
1904static int
1905bge_detach(dev)
1906 device_t dev;
1907{
1908 struct bge_softc *sc;
1909 struct ifnet *ifp;
1910 int s;
1911
1912 s = splimp();
1913
1914 sc = device_get_softc(dev);
1915 ifp = &sc->arpcom.ac_if;
1916
0a8b5977 1917 ether_ifdetach(ifp);
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MD
1918 bge_stop(sc);
1919 bge_reset(sc);
1920
1921 if (sc->bge_tbi) {
1922 ifmedia_removeall(&sc->bge_ifmedia);
1923 } else {
1924 bus_generic_detach(dev);
1925 device_delete_child(dev, sc->bge_miibus);
1926 }
1927
1928 bge_release_resources(sc);
7e40b8c5
HP
1929 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1930 bge_free_jumbo_mem(sc);
984263bc
MD
1931
1932 splx(s);
1933
1934 return(0);
1935}
1936
1937static void
1938bge_release_resources(sc)
1939 struct bge_softc *sc;
1940{
1941 device_t dev;
1942
1943 dev = sc->bge_dev;
1944
1945 if (sc->bge_vpd_prodname != NULL)
1946 free(sc->bge_vpd_prodname, M_DEVBUF);
1947
1948 if (sc->bge_vpd_readonly != NULL)
1949 free(sc->bge_vpd_readonly, M_DEVBUF);
1950
1951 if (sc->bge_intrhand != NULL)
1952 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1953
1954 if (sc->bge_irq != NULL)
1955 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
1956
1957 if (sc->bge_res != NULL)
1958 bus_release_resource(dev, SYS_RES_MEMORY,
1959 BGE_PCI_BAR0, sc->bge_res);
1960
1961 if (sc->bge_rdata != NULL)
1962 contigfree(sc->bge_rdata,
1963 sizeof(struct bge_ring_data), M_DEVBUF);
1964
1965 return;
1966}
1967
1968static void
1969bge_reset(sc)
1970 struct bge_softc *sc;
1971{
1972 device_t dev;
1973 u_int32_t cachesize, command, pcistate;
1974 int i, val = 0;
1975
1976 dev = sc->bge_dev;
1977
1978 /* Save some important PCI state. */
1979 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
1980 command = pci_read_config(dev, BGE_PCI_CMD, 4);
1981 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
1982
1983 pci_write_config(dev, BGE_PCI_MISC_CTL,
1984 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1985 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1986
1987 /* Issue global reset */
1988 bge_writereg_ind(sc, BGE_MISC_CFG,
1989 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1));
1990
1991 DELAY(1000);
1992
1993 /* Reset some of the PCI state that got zapped by reset */
1994 pci_write_config(dev, BGE_PCI_MISC_CTL,
1995 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1996 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1997 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
1998 pci_write_config(dev, BGE_PCI_CMD, command, 4);
1999 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
2000
2001 /*
2002 * Prevent PXE restart: write a magic number to the
2003 * general communications memory at 0xB50.
2004 */
2005 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2006 /*
2007 * Poll the value location we just wrote until
2008 * we see the 1's complement of the magic number.
2009 * This indicates that the firmware initialization
2010 * is complete.
2011 */
2012 for (i = 0; i < BGE_TIMEOUT; i++) {
2013 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2014 if (val == ~BGE_MAGIC_NUMBER)
2015 break;
2016 DELAY(10);
2017 }
2018
2019 if (i == BGE_TIMEOUT) {
2020 printf("bge%d: firmware handshake timed out\n", sc->bge_unit);
2021 return;
2022 }
2023
2024 /*
2025 * XXX Wait for the value of the PCISTATE register to
2026 * return to its original pre-reset state. This is a
2027 * fairly good indicator of reset completion. If we don't
2028 * wait for the reset to fully complete, trying to read
2029 * from the device's non-PCI registers may yield garbage
2030 * results.
2031 */
2032 for (i = 0; i < BGE_TIMEOUT; i++) {
2033 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2034 break;
2035 DELAY(10);
2036 }
2037
2038 /* Enable memory arbiter. */
7e40b8c5
HP
2039 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2040 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
984263bc
MD
2041
2042 /* Fix up byte swapping */
2043 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME|
2044 BGE_MODECTL_BYTESWAP_DATA);
2045
2046 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2047
2048 DELAY(10000);
2049
2050 return;
2051}
2052
2053/*
2054 * Frame reception handling. This is called if there's a frame
2055 * on the receive return list.
2056 *
2057 * Note: we have to be able to handle two possibilities here:
2058 * 1) the frame is from the jumbo recieve ring
2059 * 2) the frame is from the standard receive ring
2060 */
2061
2062static void
2063bge_rxeof(sc)
2064 struct bge_softc *sc;
2065{
2066 struct ifnet *ifp;
2067 int stdcnt = 0, jumbocnt = 0;
2068
2069 ifp = &sc->arpcom.ac_if;
2070
2071 while(sc->bge_rx_saved_considx !=
2072 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) {
2073 struct bge_rx_bd *cur_rx;
2074 u_int32_t rxidx;
984263bc
MD
2075 struct mbuf *m = NULL;
2076 u_int16_t vlan_tag = 0;
2077 int have_tag = 0;
2078
2079 cur_rx =
2080 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx];
2081
2082 rxidx = cur_rx->bge_idx;
7e40b8c5 2083 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
984263bc
MD
2084
2085 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2086 have_tag = 1;
2087 vlan_tag = cur_rx->bge_vlan_tag;
2088 }
2089
2090 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2091 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2092 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
2093 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
2094 jumbocnt++;
2095 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2096 ifp->if_ierrors++;
2097 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2098 continue;
2099 }
2100 if (bge_newbuf_jumbo(sc,
2101 sc->bge_jumbo, NULL) == ENOBUFS) {
2102 ifp->if_ierrors++;
2103 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2104 continue;
2105 }
2106 } else {
2107 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2108 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2109 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2110 stdcnt++;
2111 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2112 ifp->if_ierrors++;
2113 bge_newbuf_std(sc, sc->bge_std, m);
2114 continue;
2115 }
2116 if (bge_newbuf_std(sc, sc->bge_std,
2117 NULL) == ENOBUFS) {
2118 ifp->if_ierrors++;
2119 bge_newbuf_std(sc, sc->bge_std, m);
2120 continue;
2121 }
2122 }
2123
2124 ifp->if_ipackets++;
2125#ifndef __i386__
2126 /*
2127 * The i386 allows unaligned accesses, but for other
2128 * platforms we must make sure the payload is aligned.
2129 */
2130 if (sc->bge_rx_alignment_bug) {
2131 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2132 cur_rx->bge_len);
2133 m->m_data += ETHER_ALIGN;
2134 }
2135#endif
160185fa 2136 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
984263bc
MD
2137 m->m_pkthdr.rcvif = ifp;
2138
984263bc
MD
2139#if 0 /* currently broken for some packets, possibly related to TCP options */
2140 if (ifp->if_hwassist) {
2141 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2142 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2143 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2144 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2145 m->m_pkthdr.csum_data =
2146 cur_rx->bge_tcp_udp_csum;
2147 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
2148 }
2149 }
2150#endif
2151
2152 /*
2153 * If we received a packet with a vlan tag, pass it
2154 * to vlan_input() instead of ether_input().
2155 */
2156 if (have_tag) {
3013ac0e 2157 VLAN_INPUT_TAG(m, vlan_tag);
984263bc
MD
2158 have_tag = vlan_tag = 0;
2159 continue;
2160 }
2161
3013ac0e 2162 (*ifp->if_input)(ifp, m);
984263bc
MD
2163 }
2164
2165 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2166 if (stdcnt)
2167 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2168 if (jumbocnt)
2169 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2170
2171 return;
2172}
2173
2174static void
2175bge_txeof(sc)
2176 struct bge_softc *sc;
2177{
2178 struct bge_tx_bd *cur_tx = NULL;
2179 struct ifnet *ifp;
2180
2181 ifp = &sc->arpcom.ac_if;
2182
2183 /*
2184 * Go through our tx ring and free mbufs for those
2185 * frames that have been sent.
2186 */
2187 while (sc->bge_tx_saved_considx !=
2188 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) {
2189 u_int32_t idx = 0;
2190
2191 idx = sc->bge_tx_saved_considx;
2192 cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
2193 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2194 ifp->if_opackets++;
2195 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2196 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2197 sc->bge_cdata.bge_tx_chain[idx] = NULL;
2198 }
2199 sc->bge_txcnt--;
2200 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2201 ifp->if_timer = 0;
2202 }
2203
2204 if (cur_tx != NULL)
2205 ifp->if_flags &= ~IFF_OACTIVE;
2206
2207 return;
2208}
2209
2210static void
2211bge_intr(xsc)
2212 void *xsc;
2213{
2214 struct bge_softc *sc;
2215 struct ifnet *ifp;
085ed1a0 2216 u_int32_t status;
984263bc
MD
2217
2218 sc = xsc;
2219 ifp = &sc->arpcom.ac_if;
2220
2221#ifdef notdef
2222 /* Avoid this for now -- checking this register is expensive. */
2223 /* Make sure this is really our interrupt. */
2224 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))
2225 return;
2226#endif
2227 /* Ack interrupt and stop others from occuring. */
2228 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2229
2230 /*
2231 * Process link state changes.
2232 * Grrr. The link status word in the status block does
2233 * not work correctly on the BCM5700 rev AX and BX chips,
f952ab63 2234 * according to all available information. Hence, we have
984263bc 2235 * to enable MII interrupts in order to properly obtain
f952ab63 2236 * async link changes. Unfortunately, this also means that
984263bc
MD
2237 * we have to read the MAC status register to detect link
2238 * changes, thereby adding an additional register access to
2239 * the interrupt handler.
2240 */
2241
2242 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) {
984263bc
MD
2243 status = CSR_READ_4(sc, BGE_MAC_STS);
2244 if (status & BGE_MACSTAT_MI_INTERRUPT) {
2245 sc->bge_link = 0;
263489fb 2246 callout_stop(&sc->bge_stat_timer);
984263bc
MD
2247 bge_tick(sc);
2248 /* Clear the interrupt */
2249 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2250 BGE_EVTENB_MI_INTERRUPT);
2251 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
2252 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
2253 BRGPHY_INTRS);
2254 }
2255 } else {
2256 if ((sc->bge_rdata->bge_status_block.bge_status &
2257 BGE_STATFLAG_UPDATED) &&
2258 (sc->bge_rdata->bge_status_block.bge_status &
2259 BGE_STATFLAG_LINKSTATE_CHANGED)) {
7e40b8c5
HP
2260 sc->bge_rdata->bge_status_block.bge_status &=
2261 ~(BGE_STATFLAG_UPDATED|
2262 BGE_STATFLAG_LINKSTATE_CHANGED);
085ed1a0 2263 /*
f952ab63 2264 * Sometimes PCS encoding errors are detected in
085ed1a0
DR
2265 * TBI mode (on fiber NICs), and for some reason
2266 * the chip will signal them as link changes.
2267 * If we get a link change event, but the 'PCS
2268 * encoding error' bit in the MAC status register
2269 * is set, don't bother doing a link check.
2270 * This avoids spurious "gigabit link up" messages
f952ab63 2271 * that sometimes appear on fiber NICs during
085ed1a0
DR
2272 * periods of heavy traffic. (There should be no
2273 * effect on copper NICs.)
2274 */
2275 status = CSR_READ_4(sc, BGE_MAC_STS);
7e40b8c5
HP
2276 if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR|
2277 BGE_MACSTAT_MI_COMPLETE))) {
085ed1a0 2278 sc->bge_link = 0;
263489fb 2279 callout_stop(&sc->bge_stat_timer);
085ed1a0
DR
2280 bge_tick(sc);
2281 }
984263bc 2282 sc->bge_link = 0;
263489fb 2283 callout_stop(&sc->bge_stat_timer);
984263bc
MD
2284 bge_tick(sc);
2285 /* Clear the interrupt */
2286 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
7e40b8c5
HP
2287 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
2288 BGE_MACSTAT_LINK_CHANGED);
984263bc
MD
2289
2290 /* Force flush the status block cached by PCI bridge */
2291 CSR_READ_4(sc, BGE_MBX_IRQ0_LO);
2292 }
2293 }
2294
2295 if (ifp->if_flags & IFF_RUNNING) {
2296 /* Check RX return ring producer/consumer */
2297 bge_rxeof(sc);
2298
2299 /* Check TX ring producer/consumer */
2300 bge_txeof(sc);
2301 }
2302
2303 bge_handle_events(sc);
2304
2305 /* Re-enable interrupts. */
2306 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2307
936ff230 2308 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
984263bc
MD
2309 bge_start(ifp);
2310
2311 return;
2312}
2313
2314static void
2315bge_tick(xsc)
2316 void *xsc;
2317{
2318 struct bge_softc *sc;
2319 struct mii_data *mii = NULL;
2320 struct ifmedia *ifm = NULL;
2321 struct ifnet *ifp;
2322 int s;
2323
2324 sc = xsc;
2325 ifp = &sc->arpcom.ac_if;
2326
2327 s = splimp();
2328
7e40b8c5
HP
2329 if (sc->bge_asicrev == BGE_ASICREV_BCM5705)
2330 bge_stats_update_regs(sc);
2331 else
2332 bge_stats_update(sc);
263489fb 2333 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
984263bc
MD
2334 if (sc->bge_link) {
2335 splx(s);
2336 return;
2337 }
2338
2339 if (sc->bge_tbi) {
2340 ifm = &sc->bge_ifmedia;
2341 if (CSR_READ_4(sc, BGE_MAC_STS) &
2342 BGE_MACSTAT_TBI_PCS_SYNCHED) {
2343 sc->bge_link++;
2344 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
2345 printf("bge%d: gigabit link up\n", sc->bge_unit);
936ff230 2346 if (!ifq_is_empty(&ifp->if_snd))
984263bc
MD
2347 bge_start(ifp);
2348 }
2349 splx(s);
2350 return;
2351 }
2352
2353 mii = device_get_softc(sc->bge_miibus);
2354 mii_tick(mii);
2355
2356 if (!sc->bge_link) {
2357 mii_pollstat(mii);
2358 if (mii->mii_media_status & IFM_ACTIVE &&
2359 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2360 sc->bge_link++;
7f259627 2361 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
984263bc
MD
2362 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
2363 printf("bge%d: gigabit link up\n",
2364 sc->bge_unit);
936ff230 2365 if (!ifq_is_empty(&ifp->if_snd))
984263bc
MD
2366 bge_start(ifp);
2367 }
2368 }
2369
2370 splx(s);
2371
2372 return;
2373}
2374
7e40b8c5
HP
2375static void
2376bge_stats_update_regs(sc)
2377 struct bge_softc *sc;
2378{
2379 struct ifnet *ifp;
2380 struct bge_mac_stats_regs stats;
2381 u_int32_t *s;
2382 int i;
2383
2384 ifp = &sc->arpcom.ac_if;
2385
2386 s = (u_int32_t *)&stats;
2387 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2388 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2389 s++;
2390 }
2391
2392 ifp->if_collisions +=
2393 (stats.dot3StatsSingleCollisionFrames +
2394 stats.dot3StatsMultipleCollisionFrames +
2395 stats.dot3StatsExcessiveCollisions +
2396 stats.dot3StatsLateCollisions) -
2397 ifp->if_collisions;
2398
2399 return;
2400}
2401
984263bc
MD
2402static void
2403bge_stats_update(sc)
2404 struct bge_softc *sc;
2405{
2406 struct ifnet *ifp;
2407 struct bge_stats *stats;
2408
2409 ifp = &sc->arpcom.ac_if;
2410
2411 stats = (struct bge_stats *)(sc->bge_vhandle +
2412 BGE_MEMWIN_START + BGE_STATS_BLOCK);
2413
2414 ifp->if_collisions +=
7e40b8c5
HP
2415 (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo +
2416 stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo +
2417 stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo +
2418 stats->txstats.dot3StatsLateCollisions.bge_addr_lo) -
984263bc
MD
2419 ifp->if_collisions;
2420
2421#ifdef notdef
2422 ifp->if_collisions +=
2423 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2424 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2425 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2426 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2427 ifp->if_collisions;
2428#endif
2429
2430 return;
2431}
2432
2433/*
2434 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2435 * pointers to descriptors.
2436 */
2437static int
2438bge_encap(sc, m_head, txidx)
2439 struct bge_softc *sc;
2440 struct mbuf *m_head;
2441 u_int32_t *txidx;
2442{
2443 struct bge_tx_bd *f = NULL;
2444 struct mbuf *m;
2445 u_int32_t frag, cur, cnt = 0;
2446 u_int16_t csum_flags = 0;
2447 struct ifvlan *ifv = NULL;
2448
2449 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2450 m_head->m_pkthdr.rcvif != NULL &&
2451 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2452 ifv = m_head->m_pkthdr.rcvif->if_softc;
2453
2454 m = m_head;
2455 cur = frag = *txidx;
2456
2457 if (m_head->m_pkthdr.csum_flags) {
2458 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2459 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2460 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2461 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2462 if (m_head->m_flags & M_LASTFRAG)
2463 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2464 else if (m_head->m_flags & M_FRAG)
2465 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2466 }
2467 /*
2468 * Start packing the mbufs in this chain into
2469 * the fragment pointers. Stop when we run out
2470 * of fragments or hit the end of the mbuf chain.
2471 */
2472 for (m = m_head; m != NULL; m = m->m_next) {
2473 if (m->m_len != 0) {
2474 f = &sc->bge_rdata->bge_tx_ring[frag];
2475 if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
2476 break;
7e40b8c5
HP
2477 BGE_HOSTADDR(f->bge_addr,
2478 vtophys(mtod(m, vm_offset_t)));
984263bc
MD
2479 f->bge_len = m->m_len;
2480 f->bge_flags = csum_flags;
2481 if (ifv != NULL) {
2482 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2483 f->bge_vlan_tag = ifv->ifv_tag;
2484 } else {
2485 f->bge_vlan_tag = 0;
2486 }
2487 /*
2488 * Sanity check: avoid coming within 16 descriptors
2489 * of the end of the ring.
2490 */
2491 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16)
2492 return(ENOBUFS);
2493 cur = frag;
2494 BGE_INC(frag, BGE_TX_RING_CNT);
2495 cnt++;
2496 }
2497 }
2498
2499 if (m != NULL)
2500 return(ENOBUFS);
2501
2502 if (frag == sc->bge_tx_saved_considx)
2503 return(ENOBUFS);
2504
2505 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
2506 sc->bge_cdata.bge_tx_chain[cur] = m_head;
2507 sc->bge_txcnt += cnt;
2508
2509 *txidx = frag;
2510
2511 return(0);
2512}
2513
2514/*
2515 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2516 * to the mbuf data regions directly in the transmit descriptors.
2517 */
2518static void
2519bge_start(ifp)
2520 struct ifnet *ifp;
2521{
2522 struct bge_softc *sc;
2523 struct mbuf *m_head = NULL;
2524 u_int32_t prodidx = 0;
2525
2526 sc = ifp->if_softc;
2527
936ff230 2528 if (!sc->bge_link)
984263bc
MD
2529 return;
2530
2531 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO);
2532
2533 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
936ff230 2534 m_head = ifq_poll(&ifp->if_snd);
984263bc
MD
2535 if (m_head == NULL)
2536 break;
2537
2538 /*
2539 * XXX
2540 * safety overkill. If this is a fragmented packet chain
2541 * with delayed TCP/UDP checksums, then only encapsulate
2542 * it if we have enough descriptors to handle the entire
2543 * chain at once.
2544 * (paranoia -- may not actually be needed)
2545 */
2546 if (m_head->m_flags & M_FIRSTFRAG &&
2547 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2548 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2549 m_head->m_pkthdr.csum_data + 16) {
984263bc
MD
2550 ifp->if_flags |= IFF_OACTIVE;
2551 break;
2552 }
2553 }
2554
2555 /*
2556 * Pack the data into the transmit ring. If we
2557 * don't have room, set the OACTIVE flag and wait
2558 * for the NIC to drain the ring.
2559 */
2560 if (bge_encap(sc, m_head, &prodidx)) {
984263bc
MD
2561 ifp->if_flags |= IFF_OACTIVE;
2562 break;
2563 }
936ff230 2564 m_head = ifq_dequeue(&ifp->if_snd);
984263bc 2565
7600679e 2566 BPF_MTAP(ifp, m_head);
984263bc
MD
2567 }
2568
2569 /* Transmit */
2570 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2571 /* 5700 b2 errata */
2572 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2573 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2574
2575 /*
2576 * Set a timeout in case the chip goes out to lunch.
2577 */
2578 ifp->if_timer = 5;
2579
2580 return;
2581}
2582
2583static void
2584bge_init(xsc)
2585 void *xsc;
2586{
2587 struct bge_softc *sc = xsc;
2588 struct ifnet *ifp;
2589 u_int16_t *m;
2590 int s;
2591
2592 s = splimp();
2593
2594 ifp = &sc->arpcom.ac_if;
2595
2596 if (ifp->if_flags & IFF_RUNNING) {
2597 splx(s);
2598 return;
2599 }
2600
2601 /* Cancel pending I/O and flush buffers. */
2602 bge_stop(sc);
2603 bge_reset(sc);
2604 bge_chipinit(sc);
2605
2606 /*
2607 * Init the various state machines, ring
2608 * control blocks and firmware.
2609 */
2610 if (bge_blockinit(sc)) {
2611 printf("bge%d: initialization failure\n", sc->bge_unit);
2612 splx(s);
2613 return;
2614 }
2615
2616 ifp = &sc->arpcom.ac_if;
2617
2618 /* Specify MTU. */
2619 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2620 ETHER_HDR_LEN + ETHER_CRC_LEN);
2621
2622 /* Load our MAC address. */
2623 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
2624 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2625 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2626
2627 /* Enable or disable promiscuous mode as needed. */
2628 if (ifp->if_flags & IFF_PROMISC) {
2629 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2630 } else {
2631 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2632 }
2633
2634 /* Program multicast filter. */
2635 bge_setmulti(sc);
2636
2637 /* Init RX ring. */
2638 bge_init_rx_ring_std(sc);
2639
7e40b8c5
HP
2640 /*
2641 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2642 * memory to insure that the chip has in fact read the first
2643 * entry of the ring.
2644 */
2645 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2646 u_int32_t v, i;
2647 for (i = 0; i < 10; i++) {
2648 DELAY(20);
2649 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2650 if (v == (MCLBYTES - ETHER_ALIGN))
2651 break;
2652 }
2653 if (i == 10)
2654 printf ("bge%d: 5705 A0 chip failed to load RX ring\n",
2655 sc->bge_unit);
2656 }
2657
984263bc
MD
2658 /* Init jumbo RX ring. */
2659 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2660 bge_init_rx_ring_jumbo(sc);
2661
2662 /* Init our RX return ring index */
2663 sc->bge_rx_saved_considx = 0;
2664
2665 /* Init TX ring. */
2666 bge_init_tx_ring(sc);
2667
2668 /* Turn on transmitter */
2669 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2670
2671 /* Turn on receiver */
2672 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2673
2674 /* Tell firmware we're alive. */
2675 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2676
2677 /* Enable host interrupts. */
2678 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2679 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2680 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2681
2682 bge_ifmedia_upd(ifp);
2683
2684 ifp->if_flags |= IFF_RUNNING;
2685 ifp->if_flags &= ~IFF_OACTIVE;
2686
2687 splx(s);
2688
263489fb 2689 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
984263bc
MD
2690}
2691
2692/*
2693 * Set media options.
2694 */
2695static int
2696bge_ifmedia_upd(ifp)
2697 struct ifnet *ifp;
2698{
2699 struct bge_softc *sc;
2700 struct mii_data *mii;
2701 struct ifmedia *ifm;
2702
2703 sc = ifp->if_softc;
2704 ifm = &sc->bge_ifmedia;
2705
2706 /* If this is a 1000baseX NIC, enable the TBI port. */
2707 if (sc->bge_tbi) {
2708 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2709 return(EINVAL);
2710 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2711 case IFM_AUTO:
2712 break;
2713 case IFM_1000_SX:
2714 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2715 BGE_CLRBIT(sc, BGE_MAC_MODE,
2716 BGE_MACMODE_HALF_DUPLEX);
2717 } else {
2718 BGE_SETBIT(sc, BGE_MAC_MODE,
2719 BGE_MACMODE_HALF_DUPLEX);
2720 }
2721 break;
2722 default:
2723 return(EINVAL);
2724 }
2725 return(0);
2726 }
2727
2728 mii = device_get_softc(sc->bge_miibus);
2729 sc->bge_link = 0;
2730 if (mii->mii_instance) {
2731 struct mii_softc *miisc;
2732 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
2733 miisc = LIST_NEXT(miisc, mii_list))
2734 mii_phy_reset(miisc);
2735 }
2736 mii_mediachg(mii);
2737
2738 return(0);
2739}
2740
2741/*
2742 * Report current media status.
2743 */
2744static void
2745bge_ifmedia_sts(ifp, ifmr)
2746 struct ifnet *ifp;
2747 struct ifmediareq *ifmr;
2748{
2749 struct bge_softc *sc;
2750 struct mii_data *mii;
2751
2752 sc = ifp->if_softc;
2753
2754 if (sc->bge_tbi) {
2755 ifmr->ifm_status = IFM_AVALID;
2756 ifmr->ifm_active = IFM_ETHER;
2757 if (CSR_READ_4(sc, BGE_MAC_STS) &
2758 BGE_MACSTAT_TBI_PCS_SYNCHED)
2759 ifmr->ifm_status |= IFM_ACTIVE;
2760 ifmr->ifm_active |= IFM_1000_SX;
2761 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
2762 ifmr->ifm_active |= IFM_HDX;
2763 else
2764 ifmr->ifm_active |= IFM_FDX;
2765 return;
2766 }
2767
2768 mii = device_get_softc(sc->bge_miibus);
2769 mii_pollstat(mii);
2770 ifmr->ifm_active = mii->mii_media_active;
2771 ifmr->ifm_status = mii->mii_media_status;
2772
2773 return;
2774}
2775
2776static int
bd4539cc 2777bge_ioctl(ifp, command, data, cr)
984263bc
MD
2778 struct ifnet *ifp;
2779 u_long command;
2780 caddr_t data;
bd4539cc 2781 struct ucred *cr;
984263bc
MD
2782{
2783 struct bge_softc *sc = ifp->if_softc;
2784 struct ifreq *ifr = (struct ifreq *) data;
2785 int s, mask, error = 0;
2786 struct mii_data *mii;
2787
2788 s = splimp();
2789
2790 switch(command) {
2791 case SIOCSIFADDR:
2792 case SIOCGIFADDR:
2793 error = ether_ioctl(ifp, command, data);
2794 break;
2795 case SIOCSIFMTU:
7e40b8c5
HP
2796 /* Disallow jumbo frames on 5705. */
2797 if ((sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2798 ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU)
984263bc
MD
2799 error = EINVAL;
2800 else {
2801 ifp->if_mtu = ifr->ifr_mtu;
2802 ifp->if_flags &= ~IFF_RUNNING;
2803 bge_init(sc);
2804 }
2805 break;
2806 case SIOCSIFFLAGS:
2807 if (ifp->if_flags & IFF_UP) {
2808 /*
2809 * If only the state of the PROMISC flag changed,
2810 * then just use the 'set promisc mode' command
2811 * instead of reinitializing the entire NIC. Doing
2812 * a full re-init means reloading the firmware and
2813 * waiting for it to start up, which may take a
2814 * second or two.
2815 */
2816 if (ifp->if_flags & IFF_RUNNING &&
2817 ifp->if_flags & IFF_PROMISC &&
2818 !(sc->bge_if_flags & IFF_PROMISC)) {
2819 BGE_SETBIT(sc, BGE_RX_MODE,
2820 BGE_RXMODE_RX_PROMISC);
2821 } else if (ifp->if_flags & IFF_RUNNING &&
2822 !(ifp->if_flags & IFF_PROMISC) &&
2823 sc->bge_if_flags & IFF_PROMISC) {
2824 BGE_CLRBIT(sc, BGE_RX_MODE,
2825 BGE_RXMODE_RX_PROMISC);
2826 } else
2827 bge_init(sc);
2828 } else {
2829 if (ifp->if_flags & IFF_RUNNING) {
2830 bge_stop(sc);
2831 }
2832 }
2833 sc->bge_if_flags = ifp->if_flags;
2834 error = 0;
2835 break;
2836 case SIOCADDMULTI:
2837 case SIOCDELMULTI:
2838 if (ifp->if_flags & IFF_RUNNING) {
2839 bge_setmulti(sc);
2840 error = 0;
2841 }
2842 break;
2843 case SIOCSIFMEDIA:
2844 case SIOCGIFMEDIA:
2845 if (sc->bge_tbi) {
2846 error = ifmedia_ioctl(ifp, ifr,
2847 &sc->bge_ifmedia, command);
2848 } else {
2849 mii = device_get_softc(sc->bge_miibus);
2850 error = ifmedia_ioctl(ifp, ifr,
2851 &mii->mii_media, command);
2852 }
2853 break;
2854 case SIOCSIFCAP:
2855 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2856 if (mask & IFCAP_HWCSUM) {
2857 if (IFCAP_HWCSUM & ifp->if_capenable)
2858 ifp->if_capenable &= ~IFCAP_HWCSUM;
2859 else
2860 ifp->if_capenable |= IFCAP_HWCSUM;
2861 }
2862 error = 0;
2863 break;
2864 default:
2865 error = EINVAL;
2866 break;
2867 }
2868
2869 (void)splx(s);
2870
2871 return(error);
2872}
2873
2874static void
2875bge_watchdog(ifp)
2876 struct ifnet *ifp;
2877{
2878 struct bge_softc *sc;
2879
2880 sc = ifp->if_softc;
2881
2882 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit);
2883
2884 ifp->if_flags &= ~IFF_RUNNING;
2885 bge_init(sc);
2886
2887 ifp->if_oerrors++;
2888
2889 return;
2890}
2891
2892/*
2893 * Stop the adapter and free any mbufs allocated to the
2894 * RX and TX lists.
2895 */
2896static void
2897bge_stop(sc)
2898 struct bge_softc *sc;
2899{
2900 struct ifnet *ifp;
2901 struct ifmedia_entry *ifm;
2902 struct mii_data *mii = NULL;
2903 int mtmp, itmp;
2904
2905 ifp = &sc->arpcom.ac_if;
2906
2907 if (!sc->bge_tbi)
2908 mii = device_get_softc(sc->bge_miibus);
2909
263489fb 2910 callout_stop(&sc->bge_stat_timer);
984263bc
MD
2911
2912 /*
2913 * Disable all of the receiver blocks
2914 */
2915 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2916 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2917 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
7e40b8c5
HP
2918 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2919 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
984263bc
MD
2920 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
2921 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2922 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
2923
2924 /*
2925 * Disable all of the transmit blocks
2926 */
2927 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2928 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2929 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2930 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
2931 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
7e40b8c5
HP
2932 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2933 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
984263bc
MD
2934 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2935
2936 /*
2937 * Shut down all of the memory managers and related
2938 * state machines.
2939 */
2940 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
2941 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
7e40b8c5
HP
2942 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2943 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
984263bc
MD
2944 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2945 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
7e40b8c5
HP
2946 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
2947 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
2948 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2949 }
984263bc
MD
2950
2951 /* Disable host interrupts. */
2952 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2953 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2954
2955 /*
2956 * Tell firmware we're shutting down.
2957 */
2958 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2959
2960 /* Free the RX lists. */
2961 bge_free_rx_ring_std(sc);
2962
2963 /* Free jumbo RX list. */
7e40b8c5
HP
2964 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2965 bge_free_rx_ring_jumbo(sc);
984263bc
MD
2966
2967 /* Free TX buffers. */
2968 bge_free_tx_ring(sc);
2969
2970 /*
2971 * Isolate/power down the PHY, but leave the media selection
2972 * unchanged so that things will be put back to normal when
2973 * we bring the interface back up.
2974 */
2975 if (!sc->bge_tbi) {
2976 itmp = ifp->if_flags;
2977 ifp->if_flags |= IFF_UP;
2978 ifm = mii->mii_media.ifm_cur;
2979 mtmp = ifm->ifm_media;
2980 ifm->ifm_media = IFM_ETHER|IFM_NONE;
2981 mii_mediachg(mii);
2982 ifm->ifm_media = mtmp;
2983 ifp->if_flags = itmp;
2984 }
2985
2986 sc->bge_link = 0;
2987
2988 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
2989
2990 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2991
2992 return;
2993}
2994
2995/*
2996 * Stop all chip I/O so that the kernel's probe routines don't
2997 * get confused by errant DMAs when rebooting.
2998 */
2999static void
3000bge_shutdown(dev)
3001 device_t dev;
3002{
3003 struct bge_softc *sc;
3004
3005 sc = device_get_softc(dev);
3006
3007 bge_stop(sc);
3008 bge_reset(sc);
3009
3010 return;
3011}