drm/ttm: convert to unified vma offset manager
[dragonfly.git] / sys / dev / drm / radeon / radeon_ttm.c
CommitLineData
926deccb
FT
1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 *
32 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_ttm.c 254885 2013-08-25 19:37:15Z dumbbell $
33 */
34
216f7a2c
FT
35#include <drm/ttm/ttm_bo_api.h>
36#include <drm/ttm/ttm_bo_driver.h>
37#include <drm/ttm/ttm_placement.h>
38#include <drm/ttm/ttm_module.h>
39#include <drm/ttm/ttm_page_alloc.h>
926deccb 40#include <drm/drmP.h>
83b4b9b9 41#include <drm/radeon_drm.h>
c4ef309b 42#include <linux/seq_file.h>
43#include <linux/slab.h>
926deccb
FT
44#include "radeon_reg.h"
45#include "radeon.h"
46
47#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
48
49static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
c6f73aab 50static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
926deccb
FT
51
52static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
53{
54 struct radeon_mman *mman;
55 struct radeon_device *rdev;
56
57 mman = container_of(bdev, struct radeon_mman, bdev);
58 rdev = container_of(mman, struct radeon_device, mman);
59 return rdev;
60}
61
62
63/*
64 * Global memory.
65 */
66static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
67{
68 return ttm_mem_global_init(ref->object);
69}
70
71static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
72{
73 ttm_mem_global_release(ref->object);
74}
75
76static int radeon_ttm_global_init(struct radeon_device *rdev)
77{
78 struct drm_global_reference *global_ref;
79 int r;
80
81 rdev->mman.mem_global_referenced = false;
82 global_ref = &rdev->mman.mem_global_ref;
83 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
84 global_ref->size = sizeof(struct ttm_mem_global);
85 global_ref->init = &radeon_ttm_mem_global_init;
86 global_ref->release = &radeon_ttm_mem_global_release;
87 r = drm_global_item_ref(global_ref);
88 if (r != 0) {
89 DRM_ERROR("Failed setting up TTM memory accounting "
90 "subsystem.\n");
91 return r;
92 }
93
94 rdev->mman.bo_global_ref.mem_glob =
95 rdev->mman.mem_global_ref.object;
96 global_ref = &rdev->mman.bo_global_ref.ref;
97 global_ref->global_type = DRM_GLOBAL_TTM_BO;
98 global_ref->size = sizeof(struct ttm_bo_global);
99 global_ref->init = &ttm_bo_global_init;
100 global_ref->release = &ttm_bo_global_release;
101 r = drm_global_item_ref(global_ref);
102 if (r != 0) {
103 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
104 drm_global_item_unref(&rdev->mman.mem_global_ref);
105 return r;
106 }
107
108 rdev->mman.mem_global_referenced = true;
109 return 0;
110}
111
112static void radeon_ttm_global_fini(struct radeon_device *rdev)
113{
114 if (rdev->mman.mem_global_referenced) {
115 drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
116 drm_global_item_unref(&rdev->mman.mem_global_ref);
117 rdev->mman.mem_global_referenced = false;
118 }
119}
120
121static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
122{
123 return 0;
124}
125
126static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
127 struct ttm_mem_type_manager *man)
128{
129 struct radeon_device *rdev;
130
131 rdev = radeon_get_rdev(bdev);
132
133 switch (type) {
134 case TTM_PL_SYSTEM:
135 /* System memory */
136 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
137 man->available_caching = TTM_PL_MASK_CACHING;
138 man->default_caching = TTM_PL_FLAG_CACHED;
139 break;
140 case TTM_PL_TT:
141 man->func = &ttm_bo_manager_func;
142 man->gpu_offset = rdev->mc.gtt_start;
143 man->available_caching = TTM_PL_MASK_CACHING;
144 man->default_caching = TTM_PL_FLAG_CACHED;
145 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
146#if __OS_HAS_AGP
147 if (rdev->flags & RADEON_IS_AGP) {
53e4e524 148 if (!rdev->ddev->agp) {
926deccb
FT
149 DRM_ERROR("AGP is not enabled for memory type %u\n",
150 (unsigned)type);
151 return -EINVAL;
152 }
153 if (!rdev->ddev->agp->cant_use_aperture)
154 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
155 man->available_caching = TTM_PL_FLAG_UNCACHED |
156 TTM_PL_FLAG_WC;
157 man->default_caching = TTM_PL_FLAG_WC;
158 }
159#endif
160 break;
161 case TTM_PL_VRAM:
162 /* "On-card" video ram */
163 man->func = &ttm_bo_manager_func;
164 man->gpu_offset = rdev->mc.vram_start;
165 man->flags = TTM_MEMTYPE_FLAG_FIXED |
166 TTM_MEMTYPE_FLAG_MAPPABLE;
167 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
168 man->default_caching = TTM_PL_FLAG_WC;
169 break;
170 default:
171 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
172 return -EINVAL;
173 }
174 return 0;
175}
176
177static void radeon_evict_flags(struct ttm_buffer_object *bo,
178 struct ttm_placement *placement)
179{
591d5043
FT
180 static struct ttm_place placements = {
181 .fpfn = 0,
182 .lpfn = 0,
183 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
184 };
185
926deccb 186 struct radeon_bo *rbo;
926deccb
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187
188 if (!radeon_ttm_bo_is_radeon_bo(bo)) {
926deccb
FT
189 placement->placement = &placements;
190 placement->busy_placement = &placements;
191 placement->num_placement = 1;
192 placement->num_busy_placement = 1;
193 return;
194 }
195 rbo = container_of(bo, struct radeon_bo, tbo);
196 switch (bo->mem.mem_type) {
197 case TTM_PL_VRAM:
ee479021 198 if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false)
926deccb 199 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
ee479021 200 else
926deccb
FT
201 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
202 break;
203 case TTM_PL_TT:
204 default:
205 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
206 }
207 *placement = rbo->placement;
208}
209
a34b4168 210static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *fp)
926deccb 211{
a34b4168
MD
212#if 0
213 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
214#endif
215
926deccb 216 return 0;
a34b4168
MD
217
218#if 0
219 /* XXX needs radeon_gem_userptr_ioctl() and related infrastructure */
220 if (radeon_ttm_tt_has_userptr(bo->ttm))
221 return -EPERM;
222 return drm_vma_node_verify_access(&rbo->gem_base.vma_node,
223 fp->private_data);
224#endif
926deccb
FT
225}
226
227static void radeon_move_null(struct ttm_buffer_object *bo,
228 struct ttm_mem_reg *new_mem)
229{
230 struct ttm_mem_reg *old_mem = &bo->mem;
231
c4ef309b 232 BUG_ON(old_mem->mm_node != NULL);
926deccb
FT
233 *old_mem = *new_mem;
234 new_mem->mm_node = NULL;
235}
236
237static int radeon_move_blit(struct ttm_buffer_object *bo,
238 bool evict, bool no_wait_gpu,
239 struct ttm_mem_reg *new_mem,
240 struct ttm_mem_reg *old_mem)
241{
242 struct radeon_device *rdev;
243 uint64_t old_start, new_start;
244 struct radeon_fence *fence;
245 int r, ridx;
246
247 rdev = radeon_get_rdev(bo->bdev);
248 ridx = radeon_copy_ring_index(rdev);
ee479021
IV
249 old_start = old_mem->start << PAGE_SHIFT;
250 new_start = new_mem->start << PAGE_SHIFT;
926deccb
FT
251
252 switch (old_mem->mem_type) {
253 case TTM_PL_VRAM:
254 old_start += rdev->mc.vram_start;
255 break;
256 case TTM_PL_TT:
257 old_start += rdev->mc.gtt_start;
258 break;
259 default:
260 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
261 return -EINVAL;
262 }
263 switch (new_mem->mem_type) {
264 case TTM_PL_VRAM:
265 new_start += rdev->mc.vram_start;
266 break;
267 case TTM_PL_TT:
268 new_start += rdev->mc.gtt_start;
269 break;
270 default:
271 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
272 return -EINVAL;
273 }
274 if (!rdev->ring[ridx].ready) {
275 DRM_ERROR("Trying to move memory with ring turned off.\n");
276 return -EINVAL;
277 }
278
c4ef309b 279 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
926deccb
FT
280
281 /* sync other rings */
282 fence = bo->sync_obj;
283 r = radeon_copy(rdev, old_start, new_start,
284 new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */
285 &fence);
286 /* FIXME: handle copy error */
287 r = ttm_bo_move_accel_cleanup(bo, (void *)fence,
288 evict, no_wait_gpu, new_mem);
289 radeon_fence_unref(&fence);
290 return r;
291}
292
293static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
294 bool evict, bool interruptible,
295 bool no_wait_gpu,
296 struct ttm_mem_reg *new_mem)
297{
298 struct radeon_device *rdev;
299 struct ttm_mem_reg *old_mem = &bo->mem;
300 struct ttm_mem_reg tmp_mem;
591d5043 301 struct ttm_place placements;
926deccb
FT
302 struct ttm_placement placement;
303 int r;
304
305 rdev = radeon_get_rdev(bo->bdev);
306 tmp_mem = *new_mem;
307 tmp_mem.mm_node = NULL;
926deccb
FT
308 placement.num_placement = 1;
309 placement.placement = &placements;
310 placement.num_busy_placement = 1;
311 placement.busy_placement = &placements;
591d5043
FT
312 placements.fpfn = 0;
313 placements.lpfn = 0;
314 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
926deccb
FT
315 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
316 interruptible, no_wait_gpu);
317 if (unlikely(r)) {
318 return r;
319 }
320
321 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
322 if (unlikely(r)) {
323 goto out_cleanup;
324 }
325
326 r = ttm_tt_bind(bo->ttm, &tmp_mem);
327 if (unlikely(r)) {
328 goto out_cleanup;
329 }
330 r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
331 if (unlikely(r)) {
332 goto out_cleanup;
333 }
334 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
335out_cleanup:
336 ttm_bo_mem_put(bo, &tmp_mem);
337 return r;
338}
339
340static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
341 bool evict, bool interruptible,
342 bool no_wait_gpu,
343 struct ttm_mem_reg *new_mem)
344{
345 struct radeon_device *rdev;
346 struct ttm_mem_reg *old_mem = &bo->mem;
347 struct ttm_mem_reg tmp_mem;
348 struct ttm_placement placement;
591d5043 349 struct ttm_place placements;
926deccb
FT
350 int r;
351
352 rdev = radeon_get_rdev(bo->bdev);
353 tmp_mem = *new_mem;
354 tmp_mem.mm_node = NULL;
926deccb
FT
355 placement.num_placement = 1;
356 placement.placement = &placements;
357 placement.num_busy_placement = 1;
358 placement.busy_placement = &placements;
591d5043
FT
359 placements.fpfn = 0;
360 placements.lpfn = 0;
361 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
926deccb
FT
362 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
363 interruptible, no_wait_gpu);
364 if (unlikely(r)) {
365 return r;
366 }
367 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
368 if (unlikely(r)) {
369 goto out_cleanup;
370 }
371 r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
372 if (unlikely(r)) {
373 goto out_cleanup;
374 }
375out_cleanup:
376 ttm_bo_mem_put(bo, &tmp_mem);
377 return r;
378}
379
380static int radeon_bo_move(struct ttm_buffer_object *bo,
381 bool evict, bool interruptible,
382 bool no_wait_gpu,
383 struct ttm_mem_reg *new_mem)
384{
385 struct radeon_device *rdev;
386 struct ttm_mem_reg *old_mem = &bo->mem;
387 int r;
388
389 rdev = radeon_get_rdev(bo->bdev);
390 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
391 radeon_move_null(bo, new_mem);
392 return 0;
393 }
394 if ((old_mem->mem_type == TTM_PL_TT &&
395 new_mem->mem_type == TTM_PL_SYSTEM) ||
396 (old_mem->mem_type == TTM_PL_SYSTEM &&
397 new_mem->mem_type == TTM_PL_TT)) {
398 /* bind is enough */
399 radeon_move_null(bo, new_mem);
400 return 0;
401 }
402 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready ||
403 rdev->asic->copy.copy == NULL) {
404 /* use memcpy */
405 goto memcpy;
406 }
407
408 if (old_mem->mem_type == TTM_PL_VRAM &&
409 new_mem->mem_type == TTM_PL_SYSTEM) {
410 r = radeon_move_vram_ram(bo, evict, interruptible,
411 no_wait_gpu, new_mem);
412 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
413 new_mem->mem_type == TTM_PL_VRAM) {
414 r = radeon_move_ram_vram(bo, evict, interruptible,
415 no_wait_gpu, new_mem);
416 } else {
417 r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
418 }
419
420 if (r) {
421memcpy:
422 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
c6f73aab
FT
423 if (r) {
424 return r;
425 }
926deccb 426 }
c6f73aab
FT
427
428 /* update statistics */
429 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved);
430 return 0;
926deccb
FT
431}
432
433static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
434{
435 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
436 struct radeon_device *rdev = radeon_get_rdev(bdev);
437
438 mem->bus.addr = NULL;
439 mem->bus.offset = 0;
440 mem->bus.size = mem->num_pages << PAGE_SHIFT;
441 mem->bus.base = 0;
442 mem->bus.is_iomem = false;
443 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
444 return -EINVAL;
445 switch (mem->mem_type) {
446 case TTM_PL_SYSTEM:
447 /* system memory */
448 return 0;
449 case TTM_PL_TT:
450#if __OS_HAS_AGP
451 if (rdev->flags & RADEON_IS_AGP) {
452 /* RADEON_IS_AGP is set only if AGP is active */
453 mem->bus.offset = mem->start << PAGE_SHIFT;
454 mem->bus.base = rdev->mc.agp_base;
455 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
456 }
457#endif
458 break;
459 case TTM_PL_VRAM:
460 mem->bus.offset = mem->start << PAGE_SHIFT;
461 /* check if it's visible */
462 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
463 return -EINVAL;
464 mem->bus.base = rdev->mc.aper_base;
465 mem->bus.is_iomem = true;
466#ifdef __alpha__
467 /*
468 * Alpha: use bus.addr to hold the ioremap() return,
469 * so we can modify bus.base below.
470 */
471 if (mem->placement & TTM_PL_FLAG_WC)
472 mem->bus.addr =
473 ioremap_wc(mem->bus.base + mem->bus.offset,
474 mem->bus.size);
475 else
476 mem->bus.addr =
477 ioremap_nocache(mem->bus.base + mem->bus.offset,
478 mem->bus.size);
479
480 /*
481 * Alpha: Use just the bus offset plus
482 * the hose/domain memory base for bus.base.
483 * It then can be used to build PTEs for VRAM
484 * access, as done in ttm_bo_vm_fault().
485 */
486 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
487 rdev->ddev->hose->dense_mem_base;
488#endif
489 break;
490 default:
491 return -EINVAL;
492 }
493 return 0;
494}
495
496static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
497{
498}
499
500static int radeon_sync_obj_wait(void *sync_obj, bool lazy, bool interruptible)
501{
502 return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible);
503}
504
505static int radeon_sync_obj_flush(void *sync_obj)
506{
507 return 0;
508}
509
510static void radeon_sync_obj_unref(void **sync_obj)
511{
512 radeon_fence_unref((struct radeon_fence **)sync_obj);
513}
514
515static void *radeon_sync_obj_ref(void *sync_obj)
516{
517 return radeon_fence_ref((struct radeon_fence *)sync_obj);
518}
519
520static bool radeon_sync_obj_signaled(void *sync_obj)
521{
522 return radeon_fence_signaled((struct radeon_fence *)sync_obj);
523}
524
525/*
526 * TTM backend functions.
527 */
528struct radeon_ttm_tt {
529 struct ttm_dma_tt ttm;
530 struct radeon_device *rdev;
531 u64 offset;
532};
533
534static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
535 struct ttm_mem_reg *bo_mem)
536{
537 struct radeon_ttm_tt *gtt = (void*)ttm;
c6f73aab
FT
538 uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |
539 RADEON_GART_PAGE_WRITE;
926deccb
FT
540 int r;
541
542 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
543 if (!ttm->num_pages) {
c4ef309b 544 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
926deccb
FT
545 ttm->num_pages, bo_mem, ttm);
546 }
c6f73aab
FT
547 if (ttm->caching_state == tt_cached)
548 flags |= RADEON_GART_PAGE_SNOOP;
549 r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages,
550 ttm->pages, gtt->ttm.dma_address, flags);
926deccb
FT
551 if (r) {
552 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
553 ttm->num_pages, (unsigned)gtt->offset);
554 return r;
555 }
556 return 0;
557}
558
559static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
560{
561 struct radeon_ttm_tt *gtt = (void *)ttm;
562
563 radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
564 return 0;
565}
566
567static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
568{
569 struct radeon_ttm_tt *gtt = (void *)ttm;
570
571 ttm_dma_tt_fini(&gtt->ttm);
c4ef309b 572 kfree(gtt);
926deccb
FT
573}
574
575static struct ttm_backend_func radeon_backend_func = {
576 .bind = &radeon_ttm_backend_bind,
577 .unbind = &radeon_ttm_backend_unbind,
578 .destroy = &radeon_ttm_backend_destroy,
579};
580
581static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev,
582 unsigned long size, uint32_t page_flags,
f0bba3d1 583 struct page *dummy_read_page)
926deccb
FT
584{
585 struct radeon_device *rdev;
586 struct radeon_ttm_tt *gtt;
587
588 rdev = radeon_get_rdev(bdev);
589#if __OS_HAS_AGP
590#ifdef DUMBBELL_WIP
591 if (rdev->flags & RADEON_IS_AGP) {
592 return ttm_agp_tt_create(bdev, rdev->ddev->agp->agpdev,
593 size, page_flags, dummy_read_page);
594 }
595#endif /* DUMBBELL_WIP */
596#endif
597
c4ef309b 598 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
926deccb
FT
599 if (gtt == NULL) {
600 return NULL;
601 }
602 gtt->ttm.ttm.func = &radeon_backend_func;
603 gtt->rdev = rdev;
604 if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
c4ef309b 605 kfree(gtt);
926deccb
FT
606 return NULL;
607 }
608 return &gtt->ttm.ttm;
609}
610
611static int radeon_ttm_tt_populate(struct ttm_tt *ttm)
612{
613 struct radeon_device *rdev;
614 struct radeon_ttm_tt *gtt = (void *)ttm;
615 unsigned i;
616 int r;
617#ifdef DUMBBELL_WIP
618 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
619#endif /* DUMBBELL_WIP */
620
621 if (ttm->state != tt_unpopulated)
622 return 0;
623
624#ifdef DUMBBELL_WIP
625 /*
626 * Maybe unneeded on FreeBSD.
627 * -- dumbbell@
628 */
629 if (slave && ttm->sg) {
630 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
631 gtt->ttm.dma_address, ttm->num_pages);
632 ttm->state = tt_unbound;
633 return 0;
634 }
635#endif /* DUMBBELL_WIP */
636
637 rdev = radeon_get_rdev(ttm->bdev);
638#if __OS_HAS_AGP
639#ifdef DUMBBELL_WIP
640 if (rdev->flags & RADEON_IS_AGP) {
641 return ttm_agp_tt_populate(ttm);
642 }
643#endif /* DUMBBELL_WIP */
644#endif
645
646#ifdef CONFIG_SWIOTLB
647 if (swiotlb_nr_tbl()) {
648 return ttm_dma_populate(&gtt->ttm, rdev->dev);
649 }
650#endif
651
652 r = ttm_pool_populate(ttm);
653 if (r) {
654 return r;
655 }
656
657 for (i = 0; i < ttm->num_pages; i++) {
f0bba3d1 658 gtt->ttm.dma_address[i] = VM_PAGE_TO_PHYS((struct vm_page *)ttm->pages[i]);
926deccb
FT
659#ifdef DUMBBELL_WIP
660 gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i],
661 0, PAGE_SIZE,
662 PCI_DMA_BIDIRECTIONAL);
663 if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) {
ee479021 664 while (--i) {
926deccb
FT
665 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
666 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
667 gtt->ttm.dma_address[i] = 0;
668 }
669 ttm_pool_unpopulate(ttm);
670 return -EFAULT;
671 }
672#endif /* DUMBBELL_WIP */
673 }
674 return 0;
675}
676
677static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
678{
679 struct radeon_device *rdev;
680 struct radeon_ttm_tt *gtt = (void *)ttm;
681 unsigned i;
682 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
683
684 if (slave)
685 return;
686
687 rdev = radeon_get_rdev(ttm->bdev);
688#if __OS_HAS_AGP
689#ifdef DUMBBELL_WIP
690 if (rdev->flags & RADEON_IS_AGP) {
691 ttm_agp_tt_unpopulate(ttm);
692 return;
693 }
694#endif /* DUMBBELL_WIP */
695#endif
696
697#ifdef CONFIG_SWIOTLB
698 if (swiotlb_nr_tbl()) {
699 ttm_dma_unpopulate(&gtt->ttm, rdev->dev);
700 return;
701 }
702#endif
703
704 for (i = 0; i < ttm->num_pages; i++) {
705 if (gtt->ttm.dma_address[i]) {
706 gtt->ttm.dma_address[i] = 0;
707#ifdef DUMBBELL_WIP
708 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
709 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
710#endif /* DUMBBELL_WIP */
711 }
712 }
713
714 ttm_pool_unpopulate(ttm);
715}
716
717static struct ttm_bo_driver radeon_bo_driver = {
718 .ttm_tt_create = &radeon_ttm_tt_create,
719 .ttm_tt_populate = &radeon_ttm_tt_populate,
720 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
721 .invalidate_caches = &radeon_invalidate_caches,
722 .init_mem_type = &radeon_init_mem_type,
723 .evict_flags = &radeon_evict_flags,
724 .move = &radeon_bo_move,
725 .verify_access = &radeon_verify_access,
726 .sync_obj_signaled = &radeon_sync_obj_signaled,
727 .sync_obj_wait = &radeon_sync_obj_wait,
728 .sync_obj_flush = &radeon_sync_obj_flush,
729 .sync_obj_unref = &radeon_sync_obj_unref,
730 .sync_obj_ref = &radeon_sync_obj_ref,
731 .move_notify = &radeon_bo_move_notify,
732 .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
733 .io_mem_reserve = &radeon_ttm_io_mem_reserve,
734 .io_mem_free = &radeon_ttm_io_mem_free,
735};
736
737int radeon_ttm_init(struct radeon_device *rdev)
738{
ee479021 739 int r, r2;
926deccb
FT
740
741 r = radeon_ttm_global_init(rdev);
742 if (r) {
743 return r;
744 }
745 /* No others user of address space so set it to 0 */
746 r = ttm_bo_device_init(&rdev->mman.bdev,
747 rdev->mman.bo_global_ref.ref.object,
748 &radeon_bo_driver, DRM_FILE_PAGE_OFFSET,
749 rdev->need_dma32);
750 if (r) {
751 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
752 return r;
753 }
754 rdev->mman.initialized = true;
755 rdev->ddev->drm_ttm_bdev = &rdev->mman.bdev;
756 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
757 rdev->mc.real_vram_size >> PAGE_SHIFT);
758 if (r) {
759 DRM_ERROR("Failed initializing VRAM heap.\n");
760 return r;
761 }
c6f73aab
FT
762 /* Change the size here instead of the init above so only lpfn is affected */
763 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
764
926deccb 765 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
c6f73aab 766 RADEON_GEM_DOMAIN_VRAM, 0,
926deccb
FT
767 NULL, &rdev->stollen_vga_memory);
768 if (r) {
769 return r;
770 }
771 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
ee479021
IV
772 if (r) {
773 radeon_bo_unref(&rdev->stollen_vga_memory);
774 return r;
775 }
926deccb
FT
776 r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
777 radeon_bo_unreserve(rdev->stollen_vga_memory);
778 if (r) {
779 radeon_bo_unref(&rdev->stollen_vga_memory);
780 return r;
781 }
782 DRM_INFO("radeon: %uM of VRAM memory ready\n",
f43cf1b1 783 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
926deccb
FT
784 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
785 rdev->mc.gtt_size >> PAGE_SHIFT);
786 if (r) {
787 DRM_ERROR("Failed initializing GTT heap.\n");
ee479021
IV
788 r2 = radeon_bo_reserve(rdev->stollen_vga_memory, false);
789 if (likely(r2 == 0)) {
790 radeon_bo_unpin(rdev->stollen_vga_memory);
791 radeon_bo_unreserve(rdev->stollen_vga_memory);
792 }
793 radeon_bo_unref(&rdev->stollen_vga_memory);
926deccb
FT
794 return r;
795 }
796 DRM_INFO("radeon: %uM of GTT memory ready.\n",
797 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
798
799 r = radeon_ttm_debugfs_init(rdev);
800 if (r) {
801 DRM_ERROR("Failed to init debugfs\n");
ee479021
IV
802 r2 = radeon_bo_reserve(rdev->stollen_vga_memory, false);
803 if (likely(r2 == 0)) {
804 radeon_bo_unpin(rdev->stollen_vga_memory);
805 radeon_bo_unreserve(rdev->stollen_vga_memory);
806 }
807 radeon_bo_unref(&rdev->stollen_vga_memory);
926deccb
FT
808 return r;
809 }
810 return 0;
811}
812
813void radeon_ttm_fini(struct radeon_device *rdev)
814{
815 int r;
816
817 if (!rdev->mman.initialized)
818 return;
c6f73aab 819 radeon_ttm_debugfs_fini(rdev);
926deccb
FT
820 if (rdev->stollen_vga_memory) {
821 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
822 if (r == 0) {
823 radeon_bo_unpin(rdev->stollen_vga_memory);
824 radeon_bo_unreserve(rdev->stollen_vga_memory);
825 }
826 radeon_bo_unref(&rdev->stollen_vga_memory);
827 }
828 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
829 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
830 ttm_bo_device_release(&rdev->mman.bdev);
831 radeon_gart_fini(rdev);
832 radeon_ttm_global_fini(rdev);
833 rdev->mman.initialized = false;
834 DRM_INFO("radeon: ttm finalized\n");
835}
836
837/* this should only be called at bootup or when userspace
838 * isn't running */
839void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
840{
841 struct ttm_mem_type_manager *man;
842
843 if (!rdev->mman.initialized)
844 return;
845
846 man = &rdev->mman.bdev.man[TTM_PL_VRAM];
847 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
848 man->size = size >> PAGE_SHIFT;
849}
850
851#ifdef DUMBBELL_WIP
852static struct vm_operations_struct radeon_ttm_vm_ops;
853static const struct vm_operations_struct *ttm_vm_ops = NULL;
854
855static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
856{
857 struct ttm_buffer_object *bo;
858 struct radeon_device *rdev;
859 int r;
860
861 bo = (struct ttm_buffer_object *)vma->vm_private_data;
862 if (bo == NULL) {
863 return VM_FAULT_NOPAGE;
864 }
865 rdev = radeon_get_rdev(bo->bdev);
866 lockmgr(&rdev->pm.mclk_lock, LK_SHARED);
867 r = ttm_vm_ops->fault(vma, vmf);
868 lockmgr(&rdev->pm.mclk_lock, LK_RELEASE);
869 return r;
870}
871
872int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
873{
874 struct drm_file *file_priv;
875 struct radeon_device *rdev;
876 int r;
877
878 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
591d5043 879 return -EINVAL;
926deccb
FT
880 }
881
882 file_priv = filp->private_data;
883 rdev = file_priv->minor->dev->dev_private;
884 if (rdev == NULL) {
885 return -EINVAL;
886 }
887 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
888 if (unlikely(r != 0)) {
889 return r;
890 }
891 if (unlikely(ttm_vm_ops == NULL)) {
892 ttm_vm_ops = vma->vm_ops;
893 radeon_ttm_vm_ops = *ttm_vm_ops;
894 radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
895 }
896 vma->vm_ops = &radeon_ttm_vm_ops;
897 return 0;
898}
899#endif /* DUMBBELL_WIP */
900
926deccb 901#if defined(CONFIG_DEBUG_FS)
c6f73aab 902
926deccb
FT
903static int radeon_mm_dump_table(struct seq_file *m, void *data)
904{
905 struct drm_info_node *node = (struct drm_info_node *)m->private;
c6f73aab 906 unsigned ttm_pl = *(int *)node->info_ent->data;
926deccb
FT
907 struct drm_device *dev = node->minor->dev;
908 struct radeon_device *rdev = dev->dev_private;
c6f73aab 909 struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv;
926deccb
FT
910 int ret;
911 struct ttm_bo_global *glob = rdev->mman.bdev.glob;
912
913 spin_lock(&glob->lru_lock);
914 ret = drm_mm_dump_table(m, mm);
915 spin_unlock(&glob->lru_lock);
916 return ret;
917}
c6f73aab
FT
918
919static int ttm_pl_vram = TTM_PL_VRAM;
920static int ttm_pl_tt = TTM_PL_TT;
921
922static struct drm_info_list radeon_ttm_debugfs_list[] = {
923 {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram},
924 {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt},
925 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
926#ifdef CONFIG_SWIOTLB
927 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
926deccb 928#endif
c6f73aab 929};
926deccb 930
c6f73aab 931static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
926deccb 932{
c6f73aab
FT
933 struct radeon_device *rdev = inode->i_private;
934 i_size_write(inode, rdev->mc.mc_vram_size);
935 filep->private_data = inode->i_private;
936 return 0;
937}
926deccb 938
c6f73aab
FT
939static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
940 size_t size, loff_t *pos)
941{
942 struct radeon_device *rdev = f->private_data;
943 ssize_t result = 0;
944 int r;
945
946 if (size & 0x3 || *pos & 0x3)
947 return -EINVAL;
948
949 while (size) {
950 unsigned long flags;
951 uint32_t value;
952
953 if (*pos >= rdev->mc.mc_vram_size)
954 return result;
955
956 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
957 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
958 if (rdev->family >= CHIP_CEDAR)
959 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
960 value = RREG32(RADEON_MM_DATA);
961 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
962
963 r = put_user(value, (uint32_t *)buf);
964 if (r)
965 return r;
926deccb 966
c6f73aab
FT
967 result += 4;
968 buf += 4;
969 *pos += 4;
970 size -= 4;
926deccb 971 }
c6f73aab
FT
972
973 return result;
974}
975
976static const struct file_operations radeon_ttm_vram_fops = {
977 .owner = THIS_MODULE,
978 .open = radeon_ttm_vram_open,
979 .read = radeon_ttm_vram_read,
980 .llseek = default_llseek
981};
982
983static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
984{
985 struct radeon_device *rdev = inode->i_private;
986 i_size_write(inode, rdev->mc.gtt_size);
987 filep->private_data = inode->i_private;
988 return 0;
989}
990
991static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
992 size_t size, loff_t *pos)
993{
994 struct radeon_device *rdev = f->private_data;
995 ssize_t result = 0;
996 int r;
997
998 while (size) {
999 loff_t p = *pos / PAGE_SIZE;
d653c727 1000 unsigned off = *pos & ~LINUX_PAGE_MASK;
c6f73aab
FT
1001 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1002 struct page *page;
1003 void *ptr;
1004
1005 if (p >= rdev->gart.num_cpu_pages)
1006 return result;
1007
1008 page = rdev->gart.pages[p];
1009 if (page) {
1010 ptr = kmap(page);
1011 ptr += off;
1012
1013 r = copy_to_user(buf, ptr, cur_size);
1014 kunmap(rdev->gart.pages[p]);
1015 } else
1016 r = clear_user(buf, cur_size);
1017
1018 if (r)
1019 return -EFAULT;
1020
1021 result += cur_size;
1022 buf += cur_size;
1023 *pos += cur_size;
1024 size -= cur_size;
926deccb 1025 }
c6f73aab
FT
1026
1027 return result;
1028}
1029
1030static const struct file_operations radeon_ttm_gtt_fops = {
1031 .owner = THIS_MODULE,
1032 .open = radeon_ttm_gtt_open,
1033 .read = radeon_ttm_gtt_read,
1034 .llseek = default_llseek
1035};
1036
926deccb 1037#endif
926deccb 1038
c6f73aab
FT
1039static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
1040{
1041#if defined(CONFIG_DEBUG_FS)
1042 unsigned count;
1043
1044 struct drm_minor *minor = rdev->ddev->primary;
1045 struct dentry *ent, *root = minor->debugfs_root;
1046
1047 ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root,
1048 rdev, &radeon_ttm_vram_fops);
1049 if (IS_ERR(ent))
1050 return PTR_ERR(ent);
1051 rdev->mman.vram = ent;
1052
1053 ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root,
1054 rdev, &radeon_ttm_gtt_fops);
1055 if (IS_ERR(ent))
1056 return PTR_ERR(ent);
1057 rdev->mman.gtt = ent;
1058
1059 count = ARRAY_SIZE(radeon_ttm_debugfs_list);
1060
1061#ifdef CONFIG_SWIOTLB
1062 if (!swiotlb_nr_tbl())
1063 --count;
926deccb 1064#endif
c6f73aab
FT
1065
1066 return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count);
1067#else
1068
926deccb 1069 return 0;
c6f73aab
FT
1070#endif
1071}
1072
1073static void radeon_ttm_debugfs_fini(struct radeon_device *rdev)
1074{
1075#if defined(CONFIG_DEBUG_FS)
1076
1077 debugfs_remove(rdev->mman.vram);
1078 rdev->mman.vram = NULL;
1079
1080 debugfs_remove(rdev->mman.gtt);
1081 rdev->mman.gtt = NULL;
1082#endif
926deccb 1083}