ALTQ support.
[dragonfly.git] / sys / dev / netif / sis / if_sis.c
CommitLineData
984263bc
MD
1/*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $
e25db1f0 33 * $DragonFly: src/sys/dev/netif/sis/if_sis.c,v 1.19 2005/02/14 17:38:30 joerg Exp $
1de703da
MD
34 *
35 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $
984263bc
MD
36 */
37
38/*
39 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
40 * available from http://www.sis.com.tw.
41 *
42 * This driver also supports the NatSemi DP83815. Datasheets are
43 * available from http://www.national.com.
44 *
45 * Written by Bill Paul <wpaul@ee.columbia.edu>
46 * Electrical Engineering Department
47 * Columbia University, New York City
48 */
49
50/*
51 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
52 * simple TX and RX descriptors of 3 longwords in size. The receiver
53 * has a single perfect filter entry for the station address and a
54 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
55 * transceiver while the 7016 requires an external transceiver chip.
56 * Both chips offer the standard bit-bang MII interface as well as
57 * an enchanced PHY interface which simplifies accessing MII registers.
58 *
59 * The only downside to this chipset is that RX descriptors must be
60 * longword aligned.
61 */
62
63#include <sys/param.h>
64#include <sys/systm.h>
65#include <sys/sockio.h>
66#include <sys/mbuf.h>
67#include <sys/malloc.h>
68#include <sys/kernel.h>
69#include <sys/socket.h>
70#include <sys/sysctl.h>
71
72#include <net/if.h>
e25db1f0 73#include <net/ifq_var.h>
984263bc
MD
74#include <net/if_arp.h>
75#include <net/ethernet.h>
76#include <net/if_dl.h>
77#include <net/if_media.h>
78#include <net/if_types.h>
1f2de5d4 79#include <net/vlan/if_vlan_var.h>
984263bc
MD
80
81#include <net/bpf.h>
82
984263bc
MD
83#include <machine/bus_pio.h>
84#include <machine/bus_memio.h>
85#include <machine/bus.h>
86#include <machine/resource.h>
87#include <sys/bus.h>
88#include <sys/rman.h>
89
49eef4c6
JS
90#include <dev/netif/mii_layer/mii.h>
91#include <dev/netif/mii_layer/miivar.h>
984263bc 92
1f2de5d4
MD
93#include <bus/pci/pcireg.h>
94#include <bus/pci/pcivar.h>
984263bc
MD
95
96#define SIS_USEIOSPACE
97
1f2de5d4 98#include "if_sisreg.h"
984263bc
MD
99
100/* "controller miibus0" required. See GENERIC if you get errors here. */
101#include "miibus_if.h"
102
984263bc
MD
103/*
104 * Various supported device vendors/types and their names.
105 */
106static struct sis_type sis_devs[] = {
107 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
108 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
49eef4c6 109 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
984263bc
MD
110 { 0, 0, NULL }
111};
112
49eef4c6
JS
113static int sis_probe(device_t);
114static int sis_attach(device_t);
115static int sis_detach(device_t);
116
117static int sis_newbuf(struct sis_softc *, struct sis_desc *,
118 struct mbuf *);
119static int sis_encap(struct sis_softc *, struct mbuf *, uint32_t *);
120static void sis_rxeof(struct sis_softc *);
121static void sis_rxeoc(struct sis_softc *);
122static void sis_txeof(struct sis_softc *);
123static void sis_intr(void *);
124static void sis_tick(void *);
125static void sis_start(struct ifnet *);
bd4539cc 126static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
49eef4c6
JS
127static void sis_init(void *);
128static void sis_stop(struct sis_softc *);
129static void sis_watchdog(struct ifnet *);
130static void sis_shutdown(device_t);
131static int sis_ifmedia_upd(struct ifnet *);
132static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
133
134static uint16_t sis_reverse(uint16_t);
135static void sis_delay(struct sis_softc *);
136static void sis_eeprom_idle(struct sis_softc *);
137static void sis_eeprom_putbyte(struct sis_softc *, int);
138static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *);
139static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int);
984263bc 140#ifdef __i386__
49eef4c6
JS
141static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int);
142static void sis_read_mac(struct sis_softc *, device_t, caddr_t);
143static device_t sis_find_bridge(device_t);
984263bc
MD
144#endif
145
49eef4c6
JS
146static void sis_mii_sync(struct sis_softc *);
147static void sis_mii_send(struct sis_softc *, uint32_t, int);
148static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *);
149static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *);
150static int sis_miibus_readreg(device_t, int, int);
151static int sis_miibus_writereg(device_t, int, int, int);
152static void sis_miibus_statchg(device_t);
153
154static void sis_setmulti_sis(struct sis_softc *);
155static void sis_setmulti_ns(struct sis_softc *);
156static uint32_t sis_mchash(struct sis_softc *, const uint8_t *);
157static void sis_reset(struct sis_softc *);
158static int sis_list_rx_init(struct sis_softc *);
159static int sis_list_tx_init(struct sis_softc *);
4ddeda6c
JS
160
161static void sis_dma_map_desc_ptr(void *, bus_dma_segment_t *, int, int);
162static void sis_dma_map_desc_next(void *, bus_dma_segment_t *, int, int);
163static void sis_dma_map_ring(void *, bus_dma_segment_t *, int, int);
984263bc
MD
164#ifdef SIS_USEIOSPACE
165#define SIS_RES SYS_RES_IOPORT
166#define SIS_RID SIS_PCI_LOIO
167#else
168#define SIS_RES SYS_RES_MEMORY
169#define SIS_RID SIS_PCI_LOMEM
170#endif
171
172static device_method_t sis_methods[] = {
173 /* Device interface */
174 DEVMETHOD(device_probe, sis_probe),
175 DEVMETHOD(device_attach, sis_attach),
176 DEVMETHOD(device_detach, sis_detach),
177 DEVMETHOD(device_shutdown, sis_shutdown),
178
179 /* bus interface */
180 DEVMETHOD(bus_print_child, bus_generic_print_child),
181 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
182
183 /* MII interface */
184 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
185 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
186 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
187
188 { 0, 0 }
189};
190
191static driver_t sis_driver = {
192 "sis",
193 sis_methods,
194 sizeof(struct sis_softc)
195};
196
197static devclass_t sis_devclass;
198
32832096 199DECLARE_DUMMY_MODULE(if_sis);
984263bc
MD
200DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0);
201DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);
202
203#define SIS_SETBIT(sc, reg, x) \
49eef4c6 204 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
984263bc
MD
205
206#define SIS_CLRBIT(sc, reg, x) \
49eef4c6 207 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
984263bc
MD
208
209#define SIO_SET(x) \
210 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
211
212#define SIO_CLR(x) \
213 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
214
4ddeda6c
JS
215static void
216sis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error)
217{
218 struct sis_desc *r;
219
220 r = arg;
221 r->sis_next = segs->ds_addr;
222}
223
224static void
225sis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
226{
227 struct sis_desc *r;
228
229 r = arg;
230 r->sis_ptr = segs->ds_addr;
231}
232
233static void
234sis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error)
235{
236 uint32_t *p;
237
238 p = arg;
239 *p = segs->ds_addr;
240}
241
984263bc
MD
242/*
243 * Routine to reverse the bits in a word. Stolen almost
244 * verbatim from /usr/games/fortune.
245 */
49eef4c6
JS
246static uint16_t
247sis_reverse(uint16_t n)
984263bc
MD
248{
249 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
250 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
251 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
252 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
253
254 return(n);
255}
256
49eef4c6
JS
257static void
258sis_delay(struct sis_softc *sc)
984263bc 259{
49eef4c6 260 int idx;
984263bc
MD
261
262 for (idx = (300 / 33) + 1; idx > 0; idx--)
263 CSR_READ_4(sc, SIS_CSR);
984263bc
MD
264}
265
49eef4c6
JS
266static void
267sis_eeprom_idle(struct sis_softc *sc)
984263bc 268{
49eef4c6 269 int i;
984263bc
MD
270
271 SIO_SET(SIS_EECTL_CSEL);
272 sis_delay(sc);
273 SIO_SET(SIS_EECTL_CLK);
274 sis_delay(sc);
275
276 for (i = 0; i < 25; i++) {
277 SIO_CLR(SIS_EECTL_CLK);
278 sis_delay(sc);
279 SIO_SET(SIS_EECTL_CLK);
280 sis_delay(sc);
281 }
282
283 SIO_CLR(SIS_EECTL_CLK);
284 sis_delay(sc);
285 SIO_CLR(SIS_EECTL_CSEL);
286 sis_delay(sc);
287 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
984263bc
MD
288}
289
290/*
291 * Send a read command and address to the EEPROM, check for ACK.
292 */
49eef4c6
JS
293static void
294sis_eeprom_putbyte(struct sis_softc *sc, int addr)
984263bc 295{
49eef4c6 296 int d, i;
984263bc
MD
297
298 d = addr | SIS_EECMD_READ;
299
300 /*
301 * Feed in each bit and stobe the clock.
302 */
303 for (i = 0x400; i; i >>= 1) {
49eef4c6 304 if (d & i)
984263bc 305 SIO_SET(SIS_EECTL_DIN);
49eef4c6 306 else
984263bc 307 SIO_CLR(SIS_EECTL_DIN);
984263bc
MD
308 sis_delay(sc);
309 SIO_SET(SIS_EECTL_CLK);
310 sis_delay(sc);
311 SIO_CLR(SIS_EECTL_CLK);
312 sis_delay(sc);
313 }
984263bc
MD
314}
315
316/*
317 * Read a word of data stored in the EEPROM at address 'addr.'
318 */
49eef4c6
JS
319static void
320sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
984263bc 321{
49eef4c6
JS
322 int i;
323 uint16_t word = 0;
984263bc
MD
324
325 /* Force EEPROM to idle state. */
326 sis_eeprom_idle(sc);
327
328 /* Enter EEPROM access mode. */
329 sis_delay(sc);
330 SIO_CLR(SIS_EECTL_CLK);
331 sis_delay(sc);
332 SIO_SET(SIS_EECTL_CSEL);
333 sis_delay(sc);
334
335 /*
336 * Send address of word we want to read.
337 */
338 sis_eeprom_putbyte(sc, addr);
339
340 /*
341 * Start reading bits from EEPROM.
342 */
343 for (i = 0x8000; i; i >>= 1) {
344 SIO_SET(SIS_EECTL_CLK);
345 sis_delay(sc);
346 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
347 word |= i;
348 sis_delay(sc);
349 SIO_CLR(SIS_EECTL_CLK);
350 sis_delay(sc);
351 }
352
353 /* Turn off EEPROM access mode. */
354 sis_eeprom_idle(sc);
355
356 *dest = word;
984263bc
MD
357}
358
359/*
360 * Read a sequence of words from the EEPROM.
361 */
49eef4c6
JS
362static void
363sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
984263bc 364{
49eef4c6
JS
365 int i;
366 uint16_t word = 0, *ptr;
984263bc
MD
367
368 for (i = 0; i < cnt; i++) {
369 sis_eeprom_getword(sc, off + i, &word);
49eef4c6 370 ptr = (uint16_t *)(dest + (i * 2));
984263bc
MD
371 if (swap)
372 *ptr = ntohs(word);
373 else
374 *ptr = word;
375 }
984263bc
MD
376}
377
378#ifdef __i386__
49eef4c6
JS
379static device_t
380sis_find_bridge(device_t dev)
984263bc 381{
49eef4c6
JS
382 devclass_t pci_devclass;
383 device_t *pci_devices;
384 int pci_count = 0;
385 device_t *pci_children;
386 int pci_childcount = 0;
387 device_t *busp, *childp;
388 device_t child = NULL;
389 int i, j;
984263bc
MD
390
391 if ((pci_devclass = devclass_find("pci")) == NULL)
392 return(NULL);
393
394 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
395
396 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
397 pci_childcount = 0;
398 device_get_children(*busp, &pci_children, &pci_childcount);
49eef4c6
JS
399 for (j = 0, childp = pci_children; j < pci_childcount;
400 j++, childp++) {
984263bc
MD
401 if (pci_get_vendor(*childp) == SIS_VENDORID &&
402 pci_get_device(*childp) == 0x0008) {
403 child = *childp;
404 goto done;
405 }
406 }
407 }
408
409done:
410 free(pci_devices, M_TEMP);
411 free(pci_children, M_TEMP);
412 return(child);
413}
414
49eef4c6
JS
415static void
416sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off,
417 int cnt)
984263bc 418{
49eef4c6
JS
419 device_t bridge;
420 uint8_t reg;
421 int i;
422 bus_space_tag_t btag;
984263bc
MD
423
424 bridge = sis_find_bridge(dev);
425 if (bridge == NULL)
426 return;
427 reg = pci_read_config(bridge, 0x48, 1);
428 pci_write_config(bridge, 0x48, reg|0x40, 1);
429
430 /* XXX */
431 btag = I386_BUS_SPACE_IO;
432
433 for (i = 0; i < cnt; i++) {
434 bus_space_write_1(btag, 0x0, 0x70, i + off);
435 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
436 }
437
438 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
984263bc
MD
439}
440
49eef4c6
JS
441static void
442sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
984263bc 443{
49eef4c6 444 uint32_t filtsave, csrsave;
984263bc
MD
445
446 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
447 csrsave = CSR_READ_4(sc, SIS_CSR);
448
449 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
450 CSR_WRITE_4(sc, SIS_CSR, 0);
451
452 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
453
454 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
49eef4c6 455 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
984263bc 456 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
49eef4c6 457 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
984263bc 458 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
49eef4c6 459 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
984263bc
MD
460
461 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
462 CSR_WRITE_4(sc, SIS_CSR, csrsave);
984263bc
MD
463}
464#endif
465
466/*
467 * Sync the PHYs by setting data bit and strobing the clock 32 times.
468 */
49eef4c6
JS
469static void
470sis_mii_sync(struct sis_softc *sc)
984263bc 471{
49eef4c6 472 int i;
984263bc
MD
473
474 SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
475
476 for (i = 0; i < 32; i++) {
477 SIO_SET(SIS_MII_CLK);
478 DELAY(1);
479 SIO_CLR(SIS_MII_CLK);
480 DELAY(1);
481 }
984263bc
MD
482}
483
484/*
485 * Clock a series of bits through the MII.
486 */
49eef4c6
JS
487static void
488sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt)
984263bc 489{
49eef4c6 490 int i;
984263bc
MD
491
492 SIO_CLR(SIS_MII_CLK);
493
494 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
49eef4c6 495 if (bits & i)
984263bc 496 SIO_SET(SIS_MII_DATA);
49eef4c6 497 else
984263bc 498 SIO_CLR(SIS_MII_DATA);
984263bc
MD
499 DELAY(1);
500 SIO_CLR(SIS_MII_CLK);
501 DELAY(1);
502 SIO_SET(SIS_MII_CLK);
503 }
504}
505
506/*
507 * Read an PHY register through the MII.
508 */
49eef4c6
JS
509static int
510sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame)
984263bc 511{
49eef4c6 512 int i, ack, s;
984263bc
MD
513
514 s = splimp();
515
516 /*
517 * Set up frame for RX.
518 */
519 frame->mii_stdelim = SIS_MII_STARTDELIM;
520 frame->mii_opcode = SIS_MII_READOP;
521 frame->mii_turnaround = 0;
522 frame->mii_data = 0;
523
524 /*
525 * Turn on data xmit.
526 */
527 SIO_SET(SIS_MII_DIR);
528
529 sis_mii_sync(sc);
530
531 /*
532 * Send command/address info.
533 */
534 sis_mii_send(sc, frame->mii_stdelim, 2);
535 sis_mii_send(sc, frame->mii_opcode, 2);
536 sis_mii_send(sc, frame->mii_phyaddr, 5);
537 sis_mii_send(sc, frame->mii_regaddr, 5);
538
539 /* Idle bit */
540 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
541 DELAY(1);
542 SIO_SET(SIS_MII_CLK);
543 DELAY(1);
544
545 /* Turn off xmit. */
546 SIO_CLR(SIS_MII_DIR);
547
548 /* Check for ack */
549 SIO_CLR(SIS_MII_CLK);
550 DELAY(1);
551 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
552 SIO_SET(SIS_MII_CLK);
553 DELAY(1);
554
555 /*
556 * Now try reading data bits. If the ack failed, we still
557 * need to clock through 16 cycles to keep the PHY(s) in sync.
558 */
559 if (ack) {
560 for(i = 0; i < 16; i++) {
561 SIO_CLR(SIS_MII_CLK);
562 DELAY(1);
563 SIO_SET(SIS_MII_CLK);
564 DELAY(1);
565 }
566 goto fail;
567 }
568
569 for (i = 0x8000; i; i >>= 1) {
570 SIO_CLR(SIS_MII_CLK);
571 DELAY(1);
572 if (!ack) {
573 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
574 frame->mii_data |= i;
575 DELAY(1);
576 }
577 SIO_SET(SIS_MII_CLK);
578 DELAY(1);
579 }
580
581fail:
582
583 SIO_CLR(SIS_MII_CLK);
584 DELAY(1);
585 SIO_SET(SIS_MII_CLK);
586 DELAY(1);
587
588 splx(s);
589
590 if (ack)
591 return(1);
592 return(0);
593}
594
595/*
596 * Write to a PHY register through the MII.
597 */
49eef4c6
JS
598static int
599sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame)
984263bc 600{
49eef4c6 601 int s;
984263bc
MD
602
603 s = splimp();
604 /*
605 * Set up frame for TX.
606 */
607
608 frame->mii_stdelim = SIS_MII_STARTDELIM;
609 frame->mii_opcode = SIS_MII_WRITEOP;
610 frame->mii_turnaround = SIS_MII_TURNAROUND;
49eef4c6 611
984263bc 612 /*
49eef4c6 613 * Turn on data output.
984263bc
MD
614 */
615 SIO_SET(SIS_MII_DIR);
616
617 sis_mii_sync(sc);
618
619 sis_mii_send(sc, frame->mii_stdelim, 2);
620 sis_mii_send(sc, frame->mii_opcode, 2);
621 sis_mii_send(sc, frame->mii_phyaddr, 5);
622 sis_mii_send(sc, frame->mii_regaddr, 5);
623 sis_mii_send(sc, frame->mii_turnaround, 2);
624 sis_mii_send(sc, frame->mii_data, 16);
625
626 /* Idle bit. */
627 SIO_SET(SIS_MII_CLK);
628 DELAY(1);
629 SIO_CLR(SIS_MII_CLK);
630 DELAY(1);
631
632 /*
633 * Turn off xmit.
634 */
635 SIO_CLR(SIS_MII_DIR);
636
637 splx(s);
638
639 return(0);
640}
641
49eef4c6
JS
642static int
643sis_miibus_readreg(device_t dev, int phy, int reg)
984263bc 644{
49eef4c6
JS
645 struct sis_softc *sc;
646 struct sis_mii_frame frame;
984263bc
MD
647
648 sc = device_get_softc(dev);
649
650 if (sc->sis_type == SIS_TYPE_83815) {
651 if (phy != 0)
652 return(0);
653 /*
654 * The NatSemi chip can take a while after
655 * a reset to come ready, during which the BMSR
656 * returns a value of 0. This is *never* supposed
657 * to happen: some of the BMSR bits are meant to
658 * be hardwired in the on position, and this can
659 * confuse the miibus code a bit during the probe
660 * and attach phase. So we make an effort to check
661 * for this condition and wait for it to clear.
662 */
663 if (!CSR_READ_4(sc, NS_BMSR))
664 DELAY(1000);
665 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
666 }
667 /*
49eef4c6
JS
668 * Chipsets < SIS_635 seem not to be able to read/write
669 * through mdio. Use the enhanced PHY access register
670 * again for them.
671 */
984263bc
MD
672 if (sc->sis_type == SIS_TYPE_900 &&
673 sc->sis_rev < SIS_REV_635) {
49eef4c6 674 int i, val = 0;
984263bc
MD
675
676 if (phy != 0)
677 return(0);
678
679 CSR_WRITE_4(sc, SIS_PHYCTL,
680 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
681 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
682
683 for (i = 0; i < SIS_TIMEOUT; i++) {
684 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
685 break;
686 }
687
688 if (i == SIS_TIMEOUT) {
10c5bfa0 689 device_printf(dev, "PHY failed to come ready\n");
984263bc
MD
690 return(0);
691 }
692
693 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
694
695 if (val == 0xFFFF)
696 return(0);
697
698 return(val);
699 } else {
700 bzero((char *)&frame, sizeof(frame));
49eef4c6 701
984263bc
MD
702 frame.mii_phyaddr = phy;
703 frame.mii_regaddr = reg;
704 sis_mii_readreg(sc, &frame);
49eef4c6 705
984263bc
MD
706 return(frame.mii_data);
707 }
708}
709
49eef4c6
JS
710static int
711sis_miibus_writereg(device_t dev, int phy, int reg, int data)
984263bc 712{
49eef4c6
JS
713 struct sis_softc *sc;
714 struct sis_mii_frame frame;
984263bc
MD
715
716 sc = device_get_softc(dev);
717
718 if (sc->sis_type == SIS_TYPE_83815) {
719 if (phy != 0)
720 return(0);
721 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
722 return(0);
723 }
724
725 if (sc->sis_type == SIS_TYPE_900 &&
726 sc->sis_rev < SIS_REV_635) {
49eef4c6 727 int i;
984263bc
MD
728
729 if (phy != 0)
730 return(0);
49eef4c6 731
984263bc
MD
732 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
733 (reg << 6) | SIS_PHYOP_WRITE);
734 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
735
736 for (i = 0; i < SIS_TIMEOUT; i++) {
737 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
738 break;
739 }
49eef4c6 740
984263bc 741 if (i == SIS_TIMEOUT)
10c5bfa0 742 device_printf(dev, "PHY failed to come ready\n");
984263bc
MD
743 } else {
744 bzero((char *)&frame, sizeof(frame));
49eef4c6 745
984263bc
MD
746 frame.mii_phyaddr = phy;
747 frame.mii_regaddr = reg;
748 frame.mii_data = data;
749 sis_mii_writereg(sc, &frame);
750 }
751 return(0);
752}
753
49eef4c6 754static void sis_miibus_statchg(device_t dev)
984263bc 755{
49eef4c6 756 struct sis_softc *sc;
984263bc
MD
757
758 sc = device_get_softc(dev);
759 sis_init(sc);
984263bc
MD
760}
761
49eef4c6
JS
762static uint32_t
763sis_mchash(struct sis_softc *sc, const uint8_t *addr)
984263bc 764{
49eef4c6
JS
765 uint32_t crc, carry;
766 int i, j;
767 uint8_t c;
984263bc
MD
768
769 /* Compute CRC for the address value. */
770 crc = 0xFFFFFFFF; /* initial value */
771
772 for (i = 0; i < 6; i++) {
773 c = *(addr + i);
774 for (j = 0; j < 8; j++) {
775 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
776 crc <<= 1;
777 c >>= 1;
778 if (carry)
779 crc = (crc ^ 0x04c11db6) | carry;
780 }
781 }
782
783 /*
784 * return the filter bit position
785 *
786 * The NatSemi chip has a 512-bit filter, which is
787 * different than the SiS, so we special-case it.
788 */
789 if (sc->sis_type == SIS_TYPE_83815)
790 return (crc >> 23);
49eef4c6 791 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
984263bc
MD
792 return (crc >> 24);
793 else
794 return (crc >> 25);
795}
796
49eef4c6
JS
797static void
798sis_setmulti_ns(struct sis_softc *sc)
984263bc 799{
49eef4c6
JS
800 struct ifnet *ifp;
801 struct ifmultiaddr *ifma;
802 uint32_t h = 0, i, filtsave;
803 int bit, index;
984263bc
MD
804
805 ifp = &sc->arpcom.ac_if;
806
807 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
808 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
809 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
810 return;
811 }
812
813 /*
814 * We have to explicitly enable the multicast hash table
815 * on the NatSemi chip if we want to use it, which we do.
816 */
817 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
818 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
819
820 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
821
822 /* first, zot all the existing hash bits */
823 for (i = 0; i < 32; i++) {
824 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
825 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
826 }
827
49eef4c6 828 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
984263bc
MD
829 if (ifma->ifma_addr->sa_family != AF_LINK)
830 continue;
49eef4c6
JS
831 h = sis_mchash(sc,
832 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
984263bc
MD
833 index = h >> 3;
834 bit = h & 0x1F;
835 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
836 if (bit > 0xF)
837 bit -= 0x10;
838 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
839 }
840
841 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
984263bc
MD
842}
843
49eef4c6
JS
844static void
845sis_setmulti_sis(struct sis_softc *sc)
984263bc 846{
49eef4c6
JS
847 struct ifnet *ifp;
848 struct ifmultiaddr *ifma;
849 uint32_t h, i, n, ctl;
850 uint16_t hashes[16];
984263bc
MD
851
852 ifp = &sc->arpcom.ac_if;
853
854 /* hash table size */
49eef4c6 855 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
984263bc
MD
856 n = 16;
857 else
858 n = 8;
859
860 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;
861
862 if (ifp->if_flags & IFF_BROADCAST)
863 ctl |= SIS_RXFILTCTL_BROAD;
864
865 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
866 ctl |= SIS_RXFILTCTL_ALLMULTI;
867 if (ifp->if_flags & IFF_PROMISC)
868 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS;
869 for (i = 0; i < n; i++)
870 hashes[i] = ~0;
871 } else {
872 for (i = 0; i < n; i++)
873 hashes[i] = 0;
874 i = 0;
875 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
876 if (ifma->ifma_addr->sa_family != AF_LINK)
877 continue;
49eef4c6 878 h = sis_mchash(sc,
984263bc
MD
879 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
880 hashes[h >> 4] |= 1 << (h & 0xf);
881 i++;
882 }
883 if (i > n) {
884 ctl |= SIS_RXFILTCTL_ALLMULTI;
885 for (i = 0; i < n; i++)
886 hashes[i] = ~0;
887 }
888 }
889
890 for (i = 0; i < n; i++) {
891 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
892 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
893 }
894
895 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl);
896}
897
49eef4c6
JS
898static void
899sis_reset(struct sis_softc *sc)
984263bc 900{
10c5bfa0 901 struct ifnet *ifp = &sc->arpcom.ac_if;
49eef4c6 902 int i;
984263bc
MD
903
904 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
905
906 for (i = 0; i < SIS_TIMEOUT; i++) {
907 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
908 break;
909 }
910
911 if (i == SIS_TIMEOUT)
10c5bfa0 912 if_printf(ifp, "reset never completed\n");
984263bc
MD
913
914 /* Wait a little while for the chip to get its brains in order. */
915 DELAY(1000);
916
917 /*
918 * If this is a NetSemi chip, make sure to clear
919 * PME mode.
920 */
921 if (sc->sis_type == SIS_TYPE_83815) {
922 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
923 CSR_WRITE_4(sc, NS_CLKRUN, 0);
924 }
984263bc
MD
925}
926
927/*
928 * Probe for an SiS chip. Check the PCI vendor and device
929 * IDs against our list and return a device name if we find a match.
930 */
49eef4c6
JS
931static int
932sis_probe(device_t dev)
984263bc 933{
49eef4c6 934 struct sis_type *t;
984263bc
MD
935
936 t = sis_devs;
937
938 while(t->sis_name != NULL) {
939 if ((pci_get_vendor(dev) == t->sis_vid) &&
940 (pci_get_device(dev) == t->sis_did)) {
941 device_set_desc(dev, t->sis_name);
942 return(0);
943 }
944 t++;
945 }
946
947 return(ENXIO);
948}
949
950/*
951 * Attach the interface. Allocate softc structures, do ifmedia
952 * setup and ethernet/BPF attach.
953 */
49eef4c6
JS
954static int
955sis_attach(device_t dev)
984263bc 956{
49eef4c6
JS
957 uint8_t eaddr[ETHER_ADDR_LEN];
958 uint32_t command;
959 struct sis_softc *sc;
960 struct ifnet *ifp;
10c5bfa0 961 int error, rid, waittime;
984263bc 962
984263bc
MD
963 error = waittime = 0;
964 sc = device_get_softc(dev);
984263bc
MD
965 bzero(sc, sizeof(struct sis_softc));
966
967 if (pci_get_device(dev) == SIS_DEVICEID_900)
968 sc->sis_type = SIS_TYPE_900;
969 if (pci_get_device(dev) == SIS_DEVICEID_7016)
970 sc->sis_type = SIS_TYPE_7016;
971 if (pci_get_vendor(dev) == NS_VENDORID)
972 sc->sis_type = SIS_TYPE_83815;
973
974 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
975
976 /*
977 * Handle power management nonsense.
978 */
979
980 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF;
981 if (command == 0x01) {
982
983 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4);
984 if (command & SIS_PSTATE_MASK) {
49eef4c6 985 uint32_t iobase, membase, irq;
984263bc
MD
986
987 /* Save important PCI config data. */
988 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4);
989 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4);
990 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4);
991
992 /* Reset the power state. */
10c5bfa0
JS
993 device_printf(dev, "chip is in D%d power mode "
994 "-- setting to D0\n", command & SIS_PSTATE_MASK);
984263bc
MD
995 command &= 0xFFFFFFFC;
996 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4);
997
998 /* Restore PCI config data. */
999 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4);
1000 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4);
1001 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4);
1002 }
1003 }
1004
1005 /*
1006 * Map control/status registers.
1007 */
1008 command = pci_read_config(dev, PCIR_COMMAND, 4);
1009 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1010 pci_write_config(dev, PCIR_COMMAND, command, 4);
1011 command = pci_read_config(dev, PCIR_COMMAND, 4);
1012
1013#ifdef SIS_USEIOSPACE
1014 if (!(command & PCIM_CMD_PORTEN)) {
10c5bfa0 1015 device_printf(dev, "failed to enable I/O ports!\n");
984263bc
MD
1016 error = ENXIO;;
1017 goto fail;
1018 }
1019#else
1020 if (!(command & PCIM_CMD_MEMEN)) {
10c5bfa0 1021 device_printf(dev, "failed to enable memory mapping!\n");
984263bc
MD
1022 error = ENXIO;;
1023 goto fail;
1024 }
1025#endif
1026
1027 rid = SIS_RID;
1028 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid,
1029 0, ~0, 1, RF_ACTIVE);
1030
1031 if (sc->sis_res == NULL) {
10c5bfa0 1032 device_printf(dev, "couldn't map ports/memory\n");
984263bc
MD
1033 error = ENXIO;
1034 goto fail;
1035 }
1036
1037 sc->sis_btag = rman_get_bustag(sc->sis_res);
1038 sc->sis_bhandle = rman_get_bushandle(sc->sis_res);
1039
1040 /* Allocate interrupt */
1041 rid = 0;
1042 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1043 RF_SHAREABLE | RF_ACTIVE);
1044
1045 if (sc->sis_irq == NULL) {
10c5bfa0 1046 device_printf(dev, "couldn't map interrupt\n");
984263bc
MD
1047 error = ENXIO;
1048 goto fail;
1049 }
1050
984263bc
MD
1051 /* Reset the adapter. */
1052 sis_reset(sc);
1053
1054 if (sc->sis_type == SIS_TYPE_900 &&
1055 (sc->sis_rev == SIS_REV_635 ||
1056 sc->sis_rev == SIS_REV_900B)) {
1057 SIO_SET(SIS_CFG_RND_CNT);
1058 SIO_SET(SIS_CFG_PERR_DETECT);
1059 }
1060
1061 /*
1062 * Get station address from the EEPROM.
1063 */
1064 switch (pci_get_vendor(dev)) {
1065 case NS_VENDORID:
1066 /*
1067 * Reading the MAC address out of the EEPROM on
1068 * the NatSemi chip takes a bit more work than
1069 * you'd expect. The address spans 4 16-bit words,
1070 * with the first word containing only a single bit.
1071 * You have to shift everything over one bit to
1072 * get it aligned properly. Also, the bits are
1073 * stored backwards (the LSB is really the MSB,
1074 * and so on) so you have to reverse them in order
1075 * to get the MAC address into the form we want.
1076 * Why? Who the hell knows.
1077 */
1078 {
49eef4c6 1079 uint16_t tmp[4];
984263bc
MD
1080
1081 sis_read_eeprom(sc, (caddr_t)&tmp,
1082 NS_EE_NODEADDR, 4, 0);
1083
1084 /* Shift everything over one bit. */
1085 tmp[3] = tmp[3] >> 1;
1086 tmp[3] |= tmp[2] << 15;
1087 tmp[2] = tmp[2] >> 1;
1088 tmp[2] |= tmp[1] << 15;
1089 tmp[1] = tmp[1] >> 1;
1090 tmp[1] |= tmp[0] << 15;
1091
1092 /* Now reverse all the bits. */
1093 tmp[3] = sis_reverse(tmp[3]);
1094 tmp[2] = sis_reverse(tmp[2]);
1095 tmp[1] = sis_reverse(tmp[1]);
1096
1097 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
1098 }
1099 break;
1100 case SIS_VENDORID:
1101 default:
1102#ifdef __i386__
1103 /*
1104 * If this is a SiS 630E chipset with an embedded
1105 * SiS 900 controller, we have to read the MAC address
1106 * from the APC CMOS RAM. Our method for doing this
1107 * is very ugly since we have to reach out and grab
1108 * ahold of hardware for which we cannot properly
1109 * allocate resources. This code is only compiled on
1110 * the i386 architecture since the SiS 630E chipset
1111 * is for x86 motherboards only. Note that there are
1112 * a lot of magic numbers in this hack. These are
1113 * taken from SiS's Linux driver. I'd like to replace
1114 * them with proper symbolic definitions, but that
1115 * requires some datasheets that I don't have access
1116 * to at the moment.
1117 */
1118 if (sc->sis_rev == SIS_REV_630S ||
1119 sc->sis_rev == SIS_REV_630E ||
1120 sc->sis_rev == SIS_REV_630EA1)
1121 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1122
1123 else if (sc->sis_rev == SIS_REV_635 ||
1124 sc->sis_rev == SIS_REV_630ET)
1125 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1126 else if (sc->sis_rev == SIS_REV_96x) {
1127 /*
1128 * Allow to read EEPROM from LAN. It is shared
1129 * between a 1394 controller and the NIC and each
1130 * time we access it, we need to set SIS_EECMD_REQ.
1131 */
1132 SIO_SET(SIS_EECMD_REQ);
1133 for (waittime = 0; waittime < SIS_TIMEOUT;
1134 waittime++) {
1135 /* Force EEPROM to idle state. */
1136 sis_eeprom_idle(sc);
1137 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1138 sis_read_eeprom(sc, (caddr_t)&eaddr,
1139 SIS_EE_NODEADDR, 3, 0);
1140 break;
1141 }
1142 DELAY(1);
1143 }
1144 /*
1145 * Set SIS_EECTL_CLK to high, so a other master
1146 * can operate on the i2c bus.
1147 */
1148 SIO_SET(SIS_EECTL_CLK);
1149 /* Refuse EEPROM access by LAN */
1150 SIO_SET(SIS_EECMD_DONE);
1151 } else
1152#endif
1153 sis_read_eeprom(sc, (caddr_t)&eaddr,
1154 SIS_EE_NODEADDR, 3, 0);
1155 break;
1156 }
1157
5047f29c 1158 callout_init(&sc->sis_timer);
984263bc 1159
4ddeda6c
JS
1160 /*
1161 * Allocate the parent bus DMA tag appropriate for PCI.
1162 */
1163#define SIS_NSEG_NEW 32
1164 error = bus_dma_tag_create(NULL, /* parent */
1165 1, 0, /* alignment, boundary */
1166 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1167 BUS_SPACE_MAXADDR, /* highaddr */
1168 NULL, NULL, /* filter, filterarg */
1169 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */
1170 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1171 BUS_DMA_ALLOCNOW, /* flags */
1172 &sc->sis_parent_tag);
1173 if (error)
1174 goto fail;
984263bc 1175
4ddeda6c
JS
1176 /*
1177 * Now allocate a tag for the DMA descriptor lists and a chunk
1178 * of DMA-able memory based on the tag. Also obtain the physical
1179 * addresses of the RX and TX ring, which we'll need later.
1180 * All of our lists are allocated as a contiguous block of memory.
1181 */
1182 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1183 1, 0, /* alignment, boundary */
1184 BUS_SPACE_MAXADDR, /* lowaddr */
1185 BUS_SPACE_MAXADDR, /* highaddr */
1186 NULL, NULL, /* filter, filterarg */
1187 SIS_RX_LIST_SZ, 1, /* maxsize, nsegments */
1188 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1189 0, /* flags */
1190 &sc->sis_ldata.sis_rx_tag);
1191 if (error)
1192 goto fail;
1193
1194 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag,
1195 (void **)&sc->sis_ldata.sis_rx_list,
1196 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1197 &sc->sis_ldata.sis_rx_dmamap);
1198
1199 if (error) {
1200 device_printf(dev, "no memory for rx list buffers!\n");
1201 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1202 sc->sis_ldata.sis_rx_tag = NULL;
1203 goto fail;
1204 }
1205
1206 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag,
1207 sc->sis_ldata.sis_rx_dmamap,
1208 sc->sis_ldata.sis_rx_list,
1209 sizeof(struct sis_desc), sis_dma_map_ring,
1210 &sc->sis_cdata.sis_rx_paddr, 0);
1211
1212 if (error) {
1213 device_printf(dev, "cannot get address of the rx ring!\n");
1214 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1215 sc->sis_ldata.sis_rx_list,
1216 sc->sis_ldata.sis_rx_dmamap);
1217 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1218 sc->sis_ldata.sis_rx_tag = NULL;
1219 goto fail;
1220 }
1221
1222 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1223 1, 0, /* alignment, boundary */
1224 BUS_SPACE_MAXADDR, /* lowaddr */
1225 BUS_SPACE_MAXADDR, /* highaddr */
1226 NULL, NULL, /* filter, filterarg */
1227 SIS_TX_LIST_SZ, 1, /* maxsize, nsegments */
1228 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1229 0, /* flags */
1230 &sc->sis_ldata.sis_tx_tag);
1231 if (error)
1232 goto fail;
1233
1234 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag,
1235 (void **)&sc->sis_ldata.sis_tx_list,
1236 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1237 &sc->sis_ldata.sis_tx_dmamap);
1238
1239 if (error) {
1240 device_printf(dev, "no memory for tx list buffers!\n");
1241 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1242 sc->sis_ldata.sis_tx_tag = NULL;
1243 goto fail;
1244 }
1245
1246 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag,
1247 sc->sis_ldata.sis_tx_dmamap,
1248 sc->sis_ldata.sis_tx_list,
1249 sizeof(struct sis_desc), sis_dma_map_ring,
1250 &sc->sis_cdata.sis_tx_paddr, 0);
1251
1252 if (error) {
1253 device_printf(dev, "cannot get address of the tx ring!\n");
1254 bus_dmamem_free(sc->sis_ldata.sis_tx_tag,
1255 sc->sis_ldata.sis_tx_list,
1256 sc->sis_ldata.sis_tx_dmamap);
1257 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1258 sc->sis_ldata.sis_tx_tag = NULL;
984263bc
MD
1259 goto fail;
1260 }
4ddeda6c
JS
1261
1262 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1263 1, 0, /* alignment, boundary */
1264 BUS_SPACE_MAXADDR, /* lowaddr */
1265 BUS_SPACE_MAXADDR, /* highaddr */
1266 NULL, NULL, /* filter, filterarg */
1267 MCLBYTES, 1, /* maxsize, nsegments */
1268 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1269 0, /* flags */
1270 &sc->sis_tag);
1271 if (error)
1272 goto fail;
984263bc
MD
1273
1274 ifp = &sc->arpcom.ac_if;
1275 ifp->if_softc = sc;
10c5bfa0 1276 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
984263bc
MD
1277 ifp->if_mtu = ETHERMTU;
1278 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1279 ifp->if_ioctl = sis_ioctl;
984263bc
MD
1280 ifp->if_start = sis_start;
1281 ifp->if_watchdog = sis_watchdog;
1282 ifp->if_init = sis_init;
1283 ifp->if_baudrate = 10000000;
e25db1f0
JS
1284 ifq_set_maxlen(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
1285 ifq_set_ready(&ifp->if_snd);
d9168eb7
JS
1286#ifdef DEVICE_POLLING
1287 ifp->if_capabilities |= IFCAP_POLLING;
1288#endif
1289 ifp->if_capenable = ifp->if_capabilities;
984263bc
MD
1290
1291 /*
1292 * Do MII setup.
1293 */
1294 if (mii_phy_probe(dev, &sc->sis_miibus,
1295 sis_ifmedia_upd, sis_ifmedia_sts)) {
4ddeda6c 1296 device_printf(dev, "MII without any PHY!\n");
984263bc
MD
1297 error = ENXIO;
1298 goto fail;
1299 }
1300
1301 /*
1302 * Call MI attach routine.
1303 */
0a8b5977 1304 ether_ifattach(ifp, eaddr);
984263bc
MD
1305
1306 /*
1307 * Tell the upper layer(s) we support long frames.
1308 */
1309 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1310
4ddeda6c
JS
1311 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET,
1312 sis_intr, sc, &sc->sis_intrhand);
1313
1314 if (error) {
1315 device_printf(dev, "couldn't set up irq\n");
1316 ether_ifdetach(ifp);
1317 goto fail;
1318 }
1319
984263bc 1320fail:
4ddeda6c
JS
1321 if (error)
1322 sis_detach(dev);
1323
984263bc
MD
1324 return(error);
1325}
1326
4ddeda6c
JS
1327/*
1328 * Shutdown hardware and free up resources. It is called in both the error case
1329 * and the normal detach case so it needs to be careful about only freeing
1330 * resources that have actually been allocated.
1331 */
49eef4c6
JS
1332static int
1333sis_detach(device_t dev)
984263bc 1334{
49eef4c6
JS
1335 struct sis_softc *sc;
1336 struct ifnet *ifp;
1337 int s;
984263bc
MD
1338
1339 s = splimp();
1340
1341 sc = device_get_softc(dev);
1342 ifp = &sc->arpcom.ac_if;
1343
4ddeda6c
JS
1344 if (device_is_attached(dev)) {
1345 sis_reset(sc);
1346 sis_stop(sc);
1347 ether_ifdetach(ifp);
1348 }
1349 if (sc->sis_miibus)
1350 device_delete_child(dev, sc->sis_miibus);
984263bc 1351 bus_generic_detach(dev);
984263bc 1352
4ddeda6c
JS
1353 if (sc->sis_intrhand)
1354 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1355 if (sc->sis_irq)
1356 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1357 if (sc->sis_res)
1358 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
984263bc 1359
4ddeda6c
JS
1360 if (sc->sis_ldata.sis_rx_tag) {
1361 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag,
1362 sc->sis_ldata.sis_rx_dmamap);
1363 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1364 sc->sis_ldata.sis_rx_list,
1365 sc->sis_ldata.sis_rx_dmamap);
1366 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1367 }
1368
1369 if (sc->sis_ldata.sis_tx_tag) {
1370 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag,
1371 sc->sis_ldata.sis_tx_dmamap);
1372 bus_dmamem_free(sc->sis_ldata.sis_tx_tag,
1373 sc->sis_ldata.sis_tx_list,
1374 sc->sis_ldata.sis_tx_dmamap);
1375 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1376 }
1377 if (sc->sis_tag)
1378 bus_dma_tag_destroy(sc->sis_tag);
1379 if (sc->sis_parent_tag)
1380 bus_dma_tag_destroy(sc->sis_parent_tag);
984263bc
MD
1381
1382 splx(s);
1383
1384 return(0);
1385}
1386
1387/*
1388 * Initialize the transmit descriptors.
1389 */
49eef4c6
JS
1390static int
1391sis_list_tx_init(struct sis_softc *sc)
984263bc 1392{
49eef4c6
JS
1393 struct sis_list_data *ld;
1394 struct sis_ring_data *cd;
1395 int i, nexti;
984263bc
MD
1396
1397 cd = &sc->sis_cdata;
4ddeda6c 1398 ld = &sc->sis_ldata;
984263bc
MD
1399
1400 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1401 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1;
1402 ld->sis_tx_list[i].sis_nextdesc =
1403 &ld->sis_tx_list[nexti];
4ddeda6c
JS
1404 bus_dmamap_load(sc->sis_ldata.sis_tx_tag,
1405 sc->sis_ldata.sis_tx_dmamap,
1406 &ld->sis_tx_list[nexti],
1407 sizeof(struct sis_desc), sis_dma_map_desc_next,
1408 &ld->sis_tx_list[i], 0);
984263bc
MD
1409 ld->sis_tx_list[i].sis_mbuf = NULL;
1410 ld->sis_tx_list[i].sis_ptr = 0;
1411 ld->sis_tx_list[i].sis_ctl = 0;
1412 }
1413
1414 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0;
1415
4ddeda6c
JS
1416 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, sc->sis_ldata.sis_tx_dmamap,
1417 BUS_DMASYNC_PREWRITE);
1418
984263bc
MD
1419 return(0);
1420}
1421
984263bc
MD
1422/*
1423 * Initialize the RX descriptors and allocate mbufs for them. Note that
1424 * we arrange the descriptors in a closed ring, so that the last descriptor
1425 * points back to the first.
1426 */
49eef4c6
JS
1427static int
1428sis_list_rx_init(struct sis_softc *sc)
984263bc 1429{
49eef4c6
JS
1430 struct sis_list_data *ld;
1431 struct sis_ring_data *cd;
1432 int i, nexti;
984263bc 1433
4ddeda6c 1434 ld = &sc->sis_ldata;
984263bc
MD
1435 cd = &sc->sis_cdata;
1436
1437 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1438 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS)
1439 return(ENOBUFS);
1440 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1;
1441 ld->sis_rx_list[i].sis_nextdesc =
1442 &ld->sis_rx_list[nexti];
4ddeda6c
JS
1443 bus_dmamap_load(sc->sis_ldata.sis_rx_tag,
1444 sc->sis_ldata.sis_rx_dmamap,
1445 &ld->sis_rx_list[nexti],
1446 sizeof(struct sis_desc), sis_dma_map_desc_next,
1447 &ld->sis_rx_list[i], 0);
984263bc
MD
1448 }
1449
4ddeda6c
JS
1450 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, sc->sis_ldata.sis_rx_dmamap,
1451 BUS_DMASYNC_PREWRITE);
1452
984263bc
MD
1453 cd->sis_rx_prod = 0;
1454
1455 return(0);
1456}
1457
1458/*
1459 * Initialize an RX descriptor and attach an MBUF cluster.
1460 */
49eef4c6
JS
1461static int
1462sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m)
984263bc 1463{
984263bc 1464 if (m == NULL) {
74f1caca 1465 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
984263bc
MD
1466 if (m == NULL)
1467 return(ENOBUFS);
1468 } else {
1469 m->m_data = m->m_ext.ext_buf;
1470 }
1471
1472 c->sis_mbuf = m;
984263bc
MD
1473 c->sis_ctl = SIS_RXLEN;
1474
4ddeda6c
JS
1475 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map);
1476 bus_dmamap_load(sc->sis_tag, c->sis_map, mtod(m, void *), MCLBYTES,
1477 sis_dma_map_desc_ptr, c, 0);
1478 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE);
1479
984263bc
MD
1480 return(0);
1481}
1482
1483/*
1484 * A frame has been uploaded: pass the resulting mbuf chain up to
1485 * the higher level protocols.
1486 */
49eef4c6
JS
1487static void
1488sis_rxeof(struct sis_softc *sc)
984263bc 1489{
49eef4c6
JS
1490 struct mbuf *m;
1491 struct ifnet *ifp;
1492 struct sis_desc *cur_rx;
1493 int i, total_len = 0;
1494 uint32_t rxstat;
984263bc
MD
1495
1496 ifp = &sc->arpcom.ac_if;
1497 i = sc->sis_cdata.sis_rx_prod;
1498
4ddeda6c 1499 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) {
984263bc
MD
1500
1501#ifdef DEVICE_POLLING
46f25451 1502 if (ifp->if_flags & IFF_POLLING) {
984263bc
MD
1503 if (sc->rxcycles <= 0)
1504 break;
1505 sc->rxcycles--;
1506 }
1507#endif /* DEVICE_POLLING */
4ddeda6c 1508 cur_rx = &sc->sis_ldata.sis_rx_list[i];
984263bc 1509 rxstat = cur_rx->sis_rxstat;
4ddeda6c
JS
1510 bus_dmamap_sync(sc->sis_tag, cur_rx->sis_map,
1511 BUS_DMASYNC_POSTWRITE);
1512 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map);
1513 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map);
984263bc
MD
1514 m = cur_rx->sis_mbuf;
1515 cur_rx->sis_mbuf = NULL;
1516 total_len = SIS_RXBYTES(cur_rx);
1517 SIS_INC(i, SIS_RX_LIST_CNT);
1518
1519 /*
1520 * If an error occurs, update stats, clear the
1521 * status word and leave the mbuf cluster in place:
1522 * it should simply get re-used next time this descriptor
1523 * comes up in the ring.
1524 */
1525 if (!(rxstat & SIS_CMDSTS_PKT_OK)) {
1526 ifp->if_ierrors++;
1527 if (rxstat & SIS_RXSTAT_COLL)
1528 ifp->if_collisions++;
1529 sis_newbuf(sc, cur_rx, m);
1530 continue;
1531 }
1532
1533 /* No errors; receive the packet. */
1534#ifdef __i386__
1535 /*
1536 * On the x86 we do not have alignment problems, so try to
1537 * allocate a new buffer for the receive ring, and pass up
1538 * the one where the packet is already, saving the expensive
1539 * copy done in m_devget().
1540 * If we are on an architecture with alignment problems, or
1541 * if the allocation fails, then use m_devget and leave the
1542 * existing buffer in the receive ring.
1543 */
1544 if (sis_newbuf(sc, cur_rx, NULL) == 0)
1545 m->m_pkthdr.len = m->m_len = total_len;
1546 else
1547#endif
1548 {
1549 struct mbuf *m0;
1550 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1551 total_len + ETHER_ALIGN, 0, ifp, NULL);
1552 sis_newbuf(sc, cur_rx, m);
1553 if (m0 == NULL) {
1554 ifp->if_ierrors++;
1555 continue;
1556 }
1557 m_adj(m0, ETHER_ALIGN);
1558 m = m0;
1559 }
1560
1561 ifp->if_ipackets++;
3013ac0e 1562 (*ifp->if_input)(ifp, m);
984263bc
MD
1563 }
1564
1565 sc->sis_cdata.sis_rx_prod = i;
984263bc
MD
1566}
1567
49eef4c6
JS
1568static void
1569sis_rxeoc(struct sis_softc *sc)
984263bc
MD
1570{
1571 sis_rxeof(sc);
4ddeda6c 1572 sis_init(sc);
984263bc
MD
1573}
1574
1575/*
1576 * A frame was downloaded to the chip. It's safe for us to clean up
1577 * the list buffers.
1578 */
1579
49eef4c6
JS
1580static void
1581sis_txeof(struct sis_softc *sc)
984263bc 1582{
4ddeda6c 1583 struct sis_desc *cur_tx;
49eef4c6
JS
1584 struct ifnet *ifp;
1585 uint32_t idx;
984263bc
MD
1586
1587 ifp = &sc->arpcom.ac_if;
1588
1589 /*
1590 * Go through our tx list and free mbufs for those
1591 * frames that have been transmitted.
1592 */
4ddeda6c
JS
1593 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0;
1594 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) {
1595 cur_tx = &sc->sis_ldata.sis_tx_list[idx];
984263bc
MD
1596
1597 if (SIS_OWNDESC(cur_tx))
1598 break;
1599
4ddeda6c 1600 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE)
984263bc 1601 continue;
984263bc
MD
1602
1603 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) {
1604 ifp->if_oerrors++;
1605 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS)
1606 ifp->if_collisions++;
1607 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL)
1608 ifp->if_collisions++;
1609 }
1610
1611 ifp->if_collisions +=
1612 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16;
1613
1614 ifp->if_opackets++;
1615 if (cur_tx->sis_mbuf != NULL) {
1616 m_freem(cur_tx->sis_mbuf);
1617 cur_tx->sis_mbuf = NULL;
4ddeda6c
JS
1618 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map);
1619 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map);
984263bc 1620 }
984263bc
MD
1621 }
1622
1623 if (idx != sc->sis_cdata.sis_tx_cons) {
4ddeda6c 1624 /* we freed up some buffers */
984263bc
MD
1625 sc->sis_cdata.sis_tx_cons = idx;
1626 ifp->if_flags &= ~IFF_OACTIVE;
1627 }
49eef4c6 1628
984263bc 1629 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5;
984263bc
MD
1630}
1631
49eef4c6
JS
1632static void
1633sis_tick(void *xsc)
984263bc 1634{
49eef4c6
JS
1635 struct sis_softc *sc;
1636 struct mii_data *mii;
1637 struct ifnet *ifp;
1638 int s;
984263bc
MD
1639
1640 s = splimp();
1641
1642 sc = xsc;
1643 ifp = &sc->arpcom.ac_if;
1644
1645 mii = device_get_softc(sc->sis_miibus);
1646 mii_tick(mii);
1647
1648 if (!sc->sis_link) {
1649 mii_pollstat(mii);
1650 if (mii->mii_media_status & IFM_ACTIVE &&
1651 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1652 sc->sis_link++;
e25db1f0
JS
1653 if (!ifq_is_empty(&ifp->if_snd))
1654 sis_start(ifp);
984263bc
MD
1655 }
1656
5047f29c 1657 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
984263bc
MD
1658
1659 splx(s);
984263bc
MD
1660}
1661
1662#ifdef DEVICE_POLLING
1663static poll_handler_t sis_poll;
1664
1665static void
1666sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1667{
1668 struct sis_softc *sc = ifp->if_softc;
1669
d9168eb7
JS
1670 if ((ifp->if_capenable & IFCAP_POLLING) == 0) {
1671 ether_poll_deregister(ifp);
1672 cmd = POLL_DEREGISTER;
1673 }
984263bc
MD
1674 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1675 CSR_WRITE_4(sc, SIS_IER, 1);
1676 return;
1677 }
1678
1679 /*
1680 * On the sis, reading the status register also clears it.
1681 * So before returning to intr mode we must make sure that all
1682 * possible pending sources of interrupts have been served.
1683 * In practice this means run to completion the *eof routines,
1684 * and then call the interrupt routine
1685 */
1686 sc->rxcycles = count;
1687 sis_rxeof(sc);
1688 sis_txeof(sc);
e25db1f0 1689 if (!ifq_is_empty(&ifp->if_snd))
984263bc
MD
1690 sis_start(ifp);
1691
1692 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
49eef4c6 1693 uint32_t status;
984263bc
MD
1694
1695 /* Reading the ISR register clears all interrupts. */
1696 status = CSR_READ_4(sc, SIS_ISR);
1697
1698 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1699 sis_rxeoc(sc);
1700
1701 if (status & (SIS_ISR_RX_IDLE))
1702 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1703
1704 if (status & SIS_ISR_SYSERR) {
1705 sis_reset(sc);
1706 sis_init(sc);
1707 }
1708 }
1709}
1710#endif /* DEVICE_POLLING */
1711
49eef4c6
JS
1712static void
1713sis_intr(void *arg)
984263bc 1714{
49eef4c6
JS
1715 struct sis_softc *sc;
1716 struct ifnet *ifp;
1717 uint32_t status;
984263bc
MD
1718
1719 sc = arg;
1720 ifp = &sc->arpcom.ac_if;
1721
1722#ifdef DEVICE_POLLING
46f25451 1723 if (ifp->if_flags & IFF_POLLING)
984263bc 1724 return;
d9168eb7
JS
1725 if ((ifp->if_capenable & IFCAP_POLLING) &&
1726 ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */
984263bc
MD
1727 CSR_WRITE_4(sc, SIS_IER, 0);
1728 sis_poll(ifp, 0, 1);
1729 return;
1730 }
1731#endif /* DEVICE_POLLING */
1732
1733 /* Supress unwanted interrupts */
1734 if (!(ifp->if_flags & IFF_UP)) {
1735 sis_stop(sc);
1736 return;
1737 }
1738
1739 /* Disable interrupts. */
1740 CSR_WRITE_4(sc, SIS_IER, 0);
1741
1742 for (;;) {
1743 /* Reading the ISR register clears all interrupts. */
1744 status = CSR_READ_4(sc, SIS_ISR);
1745
1746 if ((status & SIS_INTRS) == 0)
1747 break;
1748
1749 if (status &
49eef4c6
JS
1750 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK |
1751 SIS_ISR_TX_IDLE) )
984263bc
MD
1752 sis_txeof(sc);
1753
49eef4c6
JS
1754 if (status &
1755 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE))
984263bc
MD
1756 sis_rxeof(sc);
1757
49eef4c6 1758 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW))
984263bc
MD
1759 sis_rxeoc(sc);
1760
1761 if (status & (SIS_ISR_RX_IDLE))
1762 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1763
1764 if (status & SIS_ISR_SYSERR) {
1765 sis_reset(sc);
1766 sis_init(sc);
1767 }
1768 }
1769
1770 /* Re-enable interrupts. */
1771 CSR_WRITE_4(sc, SIS_IER, 1);
1772
e25db1f0 1773 if (!ifq_is_empty(&ifp->if_snd))
984263bc 1774 sis_start(ifp);
984263bc
MD
1775}
1776
1777/*
1778 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1779 * pointers to the fragment pointers.
1780 */
49eef4c6
JS
1781static int
1782sis_encap(struct sis_softc *sc, struct mbuf *m_head, uint32_t *txidx)
984263bc 1783{
49eef4c6
JS
1784 struct sis_desc *f = NULL;
1785 struct mbuf *m;
1786 int frag, cur, cnt = 0;
984263bc 1787
4ddeda6c
JS
1788 /*
1789 * If there's no way we can send any packets, return now.
1790 */
1791 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2)
1792 return (ENOBUFS);
1793
984263bc
MD
1794 /*
1795 * Start packing the mbufs in this chain into
1796 * the fragment pointers. Stop when we run out
1797 * of fragments or hit the end of the mbuf chain.
1798 */
1799 m = m_head;
1800 cur = frag = *txidx;
1801
1802 for (m = m_head; m != NULL; m = m->m_next) {
1803 if (m->m_len != 0) {
1804 if ((SIS_TX_LIST_CNT -
1805 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2)
1806 return(ENOBUFS);
4ddeda6c 1807 f = &sc->sis_ldata.sis_tx_list[frag];
984263bc 1808 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len;
4ddeda6c
JS
1809 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map);
1810 bus_dmamap_load(sc->sis_tag, f->sis_map,
1811 mtod(m, void *), m->m_len,
1812 sis_dma_map_desc_ptr, f, 0);
1813 bus_dmamap_sync(sc->sis_tag, f->sis_map,
1814 BUS_DMASYNC_PREREAD);
984263bc
MD
1815 if (cnt != 0)
1816 f->sis_ctl |= SIS_CMDSTS_OWN;
1817 cur = frag;
1818 SIS_INC(frag, SIS_TX_LIST_CNT);
1819 cnt++;
1820 }
1821 }
1822
1823 if (m != NULL)
1824 return(ENOBUFS);
1825
4ddeda6c
JS
1826 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head;
1827 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE;
1828 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN;
984263bc
MD
1829 sc->sis_cdata.sis_tx_cnt += cnt;
1830 *txidx = frag;
1831
1832 return(0);
1833}
1834
1835/*
1836 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1837 * to the mbuf data regions directly in the transmit lists. We also save a
1838 * copy of the pointers since the transmit list fragment pointers are
1839 * physical addresses.
1840 */
1841
49eef4c6
JS
1842static void
1843sis_start(struct ifnet *ifp)
984263bc 1844{
49eef4c6
JS
1845 struct sis_softc *sc;
1846 struct mbuf *m_head = NULL;
1847 uint32_t idx;
984263bc
MD
1848
1849 sc = ifp->if_softc;
1850
1851 if (!sc->sis_link)
1852 return;
1853
1854 idx = sc->sis_cdata.sis_tx_prod;
1855
1856 if (ifp->if_flags & IFF_OACTIVE)
1857 return;
1858
4ddeda6c 1859 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) {
e25db1f0 1860 m_head = ifq_poll(&ifp->if_snd);
984263bc
MD
1861 if (m_head == NULL)
1862 break;
1863
1864 if (sis_encap(sc, m_head, &idx)) {
984263bc
MD
1865 ifp->if_flags |= IFF_OACTIVE;
1866 break;
1867 }
e25db1f0 1868 m_head = ifq_dequeue(&ifp->if_snd);
984263bc
MD
1869
1870 /*
1871 * If there's a BPF listener, bounce a copy of this frame
1872 * to him.
1873 */
49eef4c6 1874 BPF_MTAP(ifp, m_head);
984263bc
MD
1875 }
1876
1877 /* Transmit */
1878 sc->sis_cdata.sis_tx_prod = idx;
1879 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1880
1881 /*
1882 * Set a timeout in case the chip goes out to lunch.
1883 */
1884 ifp->if_timer = 5;
984263bc
MD
1885}
1886
49eef4c6
JS
1887static void
1888sis_init(void *xsc)
984263bc 1889{
49eef4c6
JS
1890 struct sis_softc *sc = xsc;
1891 struct ifnet *ifp = &sc->arpcom.ac_if;
1892 struct mii_data *mii;
1893 int s;
984263bc
MD
1894
1895 s = splimp();
1896
1897 /*
1898 * Cancel pending I/O and free all RX/TX buffers.
1899 */
1900 sis_stop(sc);
1901
1902 mii = device_get_softc(sc->sis_miibus);
1903
1904 /* Set MAC address */
1905 if (sc->sis_type == SIS_TYPE_83815) {
1906 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1907 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
49eef4c6 1908 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
984263bc
MD
1909 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1910 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
49eef4c6 1911 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
984263bc
MD
1912 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1913 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
49eef4c6 1914 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
984263bc
MD
1915 } else {
1916 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1917 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
49eef4c6 1918 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
984263bc
MD
1919 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1920 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
49eef4c6 1921 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
984263bc
MD
1922 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1923 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
49eef4c6 1924 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
984263bc
MD
1925 }
1926
1927 /* Init circular RX list. */
1928 if (sis_list_rx_init(sc) == ENOBUFS) {
10c5bfa0
JS
1929 if_printf(ifp, "initialization failed: "
1930 "no memory for rx buffers\n");
984263bc 1931 sis_stop(sc);
49eef4c6 1932 splx(s);
984263bc
MD
1933 return;
1934 }
1935
1936 /*
1937 * Init tx descriptors.
1938 */
1939 sis_list_tx_init(sc);
1940
1941 /*
1942 * For the NatSemi chip, we have to explicitly enable the
1943 * reception of ARP frames, as well as turn on the 'perfect
1944 * match' filter where we store the station address, otherwise
1945 * we won't receive unicasts meant for this host.
1946 */
1947 if (sc->sis_type == SIS_TYPE_83815) {
1948 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
1949 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
1950 }
1951
1952 /* If we want promiscuous mode, set the allframes bit. */
49eef4c6 1953 if (ifp->if_flags & IFF_PROMISC)
984263bc 1954 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
49eef4c6 1955 else
984263bc 1956 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
984263bc
MD
1957
1958 /*
1959 * Set the capture broadcast bit to capture broadcast frames.
1960 */
49eef4c6 1961 if (ifp->if_flags & IFF_BROADCAST)
984263bc 1962 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
49eef4c6 1963 else
984263bc 1964 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
984263bc
MD
1965
1966 /*
1967 * Load the multicast filter.
1968 */
1969 if (sc->sis_type == SIS_TYPE_83815)
1970 sis_setmulti_ns(sc);
1971 else
1972 sis_setmulti_sis(sc);
1973
1974 /* Turn the receive filter on */
1975 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
1976
1977 /*
1978 * Load the address of the RX and TX lists.
1979 */
4ddeda6c
JS
1980 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr);
1981 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr);
984263bc
MD
1982
1983 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
1984 * the PCI bus. When this bit is set, the Max DMA Burst Size
1985 * for TX/RX DMA should be no larger than 16 double words.
1986 */
49eef4c6 1987 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN)
984263bc 1988 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
49eef4c6 1989 else
984263bc 1990 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
984263bc
MD
1991
1992 /* Accept Long Packets for VLAN support */
1993 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
1994
1995 /* Set TX configuration */
49eef4c6 1996 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)
984263bc 1997 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
49eef4c6 1998 else
984263bc 1999 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
984263bc
MD
2000
2001 /* Set full/half duplex mode. */
2002 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
2003 SIS_SETBIT(sc, SIS_TX_CFG,
2004 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
2005 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
2006 } else {
2007 SIS_CLRBIT(sc, SIS_TX_CFG,
2008 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
2009 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
2010 }
2011
2012 /*
2013 * Enable interrupts.
2014 */
2015 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
2016#ifdef DEVICE_POLLING
2017 /*
2018 * ... only enable interrupts if we are not polling, make sure
2019 * they are off otherwise.
2020 */
46f25451 2021 if (ifp->if_flags & IFF_POLLING)
984263bc
MD
2022 CSR_WRITE_4(sc, SIS_IER, 0);
2023 else
2024#endif /* DEVICE_POLLING */
2025 CSR_WRITE_4(sc, SIS_IER, 1);
2026
2027 /* Enable receiver and transmitter. */
2028 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2029 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
2030
2031#ifdef notdef
2032 mii_mediachg(mii);
2033#endif
2034
2035 /*
2036 * Page 75 of the DP83815 manual recommends the
2037 * following register settings "for optimum
2038 * performance." Note however that at least three
2039 * of the registers are listed as "reserved" in
2040 * the register map, so who knows what they do.
2041 */
2042 if (sc->sis_type == SIS_TYPE_83815) {
2043 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
2044 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
2045 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
2046 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
2047 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
2048 }
2049
2050 ifp->if_flags |= IFF_RUNNING;
2051 ifp->if_flags &= ~IFF_OACTIVE;
2052
49eef4c6 2053 splx(s);
984263bc 2054
5047f29c 2055 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
984263bc
MD
2056}
2057
2058/*
2059 * Set media options.
2060 */
49eef4c6
JS
2061static int
2062sis_ifmedia_upd(struct ifnet *ifp)
984263bc 2063{
49eef4c6
JS
2064 struct sis_softc *sc;
2065 struct mii_data *mii;
984263bc
MD
2066
2067 sc = ifp->if_softc;
2068
2069 mii = device_get_softc(sc->sis_miibus);
2070 sc->sis_link = 0;
2071 if (mii->mii_instance) {
2072 struct mii_softc *miisc;
49eef4c6 2073 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
984263bc
MD
2074 mii_phy_reset(miisc);
2075 }
2076 mii_mediachg(mii);
2077
2078 return(0);
2079}
2080
2081/*
2082 * Report current media status.
2083 */
49eef4c6
JS
2084static void
2085sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc 2086{
49eef4c6
JS
2087 struct sis_softc *sc;
2088 struct mii_data *mii;
984263bc
MD
2089
2090 sc = ifp->if_softc;
2091
2092 mii = device_get_softc(sc->sis_miibus);
2093 mii_pollstat(mii);
2094 ifmr->ifm_active = mii->mii_media_active;
2095 ifmr->ifm_status = mii->mii_media_status;
984263bc
MD
2096}
2097
49eef4c6 2098static int
bd4539cc 2099sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc 2100{
49eef4c6
JS
2101 struct sis_softc *sc = ifp->if_softc;
2102 struct ifreq *ifr = (struct ifreq *) data;
2103 struct mii_data *mii;
2104 int s, error = 0;
984263bc 2105
984263bc 2106 switch(command) {
984263bc
MD
2107 case SIOCSIFFLAGS:
2108 if (ifp->if_flags & IFF_UP) {
2109 sis_init(sc);
2110 } else {
2111 if (ifp->if_flags & IFF_RUNNING)
2112 sis_stop(sc);
2113 }
2114 error = 0;
2115 break;
2116 case SIOCADDMULTI:
2117 case SIOCDELMULTI:
4ddeda6c 2118 s = splimp();
984263bc
MD
2119 if (sc->sis_type == SIS_TYPE_83815)
2120 sis_setmulti_ns(sc);
2121 else
2122 sis_setmulti_sis(sc);
4ddeda6c 2123 splx(s);
984263bc
MD
2124 error = 0;
2125 break;
2126 case SIOCGIFMEDIA:
2127 case SIOCSIFMEDIA:
2128 mii = device_get_softc(sc->sis_miibus);
4ddeda6c 2129 s = splimp();
984263bc 2130 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
4ddeda6c 2131 splx(s);
984263bc
MD
2132 break;
2133 default:
4ddeda6c 2134 error = ether_ioctl(ifp, command, data);
984263bc
MD
2135 break;
2136 }
2137
984263bc
MD
2138 return(error);
2139}
2140
49eef4c6
JS
2141static void
2142sis_watchdog(struct ifnet *ifp)
984263bc 2143{
49eef4c6 2144 struct sis_softc *sc;
984263bc
MD
2145
2146 sc = ifp->if_softc;
2147
2148 ifp->if_oerrors++;
10c5bfa0 2149 if_printf(ifp, "watchdog timeout\n");
984263bc
MD
2150
2151 sis_stop(sc);
2152 sis_reset(sc);
2153 sis_init(sc);
2154
e25db1f0 2155 if (!ifq_is_empty(&ifp->if_snd))
984263bc 2156 sis_start(ifp);
984263bc
MD
2157}
2158
2159/*
2160 * Stop the adapter and free any mbufs allocated to the
2161 * RX and TX lists.
2162 */
49eef4c6
JS
2163static void
2164sis_stop(struct sis_softc *sc)
984263bc 2165{
49eef4c6
JS
2166 int i;
2167 struct ifnet *ifp;
984263bc
MD
2168
2169 ifp = &sc->arpcom.ac_if;
2170 ifp->if_timer = 0;
2171
5047f29c 2172 callout_stop(&sc->sis_timer);
984263bc
MD
2173
2174 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2175#ifdef DEVICE_POLLING
2176 ether_poll_deregister(ifp);
2177#endif
2178 CSR_WRITE_4(sc, SIS_IER, 0);
2179 CSR_WRITE_4(sc, SIS_IMR, 0);
2180 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2181 DELAY(1000);
2182 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2183 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2184
2185 sc->sis_link = 0;
2186
2187 /*
2188 * Free data in the RX lists.
2189 */
2190 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
4ddeda6c
JS
2191 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) {
2192 bus_dmamap_unload(sc->sis_tag,
2193 sc->sis_ldata.sis_rx_list[i].sis_map);
2194 bus_dmamap_destroy(sc->sis_tag,
2195 sc->sis_ldata.sis_rx_list[i].sis_map);
2196 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf);
2197 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL;
984263bc
MD
2198 }
2199 }
4ddeda6c 2200 bzero(sc->sis_ldata.sis_rx_list, sizeof(sc->sis_ldata.sis_rx_list));
984263bc
MD
2201
2202 /*
2203 * Free the TX list buffers.
2204 */
2205 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
4ddeda6c
JS
2206 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) {
2207 bus_dmamap_unload(sc->sis_tag,
2208 sc->sis_ldata.sis_tx_list[i].sis_map);
2209 bus_dmamap_destroy(sc->sis_tag,
2210 sc->sis_ldata.sis_tx_list[i].sis_map);
2211 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf);
2212 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL;
984263bc
MD
2213 }
2214 }
2215
4ddeda6c 2216 bzero(sc->sis_ldata.sis_tx_list, sizeof(sc->sis_ldata.sis_tx_list));
984263bc
MD
2217}
2218
2219/*
2220 * Stop all chip I/O so that the kernel's probe routines don't
2221 * get confused by errant DMAs when rebooting.
2222 */
49eef4c6
JS
2223static void
2224sis_shutdown(device_t dev)
984263bc
MD
2225{
2226 struct sis_softc *sc;
2227
2228 sc = device_get_softc(dev);
2229
2230 sis_reset(sc);
2231 sis_stop(sc);
984263bc 2232}