MPSAFE locking for the ahc/ahd drivers using lockmgr locks.
[dragonfly.git] / sys / dev / disk / aic7xxx / aic79xx.h
CommitLineData
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1/*
2 * Core definitions and data structures shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
f39dcdf3 40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#107 $
984263bc 41 *
2923a98d 42 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.h,v 1.27 2007/04/19 18:53:52 scottl Exp $
ef8ef949 43 * $DragonFly: src/sys/dev/disk/aic7xxx/aic79xx.h,v 1.14 2008/02/09 18:13:13 pavalos Exp $
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44 */
45
46#ifndef _AIC79XX_H_
47#define _AIC79XX_H_
48
49/* Register Definitions */
50#include "aic79xx_reg.h"
51
52/************************* Forward Declarations *******************************/
53struct ahd_platform_data;
54struct scb_platform_data;
55
56/****************************** Useful Macros *********************************/
57#ifndef MAX
58#define MAX(a,b) (((a) > (b)) ? (a) : (b))
59#endif
60
61#ifndef MIN
62#define MIN(a,b) (((a) < (b)) ? (a) : (b))
63#endif
64
65#ifndef TRUE
66#define TRUE 1
67#endif
68#ifndef FALSE
69#define FALSE 0
70#endif
71
72#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array))
73
74#define ALL_CHANNELS '\0'
75#define ALL_TARGETS_MASK 0xFFFF
76#define INITIATOR_WILDCARD (~0)
77#define SCB_LIST_NULL 0xFF00
750f3593 78#define SCB_LIST_NULL_LE (aic_htole16(SCB_LIST_NULL))
7009d94e 79#define QOUTFIFO_ENTRY_VALID 0x80
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80#define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL)
81
82#define SCSIID_TARGET(ahd, scsiid) \
83 (((scsiid) & TID) >> TID_SHIFT)
84#define SCSIID_OUR_ID(scsiid) \
85 ((scsiid) & OID)
86#define SCSIID_CHANNEL(ahd, scsiid) ('A')
87#define SCB_IS_SCSIBUS_B(ahd, scb) (0)
88#define SCB_GET_OUR_ID(scb) \
89 SCSIID_OUR_ID((scb)->hscb->scsiid)
90#define SCB_GET_TARGET(ahd, scb) \
91 SCSIID_TARGET((ahd), (scb)->hscb->scsiid)
92#define SCB_GET_CHANNEL(ahd, scb) \
93 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid)
94#define SCB_GET_LUN(scb) \
95 ((scb)->hscb->lun)
96#define SCB_GET_TARGET_OFFSET(ahd, scb) \
97 SCB_GET_TARGET(ahd, scb)
98#define SCB_GET_TARGET_MASK(ahd, scb) \
99 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb)))
100#ifdef AHD_DEBUG
101#define SCB_IS_SILENT(scb) \
102 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \
103 && (((scb)->flags & SCB_SILENT) != 0))
104#else
105#define SCB_IS_SILENT(scb) \
106 (((scb)->flags & SCB_SILENT) != 0)
107#endif
108/*
109 * TCLs have the following format: TTTTLLLLLLLL
110 */
111#define TCL_TARGET_OFFSET(tcl) \
112 ((((tcl) >> 4) & TID) >> 4)
113#define TCL_LUN(tcl) \
114 (tcl & (AHD_NUM_LUNS - 1))
115#define BUILD_TCL(scsiid, lun) \
116 ((lun) | (((scsiid) & TID) << 4))
117#define BUILD_TCL_RAW(target, channel, lun) \
118 ((lun) | ((target) << 8))
119
120#define SCB_GET_TAG(scb) \
750f3593 121 aic_le16toh(scb->hscb->tag)
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122
123#ifndef AHD_TARGET_MODE
124#undef AHD_TMODE_ENABLE
125#define AHD_TMODE_ENABLE 0
126#endif
127
128#define AHD_BUILD_COL_IDX(target, lun) \
129 (((lun) << 4) | target)
130
131#define AHD_GET_SCB_COL_IDX(ahd, scb) \
132 ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb))
133
134#define AHD_SET_SCB_COL_IDX(scb, col_idx) \
135do { \
136 (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \
137 (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \
138} while (0)
139
140#define AHD_COPY_SCB_COL_IDX(dst, src) \
141do { \
142 dst->hscb->scsiid = src->hscb->scsiid; \
143 dst->hscb->lun = src->hscb->lun; \
144} while (0)
145
146#define AHD_NEVER_COL_IDX 0xFFFF
147
148/**************************** Driver Constants ********************************/
149/*
150 * The maximum number of supported targets.
151 */
152#define AHD_NUM_TARGETS 16
153
154/*
155 * The maximum number of supported luns.
156 * The identify message only supports 64 luns in non-packetized transfers.
157 * You can have 2^64 luns when information unit transfers are enabled,
158 * but until we see a need to support that many, we support 256.
159 */
160#define AHD_NUM_LUNS_NONPKT 64
161#define AHD_NUM_LUNS 256
162
163/*
164 * The maximum transfer per S/G segment.
165 */
166#define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */
167
168/*
169 * The maximum amount of SCB storage in hardware on a controller.
170 * This value represents an upper bound. Due to software design,
171 * we may not be able to use this number.
172 */
173#define AHD_SCB_MAX 512
174
175/*
176 * The maximum number of concurrent transactions supported per driver instance.
177 * Sequencer Control Blocks (SCBs) store per-transaction information.
178 */
179#define AHD_MAX_QUEUE AHD_SCB_MAX
180
181/*
182 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2
183 * in size and accommodate as many transactions as can be queued concurrently.
184 */
185#define AHD_QIN_SIZE AHD_MAX_QUEUE
186#define AHD_QOUT_SIZE AHD_MAX_QUEUE
187
188#define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1))
189/*
190 * The maximum amount of SCB storage we allocate in host memory.
191 */
192#define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE
193
194/*
195 * Ring Buffer of incoming target commands.
196 * We allocate 256 to simplify the logic in the sequencer
197 * by using the natural wrap point of an 8bit counter.
198 */
199#define AHD_TMODE_CMDS 256
200
201/* Reset line assertion time in us */
202#define AHD_BUSRESET_DELAY 25
203
204/******************* Chip Characteristics/Operating Settings *****************/
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205extern uint32_t ahd_attach_to_HostRAID_controllers;
206
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207/*
208 * Chip Type
209 * The chip order is from least sophisticated to most sophisticated.
210 */
211typedef enum {
212 AHD_NONE = 0x0000,
213 AHD_CHIPID_MASK = 0x00FF,
214 AHD_AIC7901 = 0x0001,
215 AHD_AIC7902 = 0x0002,
216 AHD_AIC7901A = 0x0003,
217 AHD_PCI = 0x0100, /* Bus type PCI */
218 AHD_PCIX = 0x0200, /* Bus type PCIX */
219 AHD_BUS_MASK = 0x0F00
220} ahd_chip;
221
222/*
223 * Features available in each chip type.
224 */
225typedef enum {
226 AHD_FENONE = 0x00000,
227 AHD_WIDE = 0x00001,/* Wide Channel */
228 AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */
229 AHD_TARGETMODE = 0x01000,/* Has tested target mode support */
230 AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */
231 AHD_RTI = 0x04000,/* Retained Training Support */
232 AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */
233 AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */
750f3593 234 AHD_FAST_CDB_DELIVERY = 0x20000,/* CDB acks released to Output Sync */
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235 AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/
236 AHD_AIC7901_FE = AHD_FENONE,
0bcae99c 237 AHD_AIC7901A_FE = AHD_FENONE,
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238 AHD_AIC7902_FE = AHD_MULTI_FUNC
239} ahd_feature;
240
241/*
242 * Bugs in the silicon that we work around in software.
243 */
244typedef enum {
245 AHD_BUGNONE = 0x0000,
246 /*
247 * Rev A hardware fails to update LAST/CURR/NEXTSCB
248 * correctly in certain packetized selection cases.
249 */
250 AHD_SENT_SCB_UPDATE_BUG = 0x0001,
251 /* The wrong SCB is accessed to check the abort pending bit. */
252 AHD_ABORT_LQI_BUG = 0x0002,
253 /* Packetized bitbucket crosses packet boundaries. */
254 AHD_PKT_BITBUCKET_BUG = 0x0004,
255 /* The selection timer runs twice as long as its setting. */
256 AHD_LONG_SETIMO_BUG = 0x0008,
257 /* The Non-LQ CRC error status is delayed until phase change. */
258 AHD_NLQICRC_DELAYED_BUG = 0x0010,
259 /* The chip must be reset for all outgoing bus resets. */
260 AHD_SCSIRST_BUG = 0x0020,
261 /* Some PCIX fields must be saved and restored across chip reset. */
262 AHD_PCIX_CHIPRST_BUG = 0x0040,
263 /* MMAPIO is not functional in PCI-X mode. */
264 AHD_PCIX_MMAPIO_BUG = 0x0080,
265 /* Reads to SCBRAM fail to reset the discard timer. */
266 AHD_PCIX_SCBRAM_RD_BUG = 0x0100,
267 /* Bug workarounds that can be disabled on non-PCIX busses. */
268 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG
269 | AHD_PCIX_MMAPIO_BUG
270 | AHD_PCIX_SCBRAM_RD_BUG,
271 /*
272 * LQOSTOP0 status set even for forced selections with ATN
273 * to perform non-packetized message delivery.
274 */
275 AHD_LQO_ATNO_BUG = 0x0200,
276 /* FIFO auto-flush does not always trigger. */
277 AHD_AUTOFLUSH_BUG = 0x0400,
278 /* The CLRLQO registers are not self-clearing. */
279 AHD_CLRLQO_AUTOCLR_BUG = 0x0800,
280 /* The PACKETIZED status bit refers to the previous connection. */
281 AHD_PKTIZED_STATUS_BUG = 0x1000,
282 /* "Short Luns" are not placed into outgoing LQ packets correctly. */
283 AHD_PKT_LUN_BUG = 0x2000,
284 /*
285 * Only the FIFO allocated to the non-packetized connection may
286 * be in use during a non-packetzied connection.
287 */
288 AHD_NONPACKFIFO_BUG = 0x4000,
289 /*
290 * Writing to a DFF SCBPTR register may fail if concurent with
291 * a hardware write to the other DFF SCBPTR register. This is
292 * not currently a concern in our sequencer since all chips with
293 * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern
294 * occur in non-packetized connections.
295 */
296 AHD_MDFF_WSCBPTR_BUG = 0x8000,
297 /* SGHADDR updates are slow. */
298 AHD_REG_SLOW_SETTLE_BUG = 0x10000,
299 /*
300 * Changing the MODE_PTR coincident with an interrupt that
301 * switches to a different mode will cause the interrupt to
302 * be in the mode written outside of interrupt context.
303 */
304 AHD_SET_MODE_BUG = 0x20000,
305 /* Non-packetized busfree revision does not work. */
306 AHD_BUSFREEREV_BUG = 0x40000,
307 /*
308 * Paced transfers are indicated with a non-standard PPR
309 * option bit in the neg table, 160MHz is indicated by
310 * sync factor 0x7, and the offset if off by a factor of 2.
311 */
312 AHD_PACED_NEGTABLE_BUG = 0x80000,
313 /* LQOOVERRUN false positives. */
314 AHD_LQOOVERRUN_BUG = 0x100000,
315 /*
316 * Controller write to INTSTAT will lose to a host
317 * write to CLRINT.
318 */
319 AHD_INTCOLLISION_BUG = 0x200000,
320 /*
321 * The GEM318 violates the SCSI spec by not waiting
322 * the mandated bus settle delay between phase changes
323 * in some situations. Some aic79xx chip revs. are more
324 * strict in this regard and will treat REQ assertions
325 * that fall within the bus settle delay window as
326 * glitches. This flag tells the firmware to tolerate
327 * early REQ assertions.
328 */
329 AHD_EARLY_REQ_BUG = 0x400000,
330 /*
331 * The LED does not stay on long enough in packetized modes.
332 */
333 AHD_FAINT_LED_BUG = 0x800000
334} ahd_bug;
335
336/*
337 * Configuration specific settings.
338 * The driver determines these settings by probing the
339 * chip/controller's configuration.
340 */
341typedef enum {
342 AHD_FNONE = 0x00000,
343 AHD_BOOT_CHANNEL = 0x00001,/* We were set as the boot channel. */
344 AHD_USEDEFAULTS = 0x00004,/*
345 * For cards without an seeprom
346 * or a BIOS to initialize the chip's
347 * SRAM, we use the default target
348 * settings.
349 */
350 AHD_SEQUENCER_DEBUG = 0x00008,
351 AHD_RESET_BUS_A = 0x00010,
352 AHD_EXTENDED_TRANS_A = 0x00020,
353 AHD_TERM_ENB_A = 0x00040,
354 AHD_SPCHK_ENB_A = 0x00080,
355 AHD_STPWLEVEL_A = 0x00100,
356 AHD_INITIATORROLE = 0x00200,/*
357 * Allow initiator operations on
358 * this controller.
359 */
360 AHD_TARGETROLE = 0x00400,/*
361 * Allow target operations on this
362 * controller.
363 */
364 AHD_RESOURCE_SHORTAGE = 0x00800,
365 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */
366 AHD_INT50_SPEEDFLEX = 0x02000,/*
367 * Internal 50pin connector
368 * sits behind an aic3860
369 */
370 AHD_BIOS_ENABLED = 0x04000,
371 AHD_ALL_INTERRUPTS = 0x08000,
372 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */
373 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */
374 AHD_CURRENT_SENSING = 0x40000,
375 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */
376 AHD_HP_BOARD = 0x100000,
377 AHD_RESET_POLL_ACTIVE = 0x200000,
378 AHD_UPDATE_PEND_CMDS = 0x400000,
4b753d9e 379 AHD_RUNNING_QOUTFIFO = 0x800000,
750f3593 380 AHD_HAD_FIRST_SEL = 0x1000000,
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381 AHD_SHUTDOWN_RECOVERY = 0x2000000, /* Terminate recovery thread. */
382 AHD_HOSTRAID_BOARD = 0x4000000
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383} ahd_flag;
384
385/************************* Hardware SCB Definition ***************************/
386
387/*
388 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
389 * consists of a "hardware SCB" mirroring the fields available on the card
390 * and additional information the kernel stores for each transaction.
391 *
392 * To minimize space utilization, a portion of the hardware scb stores
393 * different data during different portions of a SCSI transaction.
394 * As initialized by the host driver for the initiator role, this area
395 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After
396 * the cdb has been presented to the target, this area serves to store
397 * residual transfer information and the SCSI status byte.
398 * For the target role, the contents of this area do not change, but
399 * still serve a different purpose than for the initiator role. See
400 * struct target_data for details.
401 */
402
403/*
404 * Status information embedded in the shared poriton of
405 * an SCB after passing the cdb to the target. The kernel
406 * driver will only read this data for transactions that
407 * complete abnormally.
408 */
409struct initiator_status {
410 uint32_t residual_datacnt; /* Residual in the current S/G seg */
411 uint32_t residual_sgptr; /* The next S/G for this transfer */
412 uint8_t scsi_status; /* Standard SCSI status byte */
413};
414
415struct target_status {
416 uint32_t residual_datacnt; /* Residual in the current S/G seg */
417 uint32_t residual_sgptr; /* The next S/G for this transfer */
418 uint8_t scsi_status; /* SCSI status to give to initiator */
419 uint8_t target_phases; /* Bitmap of phases to execute */
420 uint8_t data_phase; /* Data-In or Data-Out */
421 uint8_t initiator_tag; /* Initiator's transaction tag */
422};
423
424/*
425 * Initiator mode SCB shared data area.
426 * If the embedded CDB is 12 bytes or less, we embed
427 * the sense buffer address in the SCB. This allows
428 * us to retrieve sense information without interrupting
429 * the host in packetized mode.
430 */
431typedef uint32_t sense_addr_t;
432#define MAX_CDB_LEN 16
433#define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t))
434union initiator_data {
435 struct {
436 uint64_t cdbptr;
437 uint8_t cdblen;
438 } cdb_from_host;
439 uint8_t cdb[MAX_CDB_LEN];
440 struct {
441 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR];
442 sense_addr_t sense_addr;
443 } cdb_plus_saddr;
444};
445
446/*
447 * Target mode version of the shared data SCB segment.
448 */
449struct target_data {
450 uint32_t spare[2];
451 uint8_t scsi_status; /* SCSI status to give to initiator */
452 uint8_t target_phases; /* Bitmap of phases to execute */
453 uint8_t data_phase; /* Data-In or Data-Out */
454 uint8_t initiator_tag; /* Initiator's transaction tag */
455};
456
457struct hardware_scb {
458/*0*/ union {
459 union initiator_data idata;
460 struct target_data tdata;
461 struct initiator_status istatus;
462 struct target_status tstatus;
463 } shared_data;
464/*
465 * A word about residuals.
466 * The scb is presented to the sequencer with the dataptr and datacnt
467 * fields initialized to the contents of the first S/G element to
468 * transfer. The sgptr field is initialized to the bus address for
469 * the S/G element that follows the first in the in core S/G array
470 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid
471 * S/G entry for this transfer (single S/G element transfer with the
472 * first elements address and length preloaded in the dataptr/datacnt
473 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL.
474 * The SG_FULL_RESID flag ensures that the residual will be correctly
475 * noted even if no data transfers occur. Once the data phase is entered,
476 * the residual sgptr and datacnt are loaded from the sgptr and the
477 * datacnt fields. After each S/G element's dataptr and length are
478 * loaded into the hardware, the residual sgptr is advanced. After
479 * each S/G element is expired, its datacnt field is checked to see
480 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
481 * residual sg ptr and the transfer is considered complete. If the
482 * sequencer determines that there is a residual in the tranfer, or
483 * there is non-zero status, it will set the SG_STATUS_VALID flag in
484 * sgptr and dma the scb back into host memory. To sumarize:
485 *
486 * Sequencer:
487 * o A residual has occurred if SG_FULL_RESID is set in sgptr,
488 * or residual_sgptr does not have SG_LIST_NULL set.
489 *
490 * o We are transfering the last segment if residual_datacnt has
491 * the SG_LAST_SEG flag set.
492 *
493 * Host:
494 * o A residual can only have occurred if a completed scb has the
495 * SG_STATUS_VALID flag set. Inspection of the SCSI status field,
496 * the residual_datacnt, and the residual_sgptr field will tell
497 * for sure.
498 *
499 * o residual_sgptr and sgptr refer to the "next" sg entry
500 * and so may point beyond the last valid sg entry for the
501 * transfer.
502 */
503#define SG_PTR_MASK 0xFFFFFFF8
504/*16*/ uint16_t tag; /* Reused by Sequencer. */
505/*18*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */
506/*19*/ uint8_t scsiid; /*
507 * Selection out Id
508 * Our Id (bits 0-3) Their ID (bits 4-7)
509 */
510/*20*/ uint8_t lun;
511/*21*/ uint8_t task_attribute;
512/*22*/ uint8_t cdb_len;
513/*23*/ uint8_t task_management;
514/*24*/ uint64_t dataptr;
515/*32*/ uint32_t datacnt; /* Byte 3 is spare. */
516/*36*/ uint32_t sgptr;
517/*40*/ uint32_t hscb_busaddr;
518/*44*/ uint32_t next_hscb_busaddr;
519/********** Long lun field only downloaded for full 8 byte lun support ********/
520/*48*/ uint8_t pkt_long_lun[8];
521/******* Fields below are not Downloaded (Sequencer may use for scratch) ******/
522/*56*/ uint8_t spare[8];
523};
524
525/************************ Kernel SCB Definitions ******************************/
526/*
527 * Some fields of the SCB are OS dependent. Here we collect the
528 * definitions for elements that all OS platforms need to include
529 * in there SCB definition.
530 */
531
532/*
533 * Definition of a scatter/gather element as transfered to the controller.
534 * The aic7xxx chips only support a 24bit length. We use the top byte of
535 * the length to store additional address bits and a flag to indicate
536 * that a given segment terminates the transfer. This gives us an
537 * addressable range of 512GB on machines with 64bit PCI or with chips
538 * that can support dual address cycles on 32bit PCI busses.
539 */
540struct ahd_dma_seg {
541 uint32_t addr;
542 uint32_t len;
543#define AHD_DMA_LAST_SEG 0x80000000
544#define AHD_SG_HIGH_ADDR_MASK 0x7F000000
545#define AHD_SG_LEN_MASK 0x00FFFFFF
546};
547
548struct ahd_dma64_seg {
549 uint64_t addr;
550 uint32_t len;
551 uint32_t pad;
552};
553
554struct map_node {
555 bus_dmamap_t dmamap;
750f3593 556 bus_addr_t busaddr;
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557 uint8_t *vaddr;
558 SLIST_ENTRY(map_node) links;
559};
560
561/*
562 * The current state of this SCB.
563 */
564typedef enum {
565 SCB_FLAG_NONE = 0x00000,
566 SCB_TRANSMISSION_ERROR = 0x00001,/*
567 * We detected a parity or CRC
568 * error that has effected the
569 * payload of the command. This
570 * flag is checked when normal
571 * status is returned to catch
572 * the case of a target not
573 * responding to our attempt
574 * to report the error.
575 */
576 SCB_OTHERTCL_TIMEOUT = 0x00002,/*
577 * Another device was active
578 * during the first timeout for
579 * this SCB so we gave ourselves
580 * an additional timeout period
581 * in case it was hogging the
582 * bus.
583 */
584 SCB_DEVICE_RESET = 0x00004,
585 SCB_SENSE = 0x00008,
586 SCB_CDB32_PTR = 0x00010,
587 SCB_RECOVERY_SCB = 0x00020,
588 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */
589 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */
590 SCB_ABORT = 0x00100,
591 SCB_ACTIVE = 0x00200,
592 SCB_TARGET_IMMEDIATE = 0x00400,
593 SCB_PACKETIZED = 0x00800,
594 SCB_EXPECT_PPR_BUSFREE = 0x01000,
595 SCB_PKT_SENSE = 0x02000,
596 SCB_CMDPHASE_ABORT = 0x04000,
597 SCB_ON_COL_LIST = 0x08000,
750f3593 598 SCB_SILENT = 0x10000,/*
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599 * Be quiet about transmission type
600 * errors. They are expected and we
601 * don't want to upset the user. This
602 * flag is typically used during DV.
603 */
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604 SCB_TIMEDOUT = 0x20000/*
605 * SCB has timed out and is on the
606 * timedout list.
607 */
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608} scb_flag;
609
610struct scb {
611 struct hardware_scb *hscb;
612 union {
613 SLIST_ENTRY(scb) sle;
614 LIST_ENTRY(scb) le;
615 TAILQ_ENTRY(scb) tqe;
616 } links;
617 union {
618 SLIST_ENTRY(scb) sle;
619 LIST_ENTRY(scb) le;
620 TAILQ_ENTRY(scb) tqe;
621 } links2;
622#define pending_links links2.le
623#define collision_links links2.le
750f3593 624 LIST_ENTRY(scb) timedout_links;
984263bc 625 struct scb *col_scb;
750f3593 626 aic_io_ctx_t io_ctx;
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627 struct ahd_softc *ahd_softc;
628 scb_flag flags;
629#ifndef __linux__
630 bus_dmamap_t dmamap;
631#endif
632 struct scb_platform_data *platform_data;
633 struct map_node *hscb_map;
634 struct map_node *sg_map;
635 struct map_node *sense_map;
636 void *sg_list;
637 uint8_t *sense_data;
638 bus_addr_t sg_list_busaddr;
639 bus_addr_t sense_busaddr;
640 u_int sg_count;/* How full ahd_dma_seg is */
641#define AHD_MAX_LQ_CRC_ERRORS 5
642 u_int crc_retry_count;
ef8ef949 643 aic_timer_t io_timer;
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644};
645
646TAILQ_HEAD(scb_tailq, scb);
647LIST_HEAD(scb_list, scb);
648
649struct scb_data {
650 /*
651 * TAILQ of lists of free SCBs grouped by device
652 * collision domains.
653 */
654 struct scb_tailq free_scbs;
655
656 /*
657 * Per-device lists of SCBs whose tag ID would collide
658 * with an already active tag on the device.
659 */
660 struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT];
661
662 /*
663 * SCBs that will not collide with any active device.
664 */
665 struct scb_list any_dev_free_scb_list;
666
667 /*
668 * Mapping from tag to SCB.
669 */
670 struct scb *scbindex[AHD_SCB_MAX];
671
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672 u_int recovery_scbs; /* Transactions currently in recovery */
673
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674 /*
675 * "Bus" addresses of our data structures.
676 */
677 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */
678 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */
679 bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */
dff3fb2d 680
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681 SLIST_HEAD(, map_node) hscb_maps;
682 SLIST_HEAD(, map_node) sg_maps;
683 SLIST_HEAD(, map_node) sense_maps;
684 int scbs_left; /* unallocated scbs in head map_node */
685 int sgs_left; /* unallocated sgs in head map_node */
686 int sense_left; /* unallocated sense in head map_node */
687 uint16_t numscbs;
688 uint16_t maxhscbs; /* Number of SCBs on the card */
689 uint8_t init_level; /*
690 * How far we've initialized
691 * this structure.
692 */
693};
694
695/************************ Target Mode Definitions *****************************/
696
697/*
698 * Connection desciptor for select-in requests in target mode.
699 */
700struct target_cmd {
701 uint8_t scsiid; /* Our ID and the initiator's ID */
702 uint8_t identify; /* Identify message */
703 uint8_t bytes[22]; /*
704 * Bytes contains any additional message
705 * bytes terminated by 0xFF. The remainder
706 * is the cdb to execute.
707 */
708 uint8_t cmd_valid; /*
709 * When a command is complete, the firmware
710 * will set cmd_valid to all bits set.
711 * After the host has seen the command,
712 * the bits are cleared. This allows us
713 * to just peek at host memory to determine
714 * if more work is complete. cmd_valid is on
715 * an 8 byte boundary to simplify setting
716 * it on aic7880 hardware which only has
717 * limited direct access to the DMA FIFO.
718 */
719 uint8_t pad[7];
720};
721
722/*
723 * Number of events we can buffer up if we run out
724 * of immediate notify ccbs.
725 */
726#define AHD_TMODE_EVENT_BUFFER_SIZE 8
727struct ahd_tmode_event {
728 uint8_t initiator_id;
729 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
730#define EVENT_TYPE_BUS_RESET 0xFF
731 uint8_t event_arg;
732};
733
734/*
735 * Per enabled lun target mode state.
736 * As this state is directly influenced by the host OS'es target mode
737 * environment, we let the OS module define it. Forward declare the
738 * structure here so we can store arrays of them, etc. in OS neutral
739 * data structures.
740 */
741#ifdef AHD_TARGET_MODE
742struct ahd_tmode_lstate {
743 struct cam_path *path;
744 struct ccb_hdr_slist accept_tios;
745 struct ccb_hdr_slist immed_notifies;
746 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE];
747 uint8_t event_r_idx;
748 uint8_t event_w_idx;
749};
750#else
751struct ahd_tmode_lstate;
752#endif
753
754/******************** Transfer Negotiation Datastructures *********************/
755#define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */
756#define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */
757#define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */
758#define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */
759#define AHD_PERIOD_10MHz 0x19
760
761#define AHD_WIDTH_UNKNOWN 0xFF
762#define AHD_PERIOD_UNKNOWN 0xFF
763#define AHD_OFFSET_UNKNOWN 0xFF
764#define AHD_PPR_OPTS_UNKNOWN 0xFF
765
766/*
767 * Transfer Negotiation Information.
768 */
769struct ahd_transinfo {
770 uint8_t protocol_version; /* SCSI Revision level */
771 uint8_t transport_version; /* SPI Revision level */
772 uint8_t width; /* Bus width */
773 uint8_t period; /* Sync rate factor */
774 uint8_t offset; /* Sync offset */
775 uint8_t ppr_options; /* Parallel Protocol Request options */
776};
777
778/*
779 * Per-initiator current, goal and user transfer negotiation information. */
780struct ahd_initiator_tinfo {
781 struct ahd_transinfo curr;
782 struct ahd_transinfo goal;
783 struct ahd_transinfo user;
784};
785
786/*
787 * Per enabled target ID state.
788 * Pointers to lun target state as well as sync/wide negotiation information
789 * for each initiator<->target mapping. For the initiator role we pretend
790 * that we are the target and the targets are the initiators since the
791 * negotiation is the same regardless of role.
792 */
793struct ahd_tmode_tstate {
794 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS];
795 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS];
796
797 /*
798 * Per initiator state bitmasks.
799 */
800 uint16_t auto_negotiate;/* Auto Negotiation Required */
801 uint16_t discenable; /* Disconnection allowed */
802 uint16_t tagenable; /* Tagged Queuing allowed */
803};
804
805/*
806 * Points of interest along the negotiated transfer scale.
807 */
808#define AHD_SYNCRATE_160 0x8
809#define AHD_SYNCRATE_PACED 0x8
810#define AHD_SYNCRATE_DT 0x9
811#define AHD_SYNCRATE_ULTRA2 0xa
812#define AHD_SYNCRATE_ULTRA 0xc
813#define AHD_SYNCRATE_FAST 0x19
814#define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST
815#define AHD_SYNCRATE_SYNC 0x32
816#define AHD_SYNCRATE_MIN 0x60
817#define AHD_SYNCRATE_ASYNC 0xFF
818#define AHD_SYNCRATE_MAX AHD_SYNCRATE_160
819
820/* Safe and valid period for async negotiations. */
821#define AHD_ASYNC_XFER_PERIOD 0x44
822
823/*
824 * In RevA, the synctable uses a 120MHz rate for the period
825 * factor 8 and 160MHz for the period factor 7. The 120MHz
826 * rate never made it into the official SCSI spec, so we must
827 * compensate when setting the negotiation table for Rev A
828 * parts.
829 */
830#define AHD_SYNCRATE_REVA_120 0x8
831#define AHD_SYNCRATE_REVA_160 0x7
832
833/***************************** Lookup Tables **********************************/
834/*
835 * Phase -> name and message out response
836 * to parity errors in each phase table.
837 */
838struct ahd_phase_table_entry {
839 uint8_t phase;
840 uint8_t mesg_out; /* Message response to parity errors */
841 char *phasemsg;
842};
843
844/************************** Serial EEPROM Format ******************************/
845
846struct seeprom_config {
847/*
848 * Per SCSI ID Configuration Flags
849 */
850 uint16_t device_flags[16]; /* words 0-15 */
851#define CFXFER 0x003F /* synchronous transfer rate */
852#define CFXFER_ASYNC 0x3F
853#define CFQAS 0x0040 /* Negotiate QAS */
854#define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */
855#define CFSTART 0x0100 /* send start unit SCSI command */
856#define CFINCBIOS 0x0200 /* include in BIOS scan */
857#define CFDISC 0x0400 /* enable disconnection */
858#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */
859#define CFWIDEB 0x1000 /* wide bus device */
860#define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */
861
862/*
863 * BIOS Control Bits
864 */
865 uint16_t bios_control; /* word 16 */
866#define CFSUPREM 0x0001 /* support all removeable drives */
867#define CFSUPREMB 0x0002 /* support removeable boot drives */
868#define CFBIOSSTATE 0x000C /* BIOS Action State */
869#define CFBS_DISABLED 0x00
870#define CFBS_ENABLED 0x04
871#define CFBS_DISABLED_SCAN 0x08
872#define CFENABLEDV 0x0010 /* Perform Domain Validation */
873#define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */
874#define CFSPARITY 0x0040 /* SCSI parity */
875#define CFEXTEND 0x0080 /* extended translation enabled */
876#define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */
877#define CFMSG_LEVEL 0x0600 /* BIOS Message Level */
878#define CFMSG_VERBOSE 0x0000
879#define CFMSG_SILENT 0x0200
880#define CFMSG_DIAG 0x0400
881#define CFRESETB 0x0800 /* reset SCSI bus at boot */
882/* UNUSED 0xf000 */
883
884/*
885 * Host Adapter Control Bits
886 */
887 uint16_t adapter_control; /* word 17 */
888#define CFAUTOTERM 0x0001 /* Perform Auto termination */
889#define CFSTERM 0x0002 /* SCSI low byte termination */
890#define CFWSTERM 0x0004 /* SCSI high byte termination */
891#define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/
892#define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */
893#define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */
894#define CFSTPWLEVEL 0x0040 /* Termination level control */
895#define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */
896#define CFTERM_MENU 0x0100 /* BIOS displays termination menu */
897#define CFCLUSTERENB 0x8000 /* Cluster Enable */
898
899/*
900 * Bus Release Time, Host Adapter ID
901 */
902 uint16_t brtime_id; /* word 18 */
903#define CFSCSIID 0x000f /* host adapter SCSI ID */
904/* UNUSED 0x00f0 */
905#define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */
906
907/*
908 * Maximum targets
909 */
910 uint16_t max_targets; /* word 19 */
911#define CFMAXTARG 0x00ff /* maximum targets */
912#define CFBOOTLUN 0x0f00 /* Lun to boot from */
913#define CFBOOTID 0xf000 /* Target to boot from */
914 uint16_t res_1[10]; /* words 20-29 */
915 uint16_t signature; /* BIOS Signature */
916#define CFSIGNATURE 0x400
917 uint16_t checksum; /* word 31 */
918};
919
920/*
921 * Vital Product Data used during POST and by the BIOS.
922 */
923struct vpd_config {
924 uint8_t bios_flags;
925#define VPDMASTERBIOS 0x0001
926#define VPDBOOTHOST 0x0002
927 uint8_t reserved_1[21];
928 uint8_t resource_type;
929 uint8_t resource_len[2];
930 uint8_t resource_data[8];
931 uint8_t vpd_tag;
932 uint16_t vpd_len;
933 uint8_t vpd_keyword[2];
934 uint8_t length;
935 uint8_t revision;
936 uint8_t device_flags;
937 uint8_t termnation_menus[2];
938 uint8_t fifo_threshold;
939 uint8_t end_tag;
940 uint8_t vpd_checksum;
941 uint16_t default_target_flags;
942 uint16_t default_bios_flags;
943 uint16_t default_ctrl_flags;
944 uint8_t default_irq;
945 uint8_t pci_lattime;
946 uint8_t max_target;
947 uint8_t boot_lun;
948 uint16_t signature;
949 uint8_t reserved_2;
950 uint8_t checksum;
951 uint8_t reserved_3[4];
952};
953
954/****************************** Flexport Logic ********************************/
955#define FLXADDR_TERMCTL 0x0
956#define FLX_TERMCTL_ENSECHIGH 0x8
957#define FLX_TERMCTL_ENSECLOW 0x4
958#define FLX_TERMCTL_ENPRIHIGH 0x2
959#define FLX_TERMCTL_ENPRILOW 0x1
960#define FLXADDR_ROMSTAT_CURSENSECTL 0x1
961#define FLX_ROMSTAT_SEECFG 0xF0
962#define FLX_ROMSTAT_EECFG 0x0F
963#define FLX_ROMSTAT_SEE_93C66 0x00
964#define FLX_ROMSTAT_SEE_NONE 0xF0
965#define FLX_ROMSTAT_EE_512x8 0x0
966#define FLX_ROMSTAT_EE_1MBx8 0x1
967#define FLX_ROMSTAT_EE_2MBx8 0x2
968#define FLX_ROMSTAT_EE_4MBx8 0x3
969#define FLX_ROMSTAT_EE_16MBx8 0x4
970#define CURSENSE_ENB 0x1
971#define FLXADDR_FLEXSTAT 0x2
972#define FLX_FSTAT_BUSY 0x1
973#define FLXADDR_CURRENT_STAT 0x4
974#define FLX_CSTAT_SEC_HIGH 0xC0
975#define FLX_CSTAT_SEC_LOW 0x30
976#define FLX_CSTAT_PRI_HIGH 0x0C
977#define FLX_CSTAT_PRI_LOW 0x03
978#define FLX_CSTAT_MASK 0x03
979#define FLX_CSTAT_SHIFT 2
980#define FLX_CSTAT_OKAY 0x0
981#define FLX_CSTAT_OVER 0x1
982#define FLX_CSTAT_UNDER 0x2
983#define FLX_CSTAT_INVALID 0x3
984
985int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
986 u_int start_addr, u_int count, int bstream);
987
988int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
989 u_int start_addr, u_int count);
990int ahd_wait_seeprom(struct ahd_softc *ahd);
991int ahd_verify_vpd_cksum(struct vpd_config *vpd);
992int ahd_verify_cksum(struct seeprom_config *sc);
993int ahd_acquire_seeprom(struct ahd_softc *ahd);
994void ahd_release_seeprom(struct ahd_softc *ahd);
995
996/**************************** Message Buffer *********************************/
997typedef enum {
998 MSG_FLAG_NONE = 0x00,
999 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01,
1000 MSG_FLAG_IU_REQ_CHANGED = 0x02,
1001 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04,
1002 MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08,
1003 MSG_FLAG_PACKETIZED = 0x10
1004} ahd_msg_flags;
1005
1006typedef enum {
1007 MSG_TYPE_NONE = 0x00,
1008 MSG_TYPE_INITIATOR_MSGOUT = 0x01,
1009 MSG_TYPE_INITIATOR_MSGIN = 0x02,
1010 MSG_TYPE_TARGET_MSGOUT = 0x03,
1011 MSG_TYPE_TARGET_MSGIN = 0x04
1012} ahd_msg_type;
1013
1014typedef enum {
1015 MSGLOOP_IN_PROG,
1016 MSGLOOP_MSGCOMPLETE,
1017 MSGLOOP_TERMINATED
1018} msg_loop_stat;
1019
1020/*********************** Software Configuration Structure *********************/
1021struct ahd_suspend_channel_state {
1022 uint8_t scsiseq;
1023 uint8_t sxfrctl0;
1024 uint8_t sxfrctl1;
1025 uint8_t simode0;
1026 uint8_t simode1;
1027 uint8_t seltimer;
1028 uint8_t seqctl;
1029};
1030
1031struct ahd_suspend_state {
1032 struct ahd_suspend_channel_state channel[2];
1033 uint8_t optionmode;
1034 uint8_t dscommand0;
1035 uint8_t dspcistatus;
1036 /* hsmailbox */
1037 uint8_t crccontrol1;
1038 uint8_t scbbaddr;
1039 /* Host and sequencer SCB counts */
1040 uint8_t dff_thrsh;
1041 uint8_t *scratch_ram;
1042 uint8_t *btt;
1043};
1044
1045typedef void (*ahd_bus_intr_t)(struct ahd_softc *);
1046
1047typedef enum {
1048 AHD_MODE_DFF0,
1049 AHD_MODE_DFF1,
1050 AHD_MODE_CCHAN,
1051 AHD_MODE_SCSI,
1052 AHD_MODE_CFG,
1053 AHD_MODE_UNKNOWN
1054} ahd_mode;
1055
1056#define AHD_MK_MSK(x) (0x01 << (x))
1057#define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0)
1058#define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1)
1059#define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN)
1060#define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI)
1061#define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG)
1062#define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN)
1063#define AHD_MODE_ANY_MSK (~0)
1064
1065typedef uint8_t ahd_mode_state;
1066
1067typedef void ahd_callback_t (void *);
1068
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1069struct ahd_completion
1070{
1071 uint16_t tag;
1072 uint8_t sg_status;
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1073 uint8_t valid_tag;
1074};
1075
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1076#define AIC_SCB_DATA(softc) (&(softc)->scb_data)
1077
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1078struct ahd_softc {
1079 bus_space_tag_t tags[2];
1080 bus_space_handle_t bshs[2];
1081#ifndef __linux__
1082 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
1083#endif
1084 struct scb_data scb_data;
1085
1086 struct hardware_scb *next_queued_hscb;
750f3593 1087 struct map_node *next_queued_hscb_map;
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1088
1089 /*
1090 * SCBs that have been sent to the controller
1091 */
1092 LIST_HEAD(, scb) pending_scbs;
1093
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1094 /*
1095 * SCBs whose timeout routine has been called.
1096 */
1097 LIST_HEAD(, scb) timedout_scbs;
1098
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1099 /*
1100 * Current register window mode information.
1101 */
1102 ahd_mode dst_mode;
1103 ahd_mode src_mode;
1104
1105 /*
1106 * Saved register window mode information
1107 * used for restore on next unpause.
1108 */
1109 ahd_mode saved_dst_mode;
1110 ahd_mode saved_src_mode;
1111
1112 /*
1113 * Platform specific data.
1114 */
1115 struct ahd_platform_data *platform_data;
1116
1117 /*
1118 * Platform specific device information.
1119 */
750f3593 1120 aic_dev_softc_t dev_softc;
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1121
1122 /*
1123 * Bus specific device information.
1124 */
1125 ahd_bus_intr_t bus_intr;
1126
1127 /*
1128 * Target mode related state kept on a per enabled lun basis.
1129 * Targets that are not enabled will have null entries.
1130 * As an initiator, we keep one target entry for our initiator
1131 * ID to store our sync/wide transfer settings.
1132 */
1133 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS];
1134
1135 /*
1136 * The black hole device responsible for handling requests for
1137 * disabled luns on enabled targets.
1138 */
1139 struct ahd_tmode_lstate *black_hole;
1140
1141 /*
1142 * Device instance currently on the bus awaiting a continue TIO
1143 * for a command that was not given the disconnect priveledge.
1144 */
1145 struct ahd_tmode_lstate *pending_device;
1146
1147 /*
1148 * Timer handles for timer driven callbacks.
1149 */
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1150 aic_timer_t reset_timer;
1151 aic_timer_t stat_timer;
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1152
1153 /*
1154 * Statistics.
1155 */
ce48b5fa 1156#define AHD_STAT_UPDATE_MS 250
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1157#define AHD_STAT_BUCKETS 4
1158 u_int cmdcmplt_bucket;
1159 uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS];
1160 uint32_t cmdcmplt_total;
1161
1162 /*
1163 * Card characteristics
1164 */
1165 ahd_chip chip;
1166 ahd_feature features;
1167 ahd_bug bugs;
1168 ahd_flag flags;
1169 struct seeprom_config *seep_config;
1170
984263bc 1171 /* Command Queues */
7009d94e 1172 struct ahd_completion *qoutfifo;
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1173 uint16_t qoutfifonext;
1174 uint16_t qoutfifonext_valid_tag;
1175 uint16_t qinfifonext;
1176 uint16_t qinfifo[AHD_SCB_MAX];
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1177
1178 /*
1179 * Our qfreeze count. The sequencer compares
1180 * this value with its own counter to determine
1181 * whether to allow selections to occur.
1182 */
1183 uint16_t qfreeze_cnt;
1184
1185 /* Values to store in the SEQCTL register for pause and unpause */
1186 uint8_t unpause;
1187 uint8_t pause;
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1188
1189 /* Critical Section Data */
1190 struct cs *critical_sections;
1191 u_int num_critical_sections;
1192
1193 /* Buffer for handling packetized bitbucket. */
1194 uint8_t *overrun_buf;
1195
1196 /* Links for chaining softcs */
1197 TAILQ_ENTRY(ahd_softc) links;
1198
1199 /* Channel Names ('A', 'B', etc.) */
1200 char channel;
1201
1202 /* Initiator Bus ID */
1203 uint8_t our_id;
1204
1205 /*
1206 * Target incoming command FIFO.
1207 */
1208 struct target_cmd *targetcmds;
1209 uint8_t tqinfifonext;
1210
1211 /*
1212 * Cached verson of the hs_mailbox so we can avoid
1213 * pausing the sequencer during mailbox updates.
1214 */
1215 uint8_t hs_mailbox;
1216
1217 /*
1218 * Incoming and outgoing message handling.
1219 */
1220 uint8_t send_msg_perror;
1221 ahd_msg_flags msg_flags;
1222 ahd_msg_type msg_type;
1223 uint8_t msgout_buf[12];/* Message we are sending */
1224 uint8_t msgin_buf[12];/* Message we are receiving */
1225 u_int msgout_len; /* Length of message to send */
1226 u_int msgout_index; /* Current index in msgout */
1227 u_int msgin_index; /* Current index in msgin */
1228
1229 /*
1230 * Mapping information for data structures shared
1231 * between the sequencer and kernel.
1232 */
1233 bus_dma_tag_t parent_dmat;
1234 bus_dma_tag_t shared_data_dmat;
750f3593 1235 struct map_node shared_data_map;
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1236
1237 /* Information saved through suspend/resume cycles */
1238 struct ahd_suspend_state suspend_state;
1239
1240 /* Number of enabled target mode device on this card */
1241 u_int enabled_luns;
1242
1243 /* Initialization level of this data structure */
1244 u_int init_level;
1245
1246 /* PCI cacheline size. */
1247 u_int pci_cachesize;
1248
1249 /* IO Cell Parameters */
1250 uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS];
1251
1252 u_int stack_size;
1253 uint16_t *saved_stack;
1254
1255 /* Per-Unit descriptive information */
1256 const char *description;
1257 const char *bus_description;
1258 char *name;
1259 int unit;
1260
1261 /* Selection Timer settings */
1262 int seltime;
1263
1264 /*
1265 * Interrupt coalescing settings.
1266 */
1267#define AHD_INT_COALESCING_TIMER_DEFAULT 250 /*us*/
1268#define AHD_INT_COALESCING_MAXCMDS_DEFAULT 10
1269#define AHD_INT_COALESCING_MAXCMDS_MAX 127
1270#define AHD_INT_COALESCING_MINCMDS_DEFAULT 5
1271#define AHD_INT_COALESCING_MINCMDS_MAX 127
1272#define AHD_INT_COALESCING_THRESHOLD_DEFAULT 2000
1273#define AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT 1000
1274 u_int int_coalescing_timer;
1275 u_int int_coalescing_maxcmds;
1276 u_int int_coalescing_mincmds;
1277 u_int int_coalescing_threshold;
1278 u_int int_coalescing_stop_threshold;
1279
1280 uint16_t user_discenable;/* Disconnection allowed */
1281 uint16_t user_tagenable;/* Tagged Queuing allowed */
1282};
1283
1284TAILQ_HEAD(ahd_softc_tailq, ahd_softc);
1285extern struct ahd_softc_tailq ahd_tailq;
1286
1287/*************************** IO Cell Configuration ****************************/
1288#define AHD_PRECOMP_SLEW_INDEX \
1289 (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0)
1290
1291#define AHD_AMPLITUDE_INDEX \
1292 (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0)
1293
1294#define AHD_SET_SLEWRATE(ahd, new_slew) \
1295do { \
1296 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \
1297 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \
1298 (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \
1299} while (0)
1300
1301#define AHD_SET_PRECOMP(ahd, new_pcomp) \
1302do { \
1303 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \
1304 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \
1305 (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \
1306} while (0)
1307
1308#define AHD_SET_AMPLITUDE(ahd, new_amp) \
1309do { \
1310 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \
1311 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \
1312 (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \
1313} while (0)
1314
1315/************************ Active Device Information ***************************/
1316typedef enum {
1317 ROLE_UNKNOWN,
1318 ROLE_INITIATOR,
1319 ROLE_TARGET
1320} role_t;
1321
1322struct ahd_devinfo {
1323 int our_scsiid;
1324 int target_offset;
1325 uint16_t target_mask;
1326 u_int target;
1327 u_int lun;
1328 char channel;
1329 role_t role; /*
1330 * Only guaranteed to be correct if not
1331 * in the busfree state.
1332 */
1333};
1334
1335/****************************** PCI Structures ********************************/
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1336#define AHD_PCI_IOADDR0 PCIR_BAR(0) /* I/O BAR*/
1337#define AHD_PCI_MEMADDR PCIR_BAR(1) /* Memory BAR */
1338#define AHD_PCI_IOADDR1 PCIR_BAR(3) /* Second I/O BAR */
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1339
1340typedef int (ahd_device_setup_t)(struct ahd_softc *);
1341
1342struct ahd_pci_identity {
1343 uint64_t full_id;
1344 uint64_t id_mask;
1345 char *name;
1346 ahd_device_setup_t *setup;
1347};
1348extern struct ahd_pci_identity ahd_pci_ident_table [];
1349extern const u_int ahd_num_pci_devs;
1350
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1351/*************************** Function Declarations ****************************/
1352/******************************************************************************/
1353void ahd_reset_cmds_pending(struct ahd_softc *ahd);
1354u_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl);
1355void ahd_busy_tcl(struct ahd_softc *ahd,
1356 u_int tcl, u_int busyid);
1357static __inline void ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl);
1358static __inline void
1359ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl)
1360{
1361 ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL);
1362}
1363
1364/***************************** PCI Front End *********************************/
750f3593 1365struct ahd_pci_identity *ahd_find_pci_device(aic_dev_softc_t);
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1366int ahd_pci_config(struct ahd_softc *,
1367 struct ahd_pci_identity *);
1368int ahd_pci_test_register_access(struct ahd_softc *);
1369
1370/************************** SCB and SCB queue management **********************/
1371int ahd_probe_scbs(struct ahd_softc *);
1372void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd,
1373 struct scb *scb);
1374int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb,
1375 int target, char channel, int lun,
1376 u_int tag, role_t role);
1377
1378/****************************** Initialization ********************************/
1379struct ahd_softc *ahd_alloc(void *platform_arg, char *name);
1380int ahd_softc_init(struct ahd_softc *);
1381void ahd_controller_info(struct ahd_softc *ahd, char *buf);
1382int ahd_init(struct ahd_softc *ahd);
1383int ahd_default_config(struct ahd_softc *ahd);
1384int ahd_parse_vpddata(struct ahd_softc *ahd,
1385 struct vpd_config *vpd);
1386int ahd_parse_cfgdata(struct ahd_softc *ahd,
1387 struct seeprom_config *sc);
1388void ahd_intr_enable(struct ahd_softc *ahd, int enable);
1389void ahd_update_coalescing_values(struct ahd_softc *ahd,
1390 u_int timer,
1391 u_int maxcmds,
1392 u_int mincmds);
1393void ahd_enable_coalescing(struct ahd_softc *ahd,
1394 int enable);
1395void ahd_pause_and_flushwork(struct ahd_softc *ahd);
1396int ahd_suspend(struct ahd_softc *ahd);
1397int ahd_resume(struct ahd_softc *ahd);
1398void ahd_softc_insert(struct ahd_softc *);
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1399void ahd_set_unit(struct ahd_softc *, int);
1400void ahd_set_name(struct ahd_softc *, char *);
1401struct scb *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx);
1402void ahd_free_scb(struct ahd_softc *ahd, struct scb *scb);
2923a98d 1403int ahd_alloc_scbs(struct ahd_softc *ahd);
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1404void ahd_free(struct ahd_softc *ahd);
1405int ahd_reset(struct ahd_softc *ahd, int reinit);
1406void ahd_shutdown(void *arg);
1407int ahd_write_flexport(struct ahd_softc *ahd,
1408 u_int addr, u_int value);
1409int ahd_read_flexport(struct ahd_softc *ahd, u_int addr,
1410 uint8_t *value);
1411int ahd_wait_flexport(struct ahd_softc *ahd);
1412
1413/*************************** Interrupt Services *******************************/
1414void ahd_pci_intr(struct ahd_softc *ahd);
1415void ahd_clear_intstat(struct ahd_softc *ahd);
1416void ahd_flush_qoutfifo(struct ahd_softc *ahd);
1417void ahd_run_qoutfifo(struct ahd_softc *ahd);
1418#ifdef AHD_TARGET_MODE
1419void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused);
1420#endif
1421void ahd_handle_hwerrint(struct ahd_softc *ahd);
1422void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat);
1423void ahd_handle_scsiint(struct ahd_softc *ahd,
1424 u_int intstat);
1425void ahd_clear_critical_section(struct ahd_softc *ahd);
1426
1427/***************************** Error Recovery *********************************/
1428typedef enum {
1429 SEARCH_COMPLETE,
1430 SEARCH_COUNT,
1431 SEARCH_REMOVE,
1432 SEARCH_PRINT
1433} ahd_search_action;
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1434void ahd_done_with_status(struct ahd_softc *ahd,
1435 struct scb *scb, uint32_t status);
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1436int ahd_search_qinfifo(struct ahd_softc *ahd, int target,
1437 char channel, int lun, u_int tag,
1438 role_t role, uint32_t status,
1439 ahd_search_action action);
1440int ahd_search_disc_list(struct ahd_softc *ahd, int target,
1441 char channel, int lun, u_int tag,
1442 int stop_on_first, int remove,
1443 int save_state);
1444void ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb);
1445int ahd_reset_channel(struct ahd_softc *ahd, char channel,
1446 int initiate_reset);
1447int ahd_abort_scbs(struct ahd_softc *ahd, int target,
1448 char channel, int lun, u_int tag,
1449 role_t role, uint32_t status);
1450void ahd_restart(struct ahd_softc *ahd);
1451void ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo);
1452void ahd_handle_scb_status(struct ahd_softc *ahd,
1453 struct scb *scb);
1454void ahd_handle_scsi_status(struct ahd_softc *ahd,
1455 struct scb *scb);
1456void ahd_calc_residual(struct ahd_softc *ahd,
1457 struct scb *scb);
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1458void ahd_timeout(struct scb *scb);
1459void ahd_recover_commands(struct ahd_softc *ahd);
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1460/*************************** Utility Functions ********************************/
1461struct ahd_phase_table_entry*
1462 ahd_lookup_phase_entry(int phase);
1463void ahd_compile_devinfo(struct ahd_devinfo *devinfo,
1464 u_int our_id, u_int target,
1465 u_int lun, char channel,
1466 role_t role);
1467/************************** Transfer Negotiation ******************************/
1468void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
1469 u_int *ppr_options, u_int maxsync);
1470void ahd_validate_offset(struct ahd_softc *ahd,
1471 struct ahd_initiator_tinfo *tinfo,
1472 u_int period, u_int *offset,
1473 int wide, role_t role);
1474void ahd_validate_width(struct ahd_softc *ahd,
1475 struct ahd_initiator_tinfo *tinfo,
1476 u_int *bus_width,
1477 role_t role);
1478/*
1479 * Negotiation types. These are used to qualify if we should renegotiate
1480 * even if our goal and current transport parameters are identical.
1481 */
1482typedef enum {
1483 AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */
1484 AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */
1485 AHD_NEG_ALWAYS /* Renegotiat even if goal is async. */
1486} ahd_neg_type;
1487int ahd_update_neg_request(struct ahd_softc*,
1488 struct ahd_devinfo*,
1489 struct ahd_tmode_tstate*,
1490 struct ahd_initiator_tinfo*,
1491 ahd_neg_type);
1492void ahd_set_width(struct ahd_softc *ahd,
1493 struct ahd_devinfo *devinfo,
1494 u_int width, u_int type, int paused);
1495void ahd_set_syncrate(struct ahd_softc *ahd,
1496 struct ahd_devinfo *devinfo,
1497 u_int period, u_int offset,
1498 u_int ppr_options,
1499 u_int type, int paused);
1500typedef enum {
1501 AHD_QUEUE_NONE,
1502 AHD_QUEUE_BASIC,
1503 AHD_QUEUE_TAGGED
1504} ahd_queue_alg;
1505
1506void ahd_set_tags(struct ahd_softc *ahd,
1507 struct ahd_devinfo *devinfo,
1508 ahd_queue_alg alg);
1509
1510/**************************** Target Mode *************************************/
1511#ifdef AHD_TARGET_MODE
1512void ahd_send_lstate_events(struct ahd_softc *,
1513 struct ahd_tmode_lstate *);
1514void ahd_handle_en_lun(struct ahd_softc *ahd,
1515 struct cam_sim *sim, union ccb *ccb);
1516cam_status ahd_find_tmode_devs(struct ahd_softc *ahd,
1517 struct cam_sim *sim, union ccb *ccb,
1518 struct ahd_tmode_tstate **tstate,
1519 struct ahd_tmode_lstate **lstate,
1520 int notfound_failure);
1521#ifndef AHD_TMODE_ENABLE
1522#define AHD_TMODE_ENABLE 0
1523#endif
1524#endif
1525/******************************* Debug ***************************************/
1526#ifdef AHD_DEBUG
1527extern uint32_t ahd_debug;
1528#define AHD_SHOW_MISC 0x00001
1529#define AHD_SHOW_SENSE 0x00002
1530#define AHD_SHOW_RECOVERY 0x00004
1531#define AHD_DUMP_SEEPROM 0x00008
1532#define AHD_SHOW_TERMCTL 0x00010
1533#define AHD_SHOW_MEMORY 0x00020
1534#define AHD_SHOW_MESSAGES 0x00040
1535#define AHD_SHOW_MODEPTR 0x00080
1536#define AHD_SHOW_SELTO 0x00100
1537#define AHD_SHOW_FIFOS 0x00200
1538#define AHD_SHOW_QFULL 0x00400
1539#define AHD_SHOW_DV 0x00800
1540#define AHD_SHOW_MASKED_ERRORS 0x01000
1541#define AHD_SHOW_QUEUE 0x02000
1542#define AHD_SHOW_TQIN 0x04000
1543#define AHD_SHOW_SG 0x08000
1544#define AHD_SHOW_INT_COALESCING 0x10000
1545#define AHD_DEBUG_SEQUENCER 0x20000
1546#endif
1547void ahd_print_scb(struct scb *scb);
1548void ahd_print_devinfo(struct ahd_softc *ahd,
1549 struct ahd_devinfo *devinfo);
1550void ahd_dump_sglist(struct scb *scb);
1551void ahd_dump_all_cards_state(void);
1552void ahd_dump_card_state(struct ahd_softc *ahd);
1553int ahd_print_register(ahd_reg_parse_entry_t *table,
1554 u_int num_entries,
1555 const char *name,
1556 u_int address,
1557 u_int value,
1558 u_int *cur_column,
1559 u_int wrap_point);
1560void ahd_dump_scbs(struct ahd_softc *ahd);
1561#endif /* _AIC79XX_H_ */