MPSAFE locking for the ahc/ahd drivers using lockmgr locks.
[dragonfly.git] / sys / dev / disk / aic7xxx / aic7xxx.h
CommitLineData
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1/*
2 * Core definitions and data structures shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2001 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
750f3593 40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#85 $
984263bc 41 *
2923a98d 42 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.h,v 1.56 2007/04/19 18:53:52 scottl Exp $
ef8ef949 43 * $DragonFly: src/sys/dev/disk/aic7xxx/aic7xxx.h,v 1.7 2008/02/09 18:13:13 pavalos Exp $
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44 */
45
46#ifndef _AIC7XXX_H_
47#define _AIC7XXX_H_
48
49/* Register Definitions */
50#include "aic7xxx_reg.h"
51
52/************************* Forward Declarations *******************************/
53struct ahc_platform_data;
54struct scb_platform_data;
55struct seeprom_descriptor;
56
57/****************************** Useful Macros *********************************/
58#ifndef MAX
59#define MAX(a,b) (((a) > (b)) ? (a) : (b))
60#endif
61
62#ifndef MIN
63#define MIN(a,b) (((a) < (b)) ? (a) : (b))
64#endif
65
66#ifndef TRUE
67#define TRUE 1
68#endif
69#ifndef FALSE
70#define FALSE 0
71#endif
72
73#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array))
74
75#define ALL_CHANNELS '\0'
76#define ALL_TARGETS_MASK 0xFFFF
77#define INITIATOR_WILDCARD (~0)
78
79#define SCSIID_TARGET(ahc, scsiid) \
80 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \
81 >> TID_SHIFT)
82#define SCSIID_OUR_ID(scsiid) \
83 ((scsiid) & OID)
84#define SCSIID_CHANNEL(ahc, scsiid) \
85 ((((ahc)->features & AHC_TWIN) != 0) \
86 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \
87 : 'A')
88#define SCB_IS_SCSIBUS_B(ahc, scb) \
89 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B')
90#define SCB_GET_OUR_ID(scb) \
91 SCSIID_OUR_ID((scb)->hscb->scsiid)
92#define SCB_GET_TARGET(ahc, scb) \
93 SCSIID_TARGET((ahc), (scb)->hscb->scsiid)
94#define SCB_GET_CHANNEL(ahc, scb) \
95 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid)
96#define SCB_GET_LUN(scb) \
97 ((scb)->hscb->lun & LID)
98#define SCB_GET_TARGET_OFFSET(ahc, scb) \
99 (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0))
100#define SCB_GET_TARGET_MASK(ahc, scb) \
101 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb)))
102#ifdef AHC_DEBUG
103#define SCB_IS_SILENT(scb) \
104 ((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0 \
105 && (((scb)->flags & SCB_SILENT) != 0))
106#else
107#define SCB_IS_SILENT(scb) \
108 (((scb)->flags & SCB_SILENT) != 0)
109#endif
110#define TCL_TARGET_OFFSET(tcl) \
111 ((((tcl) >> 4) & TID) >> 4)
112#define TCL_LUN(tcl) \
113 (tcl & (AHC_NUM_LUNS - 1))
114#define BUILD_TCL(scsiid, lun) \
115 ((lun) | (((scsiid) & TID) << 4))
116
117#ifndef AHC_TARGET_MODE
118#undef AHC_TMODE_ENABLE
119#define AHC_TMODE_ENABLE 0
120#endif
121
122/**************************** Driver Constants ********************************/
123/*
124 * The maximum number of supported targets.
125 */
126#define AHC_NUM_TARGETS 16
127
128/*
129 * The maximum number of supported luns.
130 * The identify message only supports 64 luns in SPI3.
131 * You can have 2^64 luns when information unit transfers are enabled,
132 * but it is doubtful this driver will ever support IUTs.
133 */
134#define AHC_NUM_LUNS 64
135
136/*
137 * The maximum transfer per S/G segment.
138 */
139#define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */
140
141/*
142 * The maximum amount of SCB storage in hardware on a controller.
143 * This value represents an upper bound. Controllers vary in the number
144 * they actually support.
145 */
146#define AHC_SCB_MAX 255
147
148/*
149 * The maximum number of concurrent transactions supported per driver instance.
150 * Sequencer Control Blocks (SCBs) store per-transaction information. Although
151 * the space for SCBs on the host adapter varies by model, the driver will
152 * page the SCBs between host and controller memory as needed. We are limited
153 * to 253 because:
154 * 1) The 8bit nature of the RISC engine holds us to an 8bit value.
155 * 2) We reserve one value, 255, to represent the invalid element.
156 * 3) Our input queue scheme requires one SCB to always be reserved
157 * in advance of queuing any SCBs. This takes us down to 254.
158 * 4) To handle our output queue correctly on machines that only
159 * support 32bit stores, we must clear the array 4 bytes at a
160 * time. To avoid colliding with a DMA write from the sequencer,
161 * we must be sure that 4 slots are empty when we write to clear
162 * the queue. This reduces us to 253 SCBs: 1 that just completed
163 * and the known three additional empty slots in the queue that
164 * precede it.
165 */
166#define AHC_MAX_QUEUE 253
167
168/*
169 * The maximum amount of SCB storage we allocate in host memory. This
170 * number should reflect the 1 additional SCB we require to handle our
171 * qinfifo mechanism.
172 */
173#define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1)
174
175/*
176 * Ring Buffer of incoming target commands.
177 * We allocate 256 to simplify the logic in the sequencer
178 * by using the natural wrap point of an 8bit counter.
179 */
180#define AHC_TMODE_CMDS 256
181
182/* Reset line assertion time in us */
183#define AHC_BUSRESET_DELAY 25
184
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185/* Phase change constants used in target mode. */
186#define AHC_BUSSETTLE_DELAY 400
187#define AHC_DATARELEASE_DELAY 400
188
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189/******************* Chip Characteristics/Operating Settings *****************/
190/*
191 * Chip Type
192 * The chip order is from least sophisticated to most sophisticated.
193 */
194typedef enum {
195 AHC_NONE = 0x0000,
196 AHC_CHIPID_MASK = 0x00FF,
197 AHC_AIC7770 = 0x0001,
198 AHC_AIC7850 = 0x0002,
199 AHC_AIC7855 = 0x0003,
200 AHC_AIC7859 = 0x0004,
201 AHC_AIC7860 = 0x0005,
202 AHC_AIC7870 = 0x0006,
203 AHC_AIC7880 = 0x0007,
204 AHC_AIC7895 = 0x0008,
205 AHC_AIC7895C = 0x0009,
206 AHC_AIC7890 = 0x000a,
207 AHC_AIC7896 = 0x000b,
208 AHC_AIC7892 = 0x000c,
209 AHC_AIC7899 = 0x000d,
210 AHC_VL = 0x0100, /* Bus type VL */
211 AHC_EISA = 0x0200, /* Bus type EISA */
212 AHC_PCI = 0x0400, /* Bus type PCI */
213 AHC_BUS_MASK = 0x0F00
214} ahc_chip;
215
216/*
217 * Features available in each chip type.
218 */
219typedef enum {
220 AHC_FENONE = 0x00000,
221 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */
222 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */
223 AHC_WIDE = 0x00004, /* Wide Channel */
224 AHC_TWIN = 0x00008, /* Twin Channel */
225 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */
226 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */
227 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */
228 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */
229 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */
230 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */
231 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */
232 AHC_DT = 0x00800, /* Double Transition transfers */
233 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */
234 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */
235 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */
236 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/
237 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */
238 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */
239 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */
240 AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */
241 AHC_AIC7770_FE = AHC_FENONE,
242 /*
243 * The real 7850 does not support Ultra modes, but there are
244 * several cards that use the generic 7850 PCI ID even though
245 * they are using an Ultra capable chip (7859/7860). We start
246 * out with the AHC_ULTRA feature set and then check the DEVSTATUS
247 * register to determine if the capability is really present.
248 */
249 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA,
250 AHC_AIC7860_FE = AHC_AIC7850_FE,
750f3593 251 AHC_AIC7870_FE = AHC_TARGETMODE|AHC_AUTOPAUSE,
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252 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA,
253 /*
254 * Although we have space for both the initiator and
255 * target roles on ULTRA2 chips, we currently disable
256 * the initiator role to allow multi-scsi-id target mode
257 * configurations. We can only respond on the same SCSI
258 * ID as our initiator role if we allow initiator operation.
259 * At some point, we should add a configuration knob to
260 * allow both roles to be loaded.
261 */
262 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2
263 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID
264 |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS
265 |AHC_TARGETMODE,
266 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE,
267 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE
268 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS,
269 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID,
270 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC,
271 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC
272} ahc_feature;
273
274/*
275 * Bugs in the silicon that we work around in software.
276 */
277typedef enum {
278 AHC_BUGNONE = 0x00,
279 /*
280 * On all chips prior to the U2 product line,
281 * the WIDEODD S/G segment feature does not
282 * work during scsi->HostBus transfers.
283 */
284 AHC_TMODE_WIDEODD_BUG = 0x01,
285 /*
286 * On the aic7890/91 Rev 0 chips, the autoflush
287 * feature does not work. A manual flush of
288 * the DMA FIFO is required.
289 */
290 AHC_AUTOFLUSH_BUG = 0x02,
291 /*
292 * On many chips, cacheline streaming does not work.
293 */
294 AHC_CACHETHEN_BUG = 0x04,
295 /*
296 * On the aic7896/97 chips, cacheline
297 * streaming must be enabled.
298 */
299 AHC_CACHETHEN_DIS_BUG = 0x08,
300 /*
301 * PCI 2.1 Retry failure on non-empty data fifo.
302 */
303 AHC_PCI_2_1_RETRY_BUG = 0x10,
304 /*
305 * Controller does not handle cacheline residuals
306 * properly on S/G segments if PCI MWI instructions
307 * are allowed.
308 */
309 AHC_PCI_MWI_BUG = 0x20,
310 /*
311 * An SCB upload using the SCB channel's
312 * auto array entry copy feature may
313 * corrupt data. This appears to only
314 * occur on 66MHz systems.
315 */
316 AHC_SCBCHAN_UPLOAD_BUG = 0x40
317} ahc_bug;
318
319/*
320 * Configuration specific settings.
321 * The driver determines these settings by probing the
322 * chip/controller's configuration.
323 */
324typedef enum {
325 AHC_FNONE = 0x000,
326 AHC_PRIMARY_CHANNEL = 0x003, /*
327 * The channel that should
328 * be probed first.
329 */
330 AHC_USEDEFAULTS = 0x004, /*
331 * For cards without an seeprom
332 * or a BIOS to initialize the chip's
333 * SRAM, we use the default target
334 * settings.
335 */
336 AHC_SEQUENCER_DEBUG = 0x008,
337 AHC_SHARED_SRAM = 0x010,
338 AHC_LARGE_SEEPROM = 0x020, /* Uses C56_66 not C46 */
339 AHC_RESET_BUS_A = 0x040,
340 AHC_RESET_BUS_B = 0x080,
341 AHC_EXTENDED_TRANS_A = 0x100,
342 AHC_EXTENDED_TRANS_B = 0x200,
343 AHC_TERM_ENB_A = 0x400,
344 AHC_TERM_ENB_B = 0x800,
345 AHC_INITIATORROLE = 0x1000, /*
346 * Allow initiator operations on
347 * this controller.
348 */
349 AHC_TARGETROLE = 0x2000, /*
350 * Allow target operations on this
351 * controller.
352 */
353 AHC_NEWEEPROM_FMT = 0x4000,
354 AHC_RESOURCE_SHORTAGE = 0x8000,
355 AHC_TQINFIFO_BLOCKED = 0x10000, /* Blocked waiting for ATIOs */
356 AHC_INT50_SPEEDFLEX = 0x20000, /*
357 * Internal 50pin connector
358 * sits behind an aic3860
359 */
360 AHC_SCB_BTT = 0x40000, /*
361 * The busy targets table is
362 * stored in SCB space rather
363 * than SRAM.
364 */
365 AHC_BIOS_ENABLED = 0x80000,
366 AHC_ALL_INTERRUPTS = 0x100000,
367 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */
368 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */
369 AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */
370 AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */
371 AHC_SCB_CONFIG_USED = 0x4000000, /* No SEEPROM but SCB2 had info. */
372 AHC_NO_BIOS_INIT = 0x8000000, /* No BIOS left over settings. */
373 AHC_DISABLE_PCI_PERR = 0x10000000,
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374 AHC_HAS_TERM_LOGIC = 0x20000000,
375 AHC_SHUTDOWN_RECOVERY = 0x40000000 /* Terminate recovery thread. */
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376} ahc_flag;
377
378/************************* Hardware SCB Definition ***************************/
379
380/*
381 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
382 * consists of a "hardware SCB" mirroring the fields available on the card
383 * and additional information the kernel stores for each transaction.
384 *
385 * To minimize space utilization, a portion of the hardware scb stores
386 * different data during different portions of a SCSI transaction.
387 * As initialized by the host driver for the initiator role, this area
388 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After
389 * the cdb has been presented to the target, this area serves to store
390 * residual transfer information and the SCSI status byte.
391 * For the target role, the contents of this area do not change, but
392 * still serve a different purpose than for the initiator role. See
393 * struct target_data for details.
394 */
395
396/*
397 * Status information embedded in the shared poriton of
398 * an SCB after passing the cdb to the target. The kernel
399 * driver will only read this data for transactions that
400 * complete abnormally (non-zero status byte).
401 */
402struct status_pkt {
403 uint32_t residual_datacnt; /* Residual in the current S/G seg */
404 uint32_t residual_sg_ptr; /* The next S/G for this transfer */
405 uint8_t scsi_status; /* Standard SCSI status byte */
406};
407
408/*
409 * Target mode version of the shared data SCB segment.
410 */
411struct target_data {
412 uint32_t residual_datacnt; /* Residual in the current S/G seg */
413 uint32_t residual_sg_ptr; /* The next S/G for this transfer */
414 uint8_t scsi_status; /* SCSI status to give to initiator */
415 uint8_t target_phases; /* Bitmap of phases to execute */
416 uint8_t data_phase; /* Data-In or Data-Out */
417 uint8_t initiator_tag; /* Initiator's transaction tag */
418};
419
750f3593 420#define MAX_CDB_LEN 16
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421struct hardware_scb {
422/*0*/ union {
423 /*
424 * If the cdb is 12 bytes or less, we embed it directly
425 * in the SCB. For longer cdbs, we embed the address
426 * of the cdb payload as seen by the chip and a DMA
427 * is used to pull it in.
428 */
429 uint8_t cdb[12];
430 uint32_t cdb_ptr;
431 struct status_pkt status;
432 struct target_data tdata;
433 } shared_data;
434/*
435 * A word about residuals.
436 * The scb is presented to the sequencer with the dataptr and datacnt
437 * fields initialized to the contents of the first S/G element to
438 * transfer. The sgptr field is initialized to the bus address for
439 * the S/G element that follows the first in the in core S/G array
440 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid
441 * S/G entry for this transfer (single S/G element transfer with the
442 * first elements address and length preloaded in the dataptr/datacnt
443 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL.
444 * The SG_FULL_RESID flag ensures that the residual will be correctly
445 * noted even if no data transfers occur. Once the data phase is entered,
446 * the residual sgptr and datacnt are loaded from the sgptr and the
447 * datacnt fields. After each S/G element's dataptr and length are
448 * loaded into the hardware, the residual sgptr is advanced. After
449 * each S/G element is expired, its datacnt field is checked to see
450 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
451 * residual sg ptr and the transfer is considered complete. If the
452 * sequencer determines that there is a residual in the tranfer, it
453 * will set the SG_RESID_VALID flag in sgptr and dma the scb back into
454 * host memory. To sumarize:
455 *
456 * Sequencer:
457 * o A residual has occurred if SG_FULL_RESID is set in sgptr,
458 * or residual_sgptr does not have SG_LIST_NULL set.
459 *
460 * o We are transfering the last segment if residual_datacnt has
461 * the SG_LAST_SEG flag set.
462 *
463 * Host:
464 * o A residual has occurred if a completed scb has the
465 * SG_RESID_VALID flag set.
466 *
467 * o residual_sgptr and sgptr refer to the "next" sg entry
468 * and so may point beyond the last valid sg entry for the
469 * transfer.
470 */
471/*12*/ uint32_t dataptr;
472/*16*/ uint32_t datacnt; /*
473 * Byte 3 (numbered from 0) of
474 * the datacnt is really the
475 * 4th byte in that data address.
476 */
477/*20*/ uint32_t sgptr;
478#define SG_PTR_MASK 0xFFFFFFF8
479/*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */
480/*25*/ uint8_t scsiid; /* what to load in the SCSIID register */
481/*26*/ uint8_t lun;
482/*27*/ uint8_t tag; /*
483 * Index into our kernel SCB array.
484 * Also used as the tag for tagged I/O
485 */
486/*28*/ uint8_t cdb_len;
487/*29*/ uint8_t scsirate; /* Value for SCSIRATE register */
488/*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */
489/*31*/ uint8_t next; /*
490 * Used for threading SCBs in the
491 * "Waiting for Selection" and
492 * "Disconnected SCB" lists down
493 * in the sequencer.
494 */
495/*32*/ uint8_t cdb32[32]; /*
496 * CDB storage for cdbs of size
497 * 13->32. We store them here
498 * because hardware scbs are
499 * allocated from DMA safe
500 * memory so we are guaranteed
501 * the controller can access
502 * this data.
503 */
504};
505
506/************************ Kernel SCB Definitions ******************************/
507/*
508 * Some fields of the SCB are OS dependent. Here we collect the
509 * definitions for elements that all OS platforms need to include
510 * in there SCB definition.
511 */
512
513/*
514 * Definition of a scatter/gather element as transfered to the controller.
515 * The aic7xxx chips only support a 24bit length. We use the top byte of
516 * the length to store additional address bits and a flag to indicate
517 * that a given segment terminates the transfer. This gives us an
518 * addressable range of 512GB on machines with 64bit PCI or with chips
519 * that can support dual address cycles on 32bit PCI busses.
520 */
521struct ahc_dma_seg {
522 uint32_t addr;
523 uint32_t len;
524#define AHC_DMA_LAST_SEG 0x80000000
525#define AHC_SG_HIGH_ADDR_MASK 0x7F000000
526#define AHC_SG_LEN_MASK 0x00FFFFFF
527};
528
529struct sg_map_node {
530 bus_dmamap_t sg_dmamap;
531 bus_addr_t sg_physaddr;
532 struct ahc_dma_seg* sg_vaddr;
533 SLIST_ENTRY(sg_map_node) links;
534};
535
536/*
537 * The current state of this SCB.
538 */
539typedef enum {
750f3593 540 SCB_FLAG_NONE = 0x0000,
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541 SCB_OTHERTCL_TIMEOUT = 0x0002,/*
542 * Another device was active
543 * during the first timeout for
544 * this SCB so we gave ourselves
545 * an additional timeout period
546 * in case it was hogging the
547 * bus.
548 */
549 SCB_DEVICE_RESET = 0x0004,
550 SCB_SENSE = 0x0008,
551 SCB_CDB32_PTR = 0x0010,
552 SCB_RECOVERY_SCB = 0x0020,
553 SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */
554 SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */
555 SCB_ABORT = 0x0100,
556 SCB_UNTAGGEDQ = 0x0200,
557 SCB_ACTIVE = 0x0400,
558 SCB_TARGET_IMMEDIATE = 0x0800,
559 SCB_TRANSMISSION_ERROR = 0x1000,/*
560 * We detected a parity or CRC
561 * error that has effected the
562 * payload of the command. This
563 * flag is checked when normal
564 * status is returned to catch
565 * the case of a target not
566 * responding to our attempt
567 * to report the error.
568 */
569 SCB_TARGET_SCB = 0x2000,
750f3593 570 SCB_SILENT = 0x4000,/*
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571 * Be quiet about transmission type
572 * errors. They are expected and we
573 * don't want to upset the user. This
574 * flag is typically used during DV.
575 */
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576 SCB_TIMEDOUT = 0x8000 /*
577 * SCB has timed out and is on the
578 * timedout list.
579 */
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580} scb_flag;
581
582struct scb {
583 struct hardware_scb *hscb;
584 union {
585 SLIST_ENTRY(scb) sle;
586 TAILQ_ENTRY(scb) tqe;
587 } links;
588 LIST_ENTRY(scb) pending_links;
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589 LIST_ENTRY(scb) timedout_links;
590 aic_io_ctx_t io_ctx;
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591 struct ahc_softc *ahc_softc;
592 scb_flag flags;
593#ifndef __linux__
594 bus_dmamap_t dmamap;
595#endif
596 struct scb_platform_data *platform_data;
597 struct sg_map_node *sg_map;
598 struct ahc_dma_seg *sg_list;
599 bus_addr_t sg_list_phys;
600 u_int sg_count;/* How full ahc_dma_seg is */
ef8ef949 601 aic_timer_t io_timer;
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602};
603
604struct scb_data {
605 SLIST_HEAD(, scb) free_scbs; /*
606 * Pool of SCBs ready to be assigned
607 * commands to execute.
608 */
609 struct scb *scbindex[256]; /*
610 * Mapping from tag to SCB.
611 * As tag identifiers are an
612 * 8bit value, we provide space
613 * for all possible tag values.
614 * Any lookups to entries at or
615 * above AHC_SCB_MAX_ALLOC will
616 * always fail.
617 */
618 struct hardware_scb *hscbs; /* Array of hardware SCBs */
619 struct scb *scbarray; /* Array of kernel SCBs */
620 struct scsi_sense_data *sense; /* Per SCB sense data */
621
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622 u_int recovery_scbs; /* Transactions currently in recovery */
623
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624 /*
625 * "Bus" addresses of our data structures.
626 */
627 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */
628 bus_dmamap_t hscb_dmamap;
629 bus_addr_t hscb_busaddr;
630 bus_dma_tag_t sense_dmat;
631 bus_dmamap_t sense_dmamap;
632 bus_addr_t sense_busaddr;
633 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */
634 SLIST_HEAD(, sg_map_node) sg_maps;
635 uint8_t numscbs;
636 uint8_t maxhscbs; /* Number of SCBs on the card */
637 uint8_t init_level; /*
638 * How far we've initialized
639 * this structure.
640 */
641};
642
643/************************ Target Mode Definitions *****************************/
644
645/*
646 * Connection desciptor for select-in requests in target mode.
647 */
648struct target_cmd {
649 uint8_t scsiid; /* Our ID and the initiator's ID */
650 uint8_t identify; /* Identify message */
651 uint8_t bytes[22]; /*
652 * Bytes contains any additional message
653 * bytes terminated by 0xFF. The remainder
654 * is the cdb to execute.
655 */
656 uint8_t cmd_valid; /*
657 * When a command is complete, the firmware
658 * will set cmd_valid to all bits set.
659 * After the host has seen the command,
660 * the bits are cleared. This allows us
661 * to just peek at host memory to determine
662 * if more work is complete. cmd_valid is on
663 * an 8 byte boundary to simplify setting
664 * it on aic7880 hardware which only has
665 * limited direct access to the DMA FIFO.
666 */
667 uint8_t pad[7];
668};
669
670/*
671 * Number of events we can buffer up if we run out
672 * of immediate notify ccbs.
673 */
674#define AHC_TMODE_EVENT_BUFFER_SIZE 8
675struct ahc_tmode_event {
676 uint8_t initiator_id;
677 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
678#define EVENT_TYPE_BUS_RESET 0xFF
679 uint8_t event_arg;
680};
681
682/*
683 * Per enabled lun target mode state.
684 * As this state is directly influenced by the host OS'es target mode
685 * environment, we let the OS module define it. Forward declare the
686 * structure here so we can store arrays of them, etc. in OS neutral
687 * data structures.
688 */
689#ifdef AHC_TARGET_MODE
690struct ahc_tmode_lstate {
691 struct cam_path *path;
692 struct ccb_hdr_slist accept_tios;
693 struct ccb_hdr_slist immed_notifies;
694 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE];
695 uint8_t event_r_idx;
696 uint8_t event_w_idx;
697};
698#else
699struct ahc_tmode_lstate;
700#endif
701
702/******************** Transfer Negotiation Datastructures *********************/
703#define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */
704#define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */
705#define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */
706#define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */
707
708#define AHC_WIDTH_UNKNOWN 0xFF
709#define AHC_PERIOD_UNKNOWN 0xFF
710#define AHC_OFFSET_UNKNOWN 0xFF
711#define AHC_PPR_OPTS_UNKNOWN 0xFF
712
713/*
714 * Transfer Negotiation Information.
715 */
716struct ahc_transinfo {
717 uint8_t protocol_version; /* SCSI Revision level */
718 uint8_t transport_version; /* SPI Revision level */
719 uint8_t width; /* Bus width */
720 uint8_t period; /* Sync rate factor */
721 uint8_t offset; /* Sync offset */
722 uint8_t ppr_options; /* Parallel Protocol Request options */
723};
724
725/*
726 * Per-initiator current, goal and user transfer negotiation information. */
727struct ahc_initiator_tinfo {
728 uint8_t scsirate; /* Computed value for SCSIRATE reg */
729 struct ahc_transinfo curr;
730 struct ahc_transinfo goal;
731 struct ahc_transinfo user;
732};
733
734/*
735 * Per enabled target ID state.
736 * Pointers to lun target state as well as sync/wide negotiation information
737 * for each initiator<->target mapping. For the initiator role we pretend
738 * that we are the target and the targets are the initiators since the
739 * negotiation is the same regardless of role.
740 */
741struct ahc_tmode_tstate {
742 struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS];
743 struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS];
744
745 /*
746 * Per initiator state bitmasks.
747 */
748 uint16_t auto_negotiate;/* Auto Negotiation Required */
749 uint16_t ultraenb; /* Using ultra sync rate */
750 uint16_t discenable; /* Disconnection allowed */
751 uint16_t tagenable; /* Tagged Queuing allowed */
752};
753
754/*
755 * Data structure for our table of allowed synchronous transfer rates.
756 */
757struct ahc_syncrate {
758 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */
759 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */
760#define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */
761#define ST_SXFR 0x010 /* Rate Single Transition Only */
762#define DT_SXFR 0x040 /* Rate Double Transition Only */
763 uint8_t period; /* Period to send to SCSI target */
764 char *rate;
765};
766
767/* Safe and valid period for async negotiations. */
768#define AHC_ASYNC_XFER_PERIOD 0x45
769#define AHC_ULTRA2_XFER_PERIOD 0x0a
770
771/*
772 * Indexes into our table of syncronous transfer rates.
773 */
774#define AHC_SYNCRATE_DT 0
775#define AHC_SYNCRATE_ULTRA2 1
776#define AHC_SYNCRATE_ULTRA 3
777#define AHC_SYNCRATE_FAST 6
778#define AHC_SYNCRATE_MAX AHC_SYNCRATE_DT
779#define AHC_SYNCRATE_MIN 13
780
781/***************************** Lookup Tables **********************************/
782/*
783 * Phase -> name and message out response
784 * to parity errors in each phase table.
785 */
786struct ahc_phase_table_entry {
787 uint8_t phase;
788 uint8_t mesg_out; /* Message response to parity errors */
789 char *phasemsg;
790};
791
792/************************** Serial EEPROM Format ******************************/
793
794struct seeprom_config {
795/*
796 * Per SCSI ID Configuration Flags
797 */
798 uint16_t device_flags[16]; /* words 0-15 */
799#define CFXFER 0x0007 /* synchronous transfer rate */
800#define CFSYNCH 0x0008 /* enable synchronous transfer */
801#define CFDISC 0x0010 /* enable disconnection */
802#define CFWIDEB 0x0020 /* wide bus device */
803#define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/
804#define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */
805#define CFSTART 0x0100 /* send start unit SCSI command */
806#define CFINCBIOS 0x0200 /* include in BIOS scan */
807#define CFRNFOUND 0x0400 /* report even if not found */
808#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */
809#define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */
810#define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */
811
812/*
813 * BIOS Control Bits
814 */
815 uint16_t bios_control; /* word 16 */
816#define CFSUPREM 0x0001 /* support all removeable drives */
817#define CFSUPREMB 0x0002 /* support removeable boot drives */
818#define CFBIOSEN 0x0004 /* BIOS enabled */
819#define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */
820#define CFSM2DRV 0x0010 /* support more than two drives */
821#define CFSTPWLEVEL 0x0010 /* Termination level control */
822#define CF284XEXTEND 0x0020 /* extended translation (284x cards) */
823#define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */
824#define CFTERM_MENU 0x0040 /* BIOS displays termination menu */
825#define CFEXTEND 0x0080 /* extended translation enabled */
826#define CFSCAMEN 0x0100 /* SCAM enable */
827#define CFMSG_LEVEL 0x0600 /* BIOS Message Level */
828#define CFMSG_VERBOSE 0x0000
829#define CFMSG_SILENT 0x0200
830#define CFMSG_DIAG 0x0400
831#define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */
832/* UNUSED 0xff00 */
833
834/*
835 * Host Adapter Control Bits
836 */
837 uint16_t adapter_control; /* word 17 */
838#define CFAUTOTERM 0x0001 /* Perform Auto termination */
839#define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */
840#define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */
841#define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */
842#define CFSTERM 0x0004 /* SCSI low byte termination */
843#define CFWSTERM 0x0008 /* SCSI high byte termination */
844#define CFSPARITY 0x0010 /* SCSI parity */
845#define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */
846#define CFMULTILUN 0x0020
847#define CFRESETB 0x0040 /* reset SCSI bus at boot */
848#define CFCLUSTERENB 0x0080 /* Cluster Enable */
849#define CFBOOTCHAN 0x0300 /* probe this channel first */
850#define CFBOOTCHANSHIFT 8
851#define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/
852#define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */
853#define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */
854#define CFENABLEDV 0x4000 /* Perform Domain Validation*/
855
856/*
857 * Bus Release Time, Host Adapter ID
858 */
859 uint16_t brtime_id; /* word 18 */
860#define CFSCSIID 0x000f /* host adapter SCSI ID */
861/* UNUSED 0x00f0 */
862#define CFBRTIME 0xff00 /* bus release time */
863
864/*
865 * Maximum targets
866 */
867 uint16_t max_targets; /* word 19 */
868#define CFMAXTARG 0x00ff /* maximum targets */
869#define CFBOOTLUN 0x0f00 /* Lun to boot from */
870#define CFBOOTID 0xf000 /* Target to boot from */
871 uint16_t res_1[10]; /* words 20-29 */
872 uint16_t signature; /* Signature == 0x250 */
873#define CFSIGNATURE 0x250
874#define CFSIGNATURE2 0x300
875 uint16_t checksum; /* word 31 */
876};
877
878/**************************** Message Buffer *********************************/
879typedef enum {
880 MSG_TYPE_NONE = 0x00,
881 MSG_TYPE_INITIATOR_MSGOUT = 0x01,
882 MSG_TYPE_INITIATOR_MSGIN = 0x02,
883 MSG_TYPE_TARGET_MSGOUT = 0x03,
884 MSG_TYPE_TARGET_MSGIN = 0x04
885} ahc_msg_type;
886
887typedef enum {
888 MSGLOOP_IN_PROG,
889 MSGLOOP_MSGCOMPLETE,
890 MSGLOOP_TERMINATED
891} msg_loop_stat;
892
893/*********************** Software Configuration Structure *********************/
894TAILQ_HEAD(scb_tailq, scb);
895
896struct ahc_aic7770_softc {
897 /*
898 * Saved register state used for chip_init().
899 */
900 uint8_t busspd;
901 uint8_t bustime;
902};
903
904struct ahc_pci_softc {
905 /*
906 * Saved register state used for chip_init().
907 */
908 uint32_t devconfig;
909 uint16_t targcrccnt;
910 uint8_t command;
911 uint8_t csize_lattime;
912 uint8_t optionmode;
913 uint8_t crccontrol1;
914 uint8_t dscommand0;
915 uint8_t dspcistatus;
916 uint8_t scbbaddr;
917 uint8_t dff_thrsh;
918};
919
920union ahc_bus_softc {
921 struct ahc_aic7770_softc aic7770_softc;
922 struct ahc_pci_softc pci_softc;
923};
924
925typedef void (*ahc_bus_intr_t)(struct ahc_softc *);
926typedef int (*ahc_bus_chip_init_t)(struct ahc_softc *);
927typedef int (*ahc_bus_suspend_t)(struct ahc_softc *);
928typedef int (*ahc_bus_resume_t)(struct ahc_softc *);
929typedef void ahc_callback_t (void *);
930
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931#define AIC_SCB_DATA(softc) ((softc)->scb_data)
932
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933struct ahc_softc {
934 bus_space_tag_t tag;
935 bus_space_handle_t bsh;
936#ifndef __linux__
937 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
938#endif
939 struct scb_data *scb_data;
940
941 struct scb *next_queued_scb;
942
943 /*
944 * SCBs that have been sent to the controller
945 */
946 LIST_HEAD(, scb) pending_scbs;
947
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948 /*
949 * SCBs whose timeout routine has been called.
950 */
951 LIST_HEAD(, scb) timedout_scbs;
952
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953 /*
954 * Counting lock for deferring the release of additional
955 * untagged transactions from the untagged_queues. When
956 * the lock is decremented to 0, all queues in the
957 * untagged_queues array are run.
958 */
959 u_int untagged_queue_lock;
960
961 /*
962 * Per-target queue of untagged-transactions. The
963 * transaction at the head of the queue is the
964 * currently pending untagged transaction for the
965 * target. The driver only allows a single untagged
966 * transaction per target.
967 */
968 struct scb_tailq untagged_queues[AHC_NUM_TARGETS];
969
970 /*
971 * Bus attachment specific data.
972 */
973 union ahc_bus_softc bus_softc;
974
975 /*
976 * Platform specific data.
977 */
978 struct ahc_platform_data *platform_data;
979
980 /*
981 * Platform specific device information.
982 */
750f3593 983 aic_dev_softc_t dev_softc;
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984
985 /*
986 * Bus specific device information.
987 */
988 ahc_bus_intr_t bus_intr;
989
990 /*
991 * Bus specific initialization required
992 * after a chip reset.
993 */
994 ahc_bus_chip_init_t bus_chip_init;
995
996 /*
997 * Bus specific suspend routine.
998 */
999 ahc_bus_suspend_t bus_suspend;
1000
1001 /*
1002 * Bus specific resume routine.
1003 */
1004 ahc_bus_resume_t bus_resume;
1005
1006 /*
1007 * Target mode related state kept on a per enabled lun basis.
1008 * Targets that are not enabled will have null entries.
1009 * As an initiator, we keep one target entry for our initiator
1010 * ID to store our sync/wide transfer settings.
1011 */
1012 struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS];
1013
1014 /*
1015 * The black hole device responsible for handling requests for
1016 * disabled luns on enabled targets.
1017 */
1018 struct ahc_tmode_lstate *black_hole;
1019
1020 /*
1021 * Device instance currently on the bus awaiting a continue TIO
1022 * for a command that was not given the disconnect priveledge.
1023 */
1024 struct ahc_tmode_lstate *pending_device;
1025
1026 /*
1027 * Card characteristics
1028 */
1029 ahc_chip chip;
1030 ahc_feature features;
1031 ahc_bug bugs;
1032 ahc_flag flags;
1033 struct seeprom_config *seep_config;
1034
1035 /* Values to store in the SEQCTL register for pause and unpause */
1036 uint8_t unpause;
1037 uint8_t pause;
1038
1039 /* Command Queues */
1040 uint8_t qoutfifonext;
1041 uint8_t qinfifonext;
1042 uint8_t *qoutfifo;
1043 uint8_t *qinfifo;
1044
1045 /* Critical Section Data */
1046 struct cs *critical_sections;
1047 u_int num_critical_sections;
1048
1049 /* Links for chaining softcs */
1050 TAILQ_ENTRY(ahc_softc) links;
1051
1052 /* Channel Names ('A', 'B', etc.) */
1053 char channel;
1054 char channel_b;
1055
1056 /* Initiator Bus ID */
1057 uint8_t our_id;
1058 uint8_t our_id_b;
1059
1060 /*
1061 * PCI error detection.
1062 */
1063 int unsolicited_ints;
1064
1065 /*
1066 * Target incoming command FIFO.
1067 */
1068 struct target_cmd *targetcmds;
1069 uint8_t tqinfifonext;
1070
1071 /*
1072 * Cached copy of the sequencer control register.
1073 */
1074 uint8_t seqctl;
1075
1076 /*
1077 * Incoming and outgoing message handling.
1078 */
1079 uint8_t send_msg_perror;
1080 ahc_msg_type msg_type;
1081 uint8_t msgout_buf[12];/* Message we are sending */
1082 uint8_t msgin_buf[12];/* Message we are receiving */
1083 u_int msgout_len; /* Length of message to send */
1084 u_int msgout_index; /* Current index in msgout */
1085 u_int msgin_index; /* Current index in msgin */
1086
1087 /*
1088 * Mapping information for data structures shared
1089 * between the sequencer and kernel.
1090 */
1091 bus_dma_tag_t parent_dmat;
1092 bus_dma_tag_t shared_data_dmat;
1093 bus_dmamap_t shared_data_dmamap;
1094 bus_addr_t shared_data_busaddr;
1095
1096 /*
1097 * Bus address of the one byte buffer used to
1098 * work-around a DMA bug for chips <= aic7880
1099 * in target mode.
1100 */
1101 bus_addr_t dma_bug_buf;
1102
1103 /* Number of enabled target mode device on this card */
1104 u_int enabled_luns;
1105
1106 /* Initialization level of this data structure */
1107 u_int init_level;
1108
1109 /* PCI cacheline size. */
1110 u_int pci_cachesize;
1111
1112 /*
1113 * Count of parity errors we have seen as a target.
1114 * We auto-disable parity error checking after seeing
1115 * AHC_PCI_TARGET_PERR_THRESH number of errors.
1116 */
1117 u_int pci_target_perr_count;
1118#define AHC_PCI_TARGET_PERR_THRESH 10
1119
1120 /* Maximum number of sequencer instructions supported. */
1121 u_int instruction_ram_size;
1122
1123 /* Per-Unit descriptive information */
1124 const char *description;
1125 char *name;
1126 int unit;
1127
1128 /* Selection Timer settings */
1129 int seltime;
1130 int seltime_b;
1131
1132 uint16_t user_discenable;/* Disconnection allowed */
1133 uint16_t user_tagenable;/* Tagged Queuing allowed */
1134};
1135
1136TAILQ_HEAD(ahc_softc_tailq, ahc_softc);
1137extern struct ahc_softc_tailq ahc_tailq;
1138
1139/************************ Active Device Information ***************************/
1140typedef enum {
1141 ROLE_UNKNOWN,
1142 ROLE_INITIATOR,
1143 ROLE_TARGET
1144} role_t;
1145
1146struct ahc_devinfo {
1147 int our_scsiid;
1148 int target_offset;
1149 uint16_t target_mask;
1150 u_int target;
1151 u_int lun;
1152 char channel;
1153 role_t role; /*
1154 * Only guaranteed to be correct if not
1155 * in the busfree state.
1156 */
1157};
1158
1159/****************************** PCI Structures ********************************/
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1160#define AHC_PCI_IOADDR PCIR_BAR(0) /* I/O Address */
1161#define AHC_PCI_MEMADDR PCIR_BAR(1) /* Mem I/O Address */
1162
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1163typedef int (ahc_device_setup_t)(struct ahc_softc *);
1164
1165struct ahc_pci_identity {
1166 uint64_t full_id;
1167 uint64_t id_mask;
1168 char *name;
1169 ahc_device_setup_t *setup;
1170};
1171extern struct ahc_pci_identity ahc_pci_ident_table[];
1172extern const u_int ahc_num_pci_devs;
1173
1174/***************************** VL/EISA Declarations ***************************/
1175struct aic7770_identity {
1176 uint32_t full_id;
1177 uint32_t id_mask;
1178 const char *name;
1179 ahc_device_setup_t *setup;
1180};
1181extern struct aic7770_identity aic7770_ident_table[];
1182extern const int ahc_num_aic7770_devs;
1183
dff3fb2d 1184#define AHC_EISA_SLOT_SIZE 0x1000
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1185#define AHC_EISA_SLOT_OFFSET 0xc00
1186#define AHC_EISA_IOSIZE 0x100
1187
1188/*************************** Function Declarations ****************************/
1189/******************************************************************************/
1190u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl);
1191void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl);
1192void ahc_busy_tcl(struct ahc_softc *ahc,
1193 u_int tcl, u_int busyid);
1194
1195/***************************** PCI Front End *********************************/
750f3593 1196struct ahc_pci_identity *ahc_find_pci_device(aic_dev_softc_t);
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1197int ahc_pci_config(struct ahc_softc *,
1198 struct ahc_pci_identity *);
1199int ahc_pci_test_register_access(struct ahc_softc *);
1200
1201/*************************** EISA/VL Front End ********************************/
1202struct aic7770_identity *aic7770_find_device(uint32_t);
1203int aic7770_config(struct ahc_softc *ahc,
1204 struct aic7770_identity *,
1205 u_int port);
1206
1207/************************** SCB and SCB queue management **********************/
1208int ahc_probe_scbs(struct ahc_softc *);
1209void ahc_run_untagged_queues(struct ahc_softc *ahc);
1210void ahc_run_untagged_queue(struct ahc_softc *ahc,
1211 struct scb_tailq *queue);
1212void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc,
1213 struct scb *scb);
1214int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb,
1215 int target, char channel, int lun,
1216 u_int tag, role_t role);
1217
1218/****************************** Initialization ********************************/
1219struct ahc_softc *ahc_alloc(void *platform_arg, char *name);
1220int ahc_softc_init(struct ahc_softc *);
1221void ahc_controller_info(struct ahc_softc *ahc, char *buf);
1222int ahc_chip_init(struct ahc_softc *ahc);
1223int ahc_init(struct ahc_softc *ahc);
1224void ahc_intr_enable(struct ahc_softc *ahc, int enable);
1225void ahc_pause_and_flushwork(struct ahc_softc *ahc);
1226int ahc_suspend(struct ahc_softc *ahc);
1227int ahc_resume(struct ahc_softc *ahc);
1228void ahc_softc_insert(struct ahc_softc *);
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1229void ahc_set_unit(struct ahc_softc *, int);
1230void ahc_set_name(struct ahc_softc *, char *);
2923a98d 1231int ahc_alloc_scbs(struct ahc_softc *ahc);
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1232void ahc_free(struct ahc_softc *ahc);
1233int ahc_reset(struct ahc_softc *ahc, int reinit);
1234void ahc_shutdown(void *arg);
1235
1236/*************************** Interrupt Services *******************************/
1237void ahc_clear_intstat(struct ahc_softc *ahc);
1238void ahc_run_qoutfifo(struct ahc_softc *ahc);
1239#ifdef AHC_TARGET_MODE
1240void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused);
1241#endif
1242void ahc_handle_brkadrint(struct ahc_softc *ahc);
1243void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat);
1244void ahc_handle_scsiint(struct ahc_softc *ahc,
1245 u_int intstat);
1246void ahc_clear_critical_section(struct ahc_softc *ahc);
1247
1248/***************************** Error Recovery *********************************/
1249typedef enum {
1250 SEARCH_COMPLETE,
1251 SEARCH_COUNT,
1252 SEARCH_REMOVE
1253} ahc_search_action;
1254int ahc_search_qinfifo(struct ahc_softc *ahc, int target,
1255 char channel, int lun, u_int tag,
1256 role_t role, uint32_t status,
1257 ahc_search_action action);
1258int ahc_search_untagged_queues(struct ahc_softc *ahc,
750f3593 1259 aic_io_ctx_t ctx,
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1260 int target, char channel,
1261 int lun, uint32_t status,
1262 ahc_search_action action);
1263int ahc_search_disc_list(struct ahc_softc *ahc, int target,
1264 char channel, int lun, u_int tag,
1265 int stop_on_first, int remove,
1266 int save_state);
1267void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb);
1268int ahc_reset_channel(struct ahc_softc *ahc, char channel,
1269 int initiate_reset);
1270int ahc_abort_scbs(struct ahc_softc *ahc, int target,
1271 char channel, int lun, u_int tag,
1272 role_t role, uint32_t status);
1273void ahc_restart(struct ahc_softc *ahc);
1274void ahc_calc_residual(struct ahc_softc *ahc,
1275 struct scb *scb);
750f3593
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1276void ahc_timeout(struct scb *scb);
1277void ahc_recover_commands(struct ahc_softc *ahc);
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1278/*************************** Utility Functions ********************************/
1279struct ahc_phase_table_entry*
1280 ahc_lookup_phase_entry(int phase);
1281void ahc_compile_devinfo(struct ahc_devinfo *devinfo,
1282 u_int our_id, u_int target,
1283 u_int lun, char channel,
1284 role_t role);
1285/************************** Transfer Negotiation ******************************/
1286struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1287 u_int *ppr_options, u_int maxsync);
1288u_int ahc_find_period(struct ahc_softc *ahc,
1289 u_int scsirate, u_int maxsync);
1290void ahc_validate_offset(struct ahc_softc *ahc,
1291 struct ahc_initiator_tinfo *tinfo,
1292 struct ahc_syncrate *syncrate,
1293 u_int *offset, int wide,
1294 role_t role);
1295void ahc_validate_width(struct ahc_softc *ahc,
1296 struct ahc_initiator_tinfo *tinfo,
1297 u_int *bus_width,
1298 role_t role);
1299/*
1300 * Negotiation types. These are used to qualify if we should renegotiate
1301 * even if our goal and current transport parameters are identical.
1302 */
1303typedef enum {
1304 AHC_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */
1305 AHC_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */
1306 AHC_NEG_ALWAYS /* Renegotiat even if goal is async. */
1307} ahc_neg_type;
1308int ahc_update_neg_request(struct ahc_softc*,
1309 struct ahc_devinfo*,
1310 struct ahc_tmode_tstate*,
1311 struct ahc_initiator_tinfo*,
1312 ahc_neg_type);
1313void ahc_set_width(struct ahc_softc *ahc,
1314 struct ahc_devinfo *devinfo,
1315 u_int width, u_int type, int paused);
1316void ahc_set_syncrate(struct ahc_softc *ahc,
1317 struct ahc_devinfo *devinfo,
1318 struct ahc_syncrate *syncrate,
1319 u_int period, u_int offset,
1320 u_int ppr_options,
1321 u_int type, int paused);
1322typedef enum {
1323 AHC_QUEUE_NONE,
1324 AHC_QUEUE_BASIC,
1325 AHC_QUEUE_TAGGED
1326} ahc_queue_alg;
1327
1328void ahc_set_tags(struct ahc_softc *ahc,
1329 struct ahc_devinfo *devinfo,
1330 ahc_queue_alg alg);
1331
1332/**************************** Target Mode *************************************/
1333#ifdef AHC_TARGET_MODE
1334void ahc_send_lstate_events(struct ahc_softc *,
1335 struct ahc_tmode_lstate *);
1336void ahc_handle_en_lun(struct ahc_softc *ahc,
1337 struct cam_sim *sim, union ccb *ccb);
1338cam_status ahc_find_tmode_devs(struct ahc_softc *ahc,
1339 struct cam_sim *sim, union ccb *ccb,
1340 struct ahc_tmode_tstate **tstate,
1341 struct ahc_tmode_lstate **lstate,
1342 int notfound_failure);
1343#ifndef AHC_TMODE_ENABLE
1344#define AHC_TMODE_ENABLE 0
1345#endif
1346#endif
1347/******************************* Debug ***************************************/
1348#ifdef AHC_DEBUG
1349extern uint32_t ahc_debug;
1350#define AHC_SHOW_MISC 0x0001
1351#define AHC_SHOW_SENSE 0x0002
1352#define AHC_DUMP_SEEPROM 0x0004
1353#define AHC_SHOW_TERMCTL 0x0008
1354#define AHC_SHOW_MEMORY 0x0010
1355#define AHC_SHOW_MESSAGES 0x0020
1356#define AHC_SHOW_DV 0x0040
1357#define AHC_SHOW_SELTO 0x0080
1358#define AHC_SHOW_QFULL 0x0200
1359#define AHC_SHOW_QUEUE 0x0400
1360#define AHC_SHOW_TQIN 0x0800
1361#define AHC_SHOW_MASKED_ERRORS 0x1000
1362#define AHC_DEBUG_SEQUENCER 0x2000
1363#endif
1364void ahc_print_scb(struct scb *scb);
1365void ahc_print_devinfo(struct ahc_softc *ahc,
1366 struct ahc_devinfo *dev);
1367void ahc_dump_card_state(struct ahc_softc *ahc);
1368int ahc_print_register(ahc_reg_parse_entry_t *table,
1369 u_int num_entries,
1370 const char *name,
1371 u_int address,
1372 u_int value,
1373 u_int *cur_column,
1374 u_int wrap_point);
1375/******************************* SEEPROM *************************************/
1376int ahc_acquire_seeprom(struct ahc_softc *ahc,
1377 struct seeprom_descriptor *sd);
1378void ahc_release_seeprom(struct seeprom_descriptor *sd);
1379#endif /* _AIC7XXX_H_ */