Use queue(3).
[dragonfly.git] / sys / dev / netif / txp / if_txp.c
CommitLineData
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1/* $OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $ */
2/* $FreeBSD: src/sys/dev/txp/if_txp.c,v 1.4.2.4 2001/12/14 19:50:43 jlemon Exp $ */
6cc66259 3/* $DragonFly: src/sys/dev/netif/txp/if_txp.c,v 1.24 2005/06/20 13:26:15 joerg Exp $ */
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4
5/*
6 * Copyright (c) 2001
7 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and
8 * Aaron Campbell <aaron@monkey.org>. All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Jason L. Wright,
21 * Theo de Raadt and Aaron Campbell.
22 * 4. Neither the name of the author nor the names of any co-contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
36 * THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39/*
40 * Driver for 3c990 (Typhoon) Ethernet ASIC
41 */
42
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/sockio.h>
46#include <sys/mbuf.h>
47#include <sys/malloc.h>
48#include <sys/kernel.h>
49#include <sys/socket.h>
9228feed 50#include <sys/thread2.h>
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51
52#include <net/if.h>
871d7209 53#include <net/ifq_var.h>
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54#include <net/if_arp.h>
55#include <net/ethernet.h>
56#include <net/if_dl.h>
57#include <net/if_types.h>
1f2de5d4 58#include <net/vlan/if_vlan_var.h>
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59
60#include <netinet/in.h>
61#include <netinet/in_systm.h>
62#include <netinet/in_var.h>
63#include <netinet/ip.h>
64#include <netinet/if_ether.h>
3f9db7f8 65#include <sys/in_cksum.h>
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66
67#include <net/if_media.h>
68
69#include <net/bpf.h>
70
71#include <vm/vm.h> /* for vtophys */
72#include <vm/pmap.h> /* for vtophys */
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73#include <machine/bus_pio.h>
74#include <machine/bus_memio.h>
75#include <machine/bus.h>
76#include <machine/resource.h>
77#include <sys/bus.h>
78#include <sys/rman.h>
79
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MD
80#include "../mii_layer/mii.h"
81#include "../mii_layer/miivar.h"
82#include <bus/pci/pcireg.h>
83#include <bus/pci/pcivar.h>
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84
85#define TXP_USEIOSPACE
86#define __STRICT_ALIGNMENT
87
1f2de5d4
MD
88#include "if_txpreg.h"
89#include "3c990img.h"
984263bc 90
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91/*
92 * Various supported device vendors/types and their names.
93 */
94static struct txp_type txp_devs[] = {
95 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_95,
96 "3Com 3cR990-TX-95 Etherlink with 3XP Processor" },
97 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_97,
98 "3Com 3cR990-TX-97 Etherlink with 3XP Processor" },
99 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_TXM,
100 "3Com 3cR990B-TXM Etherlink with 3XP Processor" },
101 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_95,
102 "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" },
103 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_97,
104 "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" },
105 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_SRV,
106 "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" },
107 { 0, 0, NULL }
108};
109
b5101a88
RG
110static int txp_probe (device_t);
111static int txp_attach (device_t);
112static int txp_detach (device_t);
113static void txp_intr (void *);
114static void txp_tick (void *);
115static int txp_shutdown (device_t);
bd4539cc 116static int txp_ioctl (struct ifnet *, u_long, caddr_t, struct ucred *);
b5101a88
RG
117static void txp_start (struct ifnet *);
118static void txp_stop (struct txp_softc *);
119static void txp_init (void *);
120static void txp_watchdog (struct ifnet *);
121
fcb8c909 122static void txp_release_resources (device_t);
b5101a88
RG
123static int txp_chip_init (struct txp_softc *);
124static int txp_reset_adapter (struct txp_softc *);
125static int txp_download_fw (struct txp_softc *);
126static int txp_download_fw_wait (struct txp_softc *);
127static int txp_download_fw_section (struct txp_softc *,
128 struct txp_fw_section_header *, int);
129static int txp_alloc_rings (struct txp_softc *);
130static int txp_rxring_fill (struct txp_softc *);
131static void txp_rxring_empty (struct txp_softc *);
132static void txp_set_filter (struct txp_softc *);
133
134static int txp_cmd_desc_numfree (struct txp_softc *);
135static int txp_command (struct txp_softc *, u_int16_t, u_int16_t, u_int32_t,
136 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int);
137static int txp_command2 (struct txp_softc *, u_int16_t, u_int16_t,
984263bc 138 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t,
b5101a88
RG
139 struct txp_rsp_desc **, int);
140static int txp_response (struct txp_softc *, u_int32_t, u_int16_t, u_int16_t,
141 struct txp_rsp_desc **);
142static void txp_rsp_fixup (struct txp_softc *, struct txp_rsp_desc *,
143 struct txp_rsp_desc *);
144static void txp_capabilities (struct txp_softc *);
145
146static void txp_ifmedia_sts (struct ifnet *, struct ifmediareq *);
147static int txp_ifmedia_upd (struct ifnet *);
984263bc 148#ifdef TXP_DEBUG
b5101a88 149static void txp_show_descriptor (void *);
984263bc 150#endif
b5101a88
RG
151static void txp_tx_reclaim (struct txp_softc *, struct txp_tx_ring *);
152static void txp_rxbuf_reclaim (struct txp_softc *);
153static void txp_rx_reclaim (struct txp_softc *, struct txp_rx_ring *);
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154
155#ifdef TXP_USEIOSPACE
156#define TXP_RES SYS_RES_IOPORT
157#define TXP_RID TXP_PCI_LOIO
158#else
159#define TXP_RES SYS_RES_MEMORY
160#define TXP_RID TXP_PCI_LOMEM
161#endif
162
163static device_method_t txp_methods[] = {
164 /* Device interface */
165 DEVMETHOD(device_probe, txp_probe),
166 DEVMETHOD(device_attach, txp_attach),
167 DEVMETHOD(device_detach, txp_detach),
168 DEVMETHOD(device_shutdown, txp_shutdown),
169 { 0, 0 }
170};
171
172static driver_t txp_driver = {
173 "txp",
174 txp_methods,
175 sizeof(struct txp_softc)
176};
177
178static devclass_t txp_devclass;
179
32832096 180DECLARE_DUMMY_MODULE(if_txp);
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181DRIVER_MODULE(if_txp, pci, txp_driver, txp_devclass, 0, 0);
182
183static int
184txp_probe(dev)
185 device_t dev;
186{
187 struct txp_type *t;
188
189 t = txp_devs;
190
191 while(t->txp_name != NULL) {
192 if ((pci_get_vendor(dev) == t->txp_vid) &&
193 (pci_get_device(dev) == t->txp_did)) {
194 device_set_desc(dev, t->txp_name);
195 return(0);
196 }
197 t++;
198 }
199
200 return(ENXIO);
201}
202
203static int
204txp_attach(dev)
205 device_t dev;
206{
207 struct txp_softc *sc;
208 struct ifnet *ifp;
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209 u_int16_t p1;
210 u_int32_t p2;
fcb8c909 211 int error = 0, rid;
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212
213 sc = device_get_softc(dev);
9e6fd080 214 callout_init(&sc->txp_stat_timer);
984263bc 215
fcb8c909
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216 ifp = &sc->sc_arpcom.ac_if;
217 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
218
6cc66259 219 pci_enable_busmaster(dev);
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220
221 rid = TXP_RID;
4e6d744d 222 sc->sc_res = bus_alloc_resource_any(dev, TXP_RES, &rid, RF_ACTIVE);
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223
224 if (sc->sc_res == NULL) {
225 device_printf(dev, "couldn't map ports/memory\n");
226 error = ENXIO;
227 goto fail;
228 }
229
230 sc->sc_bt = rman_get_bustag(sc->sc_res);
231 sc->sc_bh = rman_get_bushandle(sc->sc_res);
232
233 /* Allocate interrupt */
234 rid = 0;
4e6d744d 235 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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236 RF_SHAREABLE | RF_ACTIVE);
237
238 if (sc->sc_irq == NULL) {
239 device_printf(dev, "couldn't map interrupt\n");
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240 error = ENXIO;
241 goto fail;
242 }
243
244 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET,
e9cb6d99 245 txp_intr, sc, &sc->sc_intrhand, NULL);
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246
247 if (error) {
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248 device_printf(dev, "couldn't set up irq\n");
249 goto fail;
250 }
251
252 if (txp_chip_init(sc)) {
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253 goto fail;
254 }
255
256 sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF,
257 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
258 error = txp_download_fw(sc);
259 contigfree(sc->sc_fwbuf, 32768, M_DEVBUF);
260 sc->sc_fwbuf = NULL;
261
262 if (error) {
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263 goto fail;
264 }
265
266 sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF,
267 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
268 bzero(sc->sc_ldata, sizeof(struct txp_ldata));
269
270 if (txp_alloc_rings(sc)) {
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271 goto fail;
272 }
273
274 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0,
275 NULL, NULL, NULL, 1)) {
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276 goto fail;
277 }
278
279 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0,
280 &p1, &p2, NULL, 1)) {
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281 goto fail;
282 }
283
284 txp_set_filter(sc);
285
0a8b5977
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286 sc->sc_arpcom.ac_enaddr[0] = ((uint8_t *)&p1)[1];
287 sc->sc_arpcom.ac_enaddr[1] = ((uint8_t *)&p1)[0];
288 sc->sc_arpcom.ac_enaddr[2] = ((uint8_t *)&p2)[3];
289 sc->sc_arpcom.ac_enaddr[3] = ((uint8_t *)&p2)[2];
290 sc->sc_arpcom.ac_enaddr[4] = ((uint8_t *)&p2)[1];
291 sc->sc_arpcom.ac_enaddr[5] = ((uint8_t *)&p2)[0];
984263bc 292
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MD
293 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts);
294 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
295 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
296 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
297 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
298 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
299 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
300 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
301
302 sc->sc_xcvr = TXP_XCVR_AUTO;
303 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0,
304 NULL, NULL, NULL, 0);
305 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO);
306
984263bc 307 ifp->if_softc = sc;
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308 ifp->if_mtu = ETHERMTU;
309 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
310 ifp->if_ioctl = txp_ioctl;
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311 ifp->if_start = txp_start;
312 ifp->if_watchdog = txp_watchdog;
313 ifp->if_init = txp_init;
314 ifp->if_baudrate = 100000000;
871d7209
JS
315 ifq_set_maxlen(&ifp->if_snd, TX_ENTRIES);
316 ifq_set_ready(&ifp->if_snd);
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317 ifp->if_hwassist = 0;
318 txp_capabilities(sc);
319
320 /*
321 * Attach us everywhere
322 */
0a8b5977 323 ether_ifattach(ifp, sc->sc_arpcom.ac_enaddr);
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324 return(0);
325
326fail:
fcb8c909 327 txp_release_resources(dev);
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328 return(error);
329}
330
331static int
332txp_detach(dev)
333 device_t dev;
334{
335 struct txp_softc *sc;
336 struct ifnet *ifp;
337 int i;
338
339 sc = device_get_softc(dev);
340 ifp = &sc->sc_arpcom.ac_if;
341
342 txp_stop(sc);
343 txp_shutdown(dev);
344
345 ifmedia_removeall(&sc->sc_ifmedia);
0a8b5977 346 ether_ifdetach(ifp);
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347
348 for (i = 0; i < RXBUF_ENTRIES; i++)
349 free(sc->sc_rxbufs[i].rb_sd, M_DEVBUF);
350
fcb8c909 351 txp_release_resources(dev);
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352
353 return(0);
354}
355
356static void
fcb8c909 357txp_release_resources(device_t dev)
984263bc 358{
fcb8c909 359 struct txp_softc *sc;
984263bc 360
fcb8c909 361 sc = device_get_softc(dev);
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MD
362
363 if (sc->sc_intrhand != NULL)
364 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
365
366 if (sc->sc_irq != NULL)
367 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
368
369 if (sc->sc_res != NULL)
370 bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res);
371
372 if (sc->sc_ldata != NULL)
373 contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF);
374
375 return;
376}
377
378static int
379txp_chip_init(sc)
380 struct txp_softc *sc;
381{
382 /* disable interrupts */
383 WRITE_REG(sc, TXP_IER, 0);
384 WRITE_REG(sc, TXP_IMR,
385 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
386 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
387 TXP_INT_LATCH);
388
389 /* ack all interrupts */
390 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
391 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
392 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
393 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
394 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0);
395
396 if (txp_reset_adapter(sc))
397 return (-1);
398
399 /* disable interrupts */
400 WRITE_REG(sc, TXP_IER, 0);
401 WRITE_REG(sc, TXP_IMR,
402 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
403 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
404 TXP_INT_LATCH);
405
406 /* ack all interrupts */
407 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
408 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
409 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
410 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
411 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0);
412
413 return (0);
414}
415
416static int
417txp_reset_adapter(sc)
418 struct txp_softc *sc;
419{
420 u_int32_t r;
421 int i;
422
423 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL);
424 DELAY(1000);
425 WRITE_REG(sc, TXP_SRR, 0);
426
427 /* Should wait max 6 seconds */
428 for (i = 0; i < 6000; i++) {
429 r = READ_REG(sc, TXP_A2H_0);
430 if (r == STAT_WAITING_FOR_HOST_REQUEST)
431 break;
432 DELAY(1000);
433 }
434
435 if (r != STAT_WAITING_FOR_HOST_REQUEST) {
fcb8c909 436 if_printf(&sc->sc_arpcom.ac_if, "reset hung\n");
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437 return (-1);
438 }
439
440 return (0);
441}
442
443static int
444txp_download_fw(sc)
445 struct txp_softc *sc;
446{
447 struct txp_fw_file_header *fileheader;
448 struct txp_fw_section_header *secthead;
449 int sect;
450 u_int32_t r, i, ier, imr;
451
452 ier = READ_REG(sc, TXP_IER);
453 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0);
454
455 imr = READ_REG(sc, TXP_IMR);
456 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0);
457
458 for (i = 0; i < 10000; i++) {
459 r = READ_REG(sc, TXP_A2H_0);
460 if (r == STAT_WAITING_FOR_HOST_REQUEST)
461 break;
462 DELAY(50);
463 }
464 if (r != STAT_WAITING_FOR_HOST_REQUEST) {
fcb8c909
JS
465 if_printf(&sc->sc_arpcom.ac_if,
466 "not waiting for host request\n");
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467 return (-1);
468 }
469
470 /* Ack the status */
471 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
472
473 fileheader = (struct txp_fw_file_header *)tc990image;
474 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) {
fcb8c909 475 if_printf(&sc->sc_arpcom.ac_if, "fw invalid magic\n");
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MD
476 return (-1);
477 }
478
479 /* Tell boot firmware to get ready for image */
480 WRITE_REG(sc, TXP_H2A_1, fileheader->addr);
481 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE);
482
483 if (txp_download_fw_wait(sc)) {
fcb8c909 484 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed, initial\n");
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485 return (-1);
486 }
487
488 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) +
489 sizeof(struct txp_fw_file_header));
490
491 for (sect = 0; sect < fileheader->nsections; sect++) {
492 if (txp_download_fw_section(sc, secthead, sect))
493 return (-1);
494 secthead = (struct txp_fw_section_header *)
495 (((u_int8_t *)secthead) + secthead->nbytes +
496 sizeof(*secthead));
497 }
498
499 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE);
500
501 for (i = 0; i < 10000; i++) {
502 r = READ_REG(sc, TXP_A2H_0);
503 if (r == STAT_WAITING_FOR_BOOT)
504 break;
505 DELAY(50);
506 }
507 if (r != STAT_WAITING_FOR_BOOT) {
fcb8c909 508 if_printf(&sc->sc_arpcom.ac_if, "not waiting for boot\n");
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509 return (-1);
510 }
511
512 WRITE_REG(sc, TXP_IER, ier);
513 WRITE_REG(sc, TXP_IMR, imr);
514
515 return (0);
516}
517
518static int
519txp_download_fw_wait(sc)
520 struct txp_softc *sc;
521{
522 u_int32_t i, r;
523
524 for (i = 0; i < 10000; i++) {
525 r = READ_REG(sc, TXP_ISR);
526 if (r & TXP_INT_A2H_0)
527 break;
528 DELAY(50);
529 }
530
531 if (!(r & TXP_INT_A2H_0)) {
fcb8c909 532 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed comm0\n");
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533 return (-1);
534 }
535
536 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
537
538 r = READ_REG(sc, TXP_A2H_0);
539 if (r != STAT_WAITING_FOR_SEGMENT) {
fcb8c909 540 if_printf(&sc->sc_arpcom.ac_if, "fw not waiting for segment\n");
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541 return (-1);
542 }
543 return (0);
544}
545
546static int
547txp_download_fw_section(sc, sect, sectnum)
548 struct txp_softc *sc;
549 struct txp_fw_section_header *sect;
550 int sectnum;
551{
552 vm_offset_t dma;
553 int rseg, err = 0;
554 struct mbuf m;
555 u_int16_t csum;
556
557 /* Skip zero length sections */
558 if (sect->nbytes == 0)
559 return (0);
560
561 /* Make sure we aren't past the end of the image */
562 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image);
563 if (rseg >= sizeof(tc990image)) {
fcb8c909 564 if_printf(&sc->sc_arpcom.ac_if, "fw invalid section address, "
984263bc
MD
565 "section %d\n", sectnum);
566 return (-1);
567 }
568
569 /* Make sure this section doesn't go past the end */
570 rseg += sect->nbytes;
571 if (rseg >= sizeof(tc990image)) {
fcb8c909 572 if_printf(&sc->sc_arpcom.ac_if, "fw truncated section %d\n",
984263bc
MD
573 sectnum);
574 return (-1);
575 }
576
577 bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes);
578 dma = vtophys(sc->sc_fwbuf);
579
580 /*
581 * dummy up mbuf and verify section checksum
582 */
583 m.m_type = MT_DATA;
584 m.m_next = m.m_nextpkt = NULL;
585 m.m_len = sect->nbytes;
586 m.m_data = sc->sc_fwbuf;
587 m.m_flags = 0;
588 csum = in_cksum(&m, sect->nbytes);
589 if (csum != sect->cksum) {
fcb8c909 590 if_printf(&sc->sc_arpcom.ac_if, "fw section %d, bad "
984263bc
MD
591 "cksum (expected 0x%x got 0x%x)\n",
592 sectnum, sect->cksum, csum);
593 err = -1;
594 goto bail;
595 }
596
597 WRITE_REG(sc, TXP_H2A_1, sect->nbytes);
598 WRITE_REG(sc, TXP_H2A_2, sect->cksum);
599 WRITE_REG(sc, TXP_H2A_3, sect->addr);
600 WRITE_REG(sc, TXP_H2A_4, 0);
601 WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff);
602 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE);
603
604 if (txp_download_fw_wait(sc)) {
fcb8c909 605 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed, "
984263bc
MD
606 "section %d\n", sectnum);
607 err = -1;
608 }
609
610bail:
611 return (err);
612}
613
614static void
615txp_intr(vsc)
616 void *vsc;
617{
618 struct txp_softc *sc = vsc;
619 struct txp_hostvar *hv = sc->sc_hostvar;
620 u_int32_t isr;
621
622 /* mask all interrupts */
623 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF |
624 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
625 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 |
626 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
627 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH);
628
629 isr = READ_REG(sc, TXP_ISR);
630 while (isr) {
631 WRITE_REG(sc, TXP_ISR, isr);
632
633 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff))
634 txp_rx_reclaim(sc, &sc->sc_rxhir);
635 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff))
636 txp_rx_reclaim(sc, &sc->sc_rxlor);
637
638 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx)
639 txp_rxbuf_reclaim(sc);
640
641 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons !=
642 TXP_OFFSET2IDX(*(sc->sc_txhir.r_off))))
643 txp_tx_reclaim(sc, &sc->sc_txhir);
644
645 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons !=
646 TXP_OFFSET2IDX(*(sc->sc_txlor.r_off))))
647 txp_tx_reclaim(sc, &sc->sc_txlor);
648
649 isr = READ_REG(sc, TXP_ISR);
650 }
651
652 /* unmask all interrupts */
653 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3);
654
655 txp_start(&sc->sc_arpcom.ac_if);
656
657 return;
658}
659
660static void
661txp_rx_reclaim(sc, r)
662 struct txp_softc *sc;
663 struct txp_rx_ring *r;
664{
665 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
666 struct txp_rx_desc *rxd;
667 struct mbuf *m;
668 struct txp_swdesc *sd = NULL;
669 u_int32_t roff, woff;
984263bc
MD
670
671 roff = *r->r_roff;
672 woff = *r->r_woff;
673 rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc));
674
675 while (roff != woff) {
676
677 if (rxd->rx_flags & RX_FLAGS_ERROR) {
fcb8c909 678 if_printf(ifp, "error 0x%x\n", rxd->rx_stat);
984263bc
MD
679 ifp->if_ierrors++;
680 goto next;
681 }
682
683 /* retrieve stashed pointer */
684 sd = rxd->rx_sd;
685
686 m = sd->sd_mbuf;
687 sd->sd_mbuf = NULL;
688
689 m->m_pkthdr.len = m->m_len = rxd->rx_len;
690
691#ifdef __STRICT_ALIGNMENT
692 {
693 /*
694 * XXX Nice chip, except it won't accept "off by 2"
695 * buffers, so we're force to copy. Supposedly
696 * this will be fixed in a newer firmware rev
697 * and this will be temporary.
698 */
699 struct mbuf *mnew;
700
74f1caca 701 MGETHDR(mnew, MB_DONTWAIT, MT_DATA);
984263bc
MD
702 if (mnew == NULL) {
703 m_freem(m);
704 goto next;
705 }
706 if (m->m_len > (MHLEN - 2)) {
74f1caca 707 MCLGET(mnew, MB_DONTWAIT);
984263bc
MD
708 if (!(mnew->m_flags & M_EXT)) {
709 m_freem(mnew);
710 m_freem(m);
711 goto next;
712 }
713 }
714 mnew->m_pkthdr.rcvif = ifp;
715 m_adj(mnew, 2);
716 mnew->m_pkthdr.len = mnew->m_len = m->m_len;
717 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t));
718 m_freem(m);
719 m = mnew;
720 }
721#endif
722
723 if (rxd->rx_stat & RX_STAT_IPCKSUMBAD)
724 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
725 else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD)
726 m->m_pkthdr.csum_flags |=
727 CSUM_IP_CHECKED|CSUM_IP_VALID;
728
729 if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) ||
730 (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) {
731 m->m_pkthdr.csum_flags |=
732 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
733 m->m_pkthdr.csum_data = 0xffff;
734 }
735
3013ac0e
JS
736 if (rxd->rx_stat & RX_STAT_VLAN)
737 VLAN_INPUT_TAG(m, htons(rxd->rx_vlan >> 16));
738 else
739 (*ifp->if_input)(ifp, m);
984263bc
MD
740
741next:
742
743 roff += sizeof(struct txp_rx_desc);
744 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) {
745 roff = 0;
746 rxd = r->r_desc;
747 } else
748 rxd++;
749 woff = *r->r_woff;
750 }
751
752 *r->r_roff = woff;
753
754 return;
755}
756
757static void
758txp_rxbuf_reclaim(sc)
759 struct txp_softc *sc;
760{
761 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
762 struct txp_hostvar *hv = sc->sc_hostvar;
763 struct txp_rxbuf_desc *rbd;
764 struct txp_swdesc *sd;
765 u_int32_t i;
766
767 if (!(ifp->if_flags & IFF_RUNNING))
768 return;
769
770 i = sc->sc_rxbufprod;
771 rbd = sc->sc_rxbufs + i;
772
773 while (1) {
774 sd = rbd->rb_sd;
775 if (sd->sd_mbuf != NULL)
776 break;
777
74f1caca 778 MGETHDR(sd->sd_mbuf, MB_DONTWAIT, MT_DATA);
984263bc
MD
779 if (sd->sd_mbuf == NULL)
780 goto err_sd;
781
74f1caca 782 MCLGET(sd->sd_mbuf, MB_DONTWAIT);
984263bc
MD
783 if ((sd->sd_mbuf->m_flags & M_EXT) == 0)
784 goto err_mbuf;
785 sd->sd_mbuf->m_pkthdr.rcvif = ifp;
786 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES;
787
788 rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t))
789 & 0xffffffff;
790 rbd->rb_paddrhi = 0;
791
792 hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i);
793
794 if (++i == RXBUF_ENTRIES) {
795 i = 0;
796 rbd = sc->sc_rxbufs;
797 } else
798 rbd++;
799 }
800
801 sc->sc_rxbufprod = i;
802
803 return;
804
805err_mbuf:
806 m_freem(sd->sd_mbuf);
807err_sd:
808 free(sd, M_DEVBUF);
809}
810
811/*
812 * Reclaim mbufs and entries from a transmit ring.
813 */
814static void
815txp_tx_reclaim(sc, r)
816 struct txp_softc *sc;
817 struct txp_tx_ring *r;
818{
819 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
820 u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off));
821 u_int32_t cons = r->r_cons, cnt = r->r_cnt;
822 struct txp_tx_desc *txd = r->r_desc + cons;
823 struct txp_swdesc *sd = sc->sc_txd + cons;
824 struct mbuf *m;
825
826 while (cons != idx) {
827 if (cnt == 0)
828 break;
829
830 if ((txd->tx_flags & TX_FLAGS_TYPE_M) ==
831 TX_FLAGS_TYPE_DATA) {
832 m = sd->sd_mbuf;
833 if (m != NULL) {
834 m_freem(m);
835 txd->tx_addrlo = 0;
836 txd->tx_addrhi = 0;
837 ifp->if_opackets++;
838 }
839 }
840 ifp->if_flags &= ~IFF_OACTIVE;
841
842 if (++cons == TX_ENTRIES) {
843 txd = r->r_desc;
844 cons = 0;
845 sd = sc->sc_txd;
846 } else {
847 txd++;
848 sd++;
849 }
850
851 cnt--;
852 }
853
854 r->r_cons = cons;
855 r->r_cnt = cnt;
856 if (cnt == 0)
857 ifp->if_timer = 0;
858}
859
860static int
861txp_shutdown(dev)
862 device_t dev;
863{
864 struct txp_softc *sc;
865
866 sc = device_get_softc(dev);
867
868 /* mask all interrupts */
869 WRITE_REG(sc, TXP_IMR,
870 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
871 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
872 TXP_INT_LATCH);
873
874 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0);
875 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0);
876 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0);
877
878 return(0);
879}
880
881static int
882txp_alloc_rings(sc)
883 struct txp_softc *sc;
884{
885 struct txp_boot_record *boot;
886 struct txp_ldata *ld;
887 u_int32_t r;
888 int i;
889
890 ld = sc->sc_ldata;
891 boot = &ld->txp_boot;
892
893 /* boot record */
894 sc->sc_boot = boot;
895
896 /* host variables */
897 bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar));
898 boot->br_hostvar_lo = vtophys(&ld->txp_hostvar);
899 boot->br_hostvar_hi = 0;
900 sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar;
901
902 /* hi priority tx ring */
903 boot->br_txhipri_lo = vtophys(&ld->txp_txhiring);;
904 boot->br_txhipri_hi = 0;
905 boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc);
906 sc->sc_txhir.r_reg = TXP_H2A_1;
907 sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring;
908 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0;
909 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx;
910
911 /* lo priority tx ring */
912 boot->br_txlopri_lo = vtophys(&ld->txp_txloring);
913 boot->br_txlopri_hi = 0;
914 boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc);
915 sc->sc_txlor.r_reg = TXP_H2A_3;
916 sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring;
917 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0;
918 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx;
919
920 /* high priority rx ring */
921 boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring);
922 boot->br_rxhipri_hi = 0;
923 boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc);
924 sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring;
925 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx;
926 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx;
927
928 /* low priority rx ring */
929 boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring);
930 boot->br_rxlopri_hi = 0;
931 boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc);
932 sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring;
933 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx;
934 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx;
935
936 /* command ring */
937 bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES);
938 boot->br_cmd_lo = vtophys(&ld->txp_cmdring);
939 boot->br_cmd_hi = 0;
940 boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc);
941 sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring;
942 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc);
943 sc->sc_cmdring.lastwrite = 0;
944
945 /* response ring */
946 bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES);
947 boot->br_resp_lo = vtophys(&ld->txp_rspring);
948 boot->br_resp_hi = 0;
949 boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc);
950 sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring;
951 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc);
952 sc->sc_rspring.lastwrite = 0;
953
954 /* receive buffer ring */
955 boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs);
956 boot->br_rxbuf_hi = 0;
957 boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc);
958 sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs;
959
960 for (i = 0; i < RXBUF_ENTRIES; i++) {
961 struct txp_swdesc *sd;
962 if (sc->sc_rxbufs[i].rb_sd != NULL)
963 continue;
964 sc->sc_rxbufs[i].rb_sd = malloc(sizeof(struct txp_swdesc),
c5541aee 965 M_DEVBUF, M_WAITOK);
984263bc
MD
966 if (sc->sc_rxbufs[i].rb_sd == NULL)
967 return(ENOBUFS);
968 sd = sc->sc_rxbufs[i].rb_sd;
969 sd->sd_mbuf = NULL;
970 }
971 sc->sc_rxbufprod = 0;
972
973 /* zero dma */
974 bzero(&ld->txp_zero, sizeof(u_int32_t));
975 boot->br_zero_lo = vtophys(&ld->txp_zero);
976 boot->br_zero_hi = 0;
977
978 /* See if it's waiting for boot, and try to boot it */
979 for (i = 0; i < 10000; i++) {
980 r = READ_REG(sc, TXP_A2H_0);
981 if (r == STAT_WAITING_FOR_BOOT)
982 break;
983 DELAY(50);
984 }
985
986 if (r != STAT_WAITING_FOR_BOOT) {
fcb8c909 987 if_printf(&sc->sc_arpcom.ac_if, "not waiting for boot\n");
984263bc
MD
988 return(ENXIO);
989 }
990
991 WRITE_REG(sc, TXP_H2A_2, 0);
992 WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot));
993 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD);
994
995 /* See if it booted */
996 for (i = 0; i < 10000; i++) {
997 r = READ_REG(sc, TXP_A2H_0);
998 if (r == STAT_RUNNING)
999 break;
1000 DELAY(50);
1001 }
1002 if (r != STAT_RUNNING) {
fcb8c909 1003 if_printf(&sc->sc_arpcom.ac_if, "fw not running\n");
984263bc
MD
1004 return(ENXIO);
1005 }
1006
1007 /* Clear TX and CMD ring write registers */
1008 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL);
1009 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL);
1010 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL);
1011 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL);
1012
1013 return (0);
1014}
1015
1016static int
bd4539cc 1017txp_ioctl(ifp, command, data, cr)
984263bc
MD
1018 struct ifnet *ifp;
1019 u_long command;
1020 caddr_t data;
bd4539cc 1021 struct ucred *cr;
984263bc
MD
1022{
1023 struct txp_softc *sc = ifp->if_softc;
1024 struct ifreq *ifr = (struct ifreq *)data;
9228feed 1025 int error = 0;
984263bc 1026
9228feed 1027 crit_enter();
984263bc 1028
984263bc 1029 switch(command) {
984263bc
MD
1030 case SIOCSIFFLAGS:
1031 if (ifp->if_flags & IFF_UP) {
1032 txp_init(sc);
1033 } else {
1034 if (ifp->if_flags & IFF_RUNNING)
1035 txp_stop(sc);
1036 }
1037 break;
1038 case SIOCADDMULTI:
1039 case SIOCDELMULTI:
1040 /*
1041 * Multicast list has changed; set the hardware
1042 * filter accordingly.
1043 */
1044 txp_set_filter(sc);
1045 error = 0;
1046 break;
1047 case SIOCGIFMEDIA:
1048 case SIOCSIFMEDIA:
1049 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command);
1050 break;
1051 default:
417b83e4 1052 error = ether_ioctl(ifp, command, data);
984263bc
MD
1053 break;
1054 }
1055
9228feed 1056 crit_exit();
984263bc
MD
1057
1058 return(error);
1059}
1060
1061static int
1062txp_rxring_fill(sc)
1063 struct txp_softc *sc;
1064{
1065 int i;
1066 struct ifnet *ifp;
1067 struct txp_swdesc *sd;
1068
1069 ifp = &sc->sc_arpcom.ac_if;
1070
1071 for (i = 0; i < RXBUF_ENTRIES; i++) {
1072 sd = sc->sc_rxbufs[i].rb_sd;
74f1caca 1073 MGETHDR(sd->sd_mbuf, MB_DONTWAIT, MT_DATA);
984263bc
MD
1074 if (sd->sd_mbuf == NULL)
1075 return(ENOBUFS);
1076
74f1caca 1077 MCLGET(sd->sd_mbuf, MB_DONTWAIT);
984263bc
MD
1078 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) {
1079 m_freem(sd->sd_mbuf);
1080 return(ENOBUFS);
1081 }
1082 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES;
1083 sd->sd_mbuf->m_pkthdr.rcvif = ifp;
1084
1085 sc->sc_rxbufs[i].rb_paddrlo =
1086 vtophys(mtod(sd->sd_mbuf, vm_offset_t));
1087 sc->sc_rxbufs[i].rb_paddrhi = 0;
1088 }
1089
1090 sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) *
1091 sizeof(struct txp_rxbuf_desc);
1092
1093 return(0);
1094}
1095
1096static void
1097txp_rxring_empty(sc)
1098 struct txp_softc *sc;
1099{
1100 int i;
1101 struct txp_swdesc *sd;
1102
1103 if (sc->sc_rxbufs == NULL)
1104 return;
1105
1106 for (i = 0; i < RXBUF_ENTRIES; i++) {
1107 if (&sc->sc_rxbufs[i] == NULL)
1108 continue;
1109 sd = sc->sc_rxbufs[i].rb_sd;
1110 if (sd == NULL)
1111 continue;
1112 if (sd->sd_mbuf != NULL) {
1113 m_freem(sd->sd_mbuf);
1114 sd->sd_mbuf = NULL;
1115 }
1116 }
1117
1118 return;
1119}
1120
1121static void
1122txp_init(xsc)
1123 void *xsc;
1124{
1125 struct txp_softc *sc;
1126 struct ifnet *ifp;
1127 u_int16_t p1;
1128 u_int32_t p2;
984263bc
MD
1129
1130 sc = xsc;
1131 ifp = &sc->sc_arpcom.ac_if;
1132
1133 if (ifp->if_flags & IFF_RUNNING)
1134 return;
1135
1136 txp_stop(sc);
1137
9228feed 1138 crit_enter();
984263bc
MD
1139
1140 txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0,
1141 NULL, NULL, NULL, 1);
1142
1143 /* Set station address. */
1144 ((u_int8_t *)&p1)[1] = sc->sc_arpcom.ac_enaddr[0];
1145 ((u_int8_t *)&p1)[0] = sc->sc_arpcom.ac_enaddr[1];
1146 ((u_int8_t *)&p2)[3] = sc->sc_arpcom.ac_enaddr[2];
1147 ((u_int8_t *)&p2)[2] = sc->sc_arpcom.ac_enaddr[3];
1148 ((u_int8_t *)&p2)[1] = sc->sc_arpcom.ac_enaddr[4];
1149 ((u_int8_t *)&p2)[0] = sc->sc_arpcom.ac_enaddr[5];
1150 txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0,
1151 NULL, NULL, NULL, 1);
1152
1153 txp_set_filter(sc);
1154
1155 txp_rxring_fill(sc);
1156
1157 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1158 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1159
1160 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF |
1161 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
1162 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 |
1163 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
1164 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH);
1165 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3);
1166
1167 ifp->if_flags |= IFF_RUNNING;
1168 ifp->if_flags &= ~IFF_OACTIVE;
1169 ifp->if_timer = 0;
1170
9e6fd080 1171 callout_reset(&sc->txp_stat_timer, hz, txp_tick, sc);
984263bc 1172
9228feed 1173 crit_exit();
984263bc
MD
1174}
1175
1176static void
1177txp_tick(vsc)
1178 void *vsc;
1179{
1180 struct txp_softc *sc = vsc;
1181 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1182 struct txp_rsp_desc *rsp = NULL;
1183 struct txp_ext_desc *ext;
984263bc 1184
9228feed 1185 crit_enter();
984263bc
MD
1186 txp_rxbuf_reclaim(sc);
1187
1188 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0,
1189 &rsp, 1))
1190 goto out;
1191 if (rsp->rsp_numdesc != 6)
1192 goto out;
1193 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0,
1194 NULL, NULL, NULL, 1))
1195 goto out;
1196 ext = (struct txp_ext_desc *)(rsp + 1);
1197
1198 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 +
1199 ext[4].ext_1 + ext[4].ext_4;
1200 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 +
1201 ext[2].ext_1;
1202 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 +
1203 ext[1].ext_3;
1204 ifp->if_opackets += rsp->rsp_par2;
1205 ifp->if_ipackets += ext[2].ext_3;
1206
1207out:
1208 if (rsp != NULL)
1209 free(rsp, M_DEVBUF);
1210
9e6fd080 1211 callout_reset(&sc->txp_stat_timer, hz, txp_tick, sc);
7113465f 1212 crit_exit();
984263bc
MD
1213}
1214
1215static void
1216txp_start(ifp)
1217 struct ifnet *ifp;
1218{
1219 struct txp_softc *sc = ifp->if_softc;
1220 struct txp_tx_ring *r = &sc->sc_txhir;
1221 struct txp_tx_desc *txd;
1222 struct txp_frag_desc *fxd;
1223 struct mbuf *m, *m0;
1224 struct txp_swdesc *sd;
1225 u_int32_t firstprod, firstcnt, prod, cnt;
1226 struct ifvlan *ifv;
1227
1228 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1229 return;
1230
1231 prod = r->r_prod;
1232 cnt = r->r_cnt;
1233
1234 while (1) {
871d7209 1235 m = ifq_poll(&ifp->if_snd);
984263bc
MD
1236 if (m == NULL)
1237 break;
1238
1239 firstprod = prod;
1240 firstcnt = cnt;
1241
1242 sd = sc->sc_txd + prod;
1243 sd->sd_mbuf = m;
1244
1245 if ((TX_ENTRIES - cnt) < 4)
1246 goto oactive;
1247
1248 txd = r->r_desc + prod;
1249
1250 txd->tx_flags = TX_FLAGS_TYPE_DATA;
1251 txd->tx_numdesc = 0;
1252 txd->tx_addrlo = 0;
1253 txd->tx_addrhi = 0;
1254 txd->tx_totlen = 0;
1255 txd->tx_pflags = 0;
1256
1257 if (++prod == TX_ENTRIES)
1258 prod = 0;
1259
1260 if (++cnt >= (TX_ENTRIES - 4))
1261 goto oactive;
1262
1263 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1264 m->m_pkthdr.rcvif != NULL) {
1265 ifv = m->m_pkthdr.rcvif->if_softc;
1266 txd->tx_pflags = TX_PFLAGS_VLAN |
1267 (htons(ifv->ifv_tag) << TX_PFLAGS_VLANTAG_S);
1268 }
1269
1270 if (m->m_pkthdr.csum_flags & CSUM_IP)
1271 txd->tx_pflags |= TX_PFLAGS_IPCKSUM;
1272
1273#if 0
1274 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1275 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM;
1276 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1277 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM;
1278#endif
1279
1280 fxd = (struct txp_frag_desc *)(r->r_desc + prod);
1281 for (m0 = m; m0 != NULL; m0 = m0->m_next) {
1282 if (m0->m_len == 0)
1283 continue;
1284 if (++cnt >= (TX_ENTRIES - 4))
1285 goto oactive;
1286
1287 txd->tx_numdesc++;
1288
1289 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG;
1290 fxd->frag_rsvd1 = 0;
1291 fxd->frag_len = m0->m_len;
1292 fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t));
1293 fxd->frag_addrhi = 0;
1294 fxd->frag_rsvd2 = 0;
1295
1296 if (++prod == TX_ENTRIES) {
1297 fxd = (struct txp_frag_desc *)r->r_desc;
1298 prod = 0;
1299 } else
1300 fxd++;
1301
1302 }
1303
1304 ifp->if_timer = 5;
1305
871d7209 1306 m = ifq_dequeue(&ifp->if_snd);
7600679e 1307 BPF_MTAP(ifp, m);
984263bc
MD
1308 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod));
1309 }
1310
1311 r->r_prod = prod;
1312 r->r_cnt = cnt;
1313 return;
1314
1315oactive:
1316 ifp->if_flags |= IFF_OACTIVE;
1317 r->r_prod = firstprod;
1318 r->r_cnt = firstcnt;
984263bc
MD
1319 return;
1320}
1321
1322/*
1323 * Handle simple commands sent to the typhoon
1324 */
1325static int
1326txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait)
1327 struct txp_softc *sc;
1328 u_int16_t id, in1, *out1;
1329 u_int32_t in2, in3, *out2, *out3;
1330 int wait;
1331{
1332 struct txp_rsp_desc *rsp = NULL;
1333
1334 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait))
1335 return (-1);
1336
1337 if (!wait)
1338 return (0);
1339
1340 if (out1 != NULL)
1341 *out1 = rsp->rsp_par1;
1342 if (out2 != NULL)
1343 *out2 = rsp->rsp_par2;
1344 if (out3 != NULL)
1345 *out3 = rsp->rsp_par3;
1346 free(rsp, M_DEVBUF);
1347 return (0);
1348}
1349
1350static int
1351txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait)
1352 struct txp_softc *sc;
1353 u_int16_t id, in1;
1354 u_int32_t in2, in3;
1355 struct txp_ext_desc *in_extp;
1356 u_int8_t in_extn;
1357 struct txp_rsp_desc **rspp;
1358 int wait;
1359{
1360 struct txp_hostvar *hv = sc->sc_hostvar;
1361 struct txp_cmd_desc *cmd;
1362 struct txp_ext_desc *ext;
1363 u_int32_t idx, i;
1364 u_int16_t seq;
1365
1366 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) {
fcb8c909 1367 if_printf(&sc->sc_arpcom.ac_if, "no free cmd descriptors\n");
984263bc
MD
1368 return (-1);
1369 }
1370
1371 idx = sc->sc_cmdring.lastwrite;
1372 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx);
1373 bzero(cmd, sizeof(*cmd));
1374
1375 cmd->cmd_numdesc = in_extn;
1376 cmd->cmd_seq = seq = sc->sc_seq++;
1377 cmd->cmd_id = id;
1378 cmd->cmd_par1 = in1;
1379 cmd->cmd_par2 = in2;
1380 cmd->cmd_par3 = in3;
1381 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD |
1382 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID;
1383
1384 idx += sizeof(struct txp_cmd_desc);
1385 if (idx == sc->sc_cmdring.size)
1386 idx = 0;
1387
1388 for (i = 0; i < in_extn; i++) {
1389 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx);
1390 bcopy(in_extp, ext, sizeof(struct txp_ext_desc));
1391 in_extp++;
1392 idx += sizeof(struct txp_cmd_desc);
1393 if (idx == sc->sc_cmdring.size)
1394 idx = 0;
1395 }
1396
1397 sc->sc_cmdring.lastwrite = idx;
1398
1399 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite);
1400
1401 if (!wait)
1402 return (0);
1403
1404 for (i = 0; i < 10000; i++) {
1405 idx = hv->hv_resp_read_idx;
1406 if (idx != hv->hv_resp_write_idx) {
1407 *rspp = NULL;
1408 if (txp_response(sc, idx, id, seq, rspp))
1409 return (-1);
1410 if (*rspp != NULL)
1411 break;
1412 }
1413 DELAY(50);
1414 }
1415 if (i == 1000 || (*rspp) == NULL) {
fcb8c909 1416 if_printf(&sc->sc_arpcom.ac_if, "0x%x command failed\n", id);
984263bc
MD
1417 return (-1);
1418 }
1419
1420 return (0);
1421}
1422
1423static int
1424txp_response(sc, ridx, id, seq, rspp)
1425 struct txp_softc *sc;
1426 u_int32_t ridx;
1427 u_int16_t id;
1428 u_int16_t seq;
1429 struct txp_rsp_desc **rspp;
1430{
1431 struct txp_hostvar *hv = sc->sc_hostvar;
1432 struct txp_rsp_desc *rsp;
1433
1434 while (ridx != hv->hv_resp_write_idx) {
1435 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx);
1436
1437 if (id == rsp->rsp_id && rsp->rsp_seq == seq) {
1438 *rspp = (struct txp_rsp_desc *)malloc(
1439 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1),
c5541aee 1440 M_DEVBUF, M_INTWAIT);
984263bc
MD
1441 if ((*rspp) == NULL)
1442 return (-1);
1443 txp_rsp_fixup(sc, rsp, *rspp);
1444 return (0);
1445 }
1446
1447 if (rsp->rsp_flags & RSP_FLAGS_ERROR) {
fcb8c909 1448 if_printf(&sc->sc_arpcom.ac_if, "response error!\n");
984263bc
MD
1449 txp_rsp_fixup(sc, rsp, NULL);
1450 ridx = hv->hv_resp_read_idx;
1451 continue;
1452 }
1453
1454 switch (rsp->rsp_id) {
1455 case TXP_CMD_CYCLE_STATISTICS:
1456 case TXP_CMD_MEDIA_STATUS_READ:
1457 break;
1458 case TXP_CMD_HELLO_RESPONSE:
fcb8c909 1459 if_printf(&sc->sc_arpcom.ac_if, "hello\n");
984263bc
MD
1460 break;
1461 default:
fcb8c909 1462 if_printf(&sc->sc_arpcom.ac_if, "unknown id(0x%x)\n",
984263bc
MD
1463 rsp->rsp_id);
1464 }
1465
1466 txp_rsp_fixup(sc, rsp, NULL);
1467 ridx = hv->hv_resp_read_idx;
1468 hv->hv_resp_read_idx = ridx;
1469 }
1470
1471 return (0);
1472}
1473
1474static void
1475txp_rsp_fixup(sc, rsp, dst)
1476 struct txp_softc *sc;
1477 struct txp_rsp_desc *rsp, *dst;
1478{
1479 struct txp_rsp_desc *src = rsp;
1480 struct txp_hostvar *hv = sc->sc_hostvar;
1481 u_int32_t i, ridx;
1482
1483 ridx = hv->hv_resp_read_idx;
1484
1485 for (i = 0; i < rsp->rsp_numdesc + 1; i++) {
1486 if (dst != NULL)
1487 bcopy(src, dst++, sizeof(struct txp_rsp_desc));
1488 ridx += sizeof(struct txp_rsp_desc);
1489 if (ridx == sc->sc_rspring.size) {
1490 src = sc->sc_rspring.base;
1491 ridx = 0;
1492 } else
1493 src++;
1494 sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx;
1495 }
1496
1497 hv->hv_resp_read_idx = ridx;
1498}
1499
1500static int
1501txp_cmd_desc_numfree(sc)
1502 struct txp_softc *sc;
1503{
1504 struct txp_hostvar *hv = sc->sc_hostvar;
1505 struct txp_boot_record *br = sc->sc_boot;
1506 u_int32_t widx, ridx, nfree;
1507
1508 widx = sc->sc_cmdring.lastwrite;
1509 ridx = hv->hv_cmd_read_idx;
1510
1511 if (widx == ridx) {
1512 /* Ring is completely free */
1513 nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc);
1514 } else {
1515 if (widx > ridx)
1516 nfree = br->br_cmd_siz -
1517 (widx - ridx + sizeof(struct txp_cmd_desc));
1518 else
1519 nfree = ridx - widx - sizeof(struct txp_cmd_desc);
1520 }
1521
1522 return (nfree / sizeof(struct txp_cmd_desc));
1523}
1524
1525static void
1526txp_stop(sc)
1527 struct txp_softc *sc;
1528{
1529 struct ifnet *ifp;
1530
1531 ifp = &sc->sc_arpcom.ac_if;
1532
1533 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1534
9e6fd080 1535 callout_stop(&sc->txp_stat_timer);
984263bc
MD
1536
1537 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1538 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1539
1540 txp_rxring_empty(sc);
1541
1542 return;
1543}
1544
1545static void
1546txp_watchdog(ifp)
1547 struct ifnet *ifp;
1548{
1549 return;
1550}
1551
1552static int
1553txp_ifmedia_upd(ifp)
1554 struct ifnet *ifp;
1555{
1556 struct txp_softc *sc = ifp->if_softc;
1557 struct ifmedia *ifm = &sc->sc_ifmedia;
1558 u_int16_t new_xcvr;
1559
1560 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1561 return (EINVAL);
1562
1563 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) {
1564 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1565 new_xcvr = TXP_XCVR_10_FDX;
1566 else
1567 new_xcvr = TXP_XCVR_10_HDX;
1568 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
1569 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1570 new_xcvr = TXP_XCVR_100_FDX;
1571 else
1572 new_xcvr = TXP_XCVR_100_HDX;
1573 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
1574 new_xcvr = TXP_XCVR_AUTO;
1575 } else
1576 return (EINVAL);
1577
1578 /* nothing to do */
1579 if (sc->sc_xcvr == new_xcvr)
1580 return (0);
1581
1582 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0,
1583 NULL, NULL, NULL, 0);
1584 sc->sc_xcvr = new_xcvr;
1585
1586 return (0);
1587}
1588
1589static void
1590txp_ifmedia_sts(ifp, ifmr)
1591 struct ifnet *ifp;
1592 struct ifmediareq *ifmr;
1593{
1594 struct txp_softc *sc = ifp->if_softc;
1595 struct ifmedia *ifm = &sc->sc_ifmedia;
1596 u_int16_t bmsr, bmcr, anlpar;
1597
1598 ifmr->ifm_status = IFM_AVALID;
1599 ifmr->ifm_active = IFM_ETHER;
1600
1601 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0,
1602 &bmsr, NULL, NULL, 1))
1603 goto bail;
1604 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0,
1605 &bmsr, NULL, NULL, 1))
1606 goto bail;
1607
1608 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0,
1609 &bmcr, NULL, NULL, 1))
1610 goto bail;
1611
1612 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0,
1613 &anlpar, NULL, NULL, 1))
1614 goto bail;
1615
1616 if (bmsr & BMSR_LINK)
1617 ifmr->ifm_status |= IFM_ACTIVE;
1618
1619 if (bmcr & BMCR_ISO) {
1620 ifmr->ifm_active |= IFM_NONE;
1621 ifmr->ifm_status = 0;
1622 return;
1623 }
1624
1625 if (bmcr & BMCR_LOOP)
1626 ifmr->ifm_active |= IFM_LOOP;
1627
1628 if (bmcr & BMCR_AUTOEN) {
1629 if ((bmsr & BMSR_ACOMP) == 0) {
1630 ifmr->ifm_active |= IFM_NONE;
1631 return;
1632 }
1633
1634 if (anlpar & ANLPAR_T4)
1635 ifmr->ifm_active |= IFM_100_T4;
1636 else if (anlpar & ANLPAR_TX_FD)
1637 ifmr->ifm_active |= IFM_100_TX|IFM_FDX;
1638 else if (anlpar & ANLPAR_TX)
1639 ifmr->ifm_active |= IFM_100_TX;
1640 else if (anlpar & ANLPAR_10_FD)
1641 ifmr->ifm_active |= IFM_10_T|IFM_FDX;
1642 else if (anlpar & ANLPAR_10)
1643 ifmr->ifm_active |= IFM_10_T;
1644 else
1645 ifmr->ifm_active |= IFM_NONE;
1646 } else
1647 ifmr->ifm_active = ifm->ifm_cur->ifm_media;
1648 return;
1649
1650bail:
1651 ifmr->ifm_active |= IFM_NONE;
1652 ifmr->ifm_status &= ~IFM_AVALID;
1653}
1654
1655#ifdef TXP_DEBUG
1656static void
1657txp_show_descriptor(d)
1658 void *d;
1659{
1660 struct txp_cmd_desc *cmd = d;
1661 struct txp_rsp_desc *rsp = d;
1662 struct txp_tx_desc *txd = d;
1663 struct txp_frag_desc *frgd = d;
1664
1665 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) {
1666 case CMD_FLAGS_TYPE_CMD:
1667 /* command descriptor */
1668 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1669 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq,
1670 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3);
1671 break;
1672 case CMD_FLAGS_TYPE_RESP:
1673 /* response descriptor */
1674 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1675 rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq,
1676 rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3);
1677 break;
1678 case CMD_FLAGS_TYPE_DATA:
1679 /* data header (assuming tx for now) */
1680 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]",
1681 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen,
1682 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags);
1683 break;
1684 case CMD_FLAGS_TYPE_FRAG:
1685 /* fragment descriptor */
1686 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]",
1687 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len,
1688 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2);
1689 break;
1690 default:
1691 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1692 cmd->cmd_flags & CMD_FLAGS_TYPE_M,
1693 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq,
1694 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3);
1695 break;
1696 }
1697}
1698#endif
1699
1700static void
1701txp_set_filter(sc)
1702 struct txp_softc *sc;
1703{
1704 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1705 u_int32_t crc, carry, hashbit, hash[2];
1706 u_int16_t filter;
1707 u_int8_t octet;
1708 int i, j, mcnt = 0;
1709 struct ifmultiaddr *ifma;
1710 char *enm;
1711
1712 if (ifp->if_flags & IFF_PROMISC) {
1713 filter = TXP_RXFILT_PROMISC;
1714 goto setit;
1715 }
1716
1717 filter = TXP_RXFILT_DIRECT;
1718
1719 if (ifp->if_flags & IFF_BROADCAST)
1720 filter |= TXP_RXFILT_BROADCAST;
1721
1722 if (ifp->if_flags & IFF_ALLMULTI)
1723 filter |= TXP_RXFILT_ALLMULTI;
1724 else {
1725 hash[0] = hash[1] = 0;
1726
1727 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1728 ifma = ifma->ifma_link.le_next) {
1729 if (ifma->ifma_addr->sa_family != AF_LINK)
1730 continue;
1731
1732 enm = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
1733 mcnt++;
1734 crc = 0xffffffff;
1735
1736 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1737 octet = enm[i];
1738 for (j = 0; j < 8; j++) {
1739 carry = ((crc & 0x80000000) ? 1 : 0) ^
1740 (octet & 1);
1741 crc <<= 1;
1742 octet >>= 1;
1743 if (carry)
1744 crc = (crc ^ TXP_POLYNOMIAL) |
1745 carry;
1746 }
1747 }
1748 hashbit = (u_int16_t)(crc & (64 - 1));
1749 hash[hashbit / 32] |= (1 << hashbit % 32);
1750 }
1751
1752 if (mcnt > 0) {
1753 filter |= TXP_RXFILT_HASHMULTI;
1754 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE,
1755 2, hash[0], hash[1], NULL, NULL, NULL, 0);
1756 }
1757 }
1758
1759setit:
1760
1761 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0,
1762 NULL, NULL, NULL, 1);
1763
1764 return;
1765}
1766
1767static void
1768txp_capabilities(sc)
1769 struct txp_softc *sc;
1770{
1771 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1772 struct txp_rsp_desc *rsp = NULL;
1773 struct txp_ext_desc *ext;
1774
1775 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1))
1776 goto out;
1777
1778 if (rsp->rsp_numdesc != 1)
1779 goto out;
1780 ext = (struct txp_ext_desc *)(rsp + 1);
1781
1782 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK;
1783 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK;
1784 ifp->if_capabilities = 0;
1785
1786 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) {
1787 sc->sc_tx_capability |= OFFLOAD_VLAN;
1788 sc->sc_rx_capability |= OFFLOAD_VLAN;
1789 }
1790
1791#if 0
1792 /* not ready yet */
1793 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) {
1794 sc->sc_tx_capability |= OFFLOAD_IPSEC;
1795 sc->sc_rx_capability |= OFFLOAD_IPSEC;
1796 ifp->if_capabilities |= IFCAP_IPSEC;
1797 }
1798#endif
1799
1800 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) {
1801 sc->sc_tx_capability |= OFFLOAD_IPCKSUM;
1802 sc->sc_rx_capability |= OFFLOAD_IPCKSUM;
1803 ifp->if_capabilities |= IFCAP_HWCSUM;
1804 ifp->if_hwassist |= CSUM_IP;
1805 }
1806
1807 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) {
1808#if 0
1809 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM;
1810#endif
1811 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM;
1812 ifp->if_capabilities |= IFCAP_HWCSUM;
1813 }
1814
1815 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) {
1816#if 0
1817 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM;
1818#endif
1819 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM;
1820 ifp->if_capabilities |= IFCAP_HWCSUM;
1821 }
1822 ifp->if_capenable = ifp->if_capabilities;
1823
1824 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0,
1825 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1))
1826 goto out;
1827
1828out:
1829 if (rsp != NULL)
1830 free(rsp, M_DEVBUF);
1831
1832 return;
1833}