Directly use ifp->if_snd, it's type will change soon.
[dragonfly.git] / sys / dev / atm / en / midway.c
CommitLineData
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1/* $NetBSD: midway.c,v 1.30 1997/09/29 17:40:38 chuck Exp $ */
2/* (sync'd to midway.c 1.68) */
3
4/*
5 *
6 * Copyright (c) 1996 Charles D. Cranor and Washington University.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Charles D. Cranor and
20 * Washington University.
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * $FreeBSD: src/sys/dev/en/midway.c,v 1.19.2.1 2003/01/23 21:06:42 sam Exp $
fea370b7 36 * $DragonFly: src/sys/dev/atm/en/midway.c,v 1.16 2005/02/10 00:07:23 joerg Exp $
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37 */
38
39/*
40 *
41 * m i d w a y . c e n i 1 5 5 d r i v e r
42 *
43 * author: Chuck Cranor <chuck@ccrc.wustl.edu>
44 * started: spring, 1996 (written from scratch).
45 *
46 * notes from the author:
47 * Extra special thanks go to Werner Almesberger, EPFL LRC. Werner's
48 * ENI driver was especially useful in figuring out how this card works.
49 * I would also like to thank Werner for promptly answering email and being
50 * generally helpful.
51 */
52
53#undef EN_DEBUG
54#undef EN_DEBUG_RANGE /* check ranges on en_read/en_write's? */
55#define EN_MBUF_OPT /* try and put more stuff in mbuf? */
56#define EN_DIAG
57#define EN_STAT
58#ifndef EN_DMA
59#define EN_DMA 1 /* use dma? */
60#endif
61#define EN_NOTXDMA 0 /* hook to disable tx dma only */
62#define EN_NORXDMA 0 /* hook to disable rx dma only */
63#define EN_DDBHOOK 1 /* compile in ddb functions */
64#if defined(MIDWAY_ADPONLY)
65#define EN_ENIDMAFIX 0 /* no ENI cards to worry about */
66#else
67#define EN_ENIDMAFIX 1 /* avoid byte DMA on the ENI card (see below) */
68#endif
69
70/*
71 * note on EN_ENIDMAFIX: the byte aligner on the ENI version of the card
72 * appears to be broken. it works just fine if there is no load... however
73 * when the card is loaded the data get corrupted. to see this, one only
74 * has to use "telnet" over ATM. do the following command in "telnet":
75 * cat /usr/share/misc/termcap
76 * "telnet" seems to generate lots of 1023 byte mbufs (which make great
77 * use of the byte aligner). watch "netstat -s" for checksum errors.
78 *
79 * I further tested this by adding a function that compared the transmit
80 * data on the card's SRAM with the data in the mbuf chain _after_ the
81 * "transmit DMA complete" interrupt. using the "telnet" test I got data
82 * mismatches where the byte-aligned data should have been. using ddb
83 * and en_dumpmem() I verified that the DTQs fed into the card were
84 * absolutely correct. thus, we are forced to concluded that the ENI
85 * hardware is buggy. note that the Adaptec version of the card works
86 * just fine with byte DMA.
87 *
88 * bottom line: we set EN_ENIDMAFIX to 1 to avoid byte DMAs on the ENI
89 * card.
90 */
91
92#if defined(DIAGNOSTIC) && !defined(EN_DIAG)
93#define EN_DIAG /* link in with master DIAG option */
94#endif
95#ifdef EN_STAT
96#define EN_COUNT(X) (X)++
97#else
98#define EN_COUNT(X) /* nothing */
99#endif
100
101#ifdef EN_DEBUG
102#undef EN_DDBHOOK
103#define EN_DDBHOOK 1
104#define STATIC /* nothing */
105#define INLINE /* nothing */
106#else /* EN_DEBUG */
107#define STATIC static
108#define INLINE __inline
109#endif /* EN_DEBUG */
110
1f2de5d4 111#include "use_en.h" /* XXX for midwayvar.h's NEN */
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112#include "opt_inet.h"
113#include "opt_natm.h"
114#include "opt_ddb.h"
115/* enable DDBHOOK when DDB is available */
116#undef EN_DDBHOOK
117#ifdef DDB
118#define EN_DDBHOOK 1
119#endif
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120
121#include <sys/param.h>
122#include <sys/systm.h>
123#include <sys/queue.h>
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124#include <sys/sockio.h>
125#include <sys/mbuf.h>
126#include <sys/socket.h>
127#include <sys/proc.h>
128
129#include <net/if.h>
130#include <net/if_atm.h>
131
132#include <vm/vm.h>
133
134#if defined(INET) || defined(INET6)
135#include <netinet/in.h>
136#include <netinet/if_atm.h>
137#endif
138
139#ifdef NATM
d2438d69 140#include <netproto/natm/natm.h>
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141#endif
142
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143#include "midwayreg.h"
144#include "midwayvar.h"
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145#include <vm/pmap.h> /* for vtophys proto */
146
147#ifndef IFF_NOTRAILERS
148#define IFF_NOTRAILERS 0
149#endif
150
984263bc 151#include <net/bpf.h>
984263bc 152#define BPFATTACH(ifp, dlt, hlen) bpfattach((ifp), (dlt), (hlen))
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153
154/*
155 * params
156 */
157
158#ifndef EN_TXHIWAT
159#define EN_TXHIWAT (64*1024) /* max 64 KB waiting to be DMAd out */
160#endif
161
162#ifndef EN_MINDMA
163#define EN_MINDMA 32 /* don't DMA anything less than this (bytes) */
164#endif
165
166#define RX_NONE 0xffff /* recv VC not in use */
167
168#define EN_OBHDR ATM_PH_DRIVER7 /* TBD in first mbuf ! */
169#define EN_OBTRL ATM_PH_DRIVER8 /* PDU trailier in last mbuf ! */
170
171#define ENOTHER_FREE 0x01 /* free rxslot */
172#define ENOTHER_DRAIN 0x02 /* almost free (drain DRQ dma) */
173#define ENOTHER_RAW 0x04 /* 'raw' access (aka boodi mode) */
174#define ENOTHER_SWSL 0x08 /* in software service list */
175
176static int en_dma = EN_DMA; /* use DMA (switch off for dbg) */
177
178/*
179 * autoconfig attachments
180 */
181
182struct cfdriver en_cd = {
183 0, "en", DV_IFNET,
184};
185
186/*
187 * local structures
188 */
189
190/*
191 * params to en_txlaunch() function
192 */
193
194struct en_launch {
195 u_int32_t tbd1; /* TBD 1 */
196 u_int32_t tbd2; /* TBD 2 */
197 u_int32_t pdu1; /* PDU 1 (aal5) */
198 int nodma; /* don't use DMA */
199 int need; /* total space we need (pad out if less data) */
200 int mlen; /* length of mbuf (for dtq) */
201 struct mbuf *t; /* data */
202 u_int32_t aal; /* aal code */
203 u_int32_t atm_vci; /* vci */
204 u_int8_t atm_flags; /* flags */
205};
206
207
208/*
209 * dma table (index by # of words)
210 *
211 * plan A: use WMAYBE (obsolete)
212 * plan B: avoid WMAYBE
213 */
214
215struct en_dmatab {
216 u_int8_t bcode; /* code */
217 u_int8_t divshift; /* byte divisor */
218};
219
220static struct en_dmatab en_dma_planB[] = {
221 { 0, 0 }, /* 0 */ { MIDDMA_WORD, 2}, /* 1 */
222 { MIDDMA_2WORD, 3}, /* 2 */ { MIDDMA_WORD, 2}, /* 3 */
223 { MIDDMA_4WORD, 4}, /* 4 */ { MIDDMA_WORD, 2}, /* 5 */
224 { MIDDMA_2WORD, 3}, /* 6 */ { MIDDMA_WORD, 2}, /* 7 */
225 { MIDDMA_8WORD, 5}, /* 8 */ { MIDDMA_WORD, 2}, /* 9 */
226 { MIDDMA_2WORD, 3}, /* 10 */ { MIDDMA_WORD, 2}, /* 11 */
227 { MIDDMA_4WORD, 4}, /* 12 */ { MIDDMA_WORD, 2}, /* 13 */
228 { MIDDMA_2WORD, 3}, /* 14 */ { MIDDMA_WORD, 2}, /* 15 */
229 { MIDDMA_16WORD, 6}, /* 16 */
230};
231
232static struct en_dmatab *en_dmaplan = en_dma_planB;
233
234/*
235 * prototypes
236 */
237
38e94a25 238STATIC INLINE int en_b2sz (int) __attribute__ ((unused));
984263bc 239#ifdef EN_DDBHOOK
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240 int en_dump (int,int);
241 int en_dumpmem (int,int,int);
984263bc 242#endif
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243STATIC void en_dmaprobe (struct en_softc *);
244STATIC int en_dmaprobe_doit (struct en_softc *, u_int8_t *,
245 u_int8_t *, int);
246STATIC INLINE int en_dqneed (struct en_softc *, caddr_t, u_int,
247 u_int) __attribute__ ((unused));
248STATIC void en_init (struct en_softc *);
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249STATIC int en_ioctl (struct ifnet *, EN_IOCTL_CMDT, caddr_t,
250 struct ucred *);
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251STATIC INLINE int en_k2sz (int) __attribute__ ((unused));
252STATIC void en_loadvc (struct en_softc *, int);
253STATIC int en_mfix (struct en_softc *, struct mbuf **,
254 struct mbuf *);
255STATIC INLINE struct mbuf *en_mget (struct en_softc *, u_int,
256 u_int *) __attribute__ ((unused));
257STATIC INLINE u_int32_t en_read (struct en_softc *,
258 u_int32_t) __attribute__ ((unused));
259STATIC int en_rxctl (struct en_softc *, struct atm_pseudoioctl *,
260 int);
261STATIC void en_txdma (struct en_softc *, int);
262STATIC void en_txlaunch (struct en_softc *, int,
263 struct en_launch *);
264STATIC void en_service (struct en_softc *);
265STATIC void en_start (struct ifnet *);
266STATIC INLINE int en_sz2b (int) __attribute__ ((unused));
267STATIC INLINE void en_write (struct en_softc *, u_int32_t,
268 u_int32_t) __attribute__ ((unused));
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269
270/*
271 * macros/inline
272 */
273
274/*
275 * raw read/write macros
276 */
277
278#define EN_READDAT(SC,R) en_read(SC,R)
279#define EN_WRITEDAT(SC,R,V) en_write(SC,R,V)
280
281/*
282 * cooked read/write macros
283 */
284
285#define EN_READ(SC,R) ntohl(en_read(SC,R))
286#define EN_WRITE(SC,R,V) en_write(SC,R, htonl(V))
287
288#define EN_WRAPADD(START,STOP,CUR,VAL) { \
289 (CUR) = (CUR) + (VAL); \
290 if ((CUR) >= (STOP)) \
291 (CUR) = (START) + ((CUR) - (STOP)); \
292 }
293
294#define WORD_IDX(START, X) (((X) - (START)) / sizeof(u_int32_t))
295
296/* we store sc->dtq and sc->drq data in the following format... */
297#define EN_DQ_MK(SLOT,LEN) (((SLOT) << 20)|(LEN)|(0x80000))
298 /* the 0x80000 ensures we != 0 */
299#define EN_DQ_SLOT(X) ((X) >> 20)
300#define EN_DQ_LEN(X) ((X) & 0x3ffff)
301
302/* format of DTQ/DRQ word 1 differs between ENI and ADP */
303#if defined(MIDWAY_ENIONLY)
304
305#define MID_MK_TXQ(SC,CNT,CHAN,END,BCODE) \
306 EN_WRITE((SC), (SC)->dtq_us, \
307 MID_MK_TXQ_ENI((CNT), (CHAN), (END), (BCODE)));
308
309#define MID_MK_RXQ(SC,CNT,VCI,END,BCODE) \
310 EN_WRITE((SC), (SC)->drq_us, \
311 MID_MK_RXQ_ENI((CNT), (VCI), (END), (BCODE)));
312
313#elif defined(MIDWAY_ADPONLY)
314
315#define MID_MK_TXQ(SC,CNT,CHAN,END,JK) \
316 EN_WRITE((SC), (SC)->dtq_us, \
317 MID_MK_TXQ_ADP((CNT), (CHAN), (END), (JK)));
318
319#define MID_MK_RXQ(SC,CNT,VCI,END,JK) \
320 EN_WRITE((SC), (SC)->drq_us, \
321 MID_MK_RXQ_ADP((CNT), (VCI), (END), (JK)));
322
323#else
324
325#define MID_MK_TXQ(SC,CNT,CHAN,END,JK_OR_BCODE) { \
326 if ((SC)->is_adaptec) \
327 EN_WRITE((SC), (SC)->dtq_us, \
328 MID_MK_TXQ_ADP((CNT), (CHAN), (END), (JK_OR_BCODE))); \
329 else \
330 EN_WRITE((SC), (SC)->dtq_us, \
331 MID_MK_TXQ_ENI((CNT), (CHAN), (END), (JK_OR_BCODE))); \
332 }
333
334#define MID_MK_RXQ(SC,CNT,VCI,END,JK_OR_BCODE) { \
335 if ((SC)->is_adaptec) \
336 EN_WRITE((SC), (SC)->drq_us, \
337 MID_MK_RXQ_ADP((CNT), (VCI), (END), (JK_OR_BCODE))); \
338 else \
339 EN_WRITE((SC), (SC)->drq_us, \
340 MID_MK_RXQ_ENI((CNT), (VCI), (END), (JK_OR_BCODE))); \
341 }
342
343#endif
344
345/* add an item to the DTQ */
346#define EN_DTQADD(SC,CNT,CHAN,JK_OR_BCODE,ADDR,LEN,END) { \
347 if (END) \
348 (SC)->dtq[MID_DTQ_A2REG((SC)->dtq_us)] = EN_DQ_MK(CHAN,LEN); \
349 MID_MK_TXQ(SC,CNT,CHAN,END,JK_OR_BCODE); \
350 (SC)->dtq_us += 4; \
351 EN_WRITE((SC), (SC)->dtq_us, (ADDR)); \
352 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, (SC)->dtq_us, 4); \
353 (SC)->dtq_free--; \
354 if (END) \
355 EN_WRITE((SC), MID_DMA_WRTX, MID_DTQ_A2REG((SC)->dtq_us)); \
356}
357
358/* DRQ add macro */
359#define EN_DRQADD(SC,CNT,VCI,JK_OR_BCODE,ADDR,LEN,SLOT,END) { \
360 if (END) \
361 (SC)->drq[MID_DRQ_A2REG((SC)->drq_us)] = EN_DQ_MK(SLOT,LEN); \
362 MID_MK_RXQ(SC,CNT,VCI,END,JK_OR_BCODE); \
363 (SC)->drq_us += 4; \
364 EN_WRITE((SC), (SC)->drq_us, (ADDR)); \
365 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, (SC)->drq_us, 4); \
366 (SC)->drq_free--; \
367 if (END) \
368 EN_WRITE((SC), MID_DMA_WRRX, MID_DRQ_A2REG((SC)->drq_us)); \
369}
370
371/*
372 * the driver code
373 *
374 * the code is arranged in a specific way:
375 * [1] short/inline functions
376 * [2] autoconfig stuff
377 * [3] ioctl stuff
378 * [4] reset -> init -> trasmit -> intr -> receive functions
379 *
380 */
381
382/***********************************************************************/
383
384/*
385 * en_read: read a word from the card. this is the only function
386 * that reads from the card.
387 */
388
389STATIC INLINE u_int32_t en_read(sc, r)
390
391struct en_softc *sc;
392u_int32_t r;
393
394{
395
396#ifdef EN_DEBUG_RANGE
397 if (r > MID_MAXOFF || (r % 4))
398 panic("en_read out of range, r=0x%x", r);
399#endif
400
401 return(bus_space_read_4(sc->en_memt, sc->en_base, r));
402}
403
404/*
405 * en_write: write a word to the card. this is the only function that
406 * writes to the card.
407 */
408
409STATIC INLINE void en_write(sc, r, v)
410
411struct en_softc *sc;
412u_int32_t r, v;
413
414{
415#ifdef EN_DEBUG_RANGE
416 if (r > MID_MAXOFF || (r % 4))
417 panic("en_write out of range, r=0x%x", r);
418#endif
419
420 bus_space_write_4(sc->en_memt, sc->en_base, r, v);
421}
422
423/*
424 * en_k2sz: convert KBytes to a size parameter (a log2)
425 */
426
427STATIC INLINE int en_k2sz(k)
428
429int k;
430
431{
432 switch(k) {
433 case 1: return(0);
434 case 2: return(1);
435 case 4: return(2);
436 case 8: return(3);
437 case 16: return(4);
438 case 32: return(5);
439 case 64: return(6);
440 case 128: return(7);
441 default: panic("en_k2sz");
442 }
443 return(0);
444}
445#define en_log2(X) en_k2sz(X)
446
447
448/*
449 * en_b2sz: convert a DMA burst code to its byte size
450 */
451
452STATIC INLINE int en_b2sz(b)
453
454int b;
455
456{
457 switch (b) {
458 case MIDDMA_WORD: return(1*4);
459 case MIDDMA_2WMAYBE:
460 case MIDDMA_2WORD: return(2*4);
461 case MIDDMA_4WMAYBE:
462 case MIDDMA_4WORD: return(4*4);
463 case MIDDMA_8WMAYBE:
464 case MIDDMA_8WORD: return(8*4);
465 case MIDDMA_16WMAYBE:
466 case MIDDMA_16WORD: return(16*4);
467 default: panic("en_b2sz");
468 }
469 return(0);
470}
471
472
473/*
474 * en_sz2b: convert a burst size (bytes) to DMA burst code
475 */
476
477STATIC INLINE int en_sz2b(sz)
478
479int sz;
480
481{
482 switch (sz) {
483 case 1*4: return(MIDDMA_WORD);
484 case 2*4: return(MIDDMA_2WORD);
485 case 4*4: return(MIDDMA_4WORD);
486 case 8*4: return(MIDDMA_8WORD);
487 case 16*4: return(MIDDMA_16WORD);
488 default: panic("en_sz2b");
489 }
490 return(0);
491}
492
493
494/*
495 * en_dqneed: calculate number of DTQ/DRQ's needed for a buffer
496 */
497
498STATIC INLINE int en_dqneed(sc, data, len, tx)
499
500struct en_softc *sc;
501caddr_t data;
502u_int len, tx;
503
504{
505 int result, needalign, sz;
506
507#if !defined(MIDWAY_ENIONLY)
508#if !defined(MIDWAY_ADPONLY)
509 if (sc->is_adaptec)
510#endif /* !MIDWAY_ADPONLY */
511 return(1); /* adaptec can DMA anything in one go */
512#endif
513
514#if !defined(MIDWAY_ADPONLY)
515 result = 0;
516 if (len < EN_MINDMA) {
517 if (!tx) /* XXX: conservative */
518 return(1); /* will copy/DMA_JK */
519 }
520
521 if (tx) { /* byte burst? */
522 needalign = (((uintptr_t) (void *) data) % sizeof(u_int32_t));
523 if (needalign) {
524 result++;
525 sz = min(len, sizeof(u_int32_t) - needalign);
526 len -= sz;
527 data += sz;
528 }
529 }
530
531 if (sc->alburst && len) {
532 needalign = (((uintptr_t) (void *) data) & sc->bestburstmask);
533 if (needalign) {
534 result++; /* alburst */
535 sz = min(len, sc->bestburstlen - needalign);
536 len -= sz;
537 }
538 }
539
540 if (len >= sc->bestburstlen) {
541 sz = len / sc->bestburstlen;
542 sz = sz * sc->bestburstlen;
543 len -= sz;
544 result++; /* best shot */
545 }
546
547 if (len) {
548 result++; /* clean up */
549 if (tx && (len % sizeof(u_int32_t)) != 0)
550 result++; /* byte cleanup */
551 }
552
553 return(result);
554#endif /* !MIDWAY_ADPONLY */
555}
556
557
558/*
559 * en_mget: get an mbuf chain that can hold totlen bytes and return it
560 * (for recv) [based on am7990_get from if_le and ieget from if_ie]
561 * after this call the sum of all the m_len's in the chain will be totlen.
562 */
563
564STATIC INLINE struct mbuf *en_mget(sc, totlen, drqneed)
565
566struct en_softc *sc;
567u_int totlen, *drqneed;
568
569{
570 struct mbuf *m;
571 struct mbuf *top, **mp;
572 *drqneed = 0;
573
74f1caca 574 MGETHDR(m, MB_DONTWAIT, MT_DATA);
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575 if (m == NULL)
576 return(NULL);
577 m->m_pkthdr.rcvif = &sc->enif;
578 m->m_pkthdr.len = totlen;
579 m->m_len = MHLEN;
580 top = NULL;
581 mp = &top;
582
583 /* if (top != NULL) then we've already got 1 mbuf on the chain */
584 while (totlen > 0) {
585 if (top) {
74f1caca 586 MGET(m, MB_DONTWAIT, MT_DATA);
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587 if (!m) {
588 m_freem(top);
589 return(NULL); /* out of mbufs */
590 }
591 m->m_len = MLEN;
592 }
593 if (totlen >= MINCLSIZE) {
74f1caca 594 MCLGET(m, MB_DONTWAIT);
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595 if ((m->m_flags & M_EXT) == 0) {
596 m_free(m);
597 m_freem(top);
598 return(NULL); /* out of mbuf clusters */
599 }
600 m->m_len = MCLBYTES;
601 }
602 m->m_len = min(totlen, m->m_len);
603 totlen -= m->m_len;
604 *mp = m;
605 mp = &m->m_next;
606
607 *drqneed += en_dqneed(sc, m->m_data, m->m_len, 0);
608
609 }
610 return(top);
611}
612
613/***********************************************************************/
614
615/*
616 * autoconfig stuff
617 */
618
619void en_attach(sc)
620
621struct en_softc *sc;
622
623{
624 struct ifnet *ifp = &sc->enif;
625 int sz;
626 u_int32_t reg, lcv, check, ptr, sav, midvloc;
627
628 /*
629 * probe card to determine memory size. the stupid ENI card always
630 * reports to PCI that it needs 4MB of space (2MB regs and 2MB RAM).
631 * if it has less than 2MB RAM the addresses wrap in the RAM address space.
632 * (i.e. on a 512KB card addresses 0x3ffffc, 0x37fffc, and 0x2ffffc
633 * are aliases for 0x27fffc [note that RAM starts at offset 0x200000]).
634 */
635
636 if (sc->en_busreset)
637 sc->en_busreset(sc);
638 EN_WRITE(sc, MID_RESID, 0x0); /* reset card before touching RAM */
639 for (lcv = MID_PROBEOFF; lcv <= MID_MAXOFF ; lcv += MID_PROBSIZE) {
640 EN_WRITE(sc, lcv, lcv); /* data[address] = address */
641 for (check = MID_PROBEOFF ; check < lcv ; check += MID_PROBSIZE) {
642 reg = EN_READ(sc, check);
643 if (reg != check) { /* found an alias! */
644 goto done_probe; /* and quit */
645 }
646 }
647 }
648done_probe:
649 lcv -= MID_PROBSIZE; /* take one step back */
650 sc->en_obmemsz = (lcv + 4) - MID_RAMOFF;
651
652 /*
653 * determine the largest DMA burst supported
654 */
655
656 en_dmaprobe(sc);
657
658 /*
659 * "hello world"
660 */
661
662 if (sc->en_busreset)
663 sc->en_busreset(sc);
664 EN_WRITE(sc, MID_RESID, 0x0); /* reset */
665 for (lcv = MID_RAMOFF ; lcv < MID_RAMOFF + sc->en_obmemsz ; lcv += 4)
666 EN_WRITE(sc, lcv, 0); /* zero memory */
667
668 reg = EN_READ(sc, MID_RESID);
669
670 printf("%s: ATM midway v%d, board IDs %d.%d, %s%s%s, %ldKB on-board RAM\n",
671 sc->sc_dev.dv_xname, MID_VER(reg), MID_MID(reg), MID_DID(reg),
672 (MID_IS_SABRE(reg)) ? "sabre controller, " : "",
673 (MID_IS_SUNI(reg)) ? "SUNI" : "Utopia",
674 (!MID_IS_SUNI(reg) && MID_IS_UPIPE(reg)) ? " (pipelined)" : "",
675 (long)(sc->en_obmemsz / 1024));
676
677 if (sc->is_adaptec) {
678 if (sc->bestburstlen == 64 && sc->alburst == 0)
679 printf("%s: passed 64 byte DMA test\n", sc->sc_dev.dv_xname);
680 else
681 printf("%s: FAILED DMA TEST: burst=%d, alburst=%d\n",
682 sc->sc_dev.dv_xname, sc->bestburstlen, sc->alburst);
683 } else {
684 printf("%s: maximum DMA burst length = %d bytes%s\n", sc->sc_dev.dv_xname,
685 sc->bestburstlen, (sc->alburst) ? " (must align)" : "");
686 }
687
688 /*
689 * link into network subsystem and prepare card
690 */
691
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692 sc->enif.if_softc = sc;
693 ifp->if_flags = IFF_SIMPLEX|IFF_NOTRAILERS;
694 ifp->if_ioctl = en_ioctl;
695 ifp->if_output = atm_output;
696 ifp->if_start = en_start;
697
698 /*
699 * init softc
700 */
701
702 for (lcv = 0 ; lcv < MID_N_VC ; lcv++) {
703 sc->rxvc2slot[lcv] = RX_NONE;
704 sc->txspeed[lcv] = 0; /* full */
705 sc->txvc2slot[lcv] = 0; /* full speed == slot 0 */
706 }
707
708 sz = sc->en_obmemsz - (MID_BUFOFF - MID_RAMOFF);
709 ptr = sav = MID_BUFOFF;
710 ptr = roundup(ptr, EN_TXSZ * 1024); /* align */
711 sz = sz - (ptr - sav);
712 if (EN_TXSZ*1024 * EN_NTX > sz) {
713 printf("%s: EN_NTX/EN_TXSZ too big\n", sc->sc_dev.dv_xname);
714 return;
715 }
716 for (lcv = 0 ; lcv < EN_NTX ; lcv++) {
717 sc->txslot[lcv].mbsize = 0;
718 sc->txslot[lcv].start = ptr;
719 ptr += (EN_TXSZ * 1024);
720 sz -= (EN_TXSZ * 1024);
721 sc->txslot[lcv].stop = ptr;
722 sc->txslot[lcv].nref = 0;
723 bzero(&sc->txslot[lcv].indma, sizeof(sc->txslot[lcv].indma));
724 bzero(&sc->txslot[lcv].q, sizeof(sc->txslot[lcv].q));
725#ifdef EN_DEBUG
726 printf("%s: tx%d: start 0x%x, stop 0x%x\n", sc->sc_dev.dv_xname, lcv,
727 sc->txslot[lcv].start, sc->txslot[lcv].stop);
728#endif
729 }
730
731 sav = ptr;
732 ptr = roundup(ptr, EN_RXSZ * 1024); /* align */
733 sz = sz - (ptr - sav);
734 sc->en_nrx = sz / (EN_RXSZ * 1024);
735 if (sc->en_nrx <= 0) {
736 printf("%s: EN_NTX/EN_TXSZ/EN_RXSZ too big\n", sc->sc_dev.dv_xname);
737 return;
738 }
739
740 /*
741 * ensure that there is always one VC slot on the service list free
742 * so that we can tell the difference between a full and empty list.
743 */
744 if (sc->en_nrx >= MID_N_VC)
745 sc->en_nrx = MID_N_VC - 1;
746
747 for (lcv = 0 ; lcv < sc->en_nrx ; lcv++) {
748 sc->rxslot[lcv].rxhand = NULL;
749 sc->rxslot[lcv].oth_flags = ENOTHER_FREE;
750 bzero(&sc->rxslot[lcv].indma, sizeof(sc->rxslot[lcv].indma));
751 bzero(&sc->rxslot[lcv].q, sizeof(sc->rxslot[lcv].q));
752 midvloc = sc->rxslot[lcv].start = ptr;
753 ptr += (EN_RXSZ * 1024);
754 sz -= (EN_RXSZ * 1024);
755 sc->rxslot[lcv].stop = ptr;
756 midvloc = midvloc - MID_RAMOFF;
757 midvloc = (midvloc & ~((EN_RXSZ*1024) - 1)) >> 2; /* mask, cvt to words */
758 midvloc = midvloc >> MIDV_LOCTOPSHFT; /* we only want the top 11 bits */
759 midvloc = (midvloc & MIDV_LOCMASK) << MIDV_LOCSHIFT;
760 sc->rxslot[lcv].mode = midvloc |
761 (en_k2sz(EN_RXSZ) << MIDV_SZSHIFT) | MIDV_TRASH;
762
763#ifdef EN_DEBUG
764 printf("%s: rx%d: start 0x%x, stop 0x%x, mode 0x%x\n", sc->sc_dev.dv_xname,
765 lcv, sc->rxslot[lcv].start, sc->rxslot[lcv].stop, sc->rxslot[lcv].mode);
766#endif
767 }
768
769#ifdef EN_STAT
770 sc->vtrash = sc->otrash = sc->mfix = sc->txmbovr = sc->dmaovr = 0;
771 sc->txoutspace = sc->txdtqout = sc->launch = sc->lheader = sc->ltail = 0;
772 sc->hwpull = sc->swadd = sc->rxqnotus = sc->rxqus = sc->rxoutboth = 0;
773 sc->rxdrqout = sc->ttrash = sc->rxmbufout = sc->mfixfail = 0;
774 sc->headbyte = sc->tailbyte = sc->tailflush = 0;
775#endif
776 sc->need_drqs = sc->need_dtqs = 0;
777
778 printf("%s: %d %dKB receive buffers, %d %dKB transmit buffers allocated\n",
779 sc->sc_dev.dv_xname, sc->en_nrx, EN_RXSZ, EN_NTX, EN_TXSZ);
780
781 printf("%s: End Station Identifier (mac address) %6D\n",
782 sc->sc_dev.dv_xname, sc->macaddr, ":");
783
784 /*
785 * final commit
786 */
984263bc 787 atm_ifattach(ifp);
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788}
789
790
791/*
792 * en_dmaprobe: helper function for en_attach.
793 *
794 * see how the card handles DMA by running a few DMA tests. we need
795 * to figure out the largest number of bytes we can DMA in one burst
796 * ("bestburstlen"), and if the starting address for a burst needs to
797 * be aligned on any sort of boundary or not ("alburst").
798 *
799 * typical findings:
800 * sparc1: bestburstlen=4, alburst=0 (ick, broken DMA!)
801 * sparc2: bestburstlen=64, alburst=1
802 * p166: bestburstlen=64, alburst=0
803 */
804
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805#define NBURSTS 3 /* number of bursts to use for dmaprobe */
806#define BOUNDARY 1024 /* test misaligned dma crossing the bounday.
807 should be n * 64. at least 64*(NBURSTS+1).
808 dell P6 with EDO DRAM has 1K bounday problem */
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809
810STATIC void en_dmaprobe(sc)
811
812struct en_softc *sc;
813
814{
815#ifdef NBURSTS
816 /* be careful. kernel stack is only 8K */
817 u_int8_t buffer[BOUNDARY * 2 + 64 * (NBURSTS + 1)];
818#else
819 u_int32_t srcbuf[64], dstbuf[64];
820#endif
821 u_int8_t *sp, *dp;
822 int bestalgn, bestnotalgn, lcv, try;
823
824 sc->alburst = 0;
825
826#ifdef NBURSTS
827 /* setup src and dst buf at the end of the boundary */
828 sp = (u_int8_t *)roundup((uintptr_t)(void *)buffer, 64);
829 while (((uintptr_t)(void *)sp & (BOUNDARY - 1)) != (BOUNDARY - 64))
830 sp += 64;
831 dp = sp + BOUNDARY;
832
833 /*
834 * we can't dma across page boundary so that, if buf is at a page
835 * boundary, move it to the next page. but still either src or dst
836 * will be at the boundary, which should be ok.
837 */
838 if ((((uintptr_t)(void *)sp + 64) & PAGE_MASK) == 0)
839 sp += 64;
840 if ((((uintptr_t)(void *)dp + 64) & PAGE_MASK) == 0)
841 dp += 64;
842#else /* !NBURSTS */
843 sp = (u_int8_t *) srcbuf;
844 while ((((unsigned long) sp) % MIDDMA_MAXBURST) != 0)
845 sp += 4;
846 dp = (u_int8_t *) dstbuf;
847 while ((((unsigned long) dp) % MIDDMA_MAXBURST) != 0)
848 dp += 4;
849#endif /* !NBURSTS */
850
851 bestalgn = bestnotalgn = en_dmaprobe_doit(sc, sp, dp, 0);
852
853 for (lcv = 4 ; lcv < MIDDMA_MAXBURST ; lcv += 4) {
854 try = en_dmaprobe_doit(sc, sp+lcv, dp+lcv, 0);
855#ifdef NBURSTS
856 if (try < bestnotalgn) {
857 bestnotalgn = try;
858 break;
859 }
860#else
861 if (try < bestnotalgn)
862 bestnotalgn = try;
863#endif
864 }
865
866 if (bestalgn != bestnotalgn) /* need bursts aligned */
867 sc->alburst = 1;
868
869 sc->bestburstlen = bestalgn;
870 sc->bestburstshift = en_log2(bestalgn);
871 sc->bestburstmask = sc->bestburstlen - 1; /* must be power of 2 */
872 sc->bestburstcode = en_sz2b(bestalgn);
873
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874 /*
875 * correct pci chipsets should be able to handle misaligned-64-byte DMA.
876 * but there are too many broken chipsets around. we try to work around
877 * by finding the best workable dma size, but still some broken machines
878 * exhibit the problem later. so warn it here.
879 */
880 if (bestalgn != 64 || sc->alburst != 0) {
881 printf("%s: WARNING: DMA test detects a broken PCI chipset!\n",
882 sc->sc_dev.dv_xname);
883 printf(" trying to work around the problem... but if this doesn't\n");
884 printf(" work for you, you'd better switch to a newer motherboard.\n");
885 }
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886 return;
887}
888
889
890/*
891 * en_dmaprobe_doit: do actual testing
892 */
893
894static int
895en_dmaprobe_doit(sc, sp, dp, wmtry)
896
897struct en_softc *sc;
898u_int8_t *sp, *dp;
899int wmtry;
900
901{
902 int lcv, retval = 4, cnt, count;
903 u_int32_t reg, bcode, midvloc;
904
905 /*
906 * set up a 1k buffer at MID_BUFOFF
907 */
908
909 if (sc->en_busreset)
910 sc->en_busreset(sc);
911 EN_WRITE(sc, MID_RESID, 0x0); /* reset card before touching RAM */
912
913 midvloc = ((MID_BUFOFF - MID_RAMOFF) / sizeof(u_int32_t)) >> MIDV_LOCTOPSHFT;
914 EN_WRITE(sc, MIDX_PLACE(0), MIDX_MKPLACE(en_k2sz(1), midvloc));
915 EN_WRITE(sc, MID_VC(0), (midvloc << MIDV_LOCSHIFT)
916 | (en_k2sz(1) << MIDV_SZSHIFT) | MIDV_TRASH);
917 EN_WRITE(sc, MID_DST_RP(0), 0);
918 EN_WRITE(sc, MID_WP_ST_CNT(0), 0);
919
920#ifdef NBURSTS
921 for (lcv = 0 ; lcv < 64*NBURSTS; lcv++) /* set up sample data */
922#else
923 for (lcv = 0 ; lcv < 68 ; lcv++) /* set up sample data */
924#endif
925 sp[lcv] = lcv+1;
926 EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA); /* enable DMA (only) */
927
928 sc->drq_chip = MID_DRQ_REG2A(EN_READ(sc, MID_DMA_RDRX));
929 sc->dtq_chip = MID_DTQ_REG2A(EN_READ(sc, MID_DMA_RDTX));
930
931 /*
932 * try it now . . . DMA it out, then DMA it back in and compare
933 *
934 * note: in order to get the dma stuff to reverse directions it wants
935 * the "end" flag set! since we are not dma'ing valid data we may
936 * get an ident mismatch interrupt (which we will ignore).
937 *
938 * note: we've got two different tests rolled up in the same loop
939 * if (wmtry)
940 * then we are doing a wmaybe test and wmtry is a byte count
941 * else we are doing a burst test
942 */
943
944 for (lcv = 8 ; lcv <= MIDDMA_MAXBURST ; lcv = lcv * 2) {
945
946#ifdef EN_DEBUG
947 printf("DMA test lcv=%d, sp=0x%x, dp=0x%x, wmtry=%d\n",
948 lcv, sp, dp, wmtry);
949#endif
950
951 /* zero SRAM and dest buffer */
952 for (cnt = 0 ; cnt < 1024; cnt += 4)
953 EN_WRITE(sc, MID_BUFOFF+cnt, 0); /* zero memory */
954#ifdef NBURSTS
955 for (cnt = 0 ; cnt < 64*NBURSTS; cnt++)
956#else
957 for (cnt = 0 ; cnt < 68 ; cnt++)
958#endif
959 dp[cnt] = 0;
960
961 if (wmtry) {
962 count = (sc->bestburstlen - sizeof(u_int32_t)) / sizeof(u_int32_t);
963 bcode = en_dmaplan[count].bcode;
964 count = wmtry >> en_dmaplan[count].divshift;
965 } else {
966 bcode = en_sz2b(lcv);
967 count = 1;
968 }
969#ifdef NBURSTS
970 /* build lcv-byte-DMA x NBURSTS */
971 if (sc->is_adaptec)
972 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ADP(lcv*NBURSTS, 0, MID_DMA_END, 0));
973 else
974 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ENI(count*NBURSTS, 0, MID_DMA_END, bcode));
975 EN_WRITE(sc, sc->dtq_chip+4, vtophys(sp));
976 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, sc->dtq_chip, 8);
977 EN_WRITE(sc, MID_DMA_WRTX, MID_DTQ_A2REG(sc->dtq_chip));
978 cnt = 1000;
979 while (EN_READ(sc, MID_DMA_RDTX) != MID_DTQ_A2REG(sc->dtq_chip)) {
980 DELAY(1);
981 cnt--;
982 if (cnt == 0) {
983 printf("%s: unexpected timeout in tx DMA test\n", sc->sc_dev.dv_xname);
984/*
985 printf(" alignment=0x%x, burst size=%d, dma addr reg=0x%x\n",
986 (u_long)sp & 63, lcv, EN_READ(sc, MID_DMA_ADDR));
987*/
988 return(retval); /* timeout, give up */
989 }
990 }
991#else /* !NBURSTS */
992 if (sc->is_adaptec)
993 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ADP(lcv, 0, MID_DMA_END, 0));
994 else
995 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ENI(count, 0, MID_DMA_END, bcode));
996 EN_WRITE(sc, sc->dtq_chip+4, vtophys(sp));
997 EN_WRITE(sc, MID_DMA_WRTX, MID_DTQ_A2REG(sc->dtq_chip+8));
998 cnt = 1000;
999 while (EN_READ(sc, MID_DMA_RDTX) == MID_DTQ_A2REG(sc->dtq_chip)) {
1000 DELAY(1);
1001 cnt--;
1002 if (cnt == 0) {
1003 printf("%s: unexpected timeout in tx DMA test\n", sc->sc_dev.dv_xname);
1004 return(retval); /* timeout, give up */
1005 }
1006 }
1007 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, sc->dtq_chip, 8);
1008#endif /* !NBURSTS */
1009 reg = EN_READ(sc, MID_INTACK);
1010 if ((reg & MID_INT_DMA_TX) != MID_INT_DMA_TX) {
1011 printf("%s: unexpected status in tx DMA test: 0x%x\n",
1012 sc->sc_dev.dv_xname, reg);
1013 return(retval);
1014 }
1015 EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA); /* re-enable DMA (only) */
1016
1017 /* "return to sender..." address is known ... */
1018
1019#ifdef NBURSTS
1020 /* build lcv-byte-DMA x NBURSTS */
1021 if (sc->is_adaptec)
1022 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ADP(lcv*NBURSTS, 0, MID_DMA_END, 0));
1023 else
1024 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ENI(count*NBURSTS, 0, MID_DMA_END, bcode));
1025 EN_WRITE(sc, sc->drq_chip+4, vtophys(dp));
1026 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, sc->drq_chip, 8);
1027 EN_WRITE(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip));
1028 cnt = 1000;
1029 while (EN_READ(sc, MID_DMA_RDRX) != MID_DRQ_A2REG(sc->drq_chip)) {
1030 DELAY(1);
1031 cnt--;
1032 if (cnt == 0) {
1033 printf("%s: unexpected timeout in rx DMA test\n", sc->sc_dev.dv_xname);
1034 return(retval); /* timeout, give up */
1035 }
1036 }
1037#else /* !NBURSTS */
1038 if (sc->is_adaptec)
1039 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ADP(lcv, 0, MID_DMA_END, 0));
1040 else
1041 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ENI(count, 0, MID_DMA_END, bcode));
1042 EN_WRITE(sc, sc->drq_chip+4, vtophys(dp));
1043 EN_WRITE(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip+8));
1044 cnt = 1000;
1045 while (EN_READ(sc, MID_DMA_RDRX) == MID_DRQ_A2REG(sc->drq_chip)) {
1046 DELAY(1);
1047 cnt--;
1048 if (cnt == 0) {
1049 printf("%s: unexpected timeout in rx DMA test\n", sc->sc_dev.dv_xname);
1050 return(retval); /* timeout, give up */
1051 }
1052 }
1053 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, sc->drq_chip, 8);
1054#endif /* !NBURSTS */
1055 reg = EN_READ(sc, MID_INTACK);
1056 if ((reg & MID_INT_DMA_RX) != MID_INT_DMA_RX) {
1057 printf("%s: unexpected status in rx DMA test: 0x%x\n",
1058 sc->sc_dev.dv_xname, reg);
1059 return(retval);
1060 }
1061 EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA); /* re-enable DMA (only) */
1062
1063 if (wmtry) {
1064 return(bcmp(sp, dp, wmtry)); /* wmtry always exits here, no looping */
1065 }
1066
1067#ifdef NBURSTS
1068 if (bcmp(sp, dp, lcv * NBURSTS)) {
1069/* printf("DMA test failed! lcv=%d, sp=0x%x, dp=0x%x\n", lcv, sp, dp); */
1070 return(retval); /* failed, use last value */
1071 }
1072#else
1073 if (bcmp(sp, dp, lcv))
1074 return(retval); /* failed, use last value */
1075#endif
1076
1077 retval = lcv;
1078
1079 }
1080 return(retval); /* studly 64 byte DMA present! oh baby!! */
1081}
1082
1083/***********************************************************************/
1084
1085/*
1086 * en_ioctl: handle ioctl requests
1087 *
1088 * NOTE: if you add an ioctl to set txspeed, you should choose a new
1089 * TX channel/slot. Choose the one with the lowest sc->txslot[slot].nref
1090 * value, subtract one from sc->txslot[0].nref, add one to the
1091 * sc->txslot[slot].nref, set sc->txvc2slot[vci] = slot, and then set
1092 * txspeed[vci].
1093 */
1094
9974b71d 1095STATIC int en_ioctl(ifp, cmd, data, cr)
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1096
1097struct ifnet *ifp;
1098EN_IOCTL_CMDT cmd;
1099caddr_t data;
9974b71d 1100struct ucred *cr;
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1101
1102{
1103 struct en_softc *sc = (struct en_softc *) ifp->if_softc;
1104 struct ifaddr *ifa = (struct ifaddr *) data;
1105 struct ifreq *ifr = (struct ifreq *) data;
1106 struct atm_pseudoioctl *api = (struct atm_pseudoioctl *)data;
1107#ifdef NATM
1108 struct atm_rawioctl *ario = (struct atm_rawioctl *)data;
1109 int slot;
1110#endif
1111 int s, error = 0;
1112
1113 s = splnet();
1114
1115 switch (cmd) {
1116 case SIOCATMENA: /* enable circuit for recv */
1117 error = en_rxctl(sc, api, 1);
1118 break;
1119
1120 case SIOCATMDIS: /* disable circuit for recv */
1121 error = en_rxctl(sc, api, 0);
1122 break;
1123
1124#ifdef NATM
1125 case SIOCXRAWATM:
1126 if ((slot = sc->rxvc2slot[ario->npcb->npcb_vci]) == RX_NONE) {
1127 error = EINVAL;
1128 break;
1129 }
1130 if (ario->rawvalue > EN_RXSZ*1024)
1131 ario->rawvalue = EN_RXSZ*1024;
1132 if (ario->rawvalue) {
1133 sc->rxslot[slot].oth_flags |= ENOTHER_RAW;
1134 sc->rxslot[slot].raw_threshold = ario->rawvalue;
1135 } else {
1136 sc->rxslot[slot].oth_flags &= (~ENOTHER_RAW);
1137 sc->rxslot[slot].raw_threshold = 0;
1138 }
1139#ifdef EN_DEBUG
1140 printf("%s: rxvci%d: turn %s raw (boodi) mode\n",
1141 sc->sc_dev.dv_xname, ario->npcb->npcb_vci,
1142 (ario->rawvalue) ? "on" : "off");
1143#endif
1144 break;
1145#endif
1146 case SIOCSIFADDR:
1147 ifp->if_flags |= IFF_UP;
1148#if defined(INET) || defined(INET6)
1149 if (ifa->ifa_addr->sa_family == AF_INET
1150 || ifa->ifa_addr->sa_family == AF_INET6) {
1151 en_reset(sc);
1152 en_init(sc);
1153 ifa->ifa_rtrequest = atm_rtrequest; /* ??? */
1154 break;
1155 }
1156#endif /* INET */
1157 /* what to do if not INET? */
1158 en_reset(sc);
1159 en_init(sc);
1160 break;
1161
1162 case SIOCGIFADDR:
1163 error = EINVAL;
1164 break;
1165
1166 case SIOCSIFFLAGS:
1167 error = EINVAL;
1168 break;
1169
1170#if defined(SIOCSIFMTU) /* ??? copied from if_de */
1171#if !defined(ifr_mtu)
1172#define ifr_mtu ifr_metric
1173#endif
1174 case SIOCSIFMTU:
1175 /*
1176 * Set the interface MTU.
1177 */
1178#ifdef notsure
1179 if (ifr->ifr_mtu > ATMMTU) {
1180 error = EINVAL;
1181 break;
1182 }
1183#endif
1184 ifp->if_mtu = ifr->ifr_mtu;
1185 /* XXXCDC: do we really need to reset on MTU size change? */
1186 en_reset(sc);
1187 en_init(sc);
1188 break;
1189#endif /* SIOCSIFMTU */
1190
1191 default:
1192 error = EINVAL;
1193 break;
1194 }
1195 splx(s);
1196 return error;
1197}
1198
1199
1200/*
1201 * en_rxctl: turn on and off VCs for recv.
1202 */
1203
1204STATIC int en_rxctl(sc, pi, on)
1205
1206struct en_softc *sc;
1207struct atm_pseudoioctl *pi;
1208int on;
1209
1210{
1211 u_int s, vci, flags, slot;
1212 u_int32_t oldmode, newmode;
1213
1214 vci = ATM_PH_VCI(&pi->aph);
1215 flags = ATM_PH_FLAGS(&pi->aph);
1216
1217#ifdef EN_DEBUG
1218 printf("%s: %s vpi=%d, vci=%d, flags=%d\n", sc->sc_dev.dv_xname,
1219 (on) ? "enable" : "disable", ATM_PH_VPI(&pi->aph), vci, flags);
1220#endif
1221
1222 if (ATM_PH_VPI(&pi->aph) || vci >= MID_N_VC)
1223 return(EINVAL);
1224
1225 /*
1226 * turn on VCI!
1227 */
1228
1229 if (on) {
1230 if (sc->rxvc2slot[vci] != RX_NONE)
1231 return(EINVAL);
1232 for (slot = 0 ; slot < sc->en_nrx ; slot++)
1233 if (sc->rxslot[slot].oth_flags & ENOTHER_FREE)
1234 break;
1235 if (slot == sc->en_nrx)
1236 return(ENOSPC);
1237 sc->rxvc2slot[vci] = slot;
1238 sc->rxslot[slot].rxhand = NULL;
1239 oldmode = sc->rxslot[slot].mode;
1240 newmode = (flags & ATM_PH_AAL5) ? MIDV_AAL5 : MIDV_NOAAL;
1241 sc->rxslot[slot].mode = MIDV_SETMODE(oldmode, newmode);
1242 sc->rxslot[slot].atm_vci = vci;
1243 sc->rxslot[slot].atm_flags = flags;
1244 sc->rxslot[slot].oth_flags = 0;
1245 sc->rxslot[slot].rxhand = pi->rxhand;
1246 if (sc->rxslot[slot].indma.ifq_head || sc->rxslot[slot].q.ifq_head)
1247 panic("en_rxctl: left over mbufs on enable");
1248 sc->txspeed[vci] = 0; /* full speed to start */
1249 sc->txvc2slot[vci] = 0; /* init value */
1250 sc->txslot[0].nref++; /* bump reference count */
1251 en_loadvc(sc, vci); /* does debug printf for us */
1252 return(0);
1253 }
1254
1255 /*
1256 * turn off VCI
1257 */
1258
1259 if (sc->rxvc2slot[vci] == RX_NONE)
1260 return(EINVAL);
1261 slot = sc->rxvc2slot[vci];
1262 if ((sc->rxslot[slot].oth_flags & (ENOTHER_FREE|ENOTHER_DRAIN)) != 0)
1263 return(EINVAL);
1264 s = splimp(); /* block out enintr() */
1265 oldmode = EN_READ(sc, MID_VC(vci));
1266 newmode = MIDV_SETMODE(oldmode, MIDV_TRASH) & ~MIDV_INSERVICE;
1267 EN_WRITE(sc, MID_VC(vci), (newmode | (oldmode & MIDV_INSERVICE)));
1268 /* halt in tracks, be careful to preserve inserivce bit */
1269 DELAY(27);
1270 sc->rxslot[slot].rxhand = NULL;
1271 sc->rxslot[slot].mode = newmode;
1272
1273 sc->txslot[sc->txvc2slot[vci]].nref--;
1274 sc->txspeed[vci] = 0;
1275 sc->txvc2slot[vci] = 0;
1276
1277 /* if stuff is still going on we are going to have to drain it out */
1278 if (sc->rxslot[slot].indma.ifq_head ||
1279 sc->rxslot[slot].q.ifq_head ||
1280 (sc->rxslot[slot].oth_flags & ENOTHER_SWSL) != 0) {
1281 sc->rxslot[slot].oth_flags |= ENOTHER_DRAIN;
1282 } else {
1283 sc->rxslot[slot].oth_flags = ENOTHER_FREE;
1284 sc->rxslot[slot].atm_vci = RX_NONE;
1285 sc->rxvc2slot[vci] = RX_NONE;
1286 }
1287 splx(s); /* enable enintr() */
1288#ifdef EN_DEBUG
1289 printf("%s: rx%d: VCI %d is now %s\n", sc->sc_dev.dv_xname, slot, vci,
1290 (sc->rxslot[slot].oth_flags & ENOTHER_DRAIN) ? "draining" : "free");
1291#endif
1292 return(0);
1293}
1294
1295/***********************************************************************/
1296
1297/*
1298 * en_reset: reset the board, throw away work in progress.
1299 * must en_init to recover.
1300 */
1301
1302void en_reset(sc)
1303
1304struct en_softc *sc;
1305
1306{
1307 struct mbuf *m;
1308 int lcv, slot;
1309
1310#ifdef EN_DEBUG
1311 printf("%s: reset\n", sc->sc_dev.dv_xname);
1312#endif
1313
1314 if (sc->en_busreset)
1315 sc->en_busreset(sc);
1316 EN_WRITE(sc, MID_RESID, 0x0); /* reset hardware */
1317
1318 /*
1319 * recv: dump any mbufs we are dma'ing into, if DRAINing, then a reset
1320 * will free us!
1321 */
1322
1323 for (lcv = 0 ; lcv < MID_N_VC ; lcv++) {
1324 if (sc->rxvc2slot[lcv] == RX_NONE)
1325 continue;
1326 slot = sc->rxvc2slot[lcv];
1327 while (1) {
1328 IF_DEQUEUE(&sc->rxslot[slot].indma, m);
1329 if (m == NULL)
1330 break; /* >>> exit 'while(1)' here <<< */
1331 m_freem(m);
1332 }
1333 while (1) {
1334 IF_DEQUEUE(&sc->rxslot[slot].q, m);
1335 if (m == NULL)
1336 break; /* >>> exit 'while(1)' here <<< */
1337 m_freem(m);
1338 }
1339 sc->rxslot[slot].oth_flags &= ~ENOTHER_SWSL;
1340 if (sc->rxslot[slot].oth_flags & ENOTHER_DRAIN) {
1341 sc->rxslot[slot].oth_flags = ENOTHER_FREE;
1342 sc->rxvc2slot[lcv] = RX_NONE;
1343#ifdef EN_DEBUG
1344 printf("%s: rx%d: VCI %d is now free\n", sc->sc_dev.dv_xname, slot, lcv);
1345#endif
1346 }
1347 }
1348
1349 /*
1350 * xmit: dump everything
1351 */
1352
1353 for (lcv = 0 ; lcv < EN_NTX ; lcv++) {
1354 while (1) {
1355 IF_DEQUEUE(&sc->txslot[lcv].indma, m);
1356 if (m == NULL)
1357 break; /* >>> exit 'while(1)' here <<< */
1358 m_freem(m);
1359 }
1360 while (1) {
1361 IF_DEQUEUE(&sc->txslot[lcv].q, m);
1362 if (m == NULL)
1363 break; /* >>> exit 'while(1)' here <<< */
1364 m_freem(m);
1365 }
1366
1367 sc->txslot[lcv].mbsize = 0;
1368 }
1369
1370 return;
1371}
1372
1373
1374/*
1375 * en_init: init board and sync the card with the data in the softc.
1376 */
1377
1378STATIC void en_init(sc)
1379
1380struct en_softc *sc;
1381
1382{
1383 int vc, slot;
1384 u_int32_t loc;
1385
1386 if ((sc->enif.if_flags & IFF_UP) == 0) {
1387#ifdef EN_DEBUG
1388 printf("%s: going down\n", sc->sc_dev.dv_xname);
1389#endif
1390 en_reset(sc); /* to be safe */
1391 sc->enif.if_flags &= ~IFF_RUNNING; /* disable */
1392 return;
1393 }
1394
1395#ifdef EN_DEBUG
1396 printf("%s: going up\n", sc->sc_dev.dv_xname);
1397#endif
1398 sc->enif.if_flags |= IFF_RUNNING; /* enable */
1399
1400 if (sc->en_busreset)
1401 sc->en_busreset(sc);
1402 EN_WRITE(sc, MID_RESID, 0x0); /* reset */
1403
1404 /*
1405 * init obmem data structures: vc tab, dma q's, slist.
1406 *
1407 * note that we set drq_free/dtq_free to one less than the total number
1408 * of DTQ/DRQs present. we do this because the card uses the condition
1409 * (drq_chip == drq_us) to mean "list is empty"... but if you allow the
1410 * circular list to be completely full then (drq_chip == drq_us) [i.e.
1411 * the drq_us pointer will wrap all the way around]. by restricting
1412 * the number of active requests to (N - 1) we prevent the list from
1413 * becoming completely full. note that the card will sometimes give
1414 * us an interrupt for a DTQ/DRQ we have already processes... this helps
1415 * keep that interrupt from messing us up.
1416 */
1417
1418 for (vc = 0 ; vc < MID_N_VC ; vc++)
1419 en_loadvc(sc, vc);
1420
1421 bzero(&sc->drq, sizeof(sc->drq));
1422 sc->drq_free = MID_DRQ_N - 1; /* N - 1 */
1423 sc->drq_chip = MID_DRQ_REG2A(EN_READ(sc, MID_DMA_RDRX));
1424 EN_WRITE(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip));
1425 /* ensure zero queue */
1426 sc->drq_us = sc->drq_chip;
1427
1428 bzero(&sc->dtq, sizeof(sc->dtq));
1429 sc->dtq_free = MID_DTQ_N - 1; /* N - 1 */
1430 sc->dtq_chip = MID_DTQ_REG2A(EN_READ(sc, MID_DMA_RDTX));
1431 EN_WRITE(sc, MID_DMA_WRTX, MID_DRQ_A2REG(sc->dtq_chip));
1432 /* ensure zero queue */
1433 sc->dtq_us = sc->dtq_chip;
1434
1435 sc->hwslistp = MID_SL_REG2A(EN_READ(sc, MID_SERV_WRITE));
1436 sc->swsl_size = sc->swsl_head = sc->swsl_tail = 0;
1437
1438#ifdef EN_DEBUG
1439 printf("%s: drq free/chip: %d/0x%x, dtq free/chip: %d/0x%x, hwslist: 0x%x\n",
1440 sc->sc_dev.dv_xname, sc->drq_free, sc->drq_chip,
1441 sc->dtq_free, sc->dtq_chip, sc->hwslistp);
1442#endif
1443
1444 for (slot = 0 ; slot < EN_NTX ; slot++) {
1445 sc->txslot[slot].bfree = EN_TXSZ * 1024;
1446 EN_WRITE(sc, MIDX_READPTR(slot), 0);
1447 EN_WRITE(sc, MIDX_DESCSTART(slot), 0);
1448 loc = sc->txslot[slot].cur = sc->txslot[slot].start;
1449 loc = loc - MID_RAMOFF;
1450 loc = (loc & ~((EN_TXSZ*1024) - 1)) >> 2; /* mask, cvt to words */
1451 loc = loc >> MIDV_LOCTOPSHFT; /* top 11 bits */
1452 EN_WRITE(sc, MIDX_PLACE(slot), MIDX_MKPLACE(en_k2sz(EN_TXSZ), loc));
1453#ifdef EN_DEBUG
1454 printf("%s: tx%d: place 0x%x\n", sc->sc_dev.dv_xname, slot,
1455 EN_READ(sc, MIDX_PLACE(slot)));
1456#endif
1457 }
1458
1459 /*
1460 * enable!
1461 */
1462
1463 EN_WRITE(sc, MID_INTENA, MID_INT_TX|MID_INT_DMA_OVR|MID_INT_IDENT|
1464 MID_INT_LERR|MID_INT_DMA_ERR|MID_INT_DMA_RX|MID_INT_DMA_TX|
1465 MID_INT_SERVICE| /* >>> MID_INT_SUNI| XXXCDC<<< */ MID_INT_STATS);
1466 EN_WRITE(sc, MID_MAST_CSR, MID_SETIPL(sc->ipl)|MID_MCSR_ENDMA|
1467 MID_MCSR_ENTX|MID_MCSR_ENRX);
1468
1469}
1470
1471
1472/*
1473 * en_loadvc: load a vc tab entry from a slot
1474 */
1475
1476STATIC void en_loadvc(sc, vc)
1477
1478struct en_softc *sc;
1479int vc;
1480
1481{
1482 int slot;
1483 u_int32_t reg = EN_READ(sc, MID_VC(vc));
1484
1485 reg = MIDV_SETMODE(reg, MIDV_TRASH);
1486 EN_WRITE(sc, MID_VC(vc), reg);
1487 DELAY(27);
1488
1489 if ((slot = sc->rxvc2slot[vc]) == RX_NONE)
1490 return;
1491
1492 /* no need to set CRC */
1493 EN_WRITE(sc, MID_DST_RP(vc), 0); /* read pointer = 0, desc. start = 0 */
1494 EN_WRITE(sc, MID_WP_ST_CNT(vc), 0); /* write pointer = 0 */
1495 EN_WRITE(sc, MID_VC(vc), sc->rxslot[slot].mode); /* set mode, size, loc */
1496 sc->rxslot[slot].cur = sc->rxslot[slot].start;
1497
1498#ifdef EN_DEBUG
1499 printf("%s: rx%d: assigned to VCI %d\n", sc->sc_dev.dv_xname, slot, vc);
1500#endif
1501}
1502
1503
1504/*
1505 * en_start: start transmitting the next packet that needs to go out
1506 * if there is one. note that atm_output() has already splimp()'d us.
1507 */
1508
1509STATIC void en_start(ifp)
1510
1511struct ifnet *ifp;
1512
1513{
1514 struct en_softc *sc = (struct en_softc *) ifp->if_softc;
984263bc
MD
1515 struct mbuf *m, *lastm, *prev;
1516 struct atm_pseudohdr *ap, *new_ap;
1517 int txchan, mlen, got, need, toadd, cellcnt, first;
1518 u_int32_t atm_vpi, atm_vci, atm_flags, *dat, aal;
1519 u_int8_t *cp;
1520
1521 if ((ifp->if_flags & IFF_RUNNING) == 0)
1522 return;
1523
1524 /*
1525 * remove everything from interface queue since we handle all queueing
1526 * locally ...
1527 */
1528
1529 while (1) {
1530
fea370b7 1531 IF_DEQUEUE(&ifp->if_snd, m);
984263bc
MD
1532 if (m == NULL)
1533 return; /* EMPTY: >>> exit here <<< */
1534
1535 /*
1536 * calculate size of packet (in bytes)
1537 * also, if we are not doing transmit DMA we eliminate all stupid
1538 * (non-word) alignments here using en_mfix(). calls to en_mfix()
1539 * seem to be due to tcp retransmits for the most part.
1540 *
1541 * after this loop mlen total length of mbuf chain (including atm_ph),
1542 * and lastm is a pointer to the last mbuf on the chain.
1543 */
1544
1545 lastm = m;
1546 mlen = 0;
1547 prev = NULL;
1548 while (1) {
1549 /* no DMA? */
1550 if ((!sc->is_adaptec && EN_ENIDMAFIX) || EN_NOTXDMA || !en_dma) {
1551 if ( ((uintptr_t)mtod(lastm, void *) % sizeof(u_int32_t)) != 0 ||
1552 ((lastm->m_len % sizeof(u_int32_t)) != 0 && lastm->m_next)) {
1553 first = (lastm == m);
1554 if (en_mfix(sc, &lastm, prev) == 0) { /* failed? */
1555 m_freem(m);
1556 m = NULL;
1557 break;
1558 }
1559 if (first)
1560 m = lastm; /* update */
1561 }
1562 prev = lastm;
1563 }
1564
1565 mlen += lastm->m_len;
1566 if (lastm->m_next == NULL)
1567 break;
1568 lastm = lastm->m_next;
1569 }
1570
1571 if (m == NULL) /* happens only if mfix fails */
1572 continue;
1573
1574 ap = mtod(m, struct atm_pseudohdr *);
1575
1576 atm_vpi = ATM_PH_VPI(ap);
1577 atm_vci = ATM_PH_VCI(ap);
1578 atm_flags = ATM_PH_FLAGS(ap) & ~(EN_OBHDR|EN_OBTRL);
1579 aal = ((atm_flags & ATM_PH_AAL5) != 0)
1580 ? MID_TBD_AAL5 : MID_TBD_NOAAL5;
1581
1582 /*
1583 * check that vpi/vci is one we can use
1584 */
1585
1586 if (atm_vpi || atm_vci > MID_N_VC) {
1587 printf("%s: output vpi=%d, vci=%d out of card range, dropping...\n",
1588 sc->sc_dev.dv_xname, atm_vpi, atm_vci);
1589 m_freem(m);
1590 continue;
1591 }
1592
1593 /*
1594 * computing how much padding we need on the end of the mbuf, then
1595 * see if we can put the TBD at the front of the mbuf where the
1596 * link header goes (well behaved protocols will reserve room for us).
1597 * last, check if room for PDU tail.
1598 *
1599 * got = number of bytes of data we have
1600 * cellcnt = number of cells in this mbuf
1601 * need = number of bytes of data + padding we need (excludes TBD)
1602 * toadd = number of bytes of data we need to add to end of mbuf,
1603 * [including AAL5 PDU, if AAL5]
1604 */
1605
1606 got = mlen - sizeof(struct atm_pseudohdr *);
1607 toadd = (aal == MID_TBD_AAL5) ? MID_PDU_SIZE : 0; /* PDU */
1608 cellcnt = (got + toadd + (MID_ATMDATASZ - 1)) / MID_ATMDATASZ;
1609 need = cellcnt * MID_ATMDATASZ;
1610 toadd = need - got; /* recompute, including zero padding */
1611
1612#ifdef EN_DEBUG
1613 printf("%s: txvci%d: mlen=%d, got=%d, need=%d, toadd=%d, cell#=%d\n",
1614 sc->sc_dev.dv_xname, atm_vci, mlen, got, need, toadd, cellcnt);
1615 printf(" leading_space=%d, trailing_space=%d\n",
1616 M_LEADINGSPACE(m), M_TRAILINGSPACE(lastm));
1617#endif
1618
1619#ifdef EN_MBUF_OPT
1620
1621 /*
1622 * note: external storage (M_EXT) can be shared between mbufs
1623 * to avoid copying (see m_copym()). this means that the same
1624 * data buffer could be shared by several mbufs, and thus it isn't
1625 * a good idea to try and write TBDs or PDUs to M_EXT data areas.
1626 */
1627
1628 if (M_LEADINGSPACE(m) >= MID_TBD_SIZE && (m->m_flags & M_EXT) == 0) {
1629 m->m_data -= MID_TBD_SIZE;
1630 m->m_len += MID_TBD_SIZE;
1631 mlen += MID_TBD_SIZE;
1632 new_ap = mtod(m, struct atm_pseudohdr *);
1633 *new_ap = *ap; /* move it back */
1634 ap = new_ap;
1635 dat = ((u_int32_t *) ap) + 1;
1636 /* make sure the TBD is in proper byte order */
1637 *dat++ = htonl(MID_TBD_MK1(aal, sc->txspeed[atm_vci], cellcnt));
1638 *dat = htonl(MID_TBD_MK2(atm_vci, 0, 0));
1639 atm_flags |= EN_OBHDR;
1640 }
1641
1642 if (toadd && (lastm->m_flags & M_EXT) == 0 &&
1643 M_TRAILINGSPACE(lastm) >= toadd) {
1644 cp = mtod(lastm, u_int8_t *) + lastm->m_len;
1645 lastm->m_len += toadd;
1646 mlen += toadd;
1647 if (aal == MID_TBD_AAL5) {
1648 bzero(cp, toadd - MID_PDU_SIZE);
1649 dat = (u_int32_t *)(cp + toadd - MID_PDU_SIZE);
1650 /* make sure the PDU is in proper byte order */
1651 *dat = htonl(MID_PDU_MK1(0, 0, got));
1652 } else {
1653 bzero(cp, toadd);
1654 }
1655 atm_flags |= EN_OBTRL;
1656 }
1657 ATM_PH_FLAGS(ap) = atm_flags; /* update EN_OBHDR/EN_OBTRL bits */
1658#endif /* EN_MBUF_OPT */
1659
1660 /*
1661 * get assigned channel (will be zero unless txspeed[atm_vci] is set)
1662 */
1663
1664 txchan = sc->txvc2slot[atm_vci];
1665
1666 if (sc->txslot[txchan].mbsize > EN_TXHIWAT) {
1667 EN_COUNT(sc->txmbovr);
1668 m_freem(m);
1669#ifdef EN_DEBUG
1670 printf("%s: tx%d: buffer space shortage\n", sc->sc_dev.dv_xname,
1671 txchan);
1672#endif
1673 continue;
1674 }
1675
1676 sc->txslot[txchan].mbsize += mlen;
1677
1678#ifdef EN_DEBUG
1679 printf("%s: tx%d: VPI=%d, VCI=%d, FLAGS=0x%x, speed=0x%x\n",
1680 sc->sc_dev.dv_xname, txchan, atm_vpi, atm_vci, atm_flags,
1681 sc->txspeed[atm_vci]);
1682 printf(" adjusted mlen=%d, mbsize=%d\n", mlen,
1683 sc->txslot[txchan].mbsize);
1684#endif
1685
1686 IF_ENQUEUE(&sc->txslot[txchan].q, m);
1687
1688 en_txdma(sc, txchan);
1689
1690 }
1691 /*NOTREACHED*/
1692}
1693
1694
1695/*
1696 * en_mfix: fix a stupid mbuf
1697 */
1698
984263bc
MD
1699STATIC int en_makeexclusive(struct en_softc *, struct mbuf **, struct mbuf *);
1700
1701STATIC int en_makeexclusive(sc, mm, prev)
1702 struct en_softc *sc;
1703 struct mbuf **mm, *prev;
1704{
1705 struct mbuf *m, *new;
1706
1707 m = *mm;
1708
1709 if (m->m_flags & M_EXT) {
7eccf245 1710 if (m->m_ext.ext_nfree.any) {
984263bc
MD
1711 /* external buffer isn't an ordinary mbuf cluster! */
1712 printf("%s: mfix: special buffer! can't make a copy!\n",
1713 sc->sc_dev.dv_xname);
1714 return (0);
1715 }
90775e29
MD
1716
1717 if (m_sharecount(m) > 1) {
984263bc 1718 /* make a real copy of the M_EXT mbuf since it is shared */
74f1caca 1719 MGET(new, MB_DONTWAIT, MT_DATA);
984263bc
MD
1720 if (!new) {
1721 EN_COUNT(sc->mfixfail);
1722 return(0);
1723 }
1724 if (m->m_flags & M_PKTHDR)
1725 M_MOVE_PKTHDR(new, m);
74f1caca 1726 MCLGET(new, MB_DONTWAIT);
984263bc
MD
1727 if ((new->m_flags & M_EXT) == 0) {
1728 m_free(new);
1729 EN_COUNT(sc->mfixfail);
1730 return(0);
1731 }
1732 bcopy(m->m_data, new->m_data, m->m_len);
1733 new->m_len = m->m_len;
1734 new->m_next = m->m_next;
1735 if (prev)
1736 prev->m_next = new;
1737 m_free(m);
1738 *mm = new;
1739 }
1740 else {
1741 /* the buffer is not shared, align the data offset using
1742 this buffer. */
1743 u_char *d = mtod(m, u_char *);
1744 int off = ((uintptr_t)(void *)d) % sizeof(u_int32_t);
1745
1746 if (off > 0) {
1747 bcopy(d, d - off, m->m_len);
1748 m->m_data = (caddr_t)d - off;
1749 }
1750 }
1751 }
1752 return (1);
1753}
1754
1755STATIC int en_mfix(sc, mm, prev)
1756
1757struct en_softc *sc;
1758struct mbuf **mm, *prev;
1759
1760{
1761 struct mbuf *m;
1762 u_char *d, *cp;
1763 int off;
1764 struct mbuf *nxt;
1765
1766 m = *mm;
1767
1768 EN_COUNT(sc->mfix); /* count # of calls */
1769#ifdef EN_DEBUG
1770 printf("%s: mfix mbuf m_data=0x%x, m_len=%d\n", sc->sc_dev.dv_xname,
1771 m->m_data, m->m_len);
1772#endif
1773
1774 d = mtod(m, u_char *);
1775 off = ((uintptr_t) (void *) d) % sizeof(u_int32_t);
1776
1777 if (off) {
1778 if ((m->m_flags & M_EXT) == 0) {
1779 bcopy(d, d - off, m->m_len); /* ALIGN! (with costly data copy...) */
1780 d -= off;
1781 m->m_data = (caddr_t)d;
1782 } else {
1783 /* can't write to an M_EXT mbuf since it may be shared */
1784 if (en_makeexclusive(sc, &m, prev) == 0)
1785 return (0);
1786 *mm = m; /* note: 'd' now invalid */
1787 }
1788 }
1789
1790 off = m->m_len % sizeof(u_int32_t);
1791 if (off == 0)
1792 return(1);
1793
1794 if (m->m_flags & M_EXT) {
1795 /* can't write to an M_EXT mbuf since it may be shared */
1796 if (en_makeexclusive(sc, &m, prev) == 0)
1797 return (0);
1798 *mm = m; /* note: 'd' now invalid */
1799 }
1800
1801 d = mtod(m, u_char *) + m->m_len;
1802 off = sizeof(u_int32_t) - off;
1803
1804 nxt = m->m_next;
1805 while (off--) {
1806 if (nxt != NULL && nxt->m_len == 0) {
1807 /* remove an empty mbuf. this avoids odd byte padding to an empty
1808 last mbuf. */
1809 m->m_next = nxt = m_free(nxt);
1810 }
1811 if (nxt == NULL) { /* out of data, zero fill */
1812 *d++ = 0;
1813 continue; /* next "off" */
1814 }
1815 cp = mtod(nxt, u_char *);
1816 *d++ = *cp++;
1817 m->m_len++;
1818 nxt->m_len--;
1819 nxt->m_data = (caddr_t)cp;
1820 }
1821 if (nxt != NULL && nxt->m_len == 0)
1822 m->m_next = m_free(nxt);
1823 return(1);
1824}
1825
984263bc
MD
1826/*
1827 * en_txdma: start trasmit DMA, if possible
1828 */
1829
1830STATIC void en_txdma(sc, chan)
1831
1832struct en_softc *sc;
1833int chan;
1834
1835{
1836 struct mbuf *tmp;
1837 struct atm_pseudohdr *ap;
1838 struct en_launch launch;
1839 int datalen = 0, dtqneed, len, ncells;
1840 u_int8_t *cp;
1841 struct ifnet *ifp;
1842
1843#ifdef EN_DEBUG
1844 printf("%s: tx%d: starting...\n", sc->sc_dev.dv_xname, chan);
1845#endif
1846
1847 /*
1848 * note: now that txlaunch handles non-word aligned/sized requests
1849 * the only time you can safely set launch.nodma is if you've en_mfix()'d
1850 * the mbuf chain. this happens only if EN_NOTXDMA || !en_dma.
1851 */
1852
1853 launch.nodma = (EN_NOTXDMA || !en_dma);
1854
1855again:
1856
1857 /*
1858 * get an mbuf waiting for DMA
1859 */
1860
1861 launch.t = sc->txslot[chan].q.ifq_head; /* peek at head of queue */
1862
1863 if (launch.t == NULL) {
1864#ifdef EN_DEBUG
1865 printf("%s: tx%d: ...done!\n", sc->sc_dev.dv_xname, chan);
1866#endif
1867 return; /* >>> exit here if no data waiting for DMA <<< */
1868 }
1869
1870 /*
1871 * get flags, vci
1872 *
1873 * note: launch.need = # bytes we need to get on the card
1874 * dtqneed = # of DTQs we need for this packet
1875 * launch.mlen = # of bytes in in mbuf chain (<= launch.need)
1876 */
1877
1878 ap = mtod(launch.t, struct atm_pseudohdr *);
1879 launch.atm_vci = ATM_PH_VCI(ap);
1880 launch.atm_flags = ATM_PH_FLAGS(ap);
1881 launch.aal = ((launch.atm_flags & ATM_PH_AAL5) != 0) ?
1882 MID_TBD_AAL5 : MID_TBD_NOAAL5;
1883
1884 /*
1885 * XXX: have to recompute the length again, even though we already did
1886 * it in en_start(). might as well compute dtqneed here as well, so
1887 * this isn't that bad.
1888 */
1889
1890 if ((launch.atm_flags & EN_OBHDR) == 0) {
1891 dtqneed = 1; /* header still needs to be added */
1892 launch.need = MID_TBD_SIZE; /* not includeded with mbuf */
1893 } else {
1894 dtqneed = 0; /* header on-board, dma with mbuf */
1895 launch.need = 0;
1896 }
1897
1898 launch.mlen = 0;
1899 for (tmp = launch.t ; tmp != NULL ; tmp = tmp->m_next) {
1900 len = tmp->m_len;
1901 launch.mlen += len;
1902 cp = mtod(tmp, u_int8_t *);
1903 if (tmp == launch.t) {
1904 len -= sizeof(struct atm_pseudohdr); /* don't count this! */
1905 cp += sizeof(struct atm_pseudohdr);
1906 }
1907 launch.need += len;
1908 if (len == 0)
1909 continue; /* atm_pseudohdr alone in first mbuf */
1910
1911 dtqneed += en_dqneed(sc, (caddr_t) cp, len, 1);
1912 }
1913
1914 if ((launch.need % sizeof(u_int32_t)) != 0)
1915 dtqneed++; /* need DTQ to FLUSH internal buffer */
1916
1917 if ((launch.atm_flags & EN_OBTRL) == 0) {
1918 if (launch.aal == MID_TBD_AAL5) {
1919 datalen = launch.need - MID_TBD_SIZE;
1920 launch.need += MID_PDU_SIZE; /* AAL5: need PDU tail */
1921 }
1922 dtqneed++; /* need to work on the end a bit */
1923 }
1924
1925 /*
1926 * finish calculation of launch.need (need to figure out how much padding
1927 * we will need). launch.need includes MID_TBD_SIZE, but we need to
1928 * remove that to so we can round off properly. we have to add
1929 * MID_TBD_SIZE back in after calculating ncells.
1930 */
1931
1932 launch.need = roundup(launch.need - MID_TBD_SIZE, MID_ATMDATASZ);
1933 ncells = launch.need / MID_ATMDATASZ;
1934 launch.need += MID_TBD_SIZE;
1935
1936 if (launch.need > EN_TXSZ * 1024) {
1937 printf("%s: tx%d: packet larger than xmit buffer (%d > %d)\n",
1938 sc->sc_dev.dv_xname, chan, launch.need, EN_TXSZ * 1024);
1939 goto dequeue_drop;
1940 }
1941
1942 /*
1943 * note: don't use the entire buffer space. if WRTX becomes equal
1944 * to RDTX, the transmitter stops assuming the buffer is empty! --kjc
1945 */
1946 if (launch.need >= sc->txslot[chan].bfree) {
1947 EN_COUNT(sc->txoutspace);
1948#ifdef EN_DEBUG
1949 printf("%s: tx%d: out of transmit space\n", sc->sc_dev.dv_xname, chan);
1950#endif
1951 return; /* >>> exit here if out of obmem buffer space <<< */
1952 }
1953
1954 /*
1955 * ensure we have enough dtqs to go, if not, wait for more.
1956 */
1957
1958 if (launch.nodma) {
1959 dtqneed = 1;
1960 }
1961 if (dtqneed > sc->dtq_free) {
1962 sc->need_dtqs = 1;
1963 EN_COUNT(sc->txdtqout);
1964#ifdef EN_DEBUG
1965 printf("%s: tx%d: out of transmit DTQs\n", sc->sc_dev.dv_xname, chan);
1966#endif
1967 return; /* >>> exit here if out of dtqs <<< */
1968 }
1969
1970 /*
1971 * it is a go, commit! dequeue mbuf start working on the xfer.
1972 */
1973
1974 IF_DEQUEUE(&sc->txslot[chan].q, tmp);
1975#ifdef EN_DIAG
1976 if (launch.t != tmp)
1977 panic("en dequeue");
1978#endif /* EN_DIAG */
1979
1980 /*
1981 * launch!
1982 */
1983
1984 EN_COUNT(sc->launch);
1985 ifp = &sc->enif;
1986 ifp->if_opackets++;
1987
1988 if ((launch.atm_flags & EN_OBHDR) == 0) {
1989 EN_COUNT(sc->lheader);
1990 /* store tbd1/tbd2 in host byte order */
1991 launch.tbd1 = MID_TBD_MK1(launch.aal, sc->txspeed[launch.atm_vci], ncells);
1992 launch.tbd2 = MID_TBD_MK2(launch.atm_vci, 0, 0);
1993 }
1994 if ((launch.atm_flags & EN_OBTRL) == 0 && launch.aal == MID_TBD_AAL5) {
1995 EN_COUNT(sc->ltail);
1996 launch.pdu1 = MID_PDU_MK1(0, 0, datalen); /* host byte order */
1997 }
1998
1999 en_txlaunch(sc, chan, &launch);
2000
984263bc
MD
2001 if (ifp->if_bpf) {
2002 /*
2003 * adjust the top of the mbuf to skip the pseudo atm header
2004 * (and TBD, if present) before passing the packet to bpf,
2005 * restore it afterwards.
2006 */
2007 int size = sizeof(struct atm_pseudohdr);
2008 if (launch.atm_flags & EN_OBHDR)
2009 size += MID_TBD_SIZE;
2010
2011 launch.t->m_data += size;
2012 launch.t->m_len -= size;
2013
2014 BPF_MTAP(ifp, launch.t);
2015
2016 launch.t->m_data -= size;
2017 launch.t->m_len += size;
2018 }
984263bc
MD
2019 /*
2020 * do some housekeeping and get the next packet
2021 */
2022
2023 sc->txslot[chan].bfree -= launch.need;
2024 IF_ENQUEUE(&sc->txslot[chan].indma, launch.t);
2025 goto again;
2026
2027 /*
2028 * END of txdma loop!
2029 */
2030
2031 /*
2032 * error handles
2033 */
2034
2035dequeue_drop:
2036 IF_DEQUEUE(&sc->txslot[chan].q, tmp);
2037 if (launch.t != tmp)
2038 panic("en dequeue drop");
2039 m_freem(launch.t);
2040 sc->txslot[chan].mbsize -= launch.mlen;
2041 goto again;
2042}
2043
2044
2045/*
2046 * en_txlaunch: launch an mbuf into the dma pool!
2047 */
2048
2049STATIC void en_txlaunch(sc, chan, l)
2050
2051struct en_softc *sc;
2052int chan;
2053struct en_launch *l;
2054
2055{
2056 struct mbuf *tmp;
2057 u_int32_t cur = sc->txslot[chan].cur,
2058 start = sc->txslot[chan].start,
2059 stop = sc->txslot[chan].stop,
2060 dma, *data, *datastop, count, bcode;
2061 int pad, addtail, need, len, needalign, cnt, end, mx;
2062
2063
2064 /*
2065 * vars:
2066 * need = # bytes card still needs (decr. to zero)
2067 * len = # of bytes left in current mbuf
2068 * cur = our current pointer
2069 * dma = last place we programmed into the DMA
2070 * data = pointer into data area of mbuf that needs to go next
2071 * cnt = # of bytes to transfer in this DTQ
2072 * bcode/count = DMA burst code, and chip's version of cnt
2073 *
2074 * a single buffer can require up to 5 DTQs depending on its size
2075 * and alignment requirements. the 5 possible requests are:
2076 * [1] 1, 2, or 3 byte DMA to align src data pointer to word boundary
2077 * [2] alburst DMA to align src data pointer to bestburstlen
2078 * [3] 1 or more bestburstlen DMAs
2079 * [4] clean up burst (to last word boundary)
2080 * [5] 1, 2, or 3 byte final clean up DMA
2081 */
2082
2083 need = l->need;
2084 dma = cur;
2085 addtail = (l->atm_flags & EN_OBTRL) == 0; /* add a tail? */
2086
2087#ifdef EN_DIAG
2088 if ((need - MID_TBD_SIZE) % MID_ATMDATASZ)
2089 printf("%s: tx%d: bogus trasmit needs (%d)\n", sc->sc_dev.dv_xname, chan,
2090 need);
2091#endif
2092#ifdef EN_DEBUG
2093 printf("%s: tx%d: launch mbuf %p! cur=0x%x[%d], need=%d, addtail=%d\n",
2094 sc->sc_dev.dv_xname, chan, l->t, cur, (cur-start)/4, need, addtail);
2095 count = EN_READ(sc, MIDX_PLACE(chan));
2096 printf(" HW: base_address=0x%x, size=%d, read=%d, descstart=%d\n",
2097 MIDX_BASE(count), MIDX_SZ(count), EN_READ(sc, MIDX_READPTR(chan)),
2098 EN_READ(sc, MIDX_DESCSTART(chan)));
2099#endif
2100
2101 /*
2102 * do we need to insert the TBD by hand?
2103 * note that tbd1/tbd2/pdu1 are in host byte order.
2104 */
2105
2106 if ((l->atm_flags & EN_OBHDR) == 0) {
2107#ifdef EN_DEBUG
2108 printf("%s: tx%d: insert header 0x%x 0x%x\n", sc->sc_dev.dv_xname,
2109 chan, l->tbd1, l->tbd2);
2110#endif
2111 EN_WRITE(sc, cur, l->tbd1);
2112 EN_WRAPADD(start, stop, cur, 4);
2113 EN_WRITE(sc, cur, l->tbd2);
2114 EN_WRAPADD(start, stop, cur, 4);
2115 need -= 8;
2116 }
2117
2118 /*
2119 * now do the mbufs...
2120 */
2121
2122 for (tmp = l->t ; tmp != NULL ; tmp = tmp->m_next) {
2123
2124 /* get pointer to data and length */
2125 data = mtod(tmp, u_int32_t *);
2126 len = tmp->m_len;
2127 if (tmp == l->t) {
2128 data += sizeof(struct atm_pseudohdr)/sizeof(u_int32_t);
2129 len -= sizeof(struct atm_pseudohdr);
2130 }
2131
2132 /* now, determine if we should copy it */
2133 if (l->nodma || (len < EN_MINDMA &&
2134 (len % 4) == 0 && ((uintptr_t) (void *) data % 4) == 0 &&
2135 (cur % 4) == 0)) {
2136
2137 /*
2138 * roundup len: the only time this will change the value of len
2139 * is when l->nodma is true, tmp is the last mbuf, and there is
2140 * a non-word number of bytes to transmit. in this case it is
2141 * safe to round up because we've en_mfix'd the mbuf (so the first
2142 * byte is word aligned there must be enough free bytes at the end
2143 * to round off to the next word boundary)...
2144 */
2145 len = roundup(len, sizeof(u_int32_t));
2146 datastop = data + (len / sizeof(u_int32_t));
2147 /* copy loop: preserve byte order!!! use WRITEDAT */
2148 while (data != datastop) {
2149 EN_WRITEDAT(sc, cur, *data);
2150 data++;
2151 EN_WRAPADD(start, stop, cur, 4);
2152 }
2153 need -= len;
2154#ifdef EN_DEBUG
2155 printf("%s: tx%d: copied %d bytes (%d left, cur now 0x%x)\n",
2156 sc->sc_dev.dv_xname, chan, len, need, cur);
2157#endif
2158 continue; /* continue on to next mbuf */
2159 }
2160
2161 /* going to do DMA, first make sure the dtq is in sync. */
2162 if (dma != cur) {
2163 EN_DTQADD(sc, WORD_IDX(start,cur), chan, MIDDMA_JK, 0, 0, 0);
2164#ifdef EN_DEBUG
2165 printf("%s: tx%d: dtq_sync: advance pointer to %d\n",
2166 sc->sc_dev.dv_xname, chan, cur);
2167#endif
2168 }
2169
2170 /*
2171 * if this is the last buffer, and it looks like we are going to need to
2172 * flush the internal buffer, can we extend the length of this mbuf to
2173 * avoid the FLUSH?
2174 */
2175
2176 if (tmp->m_next == NULL) {
2177 cnt = (need - len) % sizeof(u_int32_t);
2178 if (cnt && M_TRAILINGSPACE(tmp) >= cnt)
2179 len += cnt; /* pad for FLUSH */
2180 }
2181
2182#if !defined(MIDWAY_ENIONLY)
2183
2184 /*
2185 * the adaptec DMA engine is smart and handles everything for us.
2186 */
2187
2188 if (sc->is_adaptec) {
2189 /* need to DMA "len" bytes out to card */
2190 need -= len;
2191 EN_WRAPADD(start, stop, cur, len);
2192#ifdef EN_DEBUG
2193 printf("%s: tx%d: adp_dma %d bytes (%d left, cur now 0x%x)\n",
2194 sc->sc_dev.dv_xname, chan, len, need, cur);
2195#endif
2196 end = (need == 0) ? MID_DMA_END : 0;
2197 EN_DTQADD(sc, len, chan, 0, vtophys(data), l->mlen, end);
2198 if (end)
2199 goto done;
2200 dma = cur; /* update dma pointer */
2201 continue;
2202 }
2203#endif /* !MIDWAY_ENIONLY */
2204
2205#if !defined(MIDWAY_ADPONLY)
2206
2207 /*
2208 * the ENI DMA engine is not so smart and need more help from us
2209 */
2210
2211 /* do we need to do a DMA op to align to word boundary? */
2212 needalign = (uintptr_t) (void *) data % sizeof(u_int32_t);
2213 if (needalign) {
2214 EN_COUNT(sc->headbyte);
2215 cnt = sizeof(u_int32_t) - needalign;
2216 if (cnt == 2 && len >= cnt) {
2217 count = 1;
2218 bcode = MIDDMA_2BYTE;
2219 } else {
2220 cnt = min(cnt, len); /* prevent overflow */
2221 count = cnt;
2222 bcode = MIDDMA_BYTE;
2223 }
2224 need -= cnt;
2225 EN_WRAPADD(start, stop, cur, cnt);
2226#ifdef EN_DEBUG
2227 printf("%s: tx%d: small al_dma %d bytes (%d left, cur now 0x%x)\n",
2228 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2229#endif
2230 len -= cnt;
2231 end = (need == 0) ? MID_DMA_END : 0;
2232 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2233 if (end)
2234 goto done;
2235 data = (u_int32_t *) ((u_char *)data + cnt);
2236 }
2237
2238 /* do we need to do a DMA op to align? */
2239 if (sc->alburst &&
2240 (needalign = (((uintptr_t) (void *) data) & sc->bestburstmask)) != 0
2241 && len >= sizeof(u_int32_t)) {
2242 cnt = sc->bestburstlen - needalign;
2243 mx = len & ~(sizeof(u_int32_t)-1); /* don't go past end */
2244 if (cnt > mx) {
2245 cnt = mx;
2246 count = cnt / sizeof(u_int32_t);
2247 bcode = MIDDMA_WORD;
2248 } else {
2249 count = cnt / sizeof(u_int32_t);
2250 bcode = en_dmaplan[count].bcode;
2251 count = cnt >> en_dmaplan[count].divshift;
2252 }
2253 need -= cnt;
2254 EN_WRAPADD(start, stop, cur, cnt);
2255#ifdef EN_DEBUG
2256 printf("%s: tx%d: al_dma %d bytes (%d left, cur now 0x%x)\n",
2257 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2258#endif
2259 len -= cnt;
2260 end = (need == 0) ? MID_DMA_END : 0;
2261 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2262 if (end)
2263 goto done;
2264 data = (u_int32_t *) ((u_char *)data + cnt);
2265 }
2266
2267 /* do we need to do a max-sized burst? */
2268 if (len >= sc->bestburstlen) {
2269 count = len >> sc->bestburstshift;
2270 cnt = count << sc->bestburstshift;
2271 bcode = sc->bestburstcode;
2272 need -= cnt;
2273 EN_WRAPADD(start, stop, cur, cnt);
2274#ifdef EN_DEBUG
2275 printf("%s: tx%d: best_dma %d bytes (%d left, cur now 0x%x)\n",
2276 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2277#endif
2278 len -= cnt;
2279 end = (need == 0) ? MID_DMA_END : 0;
2280 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2281 if (end)
2282 goto done;
2283 data = (u_int32_t *) ((u_char *)data + cnt);
2284 }
2285
2286 /* do we need to do a cleanup burst? */
2287 cnt = len & ~(sizeof(u_int32_t)-1);
2288 if (cnt) {
2289 count = cnt / sizeof(u_int32_t);
2290 bcode = en_dmaplan[count].bcode;
2291 count = cnt >> en_dmaplan[count].divshift;
2292 need -= cnt;
2293 EN_WRAPADD(start, stop, cur, cnt);
2294#ifdef EN_DEBUG
2295 printf("%s: tx%d: cleanup_dma %d bytes (%d left, cur now 0x%x)\n",
2296 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2297#endif
2298 len -= cnt;
2299 end = (need == 0) ? MID_DMA_END : 0;
2300 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2301 if (end)
2302 goto done;
2303 data = (u_int32_t *) ((u_char *)data + cnt);
2304 }
2305
2306 /* any word fragments left? */
2307 if (len) {
2308 EN_COUNT(sc->tailbyte);
2309 if (len == 2) {
2310 count = 1;
2311 bcode = MIDDMA_2BYTE; /* use 2byte mode */
2312 } else {
2313 count = len;
2314 bcode = MIDDMA_BYTE; /* use 1 byte mode */
2315 }
2316 need -= len;
2317 EN_WRAPADD(start, stop, cur, len);
2318#ifdef EN_DEBUG
2319 printf("%s: tx%d: byte cleanup_dma %d bytes (%d left, cur now 0x%x)\n",
2320 sc->sc_dev.dv_xname, chan, len, need, cur);
2321#endif
2322 end = (need == 0) ? MID_DMA_END : 0;
2323 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2324 if (end)
2325 goto done;
2326 }
2327
2328 dma = cur; /* update dma pointer */
2329#endif /* !MIDWAY_ADPONLY */
2330
2331 } /* next mbuf, please */
2332
2333 /*
2334 * all mbuf data has been copied out to the obmem (or set up to be DMAd).
2335 * if the trailer or padding needs to be put in, do it now.
2336 *
2337 * NOTE: experimental results reveal the following fact:
2338 * if you DMA "X" bytes to the card, where X is not a multiple of 4,
2339 * then the card will internally buffer the last (X % 4) bytes (in
2340 * hopes of getting (4 - (X % 4)) more bytes to make a complete word).
2341 * it is imporant to make sure we don't leave any important data in
2342 * this internal buffer because it is discarded on the last (end) DTQ.
2343 * one way to do this is to DMA in (4 - (X % 4)) more bytes to flush
2344 * the darn thing out.
2345 */
2346
2347 if (addtail) {
2348
2349 pad = need % sizeof(u_int32_t);
2350 if (pad) {
2351 /*
2352 * FLUSH internal data buffer. pad out with random data from the front
2353 * of the mbuf chain...
2354 */
2355 bcode = (sc->is_adaptec) ? 0 : MIDDMA_BYTE;
2356 EN_COUNT(sc->tailflush);
2357 EN_WRAPADD(start, stop, cur, pad);
2358 EN_DTQADD(sc, pad, chan, bcode, vtophys(l->t->m_data), 0, 0);
2359 need -= pad;
2360#ifdef EN_DEBUG
2361 printf("%s: tx%d: pad/FLUSH dma %d bytes (%d left, cur now 0x%x)\n",
2362 sc->sc_dev.dv_xname, chan, pad, need, cur);
2363#endif
2364 }
2365
2366 /* copy data */
2367 pad = need / sizeof(u_int32_t); /* round *down* */
2368 if (l->aal == MID_TBD_AAL5)
2369 pad -= 2;
2370#ifdef EN_DEBUG
2371 printf("%s: tx%d: padding %d bytes (cur now 0x%x)\n",
2372 sc->sc_dev.dv_xname, chan, pad * sizeof(u_int32_t), cur);
2373#endif
2374 while (pad--) {
2375 EN_WRITEDAT(sc, cur, 0); /* no byte order issues with zero */
2376 EN_WRAPADD(start, stop, cur, 4);
2377 }
2378 if (l->aal == MID_TBD_AAL5) {
2379 EN_WRITE(sc, cur, l->pdu1); /* in host byte order */
2380 EN_WRAPADD(start, stop, cur, 8);
2381 }
2382 }
2383
2384 if (addtail || dma != cur) {
2385 /* write final descritor */
2386 EN_DTQADD(sc, WORD_IDX(start,cur), chan, MIDDMA_JK, 0,
2387 l->mlen, MID_DMA_END);
2388 /* dma = cur; */ /* not necessary since we are done */
2389 }
2390
2391done:
2392 /* update current pointer */
2393 sc->txslot[chan].cur = cur;
2394#ifdef EN_DEBUG
2395 printf("%s: tx%d: DONE! cur now = 0x%x\n",
2396 sc->sc_dev.dv_xname, chan, cur);
2397#endif
2398
2399 return;
2400}
2401
2402
2403/*
2404 * interrupt handler
2405 */
2406
2407EN_INTR_TYPE en_intr(arg)
2408
2409void *arg;
2410
2411{
2412 struct en_softc *sc = (struct en_softc *) arg;
2413 struct mbuf *m;
2414 struct atm_pseudohdr ah;
2415 struct ifnet *ifp;
2416 u_int32_t reg, kick, val, mask, chip, vci, slot, dtq, drq;
2417 int lcv, idx, need_softserv = 0;
2418
2419 reg = EN_READ(sc, MID_INTACK);
2420
2421 if ((reg & MID_INT_ANY) == 0)
2422 EN_INTR_RET(0); /* not us */
2423
2424#ifdef EN_DEBUG
2425 printf("%s: interrupt=0x%b\n", sc->sc_dev.dv_xname, reg, MID_INTBITS);
2426#endif
2427
2428 /*
2429 * unexpected errors that need a reset
2430 */
2431
2432 if ((reg & (MID_INT_IDENT|MID_INT_LERR|MID_INT_DMA_ERR|MID_INT_SUNI)) != 0) {
2433 printf("%s: unexpected interrupt=0x%b, resetting card\n",
2434 sc->sc_dev.dv_xname, reg, MID_INTBITS);
2435#ifdef EN_DEBUG
2436#ifdef DDB
984263bc 2437 Debugger("en: unexpected error");
984263bc
MD
2438#endif /* DDB */
2439 sc->enif.if_flags &= ~IFF_RUNNING; /* FREEZE! */
2440#else
2441 en_reset(sc);
2442 en_init(sc);
2443#endif
2444 EN_INTR_RET(1); /* for us */
2445 }
2446
2447 /*******************
2448 * xmit interrupts *
2449 ******************/
2450
2451 kick = 0; /* bitmask of channels to kick */
2452 if (reg & MID_INT_TX) { /* TX done! */
2453
2454 /*
2455 * check for tx complete, if detected then this means that some space
2456 * has come free on the card. we must account for it and arrange to
2457 * kick the channel to life (in case it is stalled waiting on the card).
2458 */
2459 for (mask = 1, lcv = 0 ; lcv < EN_NTX ; lcv++, mask = mask * 2) {
2460 if (reg & MID_TXCHAN(lcv)) {
2461 kick = kick | mask; /* want to kick later */
2462 val = EN_READ(sc, MIDX_READPTR(lcv)); /* current read pointer */
2463 val = (val * sizeof(u_int32_t)) + sc->txslot[lcv].start;
2464 /* convert to offset */
2465 if (val > sc->txslot[lcv].cur)
2466 sc->txslot[lcv].bfree = val - sc->txslot[lcv].cur;
2467 else
2468 sc->txslot[lcv].bfree = (val + (EN_TXSZ*1024)) - sc->txslot[lcv].cur;
2469#ifdef EN_DEBUG
2470 printf("%s: tx%d: trasmit done. %d bytes now free in buffer\n",
2471 sc->sc_dev.dv_xname, lcv, sc->txslot[lcv].bfree);
2472#endif
2473 }
2474 }
2475 }
2476
2477 if (reg & MID_INT_DMA_TX) { /* TX DMA done! */
2478
2479 /*
2480 * check for TX DMA complete, if detected then this means that some DTQs
2481 * are now free. it also means some indma mbufs can be freed.
2482 * if we needed DTQs, kick all channels.
2483 */
2484 val = EN_READ(sc, MID_DMA_RDTX); /* chip's current location */
2485 idx = MID_DTQ_A2REG(sc->dtq_chip);/* where we last saw chip */
2486 if (sc->need_dtqs) {
2487 kick = MID_NTX_CH - 1; /* assume power of 2, kick all! */
2488 sc->need_dtqs = 0; /* recalculated in "kick" loop below */
2489#ifdef EN_DEBUG
2490 printf("%s: cleared need DTQ condition\n", sc->sc_dev.dv_xname);
2491#endif
2492 }
2493 while (idx != val) {
2494 sc->dtq_free++;
2495 if ((dtq = sc->dtq[idx]) != 0) {
2496 sc->dtq[idx] = 0; /* don't forget to zero it out when done */
2497 slot = EN_DQ_SLOT(dtq);
2498 IF_DEQUEUE(&sc->txslot[slot].indma, m);
2499 if (!m) panic("enintr: dtqsync");
2500 sc->txslot[slot].mbsize -= EN_DQ_LEN(dtq);
2501#ifdef EN_DEBUG
2502 printf("%s: tx%d: free %d dma bytes, mbsize now %d\n",
2503 sc->sc_dev.dv_xname, slot, EN_DQ_LEN(dtq),
2504 sc->txslot[slot].mbsize);
2505#endif
2506 m_freem(m);
2507 }
2508 EN_WRAPADD(0, MID_DTQ_N, idx, 1);
2509 };
2510 sc->dtq_chip = MID_DTQ_REG2A(val); /* sync softc */
2511 }
2512
2513
2514 /*
2515 * kick xmit channels as needed
2516 */
2517
2518 if (kick) {
2519#ifdef EN_DEBUG
2520 printf("%s: tx kick mask = 0x%x\n", sc->sc_dev.dv_xname, kick);
2521#endif
2522 for (mask = 1, lcv = 0 ; lcv < EN_NTX ; lcv++, mask = mask * 2) {
2523 if ((kick & mask) && sc->txslot[lcv].q.ifq_head) {
2524 en_txdma(sc, lcv); /* kick it! */
2525 }
2526 } /* for each slot */
2527 } /* if kick */
2528
2529
2530 /*******************
2531 * recv interrupts *
2532 ******************/
2533
2534 /*
2535 * check for RX DMA complete, and pass the data "upstairs"
2536 */
2537
2538 if (reg & MID_INT_DMA_RX) {
2539 val = EN_READ(sc, MID_DMA_RDRX); /* chip's current location */
2540 idx = MID_DRQ_A2REG(sc->drq_chip);/* where we last saw chip */
2541 while (idx != val) {
2542 sc->drq_free++;
2543 if ((drq = sc->drq[idx]) != 0) {
2544 sc->drq[idx] = 0; /* don't forget to zero it out when done */
2545 slot = EN_DQ_SLOT(drq);
2546 if (EN_DQ_LEN(drq) == 0) { /* "JK" trash DMA? */
2547 m = NULL;
2548 } else {
2549 IF_DEQUEUE(&sc->rxslot[slot].indma, m);
2550 if (!m)
2551 panic("enintr: drqsync: %s: lost mbuf in slot %d!",
2552 sc->sc_dev.dv_xname, slot);
2553 }
2554 /* do something with this mbuf */
2555 if (sc->rxslot[slot].oth_flags & ENOTHER_DRAIN) { /* drain? */
2556 if (m)
2557 m_freem(m);
2558 vci = sc->rxslot[slot].atm_vci;
2559 if (sc->rxslot[slot].indma.ifq_head == NULL &&
2560 sc->rxslot[slot].q.ifq_head == NULL &&
2561 (EN_READ(sc, MID_VC(vci)) & MIDV_INSERVICE) == 0 &&
2562 (sc->rxslot[slot].oth_flags & ENOTHER_SWSL) == 0) {
2563 sc->rxslot[slot].oth_flags = ENOTHER_FREE; /* done drain */
2564 sc->rxslot[slot].atm_vci = RX_NONE;
2565 sc->rxvc2slot[vci] = RX_NONE;
2566#ifdef EN_DEBUG
2567 printf("%s: rx%d: VCI %d now free\n", sc->sc_dev.dv_xname,
2568 slot, vci);
2569#endif
2570 }
2571 } else if (m != NULL) {
2572 ATM_PH_FLAGS(&ah) = sc->rxslot[slot].atm_flags;
2573 ATM_PH_VPI(&ah) = 0;
2574 ATM_PH_SETVCI(&ah, sc->rxslot[slot].atm_vci);
2575#ifdef EN_DEBUG
2576 printf("%s: rx%d: rxvci%d: atm_input, mbuf %p, len %d, hand %p\n",
2577 sc->sc_dev.dv_xname, slot, sc->rxslot[slot].atm_vci, m,
2578 EN_DQ_LEN(drq), sc->rxslot[slot].rxhand);
2579#endif
2580
2581 ifp = &sc->enif;
2582 ifp->if_ipackets++;
2583
7600679e 2584 BPF_MTAP(ifp, m);
984263bc
MD
2585
2586 atm_input(ifp, &ah, m, sc->rxslot[slot].rxhand);
2587 }
2588
2589 }
2590 EN_WRAPADD(0, MID_DRQ_N, idx, 1);
2591 };
2592 sc->drq_chip = MID_DRQ_REG2A(val); /* sync softc */
2593
2594 if (sc->need_drqs) { /* true if we had a DRQ shortage */
2595 need_softserv = 1;
2596 sc->need_drqs = 0;
2597#ifdef EN_DEBUG
2598 printf("%s: cleared need DRQ condition\n", sc->sc_dev.dv_xname);
2599#endif
2600 }
2601 }
2602
2603 /*
2604 * handle service interrupts
2605 */
2606
2607 if (reg & MID_INT_SERVICE) {
2608 chip = MID_SL_REG2A(EN_READ(sc, MID_SERV_WRITE));
2609
2610 while (sc->hwslistp != chip) {
2611
2612 /* fetch and remove it from hardware service list */
2613 vci = EN_READ(sc, sc->hwslistp);
2614 EN_WRAPADD(MID_SLOFF, MID_SLEND, sc->hwslistp, 4);/* advance hw ptr */
2615 slot = sc->rxvc2slot[vci];
2616 if (slot == RX_NONE) {
2617#ifdef EN_DEBUG
2618 printf("%s: unexpected rx interrupt on VCI %d\n",
2619 sc->sc_dev.dv_xname, vci);
2620#endif
2621 EN_WRITE(sc, MID_VC(vci), MIDV_TRASH); /* rx off, damn it! */
2622 continue; /* next */
2623 }
2624 EN_WRITE(sc, MID_VC(vci), sc->rxslot[slot].mode); /* remove from hwsl */
2625 EN_COUNT(sc->hwpull);
2626
2627#ifdef EN_DEBUG
2628 printf("%s: pulled VCI %d off hwslist\n", sc->sc_dev.dv_xname, vci);
2629#endif
2630
2631 /* add it to the software service list (if needed) */
2632 if ((sc->rxslot[slot].oth_flags & ENOTHER_SWSL) == 0) {
2633 EN_COUNT(sc->swadd);
2634 need_softserv = 1;
2635 sc->rxslot[slot].oth_flags |= ENOTHER_SWSL;
2636 sc->swslist[sc->swsl_tail] = slot;
2637 EN_WRAPADD(0, MID_SL_N, sc->swsl_tail, 1);
2638 sc->swsl_size++;
2639#ifdef EN_DEBUG
2640 printf("%s: added VCI %d to swslist\n", sc->sc_dev.dv_xname, vci);
2641#endif
2642 }
2643 };
2644 }
2645
2646 /*
2647 * now service (function too big to include here)
2648 */
2649
2650 if (need_softserv)
2651 en_service(sc);
2652
2653 /*
2654 * keep our stats
2655 */
2656
2657 if (reg & MID_INT_DMA_OVR) {
2658 EN_COUNT(sc->dmaovr);
2659#ifdef EN_DEBUG
2660 printf("%s: MID_INT_DMA_OVR\n", sc->sc_dev.dv_xname);
2661#endif
2662 }
2663 reg = EN_READ(sc, MID_STAT);
2664#ifdef EN_STAT
2665 sc->otrash += MID_OTRASH(reg);
2666 sc->vtrash += MID_VTRASH(reg);
2667#endif
2668
2669 EN_INTR_RET(1); /* for us */
2670}
2671
2672
2673/*
2674 * en_service: handle a service interrupt
2675 *
2676 * Q: why do we need a software service list?
2677 *
2678 * A: if we remove a VCI from the hardware list and we find that we are
2679 * out of DRQs we must defer processing until some DRQs become free.
2680 * so we must remember to look at this RX VCI/slot later, but we can't
2681 * put it back on the hardware service list (since that isn't allowed).
2682 * so we instead save it on the software service list. it would be nice
2683 * if we could peek at the VCI on top of the hwservice list without removing
2684 * it, however this leads to a race condition: if we peek at it and
2685 * decide we are done with it new data could come in before we have a
2686 * chance to remove it from the hwslist. by the time we get it out of
2687 * the list the interrupt for the new data will be lost. oops!
2688 *
2689 */
2690
2691STATIC void en_service(sc)
2692
2693struct en_softc *sc;
2694
2695{
2696 struct mbuf *m, *tmp;
2697 u_int32_t cur, dstart, rbd, pdu, *sav, dma, bcode, count, *data, *datastop;
2698 u_int32_t start, stop, cnt, needalign;
2699 int slot, raw, aal5, llc, vci, fill, mlen, tlen, drqneed, need, needfill, end;
2700
2701 aal5 = 0; /* Silence gcc */
2702next_vci:
2703 if (sc->swsl_size == 0) {
2704#ifdef EN_DEBUG
2705 printf("%s: en_service done\n", sc->sc_dev.dv_xname);
2706#endif
2707 return; /* >>> exit here if swsl now empty <<< */
2708 }
2709
2710 /*
2711 * get slot/vci to service
2712 */
2713
2714 slot = sc->swslist[sc->swsl_head];
2715 vci = sc->rxslot[slot].atm_vci;
2716#ifdef EN_DIAG
2717 if (sc->rxvc2slot[vci] != slot) panic("en_service rx slot/vci sync");
2718#endif
2719
2720 /*
2721 * determine our mode and if we've got any work to do
2722 */
2723
2724 raw = sc->rxslot[slot].oth_flags & ENOTHER_RAW;
2725 start= sc->rxslot[slot].start;
2726 stop= sc->rxslot[slot].stop;
2727 cur = sc->rxslot[slot].cur;
2728
2729#ifdef EN_DEBUG
2730 printf("%s: rx%d: service vci=%d raw=%d start/stop/cur=0x%x 0x%x 0x%x\n",
2731 sc->sc_dev.dv_xname, slot, vci, raw, start, stop, cur);
2732#endif
2733
2734same_vci:
2735 dstart = MIDV_DSTART(EN_READ(sc, MID_DST_RP(vci)));
2736 dstart = (dstart * sizeof(u_int32_t)) + start;
2737
2738 /* check to see if there is any data at all */
2739 if (dstart == cur) {
2740defer: /* defer processing */
2741 EN_WRAPADD(0, MID_SL_N, sc->swsl_head, 1);
2742 sc->rxslot[slot].oth_flags &= ~ENOTHER_SWSL;
2743 sc->swsl_size--;
2744 /* >>> remove from swslist <<< */
2745#ifdef EN_DEBUG
2746 printf("%s: rx%d: remove vci %d from swslist\n",
2747 sc->sc_dev.dv_xname, slot, vci);
2748#endif
2749 goto next_vci;
2750 }
2751
2752 /*
2753 * figure out how many bytes we need
2754 * [mlen = # bytes to go in mbufs, fill = # bytes to dump (MIDDMA_JK)]
2755 */
2756
2757 if (raw) {
2758
2759 /* raw mode (aka boodi mode) */
2760 fill = 0;
2761 if (dstart > cur)
2762 mlen = dstart - cur;
2763 else
2764 mlen = (dstart + (EN_RXSZ*1024)) - cur;
2765
2766 if (mlen < sc->rxslot[slot].raw_threshold)
2767 goto defer; /* too little data to deal with */
2768
2769 } else {
2770
2771 /* normal mode */
2772 aal5 = (sc->rxslot[slot].atm_flags & ATM_PH_AAL5);
2773 llc = (aal5 && (sc->rxslot[slot].atm_flags & ATM_PH_LLCSNAP)) ? 1 : 0;
2774 rbd = EN_READ(sc, cur);
2775 if (MID_RBD_ID(rbd) != MID_RBD_STDID)
2776 panic("en_service: id mismatch");
2777
2778 if (rbd & MID_RBD_T) {
2779 mlen = 0; /* we've got trash */
2780 fill = MID_RBD_SIZE;
2781 EN_COUNT(sc->ttrash);
2782#ifdef EN_DEBUG
2783 printf("RX overflow lost %d cells!\n", MID_RBD_CNT(rbd));
2784#endif
2785 } else if (!aal5) {
2786 mlen = MID_RBD_SIZE + MID_CHDR_SIZE + MID_ATMDATASZ; /* 1 cell (ick!) */
2787 fill = 0;
2788 } else {
2789 struct ifnet *ifp;
2790
2791 tlen = (MID_RBD_CNT(rbd) * MID_ATMDATASZ) + MID_RBD_SIZE;
2792 pdu = cur + tlen - MID_PDU_SIZE;
2793 if (pdu >= stop)
2794 pdu -= (EN_RXSZ*1024);
2795 pdu = EN_READ(sc, pdu); /* get PDU in correct byte order */
2796 fill = tlen - MID_RBD_SIZE - MID_PDU_LEN(pdu);
2797 if (fill < 0 || (rbd & MID_RBD_CRCERR) != 0) {
2798 static int first = 1;
2799
2800 if (first) {
2801 printf("%s: %s, dropping frame\n", sc->sc_dev.dv_xname,
2802 (rbd & MID_RBD_CRCERR) ?
2803 "CRC error" : "invalid AAL5 PDU length");
2804 printf("%s: got %d cells (%d bytes), AAL5 len is %d bytes (pdu=0x%x)\n",
2805 sc->sc_dev.dv_xname, MID_RBD_CNT(rbd),
2806 tlen - MID_RBD_SIZE, MID_PDU_LEN(pdu), pdu);
2807#ifndef EN_DEBUG
2808 printf("CRC error report disabled from now on!\n");
2809 first = 0;
2810#endif
2811 }
2812 fill = tlen;
2813
2814 ifp = &sc->enif;
2815 ifp->if_ierrors++;
2816
2817 }
2818 mlen = tlen - fill;
2819 }
2820
2821 }
2822
2823 /*
2824 * now allocate mbufs for mlen bytes of data, if out of mbufs, trash all
2825 *
2826 * notes:
2827 * 1. it is possible that we've already allocated an mbuf for this pkt
2828 * but ran out of DRQs, in which case we saved the allocated mbuf on
2829 * "q".
2830 * 2. if we save an mbuf in "q" we store the "cur" (pointer) in the front
2831 * of the mbuf as an identity (that we can check later), and we also
2832 * store drqneed (so we don't have to recompute it).
2833 * 3. after this block of code, if m is still NULL then we ran out of mbufs
2834 */
2835
2836 m = sc->rxslot[slot].q.ifq_head;
2837 drqneed = 1;
2838 if (m) {
2839 sav = mtod(m, u_int32_t *);
2840 if (sav[0] != cur) {
2841#ifdef EN_DEBUG
2842 printf("%s: rx%d: q'ed mbuf %p not ours\n",
2843 sc->sc_dev.dv_xname, slot, m);
2844#endif
2845 m = NULL; /* wasn't ours */
2846 EN_COUNT(sc->rxqnotus);
2847 } else {
2848 EN_COUNT(sc->rxqus);
2849 IF_DEQUEUE(&sc->rxslot[slot].q, m);
2850 drqneed = sav[1];
2851#ifdef EN_DEBUG
2852 printf("%s: rx%d: recovered q'ed mbuf %p (drqneed=%d)\n",
2853 sc->sc_dev.dv_xname, slot, m, drqneed);
2854#endif
2855 }
2856 }
2857
2858 if (mlen != 0 && m == NULL) {
2859 m = en_mget(sc, mlen, &drqneed); /* allocate! */
2860 if (m == NULL) {
2861 fill += mlen;
2862 mlen = 0;
2863 EN_COUNT(sc->rxmbufout);
2864#ifdef EN_DEBUG
2865 printf("%s: rx%d: out of mbufs\n", sc->sc_dev.dv_xname, slot);
2866#endif
2867 }
2868#ifdef EN_DEBUG
2869 printf("%s: rx%d: allocate mbuf %p, mlen=%d, drqneed=%d\n",
2870 sc->sc_dev.dv_xname, slot, m, mlen, drqneed);
2871#endif
2872 }
2873
2874#ifdef EN_DEBUG
2875 printf("%s: rx%d: VCI %d, mbuf_chain %p, mlen %d, fill %d\n",
2876 sc->sc_dev.dv_xname, slot, vci, m, mlen, fill);
2877#endif
2878
2879 /*
2880 * now check to see if we've got the DRQs needed. if we are out of
2881 * DRQs we must quit (saving our mbuf, if we've got one).
2882 */
2883
2884 needfill = (fill) ? 1 : 0;
2885 if (drqneed + needfill > sc->drq_free) {
2886 sc->need_drqs = 1; /* flag condition */
2887 if (m == NULL) {
2888 EN_COUNT(sc->rxoutboth);
2889#ifdef EN_DEBUG
2890 printf("%s: rx%d: out of DRQs *and* mbufs!\n", sc->sc_dev.dv_xname, slot);
2891#endif
2892 return; /* >>> exit here if out of both mbufs and DRQs <<< */
2893 }
2894 sav = mtod(m, u_int32_t *);
2895 sav[0] = cur;
2896 sav[1] = drqneed;
2897 IF_ENQUEUE(&sc->rxslot[slot].q, m);
2898 EN_COUNT(sc->rxdrqout);
2899#ifdef EN_DEBUG
2900 printf("%s: rx%d: out of DRQs\n", sc->sc_dev.dv_xname, slot);
2901#endif
2902 return; /* >>> exit here if out of DRQs <<< */
2903 }
2904
2905 /*
2906 * at this point all resources have been allocated and we are commited
2907 * to servicing this slot.
2908 *
2909 * dma = last location we told chip about
2910 * cur = current location
2911 * mlen = space in the mbuf we want
2912 * need = bytes to xfer in (decrs to zero)
2913 * fill = how much fill we need
2914 * tlen = how much data to transfer to this mbuf
2915 * cnt/bcode/count = <same as xmit>
2916 *
2917 * 'needfill' not used after this point
2918 */
2919
2920 dma = cur; /* dma = last location we told chip about */
2921 need = roundup(mlen, sizeof(u_int32_t));
2922 fill = fill - (need - mlen); /* note: may invalidate 'needfill' */
2923
2924 for (tmp = m ; tmp != NULL && need > 0 ; tmp = tmp->m_next) {
2925 tlen = roundup(tmp->m_len, sizeof(u_int32_t)); /* m_len set by en_mget */
2926 data = mtod(tmp, u_int32_t *);
2927
2928#ifdef EN_DEBUG
2929 printf("%s: rx%d: load mbuf %p, m_len=%d, m_data=%p, tlen=%d\n",
2930 sc->sc_dev.dv_xname, slot, tmp, tmp->m_len, tmp->m_data, tlen);
2931#endif
2932
2933 /* copy data */
2934 if (EN_NORXDMA || !en_dma || tlen < EN_MINDMA) {
2935 datastop = (u_int32_t *)((u_char *) data + tlen);
2936 /* copy loop: preserve byte order!!! use READDAT */
2937 while (data != datastop) {
2938 *data = EN_READDAT(sc, cur);
2939 data++;
2940 EN_WRAPADD(start, stop, cur, 4);
2941 }
2942 need -= tlen;
2943#ifdef EN_DEBUG
2944 printf("%s: rx%d: vci%d: copied %d bytes (%d left)\n",
2945 sc->sc_dev.dv_xname, slot, vci, tlen, need);
2946#endif
2947 continue;
2948 }
2949
2950 /* DMA data (check to see if we need to sync DRQ first) */
2951 if (dma != cur) {
2952 EN_DRQADD(sc, WORD_IDX(start,cur), vci, MIDDMA_JK, 0, 0, 0, 0);
2953#ifdef EN_DEBUG
2954 printf("%s: rx%d: vci%d: drq_sync: advance pointer to %d\n",
2955 sc->sc_dev.dv_xname, slot, vci, cur);
2956#endif
2957 }
2958
2959#if !defined(MIDWAY_ENIONLY)
2960
2961 /*
2962 * the adaptec DMA engine is smart and handles everything for us.
2963 */
2964
2965 if (sc->is_adaptec) {
2966 need -= tlen;
2967 EN_WRAPADD(start, stop, cur, tlen);
2968#ifdef EN_DEBUG
2969 printf("%s: rx%d: vci%d: adp_dma %d bytes (%d left)\n",
2970 sc->sc_dev.dv_xname, slot, vci, tlen, need);
2971#endif
2972 end = (need == 0 && !fill) ? MID_DMA_END : 0;
2973 EN_DRQADD(sc, tlen, vci, 0, vtophys(data), mlen, slot, end);
2974 if (end)
2975 goto done;
2976 dma = cur; /* update dma pointer */
2977 continue;
2978 }
2979#endif /* !MIDWAY_ENIONLY */
2980
2981
2982#if !defined(MIDWAY_ADPONLY)
2983
2984 /*
2985 * the ENI DMA engine is not so smart and need more help from us
2986 */
2987
2988 /* do we need to do a DMA op to align? */
2989 if (sc->alburst &&
2990 (needalign = (((uintptr_t) (void *) data) & sc->bestburstmask)) != 0) {
2991 cnt = sc->bestburstlen - needalign;
2992 if (cnt > tlen) {
2993 cnt = tlen;
2994 count = cnt / sizeof(u_int32_t);
2995 bcode = MIDDMA_WORD;
2996 } else {
2997 count = cnt / sizeof(u_int32_t);
2998 bcode = en_dmaplan[count].bcode;
2999 count = cnt >> en_dmaplan[count].divshift;
3000 }
3001 need -= cnt;
3002 EN_WRAPADD(start, stop, cur, cnt);
3003#ifdef EN_DEBUG
3004 printf("%s: rx%d: vci%d: al_dma %d bytes (%d left)\n",
3005 sc->sc_dev.dv_xname, slot, vci, cnt, need);
3006#endif
3007 tlen -= cnt;
3008 end = (need == 0 && !fill) ? MID_DMA_END : 0;
3009 EN_DRQADD(sc, count, vci, bcode, vtophys(data), mlen, slot, end);
3010 if (end)
3011 goto done;
3012 data = (u_int32_t *)((u_char *) data + cnt);
3013 }
3014
3015 /* do we need a max-sized burst? */
3016 if (tlen >= sc->bestburstlen) {
3017 count = tlen >> sc->bestburstshift;
3018 cnt = count << sc->bestburstshift;
3019 bcode = sc->bestburstcode;
3020 need -= cnt;
3021 EN_WRAPADD(start, stop, cur, cnt);
3022#ifdef EN_DEBUG
3023 printf("%s: rx%d: vci%d: best_dma %d bytes (%d left)\n",
3024 sc->sc_dev.dv_xname, slot, vci, cnt, need);
3025#endif
3026 tlen -= cnt;
3027 end = (need == 0 && !fill) ? MID_DMA_END : 0;
3028 EN_DRQADD(sc, count, vci, bcode, vtophys(data), mlen, slot, end);
3029 if (end)
3030 goto done;
3031 data = (u_int32_t *)((u_char *) data + cnt);
3032 }
3033
3034 /* do we need to do a cleanup burst? */
3035 if (tlen) {
3036 count = tlen / sizeof(u_int32_t);
3037 bcode = en_dmaplan[count].bcode;
3038 count = tlen >> en_dmaplan[count].divshift;
3039 need -= tlen;
3040 EN_WRAPADD(start, stop, cur, tlen);
3041#ifdef EN_DEBUG
3042 printf("%s: rx%d: vci%d: cleanup_dma %d bytes (%d left)\n",
3043 sc->sc_dev.dv_xname, slot, vci, tlen, need);
3044#endif
3045 end = (need == 0 && !fill) ? MID_DMA_END : 0;
3046 EN_DRQADD(sc, count, vci, bcode, vtophys(data), mlen, slot, end);
3047 if (end)
3048 goto done;
3049 }
3050
3051 dma = cur; /* update dma pointer */
3052
3053#endif /* !MIDWAY_ADPONLY */
3054
3055 }
3056
3057 /* skip the end */
3058 if (fill || dma != cur) {
3059#ifdef EN_DEBUG
3060 if (fill)
3061 printf("%s: rx%d: vci%d: skipping %d bytes of fill\n",
3062 sc->sc_dev.dv_xname, slot, vci, fill);
3063 else
3064 printf("%s: rx%d: vci%d: syncing chip from 0x%x to 0x%x [cur]\n",
3065 sc->sc_dev.dv_xname, slot, vci, dma, cur);
3066#endif
3067 EN_WRAPADD(start, stop, cur, fill);
3068 EN_DRQADD(sc, WORD_IDX(start,cur), vci, MIDDMA_JK, 0, mlen,
3069 slot, MID_DMA_END);
3070 /* dma = cur; */ /* not necessary since we are done */
3071 }
3072
3073 /*
3074 * done, remove stuff we don't want to pass up:
3075 * raw mode (boodi mode): pass everything up for later processing
3076 * aal5: remove RBD
3077 * aal0: remove RBD + cell header
3078 */
3079
3080done:
3081 if (m) {
3082 if (!raw) {
3083 cnt = MID_RBD_SIZE;
3084 if (!aal5) cnt += MID_CHDR_SIZE;
3085 m->m_len -= cnt; /* chop! */
3086 m->m_pkthdr.len -= cnt;
3087 m->m_data += cnt;
3088 }
3089 IF_ENQUEUE(&sc->rxslot[slot].indma, m);
3090 }
3091 sc->rxslot[slot].cur = cur; /* update master copy of 'cur' */
3092
3093#ifdef EN_DEBUG
3094 printf("%s: rx%d: vci%d: DONE! cur now =0x%x\n",
3095 sc->sc_dev.dv_xname, slot, vci, cur);
3096#endif
3097
3098 goto same_vci; /* get next packet in this slot */
3099}
3100
3101
3102#ifdef EN_DDBHOOK
3103/*
3104 * functions we can call from ddb
3105 */
3106
3107/*
3108 * en_dump: dump the state
3109 */
3110
3111#define END_SWSL 0x00000040 /* swsl state */
3112#define END_DRQ 0x00000020 /* drq state */
3113#define END_DTQ 0x00000010 /* dtq state */
3114#define END_RX 0x00000008 /* rx state */
3115#define END_TX 0x00000004 /* tx state */
3116#define END_MREGS 0x00000002 /* registers */
3117#define END_STATS 0x00000001 /* dump stats */
3118
3119#define END_BITS "\20\7SWSL\6DRQ\5DTQ\4RX\3TX\2MREGS\1STATS"
3120
3121/* Do not staticize - meant for calling from DDB! */
3122int en_dump(unit, level)
3123
3124int unit, level;
3125
3126{
3127 struct en_softc *sc;
3128 int lcv, cnt, slot;
3129 u_int32_t ptr, reg;
3130
3131 for (lcv = 0 ; lcv < en_cd.cd_ndevs ; lcv++) {
3132 sc = (struct en_softc *) en_cd.cd_devs[lcv];
3133 if (sc == NULL) continue;
3134 if (unit != -1 && unit != lcv)
3135 continue;
3136
3137 printf("dumping device %s at level 0x%b\n", sc->sc_dev.dv_xname, level,
3138 END_BITS);
3139
3140 if (sc->dtq_us == 0) {
3141 printf("<hasn't been en_init'd yet>\n");
3142 continue;
3143 }
3144
3145 if (level & END_STATS) {
3146 printf(" en_stats:\n");
3147 printf(" %d mfix (%d failed); %d/%d head/tail byte DMAs, %d flushes\n",
3148 sc->mfix, sc->mfixfail, sc->headbyte, sc->tailbyte, sc->tailflush);
3149 printf(" %d rx dma overflow interrupts\n", sc->dmaovr);
3150 printf(" %d times we ran out of TX space and stalled\n",
3151 sc->txoutspace);
3152 printf(" %d times we ran out of DTQs\n", sc->txdtqout);
3153 printf(" %d times we launched a packet\n", sc->launch);
3154 printf(" %d times we launched without on-board header\n", sc->lheader);
3155 printf(" %d times we launched without on-board tail\n", sc->ltail);
3156 printf(" %d times we pulled the hw service list\n", sc->hwpull);
3157 printf(" %d times we pushed a vci on the sw service list\n",
3158 sc->swadd);
3159 printf(" %d times RX pulled an mbuf from Q that wasn't ours\n",
3160 sc->rxqnotus);
3161 printf(" %d times RX pulled a good mbuf from Q\n", sc->rxqus);
3162 printf(" %d times we ran out of mbufs *and* DRQs\n", sc->rxoutboth);
3163 printf(" %d times we ran out of DRQs\n", sc->rxdrqout);
3164
3165 printf(" %d trasmit packets dropped due to mbsize\n", sc->txmbovr);
3166 printf(" %d cells trashed due to turned off rxvc\n", sc->vtrash);
3167 printf(" %d cells trashed due to totally full buffer\n", sc->otrash);
3168 printf(" %d cells trashed due almost full buffer\n", sc->ttrash);
3169 printf(" %d rx mbuf allocation failures\n", sc->rxmbufout);
8bde602d 3170#if defined(NATM) && defined(NATM_STAT)
984263bc
MD
3171 printf(" natmintr so_rcv: ok/drop cnt: %d/%d, ok/drop bytes: %d/%d\n",
3172 natm_sookcnt, natm_sodropcnt, natm_sookbytes, natm_sodropbytes);
984263bc
MD
3173#endif
3174 }
3175
3176 if (level & END_MREGS) {
3177 printf("mregs:\n");
3178 printf("resid = 0x%lx\n", (u_long)EN_READ(sc, MID_RESID));
3179 printf("interrupt status = 0x%b\n",
3180 (int)EN_READ(sc, MID_INTSTAT), MID_INTBITS);
3181 printf("interrupt enable = 0x%b\n",
3182 (int)EN_READ(sc, MID_INTENA), MID_INTBITS);
3183 printf("mcsr = 0x%b\n", (int)EN_READ(sc, MID_MAST_CSR), MID_MCSRBITS);
3184 printf("serv_write = [chip=%ld] [us=%d]\n",
3185 (long)EN_READ(sc, MID_SERV_WRITE),
3186 MID_SL_A2REG(sc->hwslistp));
3187 printf("dma addr = 0x%lx\n", (u_long)EN_READ(sc, MID_DMA_ADDR));
3188 printf("DRQ: chip[rd=0x%lx,wr=0x%lx], sc[chip=0x%x,us=0x%x]\n",
3189 (u_long)MID_DRQ_REG2A(EN_READ(sc, MID_DMA_RDRX)),
3190 (u_long)MID_DRQ_REG2A(EN_READ(sc, MID_DMA_WRRX)),
3191 sc->drq_chip, sc->drq_us);
3192 printf("DTQ: chip[rd=0x%lx,wr=0x%lx], sc[chip=0x%x,us=0x%x]\n",
3193 (u_long)MID_DTQ_REG2A(EN_READ(sc, MID_DMA_RDTX)),
3194 (u_long)MID_DTQ_REG2A(EN_READ(sc, MID_DMA_WRTX)),
3195 sc->dtq_chip, sc->dtq_us);
3196
3197 printf(" unusal txspeeds: ");
3198 for (cnt = 0 ; cnt < MID_N_VC ; cnt++)
3199 if (sc->txspeed[cnt])
3200 printf(" vci%d=0x%x", cnt, sc->txspeed[cnt]);
3201 printf("\n");
3202
3203 printf(" rxvc slot mappings: ");
3204 for (cnt = 0 ; cnt < MID_N_VC ; cnt++)
3205 if (sc->rxvc2slot[cnt] != RX_NONE)
3206 printf(" %d->%d", cnt, sc->rxvc2slot[cnt]);
3207 printf("\n");
3208
3209 }
3210
3211 if (level & END_TX) {
3212 printf("tx:\n");
3213 for (slot = 0 ; slot < EN_NTX; slot++) {
3214 printf("tx%d: start/stop/cur=0x%x/0x%x/0x%x [%d] ", slot,
3215 sc->txslot[slot].start, sc->txslot[slot].stop, sc->txslot[slot].cur,
3216 (sc->txslot[slot].cur - sc->txslot[slot].start)/4);
3217 printf("mbsize=%d, bfree=%d\n", sc->txslot[slot].mbsize,
3218 sc->txslot[slot].bfree);
3219 printf("txhw: base_address=0x%lx, size=%ld, read=%ld, descstart=%ld\n",
3220 (u_long)MIDX_BASE(EN_READ(sc, MIDX_PLACE(slot))),
3221 (u_long)MIDX_SZ(EN_READ(sc, MIDX_PLACE(slot))),
3222 (long)EN_READ(sc, MIDX_READPTR(slot)),
3223 (long)EN_READ(sc, MIDX_DESCSTART(slot)));
3224 }
3225 }
3226
3227 if (level & END_RX) {
3228 printf(" recv slots:\n");
3229 for (slot = 0 ; slot < sc->en_nrx; slot++) {
3230 printf("rx%d: vci=%d: start/stop/cur=0x%x/0x%x/0x%x ", slot,
3231 sc->rxslot[slot].atm_vci, sc->rxslot[slot].start,
3232 sc->rxslot[slot].stop, sc->rxslot[slot].cur);
3233 printf("mode=0x%x, atm_flags=0x%x, oth_flags=0x%x\n",
3234 sc->rxslot[slot].mode, sc->rxslot[slot].atm_flags,
3235 sc->rxslot[slot].oth_flags);
3236 printf("RXHW: mode=0x%lx, DST_RP=0x%lx, WP_ST_CNT=0x%lx\n",
3237 (u_long)EN_READ(sc, MID_VC(sc->rxslot[slot].atm_vci)),
3238 (u_long)EN_READ(sc, MID_DST_RP(sc->rxslot[slot].atm_vci)),
3239 (u_long)EN_READ(sc, MID_WP_ST_CNT(sc->rxslot[slot].atm_vci)));
3240 }
3241 }
3242
3243 if (level & END_DTQ) {
3244 printf(" dtq [need_dtqs=%d,dtq_free=%d]:\n",
3245 sc->need_dtqs, sc->dtq_free);
3246 ptr = sc->dtq_chip;
3247 while (ptr != sc->dtq_us) {
3248 reg = EN_READ(sc, ptr);
3249 printf("\t0x%x=[cnt=%d, chan=%d, end=%d, type=%d @ 0x%lx]\n",
3250 sc->dtq[MID_DTQ_A2REG(ptr)], MID_DMA_CNT(reg), MID_DMA_TXCHAN(reg),
3251 (reg & MID_DMA_END) != 0, MID_DMA_TYPE(reg),
3252 (u_long)EN_READ(sc, ptr+4));
3253 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, ptr, 8);
3254 }
3255 }
3256
3257 if (level & END_DRQ) {
3258 printf(" drq [need_drqs=%d,drq_free=%d]:\n",
3259 sc->need_drqs, sc->drq_free);
3260 ptr = sc->drq_chip;
3261 while (ptr != sc->drq_us) {
3262 reg = EN_READ(sc, ptr);
3263 printf("\t0x%x=[cnt=%d, chan=%d, end=%d, type=%d @ 0x%lx]\n",
3264 sc->drq[MID_DRQ_A2REG(ptr)], MID_DMA_CNT(reg), MID_DMA_RXVCI(reg),
3265 (reg & MID_DMA_END) != 0, MID_DMA_TYPE(reg),
3266 (u_long)EN_READ(sc, ptr+4));
3267 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, ptr, 8);
3268 }
3269 }
3270
3271 if (level & END_SWSL) {
3272 printf(" swslist [size=%d]: ", sc->swsl_size);
3273 for (cnt = sc->swsl_head ; cnt != sc->swsl_tail ;
3274 cnt = (cnt + 1) % MID_SL_N)
3275 printf("0x%x ", sc->swslist[cnt]);
3276 printf("\n");
3277 }
3278 }
3279 return(0);
3280}
3281
3282/*
3283 * en_dumpmem: dump the memory
3284 */
3285
3286/* Do not staticize - meant for calling from DDB! */
3287int en_dumpmem(unit, addr, len)
3288
3289int unit, addr, len;
3290
3291{
3292 struct en_softc *sc;
3293 u_int32_t reg;
3294
3295 if (unit < 0 || unit > en_cd.cd_ndevs ||
3296 (sc = (struct en_softc *) en_cd.cd_devs[unit]) == NULL) {
3297 printf("invalid unit number: %d\n", unit);
3298 return(0);
3299 }
3300 addr = addr & ~3;
3301 if (addr < MID_RAMOFF || addr + len*4 > MID_MAXOFF || len <= 0) {
3302 printf("invalid addr/len number: %d, %d\n", addr, len);
3303 return(0);
3304 }
3305 printf("dumping %d words starting at offset 0x%x\n", len, addr);
3306 while (len--) {
3307 reg = EN_READ(sc, addr);
3308 printf("mem[0x%x] = 0x%x\n", addr, reg);
3309 addr += 4;
3310 }
3311 return(0);
3312}
3313#endif