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Update some copyright notices to become more legal compliant.
[dragonfly.git] / sys / platform / pc32 / apic / apicreg.h
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1/*
2 * Copyright (c) 1996, by Peter Wemm and Steve Passe, All rights reserved.
3 * Copyright (c) 2003 by Matthew Dillon, All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/include/apic.h,v 1.14.2.2 2003/03/21 21:46:15 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/apic/apicreg.h,v 1.2 2004/06/28 02:57:11 drhodus Exp $
27 */
28
29#ifndef _MACHINE_APICREG_H_
30#define _MACHINE_APICREG_H_
31
32/*
33 * Local && I/O APIC definitions for Pentium P54C+ Built-in APIC.
34 *
35 * A per-cpu APIC resides in memory location 0xFEE00000.
36 *
37 * 31 ... 24 23 ... 16 15 ... 8 7 ... 0
38 * +-----------+-----------+-----------+-----------+
39 * 0000 | | | | |
40 * 0010 | | | | |
41 * +-----------+-----------+-----------+-----------+
42 *
43 * +-----------+-----------+-----------+-----------+
44 * 0020 ID | | ID | | | | RW
45 * +-----------+-----------+-----------+-----------+
46 *
47 * The physical APIC ID is used with physical interrupt
48 * delivery modes.
49 *
50 * +-----------+-----------+-----------+-----------+
51 * 0030 VER | | | | |
52 * +-----------+-----------+-----------+-----------+
53 * 0040 | | | | |
54 * 0050 | | | | |
55 * 0060 | | | | |
56 * 0070 | | | | |
57 * +-----------+-----------+-----------+-----------+
58 * 0080 TPR | | | | PRIO SUBC |
59 * 0090 APR | | | | |
60 * 00A0 PPR | | | | |
61 * +-----------+-----------+-----------+-----------+
62 *
63 * The Task Priority Register provides a priority threshold
64 * mechanism for interrupting the processor. Only interrupts
65 * with a higher priority then that specified in the TPR will
66 * be served. Other interrupts are recorded and serviced
67 * as soon as the TPR value decreases enough to allow that
68 * (unless EOId by another APIC).
69 *
70 * PRIO (7:4). Main priority. If 15 the APIC will not
71 * accept any interrupts.
72 * SUBC (3:0) Sub priority. See APR/PPR.
73 *
74 *
75 * The Processor Priority Register determines whether a
76 * pending interrupt can be dispensed to the processor. ISRV
77 * Is the vector of the highest priority ISR bit set or
78 * zero if no ISR bit is set.
79 *
80 * IF TPR[7:4] >= ISRV[7:4]
81 * PPR[7:0] = TPR[7:0]
82 * ELSE
83 * PPR[7:0] = ISRV[7:4].000
84 *
85 * The Arbitration Priority Register holds the current
86 * lowest priority of the procsesor, a value used during
87 * lowest-priority arbitration.
88 *
89 * IF (TPR[7:4] >= IRRV[7:4] AND TPR[7:4] > ISRV[7:4])
90 * APR[7:0] = TPR[7:0]
91 * ELSE
92 * APR[7:4] = max((TPR[7:4]&ISRV[7:4]),IRRV[7:4]).000
93 *
94 * +-----------+-----------+-----------+-----------+
95 * 00B0 EOI | | | | |
96 * +-----------+-----------+-----------+-----------+
97 * 00C0 | | | | |
98 * +-----------+-----------+-----------+-----------+
99 * 00D0 LDR |LOG APICID | | | |
100 * +-----------+-----------+-----------+-----------+
101 * 00E0 DFR |MODEL| | | | |
102 * +-----------+-----------+-----------+-----------+
103 *
104 * The logical APIC ID is used with logical interrupt
105 * delivery modes. Interpretation of logical destination
106 * information depends on the MODEL bits in the Destination
107 * Format Regiuster.
108 *
109 * MODEL=1111 FLAT MODEL - The MDA is interpreted as
110 * a decoded address. By setting
111 * one bit in the LDR for each
112 * local apic 8 APICs can coexist.
113 *
114 * MODEL=0000 CLUSTER MODEL -
115 *
116 * 31 ... 24 23 ... 16 15 ... 8 7 ... 0
117 * +-----------+-----------+-----------+-----------+
118 * 00F0 SVR | | | | |
119 * +-----------+-----------+-----------+-----------+
120 * 0100-0170 ISR| | | | |
121 * 0180-01F0 TMR| | | | |
122 * 0200-0270 IRR| | | | |
123 * +-----------+-----------+-----------+-----------+
124 *
125 * These registers represent 256 bits, one bit for each
126 * possible interrupt. Interrupts 0-15 are reserved so
127 * bits 0-15 are also reserved.
128 *
129 * TMR - Trigger mode register. Upon acceptance of an int
130 * the corresponding bit is cleared for edge-trig and
131 * set for level-trig. If the TMR bit is set (level),
132 * the local APIC sends an EOI to all I/O APICs as
133 * a result of software issuing an EOI command.
134 *
135 * IRR - Interrupt Request Register. Contains active
136 * interrupt requests that have been accepted but not
137 * yet dispensed by the current local APIC. The bit is
138 * cleared and the corresponding ISR bit is set when
139 * the INTA cycle is issued.
140 *
141 * ISR - Interrupt In-Service register. Interrupt has been
142 * delivered but not yet fully serviced. Cleared when
143 * an EOI is issued from the processor. An EOI will
144 * also send an EOI to all I/O APICs if TMR was set.
145 *
146 * +-----------+-----------+-----------+-----------+
147 * 0280 ESR | | | | |
148 * 0290-02F0 | | | | |
149 * +--FEDCBA98-+--76543210-+--FEDCBA98-+-----------+
150 * 0300 ICR_LO | | XX | TL SDMMM | vector |
151 * 0310 ICR_HI | DEST FIELD| | | |
152 * +-----------+-----------+-----------+-----------+
153 *
154 * The interrupt command register. Generally speaking
155 * writing to ICR_LO initiates a command. All fields
156 * are R/W except the 'S' (delivery status) field, which
157 * is read-only. When
158 *
159 *
160 * XX: Destination Shorthand field:
161 *
162 * 00 Use Destination field
163 * 01 Self only. Dest field ignored.
164 * 10 All including self (uses a
165 * destination field of 0x0F)
166 * 11 All excluding self (uses a
167 * destination field of 0x0F)
168 *
169 * T: 1 = Level 0 = Edge Trigger modde, used for
170 * the INIT level de-assert delivery mode only
171 * to de-assert a request.
172 *
173 * L: 0 = De-Assert, 1 = Assert. Always write as
174 * 1 when initiating a new command. Can only
175 * write as 0 for INIT mode de-assertion of
176 * command.
177 *
178 * S: 1 = Send Pending. Interrupt has been injected
179 * but APIC has not yet accepted it.
180 *
181 * D: 0=physical 1=logical. In physical mode
182 * only 24-27 of DEST FIELD is used from ICR_HI.
183 *
184 * MMM: 000 Fixed. Deliver to all processors according
185 * to the ICR. Always treated as edge trig.
186 *
187 * 001 Lowest Priority. Deliver to just the
188 * processor running at the lowest priority.
189 *
190 * 010 SMI. The vector must be 00B. Only edge
191 * triggered is allowed. The vector field
192 * must be programmed to zero (huh?).
193 *
194 * 011 <reserved>
195 *
196 * 100 NMI. Deliver as an NMI to all processors
197 * listed in the destination field. The
198 * vector is ignored. Alawys treated as
199 * edge triggered.
200 *
201 * 101 INIT. Deliver as an INIT signal to all
202 * processors (like FIXED). Vector is ignored
203 * and it is always edge-triggered.
204 *
205 * 110 Start Up. Sends a special message between
206 * cpus. the vector contains a start-up
207 * address for MP boot protocol.
208 * Always edge triggered. Note: a startup
209 * int is not automatically tried in case of
210 * failure.
211 *
212 * 111 <reserved>
213 *
214 * +-----------+--------10-+--FEDCBA98-+-----------+
215 * 0320 LTIMER | | TM | ---S---- | vector |
216 * 0330 | | | | |
217 * +-----------+--------10-+--FEDCBA98-+-----------+
218 * 0340 LVPCINT | | -M | ---S-MMM | vector |
219 * 0350 LVINT0 | | -M | LRPS-MMM | vector |
220 * 0360 LVINT1 | | -M | LRPS-MMM | vector |
221 * 0370 LVERROR | | -M | -------- | vector |
222 * +-----------+-----------+-----------+-----------+
223 *
224 * T: 1 = periodic, 0 = one-shot
225 *
226 * M: 1 = masked
227 *
228 * L: 1 = level, 0 = edge
229 *
230 * R: For level triggered only, set to 1 when a
231 * level int is accepted, cleared by EOI.
232 *
233 * P: Pin Polarity 0 = Active High, 1 = Active Low
234 *
235 * S: 1 = Send Pending. Interrupt has been injected
236 * but APIC has not yet accepted it.
237 *
238 * MMM 000 = Fixed deliver to cpu according to LVT
239 *
240 * MMM 100 = NMI deliver as an NMI. Always edge
241 *
242 * MMM 111 = ExtInt deliver from 8259, routes INTA
243 * bus cycle to external
244 * controller. Controller is
245 * expected to supply vector.
246 * Always level.
247 *
248 * +-----------+-----------+-----------+-----------+
249 * 0380 TMR_ICR | | | | |
250 * 0390 TMR_CCR | | | | |
251 * 03A0 | | | | |
252 * 03B0 | | | | |
253 * 03C0 | | | | |
254 * 03D0 | | | | |
255 * 03E0 TMR_DCR | | | | |
256 * +-----------+-----------+-----------+-----------+
257 *
258 * Timer control and access registers.
259 *
260 *
261 * NOTE ON EOI: Upon receiving an EOI the APIC clears the highest priority
262 * interrupt in the ISR and selects the next highest priority interrupt
263 * for posting to the CPU. If the interrupt being EOId was level
264 * triggered the APIC will send an EOI to all I/O APICs. For the moment
265 * you can write garbage to the EOI register but for future compatibility
266 * 0 should be written.
267 */
268
269#ifndef LOCORE
270#include <sys/types.h>
271
272#define PAD3 int : 32; int : 32; int : 32
273#define PAD4 int : 32; int : 32; int : 32; int : 32
274
275struct LAPIC {
276 /* reserved */ PAD4;
277 /* reserved */ PAD4;
278 u_int32_t id; PAD3; /* 0020 R/W */
279 u_int32_t version; PAD3; /* 0030 RO */
280 /* reserved */ PAD4;
281 /* reserved */ PAD4;
282 /* reserved */ PAD4;
283 /* reserved */ PAD4;
284 u_int32_t tpr; PAD3;
285 u_int32_t apr; PAD3;
286 u_int32_t ppr; PAD3;
287 u_int32_t eoi; PAD3;
288 /* reserved */ PAD4;
289 u_int32_t ldr; PAD3;
290 u_int32_t dfr; PAD3;
291 u_int32_t svr; PAD3;
292 u_int32_t isr0; PAD3;
293 u_int32_t isr1; PAD3;
294 u_int32_t isr2; PAD3;
295 u_int32_t isr3; PAD3;
296 u_int32_t isr4; PAD3;
297 u_int32_t isr5; PAD3;
298 u_int32_t isr6; PAD3;
299 u_int32_t isr7; PAD3;
300 u_int32_t tmr0; PAD3;
301 u_int32_t tmr1; PAD3;
302 u_int32_t tmr2; PAD3;
303 u_int32_t tmr3; PAD3;
304 u_int32_t tmr4; PAD3;
305 u_int32_t tmr5; PAD3;
306 u_int32_t tmr6; PAD3;
307 u_int32_t tmr7; PAD3;
308 u_int32_t irr0; PAD3;
309 u_int32_t irr1; PAD3;
310 u_int32_t irr2; PAD3;
311 u_int32_t irr3; PAD3;
312 u_int32_t irr4; PAD3;
313 u_int32_t irr5; PAD3;
314 u_int32_t irr6; PAD3;
315 u_int32_t irr7; PAD3;
316 u_int32_t esr; PAD3;
317 /* reserved */ PAD4;
318 /* reserved */ PAD4;
319 /* reserved */ PAD4;
320 /* reserved */ PAD4;
321 /* reserved */ PAD4;
322 /* reserved */ PAD4;
323 /* reserved */ PAD4;
324 u_int32_t icr_lo; PAD3;
325 u_int32_t icr_hi; PAD3;
326 u_int32_t lvt_timer; PAD3;
327 /* reserved */ PAD4;
328 u_int32_t lvt_pcint; PAD3;
329 u_int32_t lvt_lint0; PAD3;
330 u_int32_t lvt_lint1; PAD3;
331 u_int32_t lvt_error; PAD3;
332 u_int32_t icr_timer; PAD3;
333 u_int32_t ccr_timer; PAD3;
334 /* reserved */ PAD4;
335 /* reserved */ PAD4;
336 /* reserved */ PAD4;
337 /* reserved */ PAD4;
338 u_int32_t dcr_timer; PAD3;
339 /* reserved */ PAD4;
340};
341
342typedef struct LAPIC lapic_t;
343
344/******************************************************************************
345 * I/O APIC structure
346 */
347
348struct IOAPIC {
349 u_int32_t ioregsel; PAD3;
350 u_int32_t iowin; PAD3;
351};
352
353typedef struct IOAPIC ioapic_t;
354
355#undef PAD4
356#undef PAD3
357
358#endif /* !LOCORE */
359
360
361/******************************************************************************
362 * various code 'logical' values
363 */
364
365#ifdef GRAB_LOPRIO
366#define LOPRIO_LEVEL 0x00000010 /* TPR of CPU accepting INTs */
367#define ALLHWI_LEVEL 0x00000000 /* TPR of CPU grabbing INTs */
368#endif /** GRAB_LOPRIO */
369
370/*
371 * XXX This code assummes that the reserved field of the
372 * local APIC TPR can be written with all 0s.
373 * This saves quite a few memory accesses.
374 * If the silicon ever changes then things will break!
375 * It affects mplock.s, swtch.s, and possibly other files.
376 */
377#define CHEAP_TPR
378
379
380/******************************************************************************
381 * LOCAL APIC defines
382 */
383
384/* default physical locations of LOCAL (CPU) APICs */
385#define DEFAULT_APIC_BASE 0xfee00000
386
387/* fields in VER */
388#define APIC_VER_VERSION 0x000000ff
389#define APIC_VER_MAXLVT 0x00ff0000
390#define MAXLVTSHIFT 16
391
392/* fields in SVR */
393#define APIC_SVR_VECTOR 0x000000ff
394#define APIC_SVR_VEC_PROG 0x000000f0
395#define APIC_SVR_VEC_FIX 0x0000000f
396#define APIC_SVR_ENABLE 0x00000100
397# define APIC_SVR_SWDIS 0x00000000
398# define APIC_SVR_SWEN 0x00000100
399#define APIC_SVR_FOCUS 0x00000200
400# define APIC_SVR_FEN 0x00000000
401# define APIC_SVR_FDIS 0x00000200
402
403/* fields in TPR */
404#define APIC_TPR_PRIO 0x000000ff
405# define APIC_TPR_INT 0x000000f0
406# define APIC_TPR_SUB 0x0000000f
407
408
409/* fields in ICR_LOW */
410#define APIC_VECTOR_MASK 0x000000ff
411
412#define APIC_DELMODE_MASK 0x00000700
413# define APIC_DELMODE_FIXED 0x00000000
414# define APIC_DELMODE_LOWPRIO 0x00000100
415# define APIC_DELMODE_SMI 0x00000200
416# define APIC_DELMODE_RR 0x00000300
417# define APIC_DELMODE_NMI 0x00000400
418# define APIC_DELMODE_INIT 0x00000500
419# define APIC_DELMODE_STARTUP 0x00000600
420# define APIC_DELMODE_RESV 0x00000700
421
422#define APIC_DESTMODE_MASK 0x00000800
423# define APIC_DESTMODE_PHY 0x00000000
424# define APIC_DESTMODE_LOG 0x00000800
425
426#define APIC_DELSTAT_MASK 0x00001000
427# define APIC_DELSTAT_IDLE 0x00000000
428# define APIC_DELSTAT_PEND 0x00001000
429
430#define APIC_RESV1_MASK 0x00002000
431
432#define APIC_LEVEL_MASK 0x00004000
433# define APIC_LEVEL_DEASSERT 0x00000000
434# define APIC_LEVEL_ASSERT 0x00004000
435
436#define APIC_TRIGMOD_MASK 0x00008000
437# define APIC_TRIGMOD_EDGE 0x00000000
438# define APIC_TRIGMOD_LEVEL 0x00008000
439
440#define APIC_RRSTAT_MASK 0x00030000
441# define APIC_RRSTAT_INVALID 0x00000000
442# define APIC_RRSTAT_INPROG 0x00010000
443# define APIC_RRSTAT_VALID 0x00020000
444# define APIC_RRSTAT_RESV 0x00030000
445
446#define APIC_DEST_MASK 0x000c0000
447# define APIC_DEST_DESTFLD 0x00000000
448# define APIC_DEST_SELF 0x00040000
449# define APIC_DEST_ALLISELF 0x00080000
450# define APIC_DEST_ALLESELF 0x000c0000
451
452#define APIC_RESV2_MASK 0xfff00000
453
454
455/* fields in ICR_HIGH */
456#define APIC_ID_MASK 0xff000000
457
458
459/* fields in LVT1/2 */
460#define APIC_LVT_VECTOR 0x000000ff
461#define APIC_LVT_DM 0x00000700
462# define APIC_LVT_DM_FIXED 0x00000000
463# define APIC_LVT_DM_NMI 0x00000400
464# define APIC_LVT_DM_EXTINT 0x00000700
465#define APIC_LVT_DS 0x00001000
466#define APIC_LVT_IIPP 0x00002000
467#define APIC_LVT_IIPP_INTALO 0x00002000
468#define APIC_LVT_IIPP_INTAHI 0x00000000
469#define APIC_LVT_RIRR 0x00004000
470#define APIC_LVT_TM 0x00008000
471#define APIC_LVT_M 0x00010000
472
473
474/* fields in LVT Timer */
475#define APIC_LVTT_VECTOR 0x000000ff
476#define APIC_LVTT_DS 0x00001000
477#define APIC_LVTT_M 0x00010000
478#define APIC_LVTT_TM 0x00020000
479
480
481/* fields in TDCR */
482#define APIC_TDCR_2 0x00
483#define APIC_TDCR_4 0x01
484#define APIC_TDCR_8 0x02
485#define APIC_TDCR_16 0x03
486#define APIC_TDCR_32 0x08
487#define APIC_TDCR_64 0x09
488#define APIC_TDCR_128 0x0a
489#define APIC_TDCR_1 0x0b
490
491
492/*
493 * fields in IRR
494 * ISA INTerrupts are in bits 16-31 of the 1st IRR register.
495 * these masks DON'T EQUAL the isa IRQs of the same name.
496 */
497#define APIC_IRQ0 0x00000001
498#define APIC_IRQ1 0x00000002
499#define APIC_IRQ2 0x00000004
500#define APIC_IRQ3 0x00000008
501#define APIC_IRQ4 0x00000010
502#define APIC_IRQ5 0x00000020
503#define APIC_IRQ6 0x00000040
504#define APIC_IRQ7 0x00000080
505#define APIC_IRQ8 0x00000100
506#define APIC_IRQ9 0x00000200
507#define APIC_IRQ10 0x00000400
508#define APIC_IRQ11 0x00000800
509#define APIC_IRQ12 0x00001000
510#define APIC_IRQ13 0x00002000
511#define APIC_IRQ14 0x00004000
512#define APIC_IRQ15 0x00008000
513#define APIC_IRQ16 0x00010000
514#define APIC_IRQ17 0x00020000
515#define APIC_IRQ18 0x00040000
516#define APIC_IRQ19 0x00080000
517#define APIC_IRQ20 0x00100000
518#define APIC_IRQ21 0x00200000
519#define APIC_IRQ22 0x00400000
520#define APIC_IRQ23 0x00800000
521
522
523/******************************************************************************
524 * I/O APIC defines
525 */
526
527/* default physical locations of an IO APIC */
528#define DEFAULT_IO_APIC_BASE 0xfec00000
529
530/* window register offset */
531#define IOAPIC_WINDOW 0x10
532
533/* indexes into IO APIC */
534#define IOAPIC_ID 0x00
535#define IOAPIC_VER 0x01
536#define IOAPIC_ARB 0x02
537#define IOAPIC_REDTBL 0x10
538#define IOAPIC_REDTBL0 IOAPIC_REDTBL
539#define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02)
540#define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04)
541#define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06)
542#define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08)
543#define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0a)
544#define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0c)
545#define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0e)
546#define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10)
547#define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12)
548#define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14)
549#define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16)
550#define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18)
551#define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1a)
552#define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1c)
553#define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1e)
554#define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20)
555#define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22)
556#define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24)
557#define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26)
558#define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28)
559#define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2a)
560#define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2c)
561#define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2e)
562
563/* fields in VER */
564#define IOART_VER_VERSION 0x000000ff
565#define IOART_VER_MAXREDIR 0x00ff0000
566#define MAXREDIRSHIFT 16
567
568/*
569 * fields in the IO APIC's redirection table entries
570 */
571#define IOART_DEST APIC_ID_MASK /* broadcast addr: all APICs */
572
573#define IOART_RESV 0x00fe0000 /* reserved */
574
575#define IOART_INTMASK 0x00010000 /* R/W: INTerrupt mask */
576# define IOART_INTMCLR 0x00000000 /* clear, allow INTs */
577# define IOART_INTMSET 0x00010000 /* set, inhibit INTs */
578
579#define IOART_TRGRMOD 0x00008000 /* R/W: trigger mode */
580# define IOART_TRGREDG 0x00000000 /* edge */
581# define IOART_TRGRLVL 0x00008000 /* level */
582
583#define IOART_REM_IRR 0x00004000 /* RO: remote IRR */
584
585#define IOART_INTPOL 0x00002000 /* R/W: INT input pin polarity */
586# define IOART_INTAHI 0x00000000 /* active high */
587# define IOART_INTALO 0x00002000 /* active low */
588
589#define IOART_DELIVS 0x00001000 /* RO: delivery status */
590
591#define IOART_DESTMOD 0x00000800 /* R/W: destination mode */
592# define IOART_DESTPHY 0x00000000 /* physical */
593# define IOART_DESTLOG 0x00000800 /* logical */
594
595#define IOART_DELMOD 0x00000700 /* R/W: delivery mode */
596# define IOART_DELFIXED 0x00000000 /* fixed */
597# define IOART_DELLOPRI 0x00000100 /* lowest priority */
598# define IOART_DELSMI 0x00000200 /* System Management INT */
599# define IOART_DELRSV1 0x00000300 /* reserved */
600# define IOART_DELNMI 0x00000400 /* NMI signal */
601# define IOART_DELINIT 0x00000500 /* INIT signal */
602# define IOART_DELRSV2 0x00000600 /* reserved */
603# define IOART_DELEXINT 0x00000700 /* External INTerrupt */
604
605#define IOART_INTVEC 0x000000ff /* R/W: INTerrupt vector field */
606
607#endif /* _MACHINE_APIC_H_ */
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