| 1 | /* |
| 2 | * Copyright (c) 1996 - 2001 John Hay. |
| 3 | * Copyright (c) 1996 SDL Communications, Inc. |
| 4 | * All rights reserved. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
| 14 | * 3. Neither the name of the author nor the names of any co-contributors |
| 15 | * may be used to endorse or promote products derived from this software |
| 16 | * without specific prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 19 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 24 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 26 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 27 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 28 | * SUCH DAMAGE. |
| 29 | * |
| 30 | * $FreeBSD: src/sys/dev/sr/if_sr.c,v 1.48.2.1 2002/06/17 15:10:58 jhay Exp $ |
| 31 | * $DragonFly: src/sys/dev/netif/sr/if_sr.c,v 1.24 2008/03/07 11:34:19 sephe Exp $ |
| 32 | */ |
| 33 | |
| 34 | /* |
| 35 | * Programming assumptions and other issues. |
| 36 | * |
| 37 | * Only a 16K window will be used. |
| 38 | * |
| 39 | * The descriptors of a DMA channel will fit in a 16K memory window. |
| 40 | * |
| 41 | * The buffers of a transmit DMA channel will fit in a 16K memory window. |
| 42 | * |
| 43 | * When interface is going up, handshaking is set and it is only cleared |
| 44 | * when the interface is down'ed. |
| 45 | * |
| 46 | * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE, |
| 47 | * internal/external clock, etc..... |
| 48 | * |
| 49 | */ |
| 50 | |
| 51 | #include "opt_netgraph.h" |
| 52 | #ifdef NETGRAPH |
| 53 | #include "if_sr.h" |
| 54 | #endif /* NETGRAPH */ |
| 55 | |
| 56 | #include <sys/param.h> |
| 57 | #include <sys/systm.h> |
| 58 | #include <sys/kernel.h> |
| 59 | #include <sys/malloc.h> |
| 60 | #include <sys/mbuf.h> |
| 61 | #include <sys/sockio.h> |
| 62 | #include <sys/socket.h> |
| 63 | #include <sys/thread2.h> |
| 64 | #include <sys/bus.h> |
| 65 | #include <sys/rman.h> |
| 66 | |
| 67 | #include <net/if.h> |
| 68 | #ifdef NETGRAPH |
| 69 | #include <sys/syslog.h> |
| 70 | #else /* NETGRAPH */ |
| 71 | #include <net/if_arp.h> |
| 72 | #include <net/sppp/if_sppp.h> |
| 73 | |
| 74 | #include <net/bpf.h> |
| 75 | #endif /* NETGRAPH */ |
| 76 | |
| 77 | #include <machine/md_var.h> |
| 78 | |
| 79 | #include "../ic_layer/hd64570.h" |
| 80 | #include "if_srregs.h" |
| 81 | |
| 82 | #ifdef NETGRAPH |
| 83 | #include <netgraph/ng_message.h> |
| 84 | #include <netgraph/netgraph.h> |
| 85 | #endif /* NETGRAPH */ |
| 86 | /* #define USE_MODEMCK */ |
| 87 | |
| 88 | #ifndef BUGGY |
| 89 | #define BUGGY 0 |
| 90 | #endif |
| 91 | |
| 92 | #ifndef NETGRAPH |
| 93 | #define PPP_HEADER_LEN 4 |
| 94 | #endif /* NETGRAPH */ |
| 95 | |
| 96 | static int next_sc_unit = 0; |
| 97 | #ifndef NETGRAPH |
| 98 | #ifdef USE_MODEMCK |
| 99 | static int sr_watcher = 0; |
| 100 | #endif |
| 101 | #endif /* NETGRAPH */ |
| 102 | |
| 103 | /* |
| 104 | * Define the software interface for the card... There is one for |
| 105 | * every channel (port). |
| 106 | */ |
| 107 | struct sr_softc { |
| 108 | #ifndef NETGRAPH |
| 109 | struct sppp ifsppp; /* PPP service w/in system */ |
| 110 | #endif /* NETGRAPH */ |
| 111 | struct sr_hardc *hc; /* card-level information */ |
| 112 | |
| 113 | int unit; /* With regard to all sr devices */ |
| 114 | int subunit; /* With regard to this card */ |
| 115 | |
| 116 | struct buf_block { |
| 117 | u_int txdesc; /* DPRAM offset */ |
| 118 | u_int txstart;/* DPRAM offset */ |
| 119 | u_int txend; /* DPRAM offset */ |
| 120 | u_int txtail; /* # of 1st free gran */ |
| 121 | u_int txmax; /* # of free grans */ |
| 122 | u_int txeda; /* err descr addr */ |
| 123 | } block[SR_TX_BLOCKS]; |
| 124 | |
| 125 | char xmit_busy; /* Transmitter is busy */ |
| 126 | char txb_inuse; /* # of tx grans in use */ |
| 127 | u_int txb_new; /* ndx to new buffer */ |
| 128 | u_int txb_next_tx; /* ndx to next gran rdy tx */ |
| 129 | |
| 130 | u_int rxdesc; /* DPRAM offset */ |
| 131 | u_int rxstart; /* DPRAM offset */ |
| 132 | u_int rxend; /* DPRAM offset */ |
| 133 | u_int rxhind; /* ndx to the hd of rx bufrs */ |
| 134 | u_int rxmax; /* # of avail grans */ |
| 135 | |
| 136 | u_int clk_cfg; /* Clock configuration */ |
| 137 | |
| 138 | int scachan; /* channel # on card */ |
| 139 | #ifdef NETGRAPH |
| 140 | int running; /* something is attached so we are running */ |
| 141 | int dcd; /* do we have dcd? */ |
| 142 | /* ---netgraph bits --- */ |
| 143 | char nodename[NG_NODESIZ]; /* store our node name */ |
| 144 | int datahooks; /* number of data hooks attached */ |
| 145 | node_p node; /* netgraph node */ |
| 146 | hook_p hook; /* data hook */ |
| 147 | hook_p debug_hook; |
| 148 | struct ifqueue xmitq_hipri; /* hi-priority transmit queue */ |
| 149 | struct ifqueue xmitq; /* transmit queue */ |
| 150 | int flags; /* state */ |
| 151 | #define SCF_RUNNING 0x01 /* board is active */ |
| 152 | #define SCF_OACTIVE 0x02 /* output is active */ |
| 153 | int out_dog; /* watchdog cycles output count-down */ |
| 154 | struct callout sr_timer; /* timeout(9) handle */ |
| 155 | u_long inbytes, outbytes; /* stats */ |
| 156 | u_long lastinbytes, lastoutbytes; /* a second ago */ |
| 157 | u_long inrate, outrate; /* highest rate seen */ |
| 158 | u_long inlast; /* last input N secs ago */ |
| 159 | u_long out_deficit; /* output since last input */ |
| 160 | u_long oerrors, ierrors[6]; |
| 161 | u_long opackets, ipackets; |
| 162 | #endif /* NETGRAPH */ |
| 163 | }; |
| 164 | |
| 165 | #ifdef NETGRAPH |
| 166 | #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */ |
| 167 | #define QUITE_A_WHILE 300 /* 5 MINUTES */ |
| 168 | #define LOTS_OF_PACKETS 100 |
| 169 | #endif /* NETGRAPH */ |
| 170 | |
| 171 | /* |
| 172 | * Baud Rate table for Sync Mode. |
| 173 | * Each entry consists of 3 elements: |
| 174 | * Baud Rate (x100) , TMC, BR |
| 175 | * |
| 176 | * Baud Rate = FCLK / TMC / 2^BR |
| 177 | * Baud table for Crystal freq. of 9.8304 Mhz |
| 178 | */ |
| 179 | #ifdef N2_TEST_SPEED |
| 180 | struct rate_line { |
| 181 | int target; /* target rate/100 */ |
| 182 | int tmc_reg; /* TMC register value */ |
| 183 | int br_reg; /* BR (BaudRateClk) selector */ |
| 184 | } n2_rates[] = { |
| 185 | /* Baudx100 TMC BR */ |
| 186 | { 3, 128, 8 }, |
| 187 | { 6, 128, 7 }, |
| 188 | { 12, 128, 6 }, |
| 189 | { 24, 128, 5 }, |
| 190 | { 48, 128, 4 }, |
| 191 | { 96, 128, 3 }, |
| 192 | { 192, 128, 2 }, |
| 193 | { 384, 128, 1 }, |
| 194 | { 560, 88, 1 }, |
| 195 | { 640, 77, 1 }, |
| 196 | { 1280, 38, 1 }, |
| 197 | { 2560, 19, 1 }, |
| 198 | { 5120, 10, 1 }, |
| 199 | { 10000, 5, 1 }, |
| 200 | { 15000, 3, 1 }, |
| 201 | { 25000, 2, 1 }, |
| 202 | { 50000, 1, 1 }, |
| 203 | { 0, 0, 0 } |
| 204 | }; |
| 205 | |
| 206 | int sr_test_speed[] = { |
| 207 | N2_TEST_SPEED, |
| 208 | N2_TEST_SPEED |
| 209 | }; |
| 210 | |
| 211 | int etc0vals[] = { |
| 212 | SR_MCR_ETC0, /* ISA channel 0 */ |
| 213 | SR_MCR_ETC1, /* ISA channel 1 */ |
| 214 | SR_FECR_ETC0, /* PCI channel 0 */ |
| 215 | SR_FECR_ETC1 /* PCI channel 1 */ |
| 216 | }; |
| 217 | #endif |
| 218 | |
| 219 | devclass_t sr_devclass; |
| 220 | #ifndef NETGRAPH |
| 221 | DECLARE_DUMMY_MODULE(if_sr); |
| 222 | MODULE_DEPEND(if_sr, sppp, 1, 1, 1); |
| 223 | #else |
| 224 | MODULE_DEPEND(ng_sync_sr, netgraph, NG_ABI_VERSION, NG_ABI_VERSION, NG_ABI_VERSION); |
| 225 | #endif |
| 226 | |
| 227 | static void srintr(void *arg); |
| 228 | static void sr_xmit(struct sr_softc *sc); |
| 229 | #ifndef NETGRAPH |
| 230 | static void srstart(struct ifnet *ifp); |
| 231 | static int srioctl(struct ifnet *ifp, u_long cmd, caddr_t data, |
| 232 | struct ucred *); |
| 233 | static void srwatchdog(struct ifnet *ifp); |
| 234 | #else |
| 235 | static void srstart(struct sr_softc *sc); |
| 236 | static void srwatchdog(struct sr_softc *sc); |
| 237 | #endif /* NETGRAPH */ |
| 238 | static int sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat); |
| 239 | static void sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len); |
| 240 | static void sr_eat_packet(struct sr_softc *sc, int single); |
| 241 | static void sr_get_packets(struct sr_softc *sc); |
| 242 | |
| 243 | static void sr_up(struct sr_softc *sc); |
| 244 | static void sr_down(struct sr_softc *sc); |
| 245 | static void src_init(struct sr_hardc *hc); |
| 246 | static void sr_init_sca(struct sr_hardc *hc); |
| 247 | static void sr_init_msci(struct sr_softc *sc); |
| 248 | static void sr_init_rx_dmac(struct sr_softc *sc); |
| 249 | static void sr_init_tx_dmac(struct sr_softc *sc); |
| 250 | static void sr_dmac_intr(struct sr_hardc *hc, u_char isr); |
| 251 | static void sr_msci_intr(struct sr_hardc *hc, u_char isr); |
| 252 | static void sr_timer_intr(struct sr_hardc *hc, u_char isr); |
| 253 | #ifndef NETGRAPH |
| 254 | #ifdef USE_MODEMCK |
| 255 | static void sr_modemck(void *x); |
| 256 | #endif |
| 257 | #else |
| 258 | static void sr_modemck(struct sr_softc *x); |
| 259 | #endif /* NETGRAPH */ |
| 260 | |
| 261 | #ifdef NETGRAPH |
| 262 | static void ngsr_watchdog_frame(void * arg); |
| 263 | static void ngsr_init(void* ignored); |
| 264 | |
| 265 | static ng_constructor_t ngsr_constructor; |
| 266 | static ng_rcvmsg_t ngsr_rcvmsg; |
| 267 | static ng_shutdown_t ngsr_rmnode; |
| 268 | static ng_newhook_t ngsr_newhook; |
| 269 | /*static ng_findhook_t ngsr_findhook; */ |
| 270 | static ng_connect_t ngsr_connect; |
| 271 | static ng_rcvdata_t ngsr_rcvdata; |
| 272 | static ng_disconnect_t ngsr_disconnect; |
| 273 | |
| 274 | static struct ng_type typestruct = { |
| 275 | NG_VERSION, |
| 276 | NG_SR_NODE_TYPE, |
| 277 | NULL, |
| 278 | ngsr_constructor, |
| 279 | ngsr_rcvmsg, |
| 280 | ngsr_rmnode, |
| 281 | ngsr_newhook, |
| 282 | NULL, |
| 283 | ngsr_connect, |
| 284 | ngsr_rcvdata, |
| 285 | ngsr_rcvdata, |
| 286 | ngsr_disconnect, |
| 287 | NULL |
| 288 | }; |
| 289 | |
| 290 | static int ngsr_done_init = 0; |
| 291 | #endif /* NETGRAPH */ |
| 292 | |
| 293 | /* |
| 294 | * Register the ports on the adapter. |
| 295 | * Fill in the info for each port. |
| 296 | #ifndef NETGRAPH |
| 297 | * Attach each port to sppp and bpf. |
| 298 | #endif |
| 299 | */ |
| 300 | int |
| 301 | sr_attach(device_t device) |
| 302 | { |
| 303 | int intf_sw, pndx; |
| 304 | u_int32_t flags; |
| 305 | u_int fecr, *fecrp; |
| 306 | struct sr_hardc *hc; |
| 307 | struct sr_softc *sc; |
| 308 | #ifndef NETGRAPH |
| 309 | struct ifnet *ifp; |
| 310 | #endif /* NETGRAPH */ |
| 311 | int unit; /* index: channel w/in card */ |
| 312 | |
| 313 | hc = (struct sr_hardc *)device_get_softc(device); |
| 314 | MALLOC(sc, struct sr_softc *, |
| 315 | hc->numports * sizeof(struct sr_softc), |
| 316 | M_DEVBUF, M_WAITOK | M_ZERO); |
| 317 | hc->sc = sc; |
| 318 | |
| 319 | /* |
| 320 | * Get the TX clock direction and configuration. The default is a |
| 321 | * single external clock which is used by RX and TX. |
| 322 | */ |
| 323 | switch(hc->cardtype) { |
| 324 | case SR_CRD_N2: |
| 325 | flags = device_get_flags(device); |
| 326 | #ifdef N2_TEST_SPEED |
| 327 | if (sr_test_speed[0] > 0) |
| 328 | hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK; |
| 329 | else |
| 330 | #endif |
| 331 | if (flags & SR_FLAGS_0_CLK_MSK) |
| 332 | hc->sc[0].clk_cfg = |
| 333 | (flags & SR_FLAGS_0_CLK_MSK) |
| 334 | >> SR_FLAGS_CLK_SHFT; |
| 335 | |
| 336 | if (hc->numports == 2) |
| 337 | #ifdef N2_TEST_SPEED |
| 338 | if (sr_test_speed[1] > 0) |
| 339 | hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK; |
| 340 | else |
| 341 | #endif |
| 342 | if (flags & SR_FLAGS_1_CLK_MSK) |
| 343 | hc->sc[1].clk_cfg = (flags & SR_FLAGS_1_CLK_MSK) |
| 344 | >> (SR_FLAGS_CLK_SHFT + |
| 345 | SR_FLAGS_CLK_CHAN_SHFT); |
| 346 | break; |
| 347 | case SR_CRD_N2PCI: |
| 348 | fecrp = (u_int *)(hc->sca_base + SR_FECR); |
| 349 | fecr = *fecrp; |
| 350 | for (pndx = 0; pndx < hc->numports; pndx++, sc++) { |
| 351 | switch (pndx) { |
| 352 | case 1: |
| 353 | intf_sw = fecr & SR_FECR_ID1 >> SR_FE_ID1_SHFT; |
| 354 | break; |
| 355 | case 0: |
| 356 | default: |
| 357 | intf_sw = fecr & SR_FECR_ID0 >> SR_FE_ID0_SHFT; |
| 358 | } |
| 359 | |
| 360 | #ifdef N2_TEST_SPEED |
| 361 | if (sr_test_speed[pndx] > 0) |
| 362 | sc->clk_cfg = SR_FLAGS_INT_CLK; |
| 363 | else |
| 364 | #endif |
| 365 | switch (intf_sw) { |
| 366 | default: |
| 367 | case SR_FE_ID_RS232: |
| 368 | case SR_FE_ID_HSSI: |
| 369 | case SR_FE_ID_RS422: |
| 370 | case SR_FE_ID_TEST: |
| 371 | break; |
| 372 | |
| 373 | case SR_FE_ID_V35: |
| 374 | sc->clk_cfg = SR_FLAGS_EXT_SEP_CLK; |
| 375 | break; |
| 376 | |
| 377 | case SR_FE_ID_X21: |
| 378 | sc->clk_cfg = SR_FLAGS_EXT_CLK; |
| 379 | break; |
| 380 | } |
| 381 | } |
| 382 | sc = hc->sc; |
| 383 | break; |
| 384 | } |
| 385 | |
| 386 | /* |
| 387 | * Report Card configuration information before we start configuring |
| 388 | * each channel on the card... |
| 389 | */ |
| 390 | kprintf("src%d: %uK RAM (%d mempages) @ %08x-%08x, %u ports.\n", |
| 391 | hc->cunit, hc->memsize / 1024, hc->mempages, |
| 392 | (u_int)hc->mem_start, (u_int)hc->mem_end, hc->numports); |
| 393 | |
| 394 | src_init(hc); |
| 395 | sr_init_sca(hc); |
| 396 | |
| 397 | if (BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq, |
| 398 | 0, srintr, hc, |
| 399 | &hc->intr_cookie, NULL) != 0) |
| 400 | goto errexit; |
| 401 | |
| 402 | /* |
| 403 | * Now configure each port on the card. |
| 404 | */ |
| 405 | for (unit = 0; unit < hc->numports; sc++, unit++) { |
| 406 | sc->hc = hc; |
| 407 | sc->subunit = unit; |
| 408 | sc->unit = next_sc_unit; |
| 409 | next_sc_unit++; |
| 410 | sc->scachan = unit % NCHAN; |
| 411 | |
| 412 | sr_init_rx_dmac(sc); |
| 413 | sr_init_tx_dmac(sc); |
| 414 | sr_init_msci(sc); |
| 415 | |
| 416 | kprintf("sr%d: Adapter %d, port %d.\n", |
| 417 | sc->unit, hc->cunit, sc->subunit); |
| 418 | |
| 419 | #ifndef NETGRAPH |
| 420 | ifp = &sc->ifsppp.pp_if; |
| 421 | ifp->if_softc = sc; |
| 422 | if_initname(ifp, "sr", sc->unit); |
| 423 | ifp->if_mtu = PP_MTU; |
| 424 | ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST; |
| 425 | ifp->if_ioctl = srioctl; |
| 426 | ifp->if_start = srstart; |
| 427 | ifp->if_watchdog = srwatchdog; |
| 428 | |
| 429 | sc->ifsppp.pp_flags = PP_KEEPALIVE; |
| 430 | sppp_attach((struct ifnet *)&sc->ifsppp); |
| 431 | if_attach(ifp, NULL); |
| 432 | |
| 433 | bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN); |
| 434 | #else /* NETGRAPH */ |
| 435 | /* |
| 436 | * we have found a node, make sure our 'type' is availabe. |
| 437 | */ |
| 438 | if (ngsr_done_init == 0) ngsr_init(NULL); |
| 439 | if (ng_make_node_common(&typestruct, &sc->node) != 0) |
| 440 | goto errexit; |
| 441 | sc->node->private = sc; |
| 442 | callout_init(&sc->sr_timer); |
| 443 | sc->xmitq.ifq_maxlen = IFQ_MAXLEN; |
| 444 | sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN; |
| 445 | ksprintf(sc->nodename, "%s%d", NG_SR_NODE_TYPE, sc->unit); |
| 446 | if (ng_name_node(sc->node, sc->nodename)) { |
| 447 | ng_rmnode(sc->node); |
| 448 | ng_unref(sc->node); |
| 449 | return (0); |
| 450 | } |
| 451 | sc->running = 0; |
| 452 | #endif /* NETGRAPH */ |
| 453 | } |
| 454 | |
| 455 | return (0); |
| 456 | |
| 457 | errexit: |
| 458 | sr_deallocate_resources(device); |
| 459 | return (ENXIO); |
| 460 | } |
| 461 | |
| 462 | int |
| 463 | sr_detach(device_t device) |
| 464 | { |
| 465 | device_t parent = device_get_parent(device); |
| 466 | struct sr_hardc *hc = device_get_softc(device); |
| 467 | |
| 468 | if (hc->intr_cookie != NULL) { |
| 469 | if (BUS_TEARDOWN_INTR(parent, device, |
| 470 | hc->res_irq, hc->intr_cookie) != 0) { |
| 471 | kprintf("intr teardown failed.. continuing\n"); |
| 472 | } |
| 473 | hc->intr_cookie = NULL; |
| 474 | } |
| 475 | |
| 476 | /* XXX Stop the DMA. */ |
| 477 | |
| 478 | /* |
| 479 | * deallocate any system resources we may have |
| 480 | * allocated on behalf of this driver. |
| 481 | */ |
| 482 | FREE(hc->sc, M_DEVBUF); |
| 483 | hc->sc = NULL; |
| 484 | hc->mem_start = NULL; |
| 485 | return (sr_deallocate_resources(device)); |
| 486 | } |
| 487 | |
| 488 | int |
| 489 | sr_allocate_irq(device_t device, int rid, u_long size) |
| 490 | { |
| 491 | struct sr_hardc *hc = device_get_softc(device); |
| 492 | |
| 493 | hc->rid_irq = rid; |
| 494 | hc->res_irq = bus_alloc_resource_any(device, SYS_RES_IRQ, |
| 495 | &hc->rid_irq, RF_SHAREABLE|RF_ACTIVE); |
| 496 | if (hc->res_irq == NULL) { |
| 497 | goto errexit; |
| 498 | } |
| 499 | return (0); |
| 500 | |
| 501 | errexit: |
| 502 | sr_deallocate_resources(device); |
| 503 | return (ENXIO); |
| 504 | } |
| 505 | |
| 506 | int |
| 507 | sr_allocate_memory(device_t device, int rid, u_long size) |
| 508 | { |
| 509 | struct sr_hardc *hc = device_get_softc(device); |
| 510 | |
| 511 | hc->rid_memory = rid; |
| 512 | hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY, |
| 513 | &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE); |
| 514 | if (hc->res_memory == NULL) { |
| 515 | goto errexit; |
| 516 | } |
| 517 | return (0); |
| 518 | |
| 519 | errexit: |
| 520 | sr_deallocate_resources(device); |
| 521 | return (ENXIO); |
| 522 | } |
| 523 | |
| 524 | int |
| 525 | sr_allocate_plx_memory(device_t device, int rid, u_long size) |
| 526 | { |
| 527 | struct sr_hardc *hc = device_get_softc(device); |
| 528 | |
| 529 | hc->rid_plx_memory = rid; |
| 530 | hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY, |
| 531 | &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE); |
| 532 | if (hc->res_plx_memory == NULL) { |
| 533 | goto errexit; |
| 534 | } |
| 535 | return (0); |
| 536 | |
| 537 | errexit: |
| 538 | sr_deallocate_resources(device); |
| 539 | return (ENXIO); |
| 540 | } |
| 541 | |
| 542 | int |
| 543 | sr_deallocate_resources(device_t device) |
| 544 | { |
| 545 | struct sr_hardc *hc = device_get_softc(device); |
| 546 | |
| 547 | if (hc->res_irq != 0) { |
| 548 | bus_deactivate_resource(device, SYS_RES_IRQ, |
| 549 | hc->rid_irq, hc->res_irq); |
| 550 | bus_release_resource(device, SYS_RES_IRQ, |
| 551 | hc->rid_irq, hc->res_irq); |
| 552 | hc->res_irq = 0; |
| 553 | } |
| 554 | if (hc->res_memory != 0) { |
| 555 | bus_deactivate_resource(device, SYS_RES_MEMORY, |
| 556 | hc->rid_memory, hc->res_memory); |
| 557 | bus_release_resource(device, SYS_RES_MEMORY, |
| 558 | hc->rid_memory, hc->res_memory); |
| 559 | hc->res_memory = 0; |
| 560 | } |
| 561 | if (hc->res_plx_memory != 0) { |
| 562 | bus_deactivate_resource(device, SYS_RES_MEMORY, |
| 563 | hc->rid_plx_memory, hc->res_plx_memory); |
| 564 | bus_release_resource(device, SYS_RES_MEMORY, |
| 565 | hc->rid_plx_memory, hc->res_plx_memory); |
| 566 | hc->res_plx_memory = 0; |
| 567 | } |
| 568 | return (0); |
| 569 | } |
| 570 | |
| 571 | /* |
| 572 | * N2 Interrupt Service Routine |
| 573 | * |
| 574 | * First figure out which SCA gave the interrupt. |
| 575 | * Process it. |
| 576 | * See if there is other interrupts pending. |
| 577 | * Repeat until there no interrupts remain. |
| 578 | */ |
| 579 | static void |
| 580 | srintr(void *arg) |
| 581 | { |
| 582 | struct sr_hardc *hc = (struct sr_hardc *)arg; |
| 583 | sca_regs *sca = hc->sca; /* MSCI register tree */ |
| 584 | u_char isr0, isr1, isr2; /* interrupt statii captured */ |
| 585 | |
| 586 | #if BUGGY > 1 |
| 587 | kprintf("sr: srintr_hc(hc=%08x)\n", hc); |
| 588 | #endif |
| 589 | |
| 590 | /* |
| 591 | * Since multiple interfaces may share this interrupt, we must loop |
| 592 | * until no interrupts are still pending service. |
| 593 | */ |
| 594 | while (1) { |
| 595 | /* |
| 596 | * Read all three interrupt status registers from the N2 |
| 597 | * card... |
| 598 | */ |
| 599 | isr0 = SRC_GET8(hc->sca_base, sca->isr0); |
| 600 | isr1 = SRC_GET8(hc->sca_base, sca->isr1); |
| 601 | isr2 = SRC_GET8(hc->sca_base, sca->isr2); |
| 602 | |
| 603 | /* |
| 604 | * If all three registers returned 0, we've finished |
| 605 | * processing interrupts from this device, so we can quit |
| 606 | * this loop... |
| 607 | */ |
| 608 | if ((isr0 | isr1 | isr2) == 0) |
| 609 | break; |
| 610 | |
| 611 | #if BUGGY > 2 |
| 612 | kprintf("src%d: srintr_hc isr0 %x, isr1 %x, isr2 %x\n", |
| 613 | #ifndef NETGRAPH |
| 614 | unit, isr0, isr1, isr2); |
| 615 | #else |
| 616 | hc->cunit, isr0, isr1, isr2); |
| 617 | #endif /* NETGRAPH */ |
| 618 | #endif |
| 619 | |
| 620 | /* |
| 621 | * Now we can dispatch the interrupts. Since we don't expect |
| 622 | * either MSCI or timer interrupts, we'll test for DMA |
| 623 | * interrupts first... |
| 624 | */ |
| 625 | if (isr1) /* DMA-initiated interrupt */ |
| 626 | sr_dmac_intr(hc, isr1); |
| 627 | |
| 628 | if (isr0) /* serial part IRQ? */ |
| 629 | sr_msci_intr(hc, isr0); |
| 630 | |
| 631 | if (isr2) /* timer-initiated interrupt */ |
| 632 | sr_timer_intr(hc, isr2); |
| 633 | } |
| 634 | } |
| 635 | |
| 636 | /* |
| 637 | * This will only start the transmitter. It is assumed that the data |
| 638 | * is already there. |
| 639 | * It is normally called from srstart() or sr_dmac_intr(). |
| 640 | */ |
| 641 | static void |
| 642 | sr_xmit(struct sr_softc *sc) |
| 643 | { |
| 644 | u_short cda_value; /* starting descriptor */ |
| 645 | u_short eda_value; /* ending descriptor */ |
| 646 | struct sr_hardc *hc; |
| 647 | #ifndef NETGRAPH |
| 648 | struct ifnet *ifp; /* O/S Network Services */ |
| 649 | #endif /* NETGRAPH */ |
| 650 | dmac_channel *dmac; /* DMA channel registers */ |
| 651 | |
| 652 | #if BUGGY > 0 |
| 653 | kprintf("sr: sr_xmit( sc=%08x)\n", sc); |
| 654 | #endif |
| 655 | |
| 656 | hc = sc->hc; |
| 657 | #ifndef NETGRAPH |
| 658 | ifp = &sc->ifsppp.pp_if; |
| 659 | #endif /* NETGRAPH */ |
| 660 | dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)]; |
| 661 | |
| 662 | /* |
| 663 | * Get the starting and ending addresses of the chain to be |
| 664 | * transmitted and pass these on to the DMA engine on-chip. |
| 665 | */ |
| 666 | cda_value = sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart; |
| 667 | cda_value &= 0x00ffff; |
| 668 | eda_value = sc->block[sc->txb_next_tx].txeda + hc->mem_pstart; |
| 669 | eda_value &= 0x00ffff; |
| 670 | |
| 671 | SRC_PUT16(hc->sca_base, dmac->cda, cda_value); |
| 672 | SRC_PUT16(hc->sca_base, dmac->eda, eda_value); |
| 673 | |
| 674 | /* |
| 675 | * Now we'll let the DMA status register know about this change |
| 676 | */ |
| 677 | SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE); |
| 678 | |
| 679 | sc->xmit_busy = 1; /* mark transmitter busy */ |
| 680 | |
| 681 | #if BUGGY > 2 |
| 682 | kprintf("sr%d: XMIT cda=%04x, eda=%4x, rcda=%08lx\n", |
| 683 | sc->unit, cda_value, eda_value, |
| 684 | sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart); |
| 685 | #endif |
| 686 | |
| 687 | sc->txb_next_tx++; /* update next transmit seq# */ |
| 688 | |
| 689 | if (sc->txb_next_tx == SR_TX_BLOCKS) /* handle wrap... */ |
| 690 | sc->txb_next_tx = 0; |
| 691 | |
| 692 | #ifndef NETGRAPH |
| 693 | /* |
| 694 | * Finally, we'll set a timout (which will start srwatchdog()) |
| 695 | * within the O/S network services layer... |
| 696 | */ |
| 697 | ifp->if_timer = 2; /* Value in seconds. */ |
| 698 | #else |
| 699 | /* |
| 700 | * Don't time out for a while. |
| 701 | */ |
| 702 | sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/ |
| 703 | #endif /* NETGRAPH */ |
| 704 | } |
| 705 | |
| 706 | /* |
| 707 | * This function will be called from the upper level when a user add a |
| 708 | * packet to be send, and from the interrupt handler after a finished |
| 709 | * transmit. |
| 710 | * |
| 711 | * This function only place the data in the oncard buffers. It does not |
| 712 | * start the transmition. sr_xmit() does that. |
| 713 | * |
| 714 | * Transmitter idle state is indicated by the IFF_OACTIVE flag. |
| 715 | * The function that clears that should ensure that the transmitter |
| 716 | * and its DMA is in a "good" idle state. |
| 717 | */ |
| 718 | #ifndef NETGRAPH |
| 719 | static void |
| 720 | srstart(struct ifnet *ifp) |
| 721 | { |
| 722 | struct sr_softc *sc; /* channel control structure */ |
| 723 | #else |
| 724 | static void |
| 725 | srstart(struct sr_softc *sc) |
| 726 | { |
| 727 | #endif /* NETGRAPH */ |
| 728 | struct sr_hardc *hc; /* card control/config block */ |
| 729 | int len; /* total length of a packet */ |
| 730 | int pkts; /* packets placed in DPRAM */ |
| 731 | int tlen; /* working length of pkt */ |
| 732 | u_int i; |
| 733 | struct mbuf *mtx; /* message buffer from O/S */ |
| 734 | u_char *txdata; /* buffer address in DPRAM */ |
| 735 | sca_descriptor *txdesc; /* working descriptor pointr */ |
| 736 | struct buf_block *blkp; |
| 737 | |
| 738 | #ifndef NETGRAPH |
| 739 | #if BUGGY > 0 |
| 740 | kprintf("sr: srstart( ifp=%08x)\n", ifp); |
| 741 | #endif |
| 742 | sc = ifp->if_softc; |
| 743 | if ((ifp->if_flags & IFF_RUNNING) == 0) |
| 744 | return; |
| 745 | #endif /* NETGRAPH */ |
| 746 | hc = sc->hc; |
| 747 | /* |
| 748 | * It is OK to set the memory window outside the loop because all tx |
| 749 | * buffers and descriptors are assumed to be in the same 16K window. |
| 750 | */ |
| 751 | |
| 752 | /* |
| 753 | * Loop to place packets into DPRAM. |
| 754 | * |
| 755 | * We stay in this loop until there is nothing in |
| 756 | * the TX queue left or the tx buffers are full. |
| 757 | */ |
| 758 | top_srstart: |
| 759 | |
| 760 | /* |
| 761 | * See if we have space for more packets. |
| 762 | */ |
| 763 | if (sc->txb_inuse == SR_TX_BLOCKS) { /* out of space? */ |
| 764 | #ifndef NETGRAPH |
| 765 | ifp->if_flags |= IFF_OACTIVE; /* yes, mark active */ |
| 766 | #else |
| 767 | /*ifp->if_flags |= IFF_OACTIVE;*/ /* yes, mark active */ |
| 768 | #endif /* NETGRAPH */ |
| 769 | |
| 770 | #if BUGGY > 9 |
| 771 | kprintf("sr%d.srstart: sc->txb_inuse=%d; DPRAM full...\n", |
| 772 | sc->unit, sc->txb_inuse); |
| 773 | #endif |
| 774 | return; |
| 775 | } |
| 776 | /* |
| 777 | * OK, the card can take more traffic. Let's see if there's any |
| 778 | * pending from the system... |
| 779 | * |
| 780 | * NOTE: |
| 781 | * The architecture of the networking interface doesn't |
| 782 | * actually call us like 'write()', providing an address. We get |
| 783 | * started, a lot like a disk strategy routine, and we actually call |
| 784 | * back out to the system to get traffic to send... |
| 785 | * |
| 786 | * NOTE: |
| 787 | * If we were gonna run through another layer, we would use a |
| 788 | * dispatch table to select the service we're getting a packet |
| 789 | * from... |
| 790 | */ |
| 791 | #ifndef NETGRAPH |
| 792 | mtx = sppp_dequeue(ifp); |
| 793 | #else /* NETGRAPH */ |
| 794 | IF_DEQUEUE(&sc->xmitq_hipri, mtx); |
| 795 | if (mtx == NULL) { |
| 796 | IF_DEQUEUE(&sc->xmitq, mtx); |
| 797 | } |
| 798 | #endif /* NETGRAPH */ |
| 799 | if (!mtx) { |
| 800 | return; |
| 801 | } |
| 802 | /* |
| 803 | * OK, we got a packet from the network services of the O/S. Now we |
| 804 | * can move it into the DPRAM (under control of the descriptors) and |
| 805 | * fire it off... |
| 806 | */ |
| 807 | pkts = 0; |
| 808 | i = 0; /* counts # of granules used */ |
| 809 | |
| 810 | blkp = &sc->block[sc->txb_new]; /* address of free granule */ |
| 811 | txdesc = (sca_descriptor *) |
| 812 | (hc->mem_start + (blkp->txdesc & hc->winmsk)); |
| 813 | |
| 814 | txdata = (u_char *)(hc->mem_start |
| 815 | + (blkp->txstart & hc->winmsk)); |
| 816 | |
| 817 | /* |
| 818 | * Now we'll try to install as many packets as possible into the |
| 819 | * card's DP RAM buffers. |
| 820 | */ |
| 821 | for (;;) { /* perform actual copy of packet */ |
| 822 | len = mtx->m_pkthdr.len; /* length of message */ |
| 823 | |
| 824 | #if BUGGY > 1 |
| 825 | kprintf("sr%d.srstart: mbuf @ %08lx, %d bytes\n", |
| 826 | sc->unit, mtx, len); |
| 827 | #endif |
| 828 | |
| 829 | #ifndef NETGRAPH |
| 830 | BPF_MTAP(ifp, mtx); |
| 831 | #else /* NETGRAPH */ |
| 832 | sc->outbytes += len; |
| 833 | #endif /* NETGRAPH */ |
| 834 | |
| 835 | /* |
| 836 | * We can perform a straight copy because the tranmit |
| 837 | * buffers won't wrap. |
| 838 | */ |
| 839 | m_copydata(mtx, 0, len, txdata); |
| 840 | |
| 841 | /* |
| 842 | * Now we know how big the message is gonna be. We must now |
| 843 | * construct the descriptors to drive this message out... |
| 844 | */ |
| 845 | tlen = len; |
| 846 | while (tlen > SR_BUF_SIZ) { /* loop for full granules */ |
| 847 | txdesc->stat = 0; /* reset bits */ |
| 848 | txdesc->len = SR_BUF_SIZ; /* size of granule */ |
| 849 | tlen -= SR_BUF_SIZ; |
| 850 | |
| 851 | txdesc++; /* move to next dscr */ |
| 852 | txdata += SR_BUF_SIZ; /* adjust data addr */ |
| 853 | i++; |
| 854 | } |
| 855 | |
| 856 | /* |
| 857 | * This section handles the setting of the final piece of a |
| 858 | * message. |
| 859 | */ |
| 860 | txdesc->stat = SCA_DESC_EOM; |
| 861 | txdesc->len = tlen; |
| 862 | pkts++; |
| 863 | |
| 864 | /* |
| 865 | * prepare for subsequent packets (if any) |
| 866 | */ |
| 867 | txdesc++; |
| 868 | txdata += SR_BUF_SIZ; /* next mem granule */ |
| 869 | i++; /* count of granules */ |
| 870 | |
| 871 | /* |
| 872 | * OK, we've now placed the message into the DPRAM where it |
| 873 | * can be transmitted. We'll now release the message memory |
| 874 | * and update the statistics... |
| 875 | */ |
| 876 | m_freem(mtx); |
| 877 | #ifndef NETGRAPH |
| 878 | ++sc->ifsppp.pp_if.if_opackets; |
| 879 | #else /* NETGRAPH */ |
| 880 | sc->opackets++; |
| 881 | #endif /* NETGRAPH */ |
| 882 | |
| 883 | /* |
| 884 | * Check if we have space for another packet. XXX This is |
| 885 | * hardcoded. A packet can't be larger than 3 buffers (3 x |
| 886 | * 512). |
| 887 | */ |
| 888 | if ((i + 3) >= blkp->txmax) { /* enough remains? */ |
| 889 | #if BUGGY > 9 |
| 890 | kprintf("sr%d.srstart: i=%d (%d pkts); card full.\n", |
| 891 | sc->unit, i, pkts); |
| 892 | #endif |
| 893 | break; |
| 894 | } |
| 895 | /* |
| 896 | * We'll pull the next message to be sent (if any) |
| 897 | */ |
| 898 | #ifndef NETGRAPH |
| 899 | mtx = sppp_dequeue(ifp); |
| 900 | #else /* NETGRAPH */ |
| 901 | IF_DEQUEUE(&sc->xmitq_hipri, mtx); |
| 902 | if (mtx == NULL) { |
| 903 | IF_DEQUEUE(&sc->xmitq, mtx); |
| 904 | } |
| 905 | #endif /* NETGRAPH */ |
| 906 | if (!mtx) { /* no message? We're done! */ |
| 907 | #if BUGGY > 9 |
| 908 | kprintf("sr%d.srstart: pending=0, pkts=%d\n", |
| 909 | sc->unit, pkts); |
| 910 | #endif |
| 911 | break; |
| 912 | } |
| 913 | } |
| 914 | |
| 915 | blkp->txtail = i; /* record next free granule */ |
| 916 | |
| 917 | /* |
| 918 | * Mark the last descriptor, so that the SCA know where to stop. |
| 919 | */ |
| 920 | txdesc--; /* back up to last descriptor in list */ |
| 921 | txdesc->stat |= SCA_DESC_EOT; /* mark as end of list */ |
| 922 | |
| 923 | /* |
| 924 | * Now we'll reset the transmit granule's descriptor address so we |
| 925 | * can record this in the structure and fire it off w/ the DMA |
| 926 | * processor of the serial chip... |
| 927 | */ |
| 928 | txdesc = (sca_descriptor *)blkp->txdesc; |
| 929 | blkp->txeda = (u_short)((u_int)&txdesc[i]); |
| 930 | |
| 931 | sc->txb_inuse++; /* update inuse status */ |
| 932 | sc->txb_new++; /* new traffic wuz added */ |
| 933 | |
| 934 | if (sc->txb_new == SR_TX_BLOCKS) |
| 935 | sc->txb_new = 0; |
| 936 | |
| 937 | /* |
| 938 | * If the tranmitter wasn't marked as "busy" we will force it to be |
| 939 | * started... |
| 940 | */ |
| 941 | if (sc->xmit_busy == 0) { |
| 942 | sr_xmit(sc); |
| 943 | #if BUGGY > 9 |
| 944 | kprintf("sr%d.srstart: called sr_xmit()\n", sc->unit); |
| 945 | #endif |
| 946 | } |
| 947 | goto top_srstart; |
| 948 | } |
| 949 | |
| 950 | #ifndef NETGRAPH |
| 951 | /* |
| 952 | * Handle ioctl's at the device level, though we *will* call up |
| 953 | * a layer... |
| 954 | */ |
| 955 | #if BUGGY > 2 |
| 956 | static int bug_splats[] = {0, 0, 0, 0, 0, 0, 0, 0}; |
| 957 | #endif |
| 958 | |
| 959 | static int |
| 960 | srioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) |
| 961 | { |
| 962 | int error, was_up, should_be_up; |
| 963 | struct sr_softc *sc = ifp->if_softc; |
| 964 | |
| 965 | #if BUGGY > 0 |
| 966 | kprintf("%s: srioctl(ifp=%08x, cmd=%08x, data=%08x)\n", |
| 967 | ifp->if_xname, ifp, cmd, data); |
| 968 | #endif |
| 969 | |
| 970 | was_up = ifp->if_flags & IFF_RUNNING; |
| 971 | |
| 972 | error = sppp_ioctl(ifp, cmd, data); |
| 973 | |
| 974 | #if BUGGY > 1 |
| 975 | kprintf("%s: ioctl: ifsppp.pp_flags = %08x, if_flags %08x.\n", |
| 976 | ifp->if_xname, ((struct sppp *)ifp)->pp_flags, ifp->if_flags); |
| 977 | #endif |
| 978 | |
| 979 | if (error) |
| 980 | return error; |
| 981 | |
| 982 | if ((cmd != SIOCSIFFLAGS) && (cmd != SIOCSIFADDR)) { |
| 983 | #if BUGGY > 2 |
| 984 | if (bug_splats[sc->unit]++ < 2) { |
| 985 | kprintf("sr(%d).if_addrheads = %08x\n", |
| 986 | sc->unit, ifp->if_addrheads); |
| 987 | kprintf("sr(%d).if_bpf = %08x\n", |
| 988 | sc->unit, ifp->if_bpf); |
| 989 | kprintf("sr(%d).if_init = %08x\n", |
| 990 | sc->unit, ifp->if_init); |
| 991 | kprintf("sr(%d).if_output = %08x\n", |
| 992 | sc->unit, ifp->if_output); |
| 993 | kprintf("sr(%d).if_start = %08x\n", |
| 994 | sc->unit, ifp->if_start); |
| 995 | kprintf("sr(%d).if_done = %08x\n", |
| 996 | sc->unit, ifp->if_done); |
| 997 | kprintf("sr(%d).if_ioctl = %08x\n", |
| 998 | sc->unit, ifp->if_ioctl); |
| 999 | kprintf("sr(%d).if_reset = %08x\n", |
| 1000 | sc->unit, ifp->if_reset); |
| 1001 | kprintf("sr(%d).if_watchdog = %08x\n", |
| 1002 | sc->unit, ifp->if_watchdog); |
| 1003 | } |
| 1004 | #endif |
| 1005 | return 0; |
| 1006 | } |
| 1007 | |
| 1008 | crit_enter(); |
| 1009 | |
| 1010 | should_be_up = ifp->if_flags & IFF_RUNNING; |
| 1011 | |
| 1012 | if (!was_up && should_be_up) { |
| 1013 | /* |
| 1014 | * Interface should be up -- start it. |
| 1015 | */ |
| 1016 | sr_up(sc); |
| 1017 | srstart(ifp); |
| 1018 | |
| 1019 | /* |
| 1020 | * XXX Clear the IFF_UP flag so that the link will only go |
| 1021 | * up after sppp lcp and ipcp negotiation. |
| 1022 | */ |
| 1023 | /* ifp->if_flags &= ~IFF_UP; */ |
| 1024 | } else if (was_up && !should_be_up) { |
| 1025 | /* |
| 1026 | * Interface should be down -- stop it. |
| 1027 | */ |
| 1028 | sr_down(sc); |
| 1029 | sppp_flush(ifp); |
| 1030 | } |
| 1031 | |
| 1032 | crit_exit(); |
| 1033 | |
| 1034 | return 0; |
| 1035 | } |
| 1036 | #endif /* NETGRAPH */ |
| 1037 | |
| 1038 | /* |
| 1039 | * This is to catch lost tx interrupts. |
| 1040 | */ |
| 1041 | static void |
| 1042 | #ifndef NETGRAPH |
| 1043 | srwatchdog(struct ifnet *ifp) |
| 1044 | #else |
| 1045 | srwatchdog(struct sr_softc *sc) |
| 1046 | #endif /* NETGRAPH */ |
| 1047 | { |
| 1048 | int got_st0, got_st1, got_st3, got_dsr; |
| 1049 | #ifndef NETGRAPH |
| 1050 | struct sr_softc *sc = ifp->if_softc; |
| 1051 | #endif /* NETGRAPH */ |
| 1052 | struct sr_hardc *hc = sc->hc; |
| 1053 | msci_channel *msci = &hc->sca->msci[sc->scachan]; |
| 1054 | dmac_channel *dmac = &sc->hc->sca->dmac[sc->scachan]; |
| 1055 | |
| 1056 | #if BUGGY > 0 |
| 1057 | #ifndef NETGRAPH |
| 1058 | kprintf("srwatchdog(unit=%d)\n", unit); |
| 1059 | #else |
| 1060 | kprintf("srwatchdog(unit=%d)\n", sc->unit); |
| 1061 | #endif /* NETGRAPH */ |
| 1062 | #endif |
| 1063 | |
| 1064 | #ifndef NETGRAPH |
| 1065 | if (!(ifp->if_flags & IFF_RUNNING)) |
| 1066 | return; |
| 1067 | |
| 1068 | ifp->if_oerrors++; /* update output error count */ |
| 1069 | #else /* NETGRAPH */ |
| 1070 | sc->oerrors++; /* update output error count */ |
| 1071 | #endif /* NETGRAPH */ |
| 1072 | |
| 1073 | got_st0 = SRC_GET8(hc->sca_base, msci->st0); |
| 1074 | got_st1 = SRC_GET8(hc->sca_base, msci->st1); |
| 1075 | got_st3 = SRC_GET8(hc->sca_base, msci->st3); |
| 1076 | got_dsr = SRC_GET8(hc->sca_base, dmac->dsr); |
| 1077 | |
| 1078 | #ifndef NETGRAPH |
| 1079 | #if 0 |
| 1080 | if (ifp->if_flags & IFF_DEBUG) |
| 1081 | #endif |
| 1082 | kprintf("sr%d: transmit failed, " |
| 1083 | #else /* NETGRAPH */ |
| 1084 | kprintf("sr%d: transmit failed, " |
| 1085 | #endif /* NETGRAPH */ |
| 1086 | "ST0 %02x, ST1 %02x, ST3 %02x, DSR %02x.\n", |
| 1087 | sc->unit, |
| 1088 | got_st0, got_st1, got_st3, got_dsr); |
| 1089 | |
| 1090 | if (SRC_GET8(hc->sca_base, msci->st1) & SCA_ST1_UDRN) { |
| 1091 | SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXABORT); |
| 1092 | SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE); |
| 1093 | SRC_PUT8(hc->sca_base, msci->st1, SCA_ST1_UDRN); |
| 1094 | } |
| 1095 | sc->xmit_busy = 0; |
| 1096 | #ifndef NETGRAPH |
| 1097 | ifp->if_flags &= ~IFF_OACTIVE; |
| 1098 | #else |
| 1099 | /*ifp->if_flags &= ~IFF_OACTIVE; */ |
| 1100 | #endif /* NETGRAPH */ |
| 1101 | |
| 1102 | if (sc->txb_inuse && --sc->txb_inuse) |
| 1103 | sr_xmit(sc); |
| 1104 | |
| 1105 | #ifndef NETGRAPH |
| 1106 | srstart(ifp); /* restart transmitter */ |
| 1107 | #else |
| 1108 | srstart(sc); /* restart transmitter */ |
| 1109 | #endif /* NETGRAPH */ |
| 1110 | } |
| 1111 | |
| 1112 | static void |
| 1113 | sr_up(struct sr_softc *sc) |
| 1114 | { |
| 1115 | u_int *fecrp; |
| 1116 | struct sr_hardc *hc = sc->hc; |
| 1117 | sca_regs *sca = hc->sca; |
| 1118 | msci_channel *msci = &sca->msci[sc->scachan]; |
| 1119 | |
| 1120 | #if BUGGY > 0 |
| 1121 | kprintf("sr_up(sc=%08x)\n", sc); |
| 1122 | #endif |
| 1123 | |
| 1124 | /* |
| 1125 | * Enable transmitter and receiver. Raise DTR and RTS. Enable |
| 1126 | * interrupts. |
| 1127 | * |
| 1128 | * XXX What about using AUTO mode in msci->md0 ??? |
| 1129 | */ |
| 1130 | SRC_PUT8(hc->sca_base, msci->ctl, |
| 1131 | SRC_GET8(hc->sca_base, msci->ctl) & ~SCA_CTL_RTS); |
| 1132 | |
| 1133 | if (sc->scachan == 0) |
| 1134 | switch (hc->cardtype) { |
| 1135 | case SR_CRD_N2PCI: |
| 1136 | fecrp = (u_int *)(hc->sca_base + SR_FECR); |
| 1137 | *fecrp &= ~SR_FECR_DTR0; |
| 1138 | break; |
| 1139 | } |
| 1140 | else |
| 1141 | switch (hc->cardtype) { |
| 1142 | case SR_CRD_N2PCI: |
| 1143 | fecrp = (u_int *)(hc->sca_base + SR_FECR); |
| 1144 | *fecrp &= ~SR_FECR_DTR1; |
| 1145 | break; |
| 1146 | } |
| 1147 | |
| 1148 | if (sc->scachan == 0) { |
| 1149 | SRC_PUT8(hc->sca_base, sca->ier0, |
| 1150 | SRC_GET8(hc->sca_base, sca->ier0) | 0x000F); |
| 1151 | SRC_PUT8(hc->sca_base, sca->ier1, |
| 1152 | SRC_GET8(hc->sca_base, sca->ier1) | 0x000F); |
| 1153 | } else { |
| 1154 | SRC_PUT8(hc->sca_base, sca->ier0, |
| 1155 | SRC_GET8(hc->sca_base, sca->ier0) | 0x00F0); |
| 1156 | SRC_PUT8(hc->sca_base, sca->ier1, |
| 1157 | SRC_GET8(hc->sca_base, sca->ier1) | 0x00F0); |
| 1158 | } |
| 1159 | |
| 1160 | SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXENABLE); |
| 1161 | DELAY(1000); /* XXX slow it down a bit. */ |
| 1162 | SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE); |
| 1163 | |
| 1164 | #ifndef NETGRAPH |
| 1165 | #ifdef USE_MODEMCK |
| 1166 | if (sr_watcher == 0) |
| 1167 | sr_modemck(NULL); |
| 1168 | #endif |
| 1169 | #else /* NETGRAPH */ |
| 1170 | callout_reset(&sc->sr_timer, hz, ngsr_watchdog_frame, sc); |
| 1171 | sc->running = 1; |
| 1172 | #endif /* NETGRAPH */ |
| 1173 | } |
| 1174 | |
| 1175 | static void |
| 1176 | sr_down(struct sr_softc *sc) |
| 1177 | { |
| 1178 | u_int *fecrp; |
| 1179 | struct sr_hardc *hc = sc->hc; |
| 1180 | sca_regs *sca = hc->sca; |
| 1181 | msci_channel *msci = &sca->msci[sc->scachan]; |
| 1182 | |
| 1183 | #if BUGGY > 0 |
| 1184 | kprintf("sr_down(sc=%08x)\n", sc); |
| 1185 | #endif |
| 1186 | #ifdef NETGRAPH |
| 1187 | callout_stop(&sc->sr_timer); |
| 1188 | sc->running = 0; |
| 1189 | #endif /* NETGRAPH */ |
| 1190 | |
| 1191 | /* |
| 1192 | * Disable transmitter and receiver. Lower DTR and RTS. Disable |
| 1193 | * interrupts. |
| 1194 | */ |
| 1195 | SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXDISABLE); |
| 1196 | DELAY(1000); /* XXX slow it down a bit. */ |
| 1197 | SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXDISABLE); |
| 1198 | |
| 1199 | SRC_PUT8(hc->sca_base, msci->ctl, |
| 1200 | SRC_GET8(hc->sca_base, msci->ctl) | SCA_CTL_RTS); |
| 1201 | |
| 1202 | if (sc->scachan == 0) |
| 1203 | switch (hc->cardtype) { |
| 1204 | case SR_CRD_N2PCI: |
| 1205 | fecrp = (u_int *)(hc->sca_base + SR_FECR); |
| 1206 | *fecrp |= SR_FECR_DTR0; |
| 1207 | break; |
| 1208 | } |
| 1209 | else |
| 1210 | switch (hc->cardtype) { |
| 1211 | case SR_CRD_N2PCI: |
| 1212 | fecrp = (u_int *)(hc->sca_base + SR_FECR); |
| 1213 | *fecrp |= SR_FECR_DTR1; |
| 1214 | break; |
| 1215 | } |
| 1216 | |
| 1217 | if (sc->scachan == 0) { |
| 1218 | SRC_PUT8(hc->sca_base, sca->ier0, |
| 1219 | SRC_GET8(hc->sca_base, sca->ier0) & ~0x0F); |
| 1220 | SRC_PUT8(hc->sca_base, sca->ier1, |
| 1221 | SRC_GET8(hc->sca_base, sca->ier1) & ~0x0F); |
| 1222 | } else { |
| 1223 | SRC_PUT8(hc->sca_base, sca->ier0, |
| 1224 | SRC_GET8(hc->sca_base, sca->ier0) & ~0xF0); |
| 1225 | SRC_PUT8(hc->sca_base, sca->ier1, |
| 1226 | SRC_GET8(hc->sca_base, sca->ier1) & ~0xF0); |
| 1227 | } |
| 1228 | } |
| 1229 | |
| 1230 | /* |
| 1231 | * Initialize the card, allocate memory for the sr_softc structures |
| 1232 | * and fill in the pointers. |
| 1233 | */ |
| 1234 | static void |
| 1235 | src_init(struct sr_hardc *hc) |
| 1236 | { |
| 1237 | struct sr_softc *sc = hc->sc; |
| 1238 | int x; |
| 1239 | u_int chanmem; |
| 1240 | u_int bufmem; |
| 1241 | u_int next; |
| 1242 | u_int descneeded; |
| 1243 | |
| 1244 | #if BUGGY > 0 |
| 1245 | kprintf("src_init(hc=%08x)\n", hc); |
| 1246 | #endif |
| 1247 | |
| 1248 | chanmem = hc->memsize / hc->numports; |
| 1249 | next = 0; |
| 1250 | |
| 1251 | for (x = 0; x < hc->numports; x++, sc++) { |
| 1252 | int blk; |
| 1253 | |
| 1254 | for (blk = 0; blk < SR_TX_BLOCKS; blk++) { |
| 1255 | sc->block[blk].txdesc = next; |
| 1256 | bufmem = (16 * 1024) / SR_TX_BLOCKS; |
| 1257 | descneeded = bufmem / SR_BUF_SIZ; |
| 1258 | |
| 1259 | sc->block[blk].txstart = sc->block[blk].txdesc |
| 1260 | + ((((descneeded * sizeof(sca_descriptor)) |
| 1261 | / SR_BUF_SIZ) + 1) |
| 1262 | * SR_BUF_SIZ); |
| 1263 | |
| 1264 | sc->block[blk].txend = next + bufmem; |
| 1265 | sc->block[blk].txmax = |
| 1266 | (sc->block[blk].txend - sc->block[blk].txstart) |
| 1267 | / SR_BUF_SIZ; |
| 1268 | next += bufmem; |
| 1269 | |
| 1270 | #if BUGGY > 2 |
| 1271 | kprintf("sr%d: blk %d: txdesc %08x, txstart %08x\n", |
| 1272 | sc->unit, blk, |
| 1273 | sc->block[blk].txdesc, sc->block[blk].txstart); |
| 1274 | #endif |
| 1275 | } |
| 1276 | |
| 1277 | sc->rxdesc = next; |
| 1278 | bufmem = chanmem - (bufmem * SR_TX_BLOCKS); |
| 1279 | descneeded = bufmem / SR_BUF_SIZ; |
| 1280 | sc->rxstart = sc->rxdesc + |
| 1281 | ((((descneeded * sizeof(sca_descriptor)) / |
| 1282 | SR_BUF_SIZ) + 1) * SR_BUF_SIZ); |
| 1283 | sc->rxend = next + bufmem; |
| 1284 | sc->rxmax = (sc->rxend - sc->rxstart) / SR_BUF_SIZ; |
| 1285 | next += bufmem; |
| 1286 | } |
| 1287 | } |
| 1288 | |
| 1289 | /* |
| 1290 | * The things done here are channel independent. |
| 1291 | * |
| 1292 | * Configure the sca waitstates. |
| 1293 | * Configure the global interrupt registers. |
| 1294 | * Enable master dma enable. |
| 1295 | */ |
| 1296 | static void |
| 1297 | sr_init_sca(struct sr_hardc *hc) |
| 1298 | { |
| 1299 | sca_regs *sca = hc->sca; |
| 1300 | |
| 1301 | #if BUGGY > 0 |
| 1302 | kprintf("sr_init_sca(hc=%08x)\n", hc); |
| 1303 | #endif |
| 1304 | |
| 1305 | /* |
| 1306 | * Do the wait registers. Set everything to 0 wait states. |
| 1307 | */ |
| 1308 | SRC_PUT8(hc->sca_base, sca->pabr0, 0); |
| 1309 | SRC_PUT8(hc->sca_base, sca->pabr1, 0); |
| 1310 | SRC_PUT8(hc->sca_base, sca->wcrl, 0); |
| 1311 | SRC_PUT8(hc->sca_base, sca->wcrm, 0); |
| 1312 | SRC_PUT8(hc->sca_base, sca->wcrh, 0); |
| 1313 | |
| 1314 | /* |
| 1315 | * Configure the interrupt registers. Most are cleared until the |
| 1316 | * interface is configured. |
| 1317 | */ |
| 1318 | SRC_PUT8(hc->sca_base, sca->ier0, 0x00); /* MSCI interrupts. */ |
| 1319 | SRC_PUT8(hc->sca_base, sca->ier1, 0x00); /* DMAC interrupts */ |
| 1320 | SRC_PUT8(hc->sca_base, sca->ier2, 0x00); /* TIMER interrupts. */ |
| 1321 | SRC_PUT8(hc->sca_base, sca->itcr, 0x00); /* Use ivr and no intr |
| 1322 | * ack */ |
| 1323 | SRC_PUT8(hc->sca_base, sca->ivr, 0x40); /* Interrupt vector. */ |
| 1324 | SRC_PUT8(hc->sca_base, sca->imvr, 0x40); |
| 1325 | |
| 1326 | /* |
| 1327 | * Configure the timers. XXX Later |
| 1328 | */ |
| 1329 | |
| 1330 | /* |
| 1331 | * Set the DMA channel priority to rotate between all four channels. |
| 1332 | * |
| 1333 | * Enable all dma channels. |
| 1334 | */ |
| 1335 | SRC_PUT8(hc->sca_base, sca->pcr, SCA_PCR_PR2); |
| 1336 | SRC_PUT8(hc->sca_base, sca->dmer, SCA_DMER_EN); |
| 1337 | } |
| 1338 | |
| 1339 | /* |
| 1340 | * Configure the msci |
| 1341 | * |
| 1342 | * NOTE: The serial port configuration is hardcoded at the moment. |
| 1343 | */ |
| 1344 | static void |
| 1345 | sr_init_msci(struct sr_softc *sc) |
| 1346 | { |
| 1347 | int portndx; /* on-board port number */ |
| 1348 | u_int *fecrp; /* pointer for PCI's MCR i/o */ |
| 1349 | struct sr_hardc *hc = sc->hc; |
| 1350 | msci_channel *msci = &hc->sca->msci[sc->scachan]; |
| 1351 | #ifdef N2_TEST_SPEED |
| 1352 | int br_v; /* contents for BR divisor */ |
| 1353 | int etcndx; /* index into ETC table */ |
| 1354 | int fifo_v, gotspeed; /* final tabled speed found */ |
| 1355 | int tmc_v; /* timer control register */ |
| 1356 | int wanted; /* speed (bitrate) wanted... */ |
| 1357 | struct rate_line *rtp; |
| 1358 | #endif |
| 1359 | |
| 1360 | portndx = sc->scachan; |
| 1361 | |
| 1362 | #if BUGGY > 0 |
| 1363 | kprintf("sr: sr_init_msci( sc=%08x)\n", sc); |
| 1364 | #endif |
| 1365 | |
| 1366 | SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RESET); |
| 1367 | SRC_PUT8(hc->sca_base, msci->md0, SCA_MD0_CRC_1 | |
| 1368 | SCA_MD0_CRC_CCITT | |
| 1369 | SCA_MD0_CRC_ENABLE | |
| 1370 | SCA_MD0_MODE_HDLC); |
| 1371 | SRC_PUT8(hc->sca_base, msci->md1, SCA_MD1_NOADDRCHK); |
| 1372 | SRC_PUT8(hc->sca_base, msci->md2, SCA_MD2_DUPLEX | SCA_MD2_NRZ); |
| 1373 | |
| 1374 | /* |
| 1375 | * According to the manual I should give a reset after changing the |
| 1376 | * mode registers. |
| 1377 | */ |
| 1378 | SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXRESET); |
| 1379 | SRC_PUT8(hc->sca_base, msci->ctl, SCA_CTL_IDLPAT | |
| 1380 | SCA_CTL_UDRNC | |
| 1381 | SCA_CTL_RTS); |
| 1382 | |
| 1383 | /* |
| 1384 | * XXX Later we will have to support different clock settings. |
| 1385 | */ |
| 1386 | switch (sc->clk_cfg) { |
| 1387 | default: |
| 1388 | #if BUGGY > 0 |
| 1389 | kprintf("sr%: clk_cfg=%08x, selected default clock.\n", |
| 1390 | portndx, sc->clk_cfg); |
| 1391 | #endif |
| 1392 | /* FALLTHROUGH */ |
| 1393 | case SR_FLAGS_EXT_CLK: |
| 1394 | /* |
| 1395 | * For now all interfaces are programmed to use the RX clock |
| 1396 | * for the TX clock. |
| 1397 | */ |
| 1398 | |
| 1399 | #if BUGGY > 0 |
| 1400 | kprintf("sr%d: External Clock Selected.\n", portndx); |
| 1401 | #endif |
| 1402 | |
| 1403 | SRC_PUT8(hc->sca_base, msci->rxs, |
| 1404 | SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1); |
| 1405 | SRC_PUT8(hc->sca_base, msci->txs, |
| 1406 | SCA_TXS_CLK_RX | SCA_TXS_DIV1); |
| 1407 | break; |
| 1408 | |
| 1409 | case SR_FLAGS_EXT_SEP_CLK: |
| 1410 | #if BUGGY > 0 |
| 1411 | kprintf("sr%d: Split Clocking Selected.\n", portndx); |
| 1412 | #endif |
| 1413 | |
| 1414 | SRC_PUT8(hc->sca_base, msci->rxs, |
| 1415 | SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1); |
| 1416 | SRC_PUT8(hc->sca_base, msci->txs, |
| 1417 | SCA_TXS_CLK_TXC | SCA_TXS_DIV1); |
| 1418 | break; |
| 1419 | |
| 1420 | case SR_FLAGS_INT_CLK: |
| 1421 | #if BUGGY > 0 |
| 1422 | kprintf("sr%d: Internal Clocking selected.\n", portndx); |
| 1423 | #endif |
| 1424 | |
| 1425 | /* |
| 1426 | * XXX I do need some code to set the baud rate here! |
| 1427 | */ |
| 1428 | #ifdef N2_TEST_SPEED |
| 1429 | switch (hc->cardtype) { |
| 1430 | case SR_CRD_N2PCI: |
| 1431 | fecrp = (u_int *)(hc->sca_base + SR_FECR); |
| 1432 | mcr_v = *fecrp; |
| 1433 | etcndx = 2; |
| 1434 | break; |
| 1435 | } |
| 1436 | |
| 1437 | fifo_v = 0x10; /* stolen from Linux version */ |
| 1438 | |
| 1439 | /* |
| 1440 | * search for appropriate speed in table, don't calc it: |
| 1441 | */ |
| 1442 | wanted = sr_test_speed[portndx]; |
| 1443 | rtp = &n2_rates[0]; /* point to first table item */ |
| 1444 | |
| 1445 | while ((rtp->target > 0) /* search table for speed */ |
| 1446 | &&(rtp->target != wanted)) |
| 1447 | rtp++; |
| 1448 | |
| 1449 | /* |
| 1450 | * We've searched the table for a matching speed. If we've |
| 1451 | * found the correct rate line, we'll get the pre-calc'd |
| 1452 | * values for the TMC and baud rate divisor for subsequent |
| 1453 | * use... |
| 1454 | */ |
| 1455 | if (rtp->target > 0) { /* use table-provided values */ |
| 1456 | gotspeed = wanted; |
| 1457 | tmc_v = rtp->tmc_reg; |
| 1458 | br_v = rtp->br_reg; |
| 1459 | } else { /* otherwise assume 1MBit comm rate */ |
| 1460 | gotspeed = 10000; |
| 1461 | tmc_v = 5; |
| 1462 | br_v = 1; |
| 1463 | } |
| 1464 | |
| 1465 | /* |
| 1466 | * Now we mask in the enable clock output for the MCR: |
| 1467 | */ |
| 1468 | mcr_v |= etc0vals[etcndx + portndx]; |
| 1469 | |
| 1470 | /* |
| 1471 | * Now we'll program the registers with these speed- related |
| 1472 | * contents... |
| 1473 | */ |
| 1474 | SRC_PUT8(hc->sca_base, msci->tmc, tmc_v); |
| 1475 | SRC_PUT8(hc->sca_base, msci->trc0, fifo_v); |
| 1476 | SRC_PUT8(hc->sca_base, msci->rxs, SCA_RXS_CLK_INT + br_v); |
| 1477 | SRC_PUT8(hc->sca_base, msci->txs, SCA_TXS_CLK_INT + br_v); |
| 1478 | |
| 1479 | switch (hc->cardtype) { |
| 1480 | case SR_CRD_N2PCI: |
| 1481 | *fecrp = mcr_v; |
| 1482 | break; |
| 1483 | } |
| 1484 | |
| 1485 | #if BUGGY > 0 |
| 1486 | if (wanted != gotspeed) |
| 1487 | kprintf("sr%d: Speed wanted=%d, found=%d\n", |
| 1488 | wanted, gotspeed); |
| 1489 | |
| 1490 | kprintf("sr%d: Internal Clock %dx100 BPS, tmc=%d, div=%d\n", |
| 1491 | portndx, gotspeed, tmc_v, br_v); |
| 1492 | #endif |
| 1493 | #else |
| 1494 | SRC_PUT8(hc->sca_base, msci->rxs, |
| 1495 | SCA_RXS_CLK_INT | SCA_RXS_DIV1); |
| 1496 | SRC_PUT8(hc->sca_base, msci->txs, |
| 1497 | SCA_TXS_CLK_INT | SCA_TXS_DIV1); |
| 1498 | |
| 1499 | SRC_PUT8(hc->sca_base, msci->tmc, 5); |
| 1500 | |
| 1501 | if (portndx == 0) |
| 1502 | switch (hc->cardtype) { |
| 1503 | case SR_CRD_N2PCI: |
| 1504 | fecrp = (u_int *)(hc->sca_base + SR_FECR); |
| 1505 | *fecrp |= SR_FECR_ETC0; |
| 1506 | break; |
| 1507 | } |
| 1508 | else |
| 1509 | switch (hc->cardtype) { |
| 1510 | case SR_CRD_N2PCI: |
| 1511 | fecrp = (u_int *)(hc->sca_base + SR_FECR); |
| 1512 | *fecrp |= SR_FECR_ETC1; |
| 1513 | break; |
| 1514 | } |
| 1515 | #endif |
| 1516 | } |
| 1517 | |
| 1518 | /* |
| 1519 | * XXX Disable all interrupts for now. I think if you are using the |
| 1520 | * dmac you don't use these interrupts. |
| 1521 | */ |
| 1522 | SRC_PUT8(hc->sca_base, msci->ie0, 0); |
| 1523 | SRC_PUT8(hc->sca_base, msci->ie1, 0x0C); |
| 1524 | SRC_PUT8(hc->sca_base, msci->ie2, 0); |
| 1525 | SRC_PUT8(hc->sca_base, msci->fie, 0); |
| 1526 | |
| 1527 | SRC_PUT8(hc->sca_base, msci->sa0, 0); |
| 1528 | SRC_PUT8(hc->sca_base, msci->sa1, 0); |
| 1529 | |
| 1530 | SRC_PUT8(hc->sca_base, msci->idl, 0x7E); /* set flags value */ |
| 1531 | |
| 1532 | SRC_PUT8(hc->sca_base, msci->rrc, 0x0E); |
| 1533 | SRC_PUT8(hc->sca_base, msci->trc0, 0x10); |
| 1534 | SRC_PUT8(hc->sca_base, msci->trc1, 0x1F); |
| 1535 | } |
| 1536 | |
| 1537 | /* |
| 1538 | * Configure the rx dma controller. |
| 1539 | */ |
| 1540 | static void |
| 1541 | sr_init_rx_dmac(struct sr_softc *sc) |
| 1542 | { |
| 1543 | struct sr_hardc *hc; |
| 1544 | dmac_channel *dmac; |
| 1545 | sca_descriptor *rxd; |
| 1546 | u_int cda_v, sarb_v, rxbuf, rxda, rxda_d; |
| 1547 | |
| 1548 | #if BUGGY > 0 |
| 1549 | kprintf("sr_init_rx_dmac(sc=%08x)\n", sc); |
| 1550 | #endif |
| 1551 | |
| 1552 | hc = sc->hc; |
| 1553 | dmac = &hc->sca->dmac[DMAC_RXCH(sc->scachan)]; |
| 1554 | |
| 1555 | /* |
| 1556 | * This phase initializes the contents of the descriptor table |
| 1557 | * needed to construct a circular buffer... |
| 1558 | */ |
| 1559 | rxd = (sca_descriptor *)(hc->mem_start + (sc->rxdesc & hc->winmsk)); |
| 1560 | rxda_d = (u_int) hc->mem_start - (sc->rxdesc & ~hc->winmsk); |
| 1561 | |
| 1562 | for (rxbuf = sc->rxstart; |
| 1563 | rxbuf < sc->rxend; |
| 1564 | rxbuf += SR_BUF_SIZ, rxd++) { |
| 1565 | /* |
| 1566 | * construct the circular chain... |
| 1567 | */ |
| 1568 | rxda = (u_int) & rxd[1] - rxda_d + hc->mem_pstart; |
| 1569 | rxd->cp = (u_short)(rxda & 0xffff); |
| 1570 | |
| 1571 | /* |
| 1572 | * set the on-card buffer address... |
| 1573 | */ |
| 1574 | rxd->bp = (u_short)((rxbuf + hc->mem_pstart) & 0xffff); |
| 1575 | rxd->bpb = (u_char)(((rxbuf + hc->mem_pstart) >> 16) & 0xff); |
| 1576 | |
| 1577 | rxd->len = 0; /* bytes resident w/in granule */ |
| 1578 | rxd->stat = 0xff; /* The sca write here when finished */ |
| 1579 | } |
| 1580 | |
| 1581 | /* |
| 1582 | * heal the chain so that the last entry points to the first... |
| 1583 | */ |
| 1584 | rxd--; |
| 1585 | rxd->cp = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff); |
| 1586 | |
| 1587 | /* |
| 1588 | * reset the reception handler's index... |
| 1589 | */ |
| 1590 | sc->rxhind = 0; |
| 1591 | |
| 1592 | /* |
| 1593 | * We'll now configure the receiver's DMA logic... |
| 1594 | */ |
| 1595 | SRC_PUT8(hc->sca_base, dmac->dsr, 0); /* Disable DMA transfer */ |
| 1596 | SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT); |
| 1597 | |
| 1598 | /* XXX maybe also SCA_DMR_CNTE */ |
| 1599 | SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF); |
| 1600 | SRC_PUT16(hc->sca_base, dmac->bfl, SR_BUF_SIZ); |
| 1601 | |
| 1602 | cda_v = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff); |
| 1603 | sarb_v = (u_char)(((sc->rxdesc + hc->mem_pstart) >> 16) & 0xff); |
| 1604 | |
| 1605 | SRC_PUT16(hc->sca_base, dmac->cda, cda_v); |
| 1606 | SRC_PUT8(hc->sca_base, dmac->sarb, sarb_v); |
| 1607 | |
| 1608 | rxd = (sca_descriptor *)sc->rxstart; |
| 1609 | |
| 1610 | SRC_PUT16(hc->sca_base, dmac->eda, |
| 1611 | (u_short)((u_int) & rxd[sc->rxmax - 1] & 0xffff)); |
| 1612 | |
| 1613 | SRC_PUT8(hc->sca_base, dmac->dir, 0xF0); |
| 1614 | |
| 1615 | |
| 1616 | SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE); /* Enable DMA */ |
| 1617 | } |
| 1618 | |
| 1619 | /* |
| 1620 | * Configure the TX DMA descriptors. |
| 1621 | * Initialize the needed values and chain the descriptors. |
| 1622 | */ |
| 1623 | static void |
| 1624 | sr_init_tx_dmac(struct sr_softc *sc) |
| 1625 | { |
| 1626 | int blk; |
| 1627 | u_int txbuf, txda, txda_d; |
| 1628 | struct sr_hardc *hc; |
| 1629 | sca_descriptor *txd; |
| 1630 | dmac_channel *dmac; |
| 1631 | struct buf_block *blkp; |
| 1632 | u_int x; |
| 1633 | u_int sarb_v; |
| 1634 | |
| 1635 | #if BUGGY > 0 |
| 1636 | kprintf("sr_init_tx_dmac(sc=%08x)\n", sc); |
| 1637 | #endif |
| 1638 | |
| 1639 | hc = sc->hc; |
| 1640 | dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)]; |
| 1641 | |
| 1642 | /* |
| 1643 | * Initialize the array of descriptors for transmission |
| 1644 | */ |
| 1645 | for (blk = 0; blk < SR_TX_BLOCKS; blk++) { |
| 1646 | blkp = &sc->block[blk]; |
| 1647 | txd = (sca_descriptor *)(hc->mem_start |
| 1648 | + (blkp->txdesc & hc->winmsk)); |
| 1649 | txda_d = (u_int) hc->mem_start |
| 1650 | - (blkp->txdesc & ~hc->winmsk); |
| 1651 | |
| 1652 | x = 0; |
| 1653 | txbuf = blkp->txstart; |
| 1654 | for (; txbuf < blkp->txend; txbuf += SR_BUF_SIZ, txd++) { |
| 1655 | txda = (u_int) & txd[1] - txda_d + hc->mem_pstart; |
| 1656 | txd->cp = (u_short)(txda & 0xffff); |
| 1657 | |
| 1658 | txd->bp = (u_short)((txbuf + hc->mem_pstart) |
| 1659 | & 0xffff); |
| 1660 | txd->bpb = (u_char)(((txbuf + hc->mem_pstart) >> 16) |
| 1661 | & 0xff); |
| 1662 | txd->len = 0; |
| 1663 | txd->stat = 0; |
| 1664 | x++; |
| 1665 | } |
| 1666 | |
| 1667 | txd--; |
| 1668 | txd->cp = (u_short)((blkp->txdesc + hc->mem_pstart) |
| 1669 | & 0xffff); |
| 1670 | |
| 1671 | blkp->txtail = (u_int)txd - (u_int)hc->mem_start; |
| 1672 | } |
| 1673 | |
| 1674 | SRC_PUT8(hc->sca_base, dmac->dsr, 0); /* Disable DMA */ |
| 1675 | SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT); |
| 1676 | SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF); |
| 1677 | SRC_PUT8(hc->sca_base, dmac->dir, |
| 1678 | SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF); |
| 1679 | |
| 1680 | sarb_v = (sc->block[0].txdesc + hc->mem_pstart) >> 16; |
| 1681 | sarb_v &= 0x00ff; |
| 1682 | |
| 1683 | SRC_PUT8(hc->sca_base, dmac->sarb, (u_char) sarb_v); |
| 1684 | } |
| 1685 | |
| 1686 | /* |
| 1687 | * Look through the descriptors to see if there is a complete packet |
| 1688 | * available. Stop if we get to where the sca is busy. |
| 1689 | * |
| 1690 | * Return the length and status of the packet. |
| 1691 | * Return nonzero if there is a packet available. |
| 1692 | * |
| 1693 | * NOTE: |
| 1694 | * It seems that we get the interrupt a bit early. The updateing of |
| 1695 | * descriptor values is not always completed when this is called. |
| 1696 | */ |
| 1697 | static int |
| 1698 | sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat) |
| 1699 | { |
| 1700 | int granules; /* count of granules in pkt */ |
| 1701 | int wki, wko; |
| 1702 | struct sr_hardc *hc; |
| 1703 | sca_descriptor *rxdesc; /* current descriptor */ |
| 1704 | sca_descriptor *endp; /* ending descriptor */ |
| 1705 | sca_descriptor *cda; /* starting descriptor */ |
| 1706 | |
| 1707 | hc = sc->hc; /* get card's information */ |
| 1708 | |
| 1709 | /* |
| 1710 | * set up starting descriptor by pulling that info from the DMA half |
| 1711 | * of the HD chip... |
| 1712 | */ |
| 1713 | wki = DMAC_RXCH(sc->scachan); |
| 1714 | wko = SRC_GET16(hc->sca_base, hc->sca->dmac[wki].cda); |
| 1715 | |
| 1716 | cda = (sca_descriptor *)(hc->mem_start + (wko & hc->winmsk)); |
| 1717 | |
| 1718 | #if BUGGY > 1 |
| 1719 | kprintf("sr_packet_avail(): wki=%d, wko=%04x, cda=%08x\n", |
| 1720 | wki, wko, cda); |
| 1721 | #endif |
| 1722 | |
| 1723 | /* |
| 1724 | * open the appropriate memory window and set our expectations... |
| 1725 | */ |
| 1726 | rxdesc = (sca_descriptor *) |
| 1727 | (hc->mem_start + (sc->rxdesc & hc->winmsk)); |
| 1728 | endp = rxdesc; |
| 1729 | rxdesc = &rxdesc[sc->rxhind]; |
| 1730 | endp = &endp[sc->rxmax]; |
| 1731 | |
| 1732 | *len = 0; /* reset result total length */ |
| 1733 | granules = 0; /* reset count of granules */ |
| 1734 | |
| 1735 | /* |
| 1736 | * This loop will scan descriptors, but it *will* puke up if we wrap |
| 1737 | * around to our starting point... |
| 1738 | */ |
| 1739 | while (rxdesc != cda) { |
| 1740 | *len += rxdesc->len; /* increment result length */ |
| 1741 | granules++; |
| 1742 | |
| 1743 | /* |
| 1744 | * If we hit a valid packet's completion we'll know we've |
| 1745 | * got a live one, and that we can deliver the packet. |
| 1746 | * Since we're only allowed to report a packet available, |
| 1747 | * somebody else does that... |
| 1748 | */ |
| 1749 | if (rxdesc->stat & SCA_DESC_EOM) { /* End Of Message */ |
| 1750 | *rxstat = rxdesc->stat; /* return closing */ |
| 1751 | #if BUGGY > 0 |
| 1752 | kprintf("sr%d: PKT AVAIL len %d, %x, bufs %u.\n", |
| 1753 | sc->unit, *len, *rxstat, granules); |
| 1754 | #endif |
| 1755 | return 1; /* indicate success */ |
| 1756 | } |
| 1757 | /* |
| 1758 | * OK, this packet take up multiple granules. Move on to |
| 1759 | * the next descriptor so we can consider it... |
| 1760 | */ |
| 1761 | rxdesc++; |
| 1762 | |
| 1763 | if (rxdesc == endp) /* recognize & act on wrap point */ |
| 1764 | rxdesc = (sca_descriptor *) |
| 1765 | (hc->mem_start + (sc->rxdesc & hc->winmsk)); |
| 1766 | } |
| 1767 | |
| 1768 | /* |
| 1769 | * Nothing found in the DPRAM. Let the caller know... |
| 1770 | */ |
| 1771 | *len = 0; |
| 1772 | *rxstat = 0; |
| 1773 | |
| 1774 | return 0; |
| 1775 | } |
| 1776 | |
| 1777 | /* |
| 1778 | * Copy a packet from the on card memory into a provided mbuf. |
| 1779 | * Take into account that buffers wrap and that a packet may |
| 1780 | * be larger than a buffer. |
| 1781 | */ |
| 1782 | static void |
| 1783 | sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len) |
| 1784 | { |
| 1785 | struct sr_hardc *hc; |
| 1786 | sca_descriptor *rxdesc; |
| 1787 | u_int rxdata; |
| 1788 | u_int rxmax; |
| 1789 | u_int off = 0; |
| 1790 | u_int tlen; |
| 1791 | |
| 1792 | #if BUGGY > 0 |
| 1793 | kprintf("sr_copy_rxbuf(m=%08x,sc=%08x,len=%d)\n", |
| 1794 | m, sc, len); |
| 1795 | #endif |
| 1796 | |
| 1797 | hc = sc->hc; |
| 1798 | |
| 1799 | rxdata = sc->rxstart + (sc->rxhind * SR_BUF_SIZ); |
| 1800 | rxmax = sc->rxstart + (sc->rxmax * SR_BUF_SIZ); |
| 1801 | |
| 1802 | rxdesc = (sca_descriptor *) |
| 1803 | (hc->mem_start + (sc->rxdesc & hc->winmsk)); |
| 1804 | rxdesc = &rxdesc[sc->rxhind]; |
| 1805 | |
| 1806 | /* |
| 1807 | * Using the count of bytes in the received packet, we decrement it |
| 1808 | * for each granule (controller by an SCA descriptor) to control the |
| 1809 | * looping... |
| 1810 | */ |
| 1811 | while (len) { |
| 1812 | /* |
| 1813 | * tlen gets the length of *this* granule... ...which is |
| 1814 | * then copied to the target buffer. |
| 1815 | */ |
| 1816 | tlen = (len < SR_BUF_SIZ) ? len : SR_BUF_SIZ; |
| 1817 | |
| 1818 | bcopy(hc->mem_start + (rxdata & hc->winmsk), |
| 1819 | mtod(m, caddr_t) +off, |
| 1820 | tlen); |
| 1821 | |
| 1822 | off += tlen; |
| 1823 | len -= tlen; |
| 1824 | |
| 1825 | /* |
| 1826 | * now, return to the descriptor's window in DPRAM and reset |
| 1827 | * the descriptor we've just suctioned... |
| 1828 | */ |
| 1829 | |
| 1830 | rxdesc->len = 0; |
| 1831 | rxdesc->stat = 0xff; |
| 1832 | |
| 1833 | /* |
| 1834 | * Move on to the next granule. If we've any remaining |
| 1835 | * bytes to process we'll just continue in our loop... |
| 1836 | */ |
| 1837 | rxdata += SR_BUF_SIZ; |
| 1838 | rxdesc++; |
| 1839 | |
| 1840 | if (rxdata == rxmax) { /* handle the wrap point */ |
| 1841 | rxdata = sc->rxstart; |
| 1842 | rxdesc = (sca_descriptor *) |
| 1843 | (hc->mem_start + (sc->rxdesc & hc->winmsk)); |
| 1844 | } |
| 1845 | } |
| 1846 | } |
| 1847 | |
| 1848 | /* |
| 1849 | * If single is set, just eat a packet. Otherwise eat everything up to |
| 1850 | * where cda points. Update pointers to point to the next packet. |
| 1851 | * |
| 1852 | * This handles "flushing" of a packet as received... |
| 1853 | * |
| 1854 | * If the "single" parameter is zero, all pending reeceive traffic will |
| 1855 | * be flushed out of existence. A non-zero value will only drop the |
| 1856 | * *next* (currently) pending packet... |
| 1857 | */ |
| 1858 | static void |
| 1859 | sr_eat_packet(struct sr_softc *sc, int single) |
| 1860 | { |
| 1861 | struct sr_hardc *hc; |
| 1862 | sca_descriptor *rxdesc; /* current descriptor being eval'd */ |
| 1863 | sca_descriptor *endp; /* last descriptor in chain */ |
| 1864 | sca_descriptor *cda; /* current start point */ |
| 1865 | u_int loopcnt = 0; /* count of packets flushed ??? */ |
| 1866 | u_char stat; /* captured status byte from descr */ |
| 1867 | |
| 1868 | hc = sc->hc; |
| 1869 | cda = (sca_descriptor *)(hc->mem_start + |
| 1870 | (SRC_GET16(hc->sca_base, |
| 1871 | hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda) & |
| 1872 | hc->winmsk)); |
| 1873 | |
| 1874 | /* |
| 1875 | * loop until desc->stat == (0xff || EOM) Clear the status and |
| 1876 | * length in the descriptor. Increment the descriptor. |
| 1877 | */ |
| 1878 | |
| 1879 | rxdesc = (sca_descriptor *) |
| 1880 | (hc->mem_start + (sc->rxdesc & hc->winmsk)); |
| 1881 | endp = rxdesc; |
| 1882 | rxdesc = &rxdesc[sc->rxhind]; |
| 1883 | endp = &endp[sc->rxmax]; |
| 1884 | |
| 1885 | /* |
| 1886 | * allow loop, but abort it if we wrap completely... |
| 1887 | */ |
| 1888 | while (rxdesc != cda) { |
| 1889 | loopcnt++; |
| 1890 | |
| 1891 | if (loopcnt > sc->rxmax) { |
| 1892 | kprintf("sr%d: eat pkt %d loop, cda %x, " |
| 1893 | "rxdesc %x, stat %x.\n", |
| 1894 | sc->unit, loopcnt, (u_int) cda, (u_int) rxdesc, |
| 1895 | rxdesc->stat); |
| 1896 | break; |
| 1897 | } |
| 1898 | stat = rxdesc->stat; |
| 1899 | |
| 1900 | rxdesc->len = 0; |
| 1901 | rxdesc->stat = 0xff; |
| 1902 | |
| 1903 | rxdesc++; |
| 1904 | sc->rxhind++; |
| 1905 | |
| 1906 | if (rxdesc == endp) { |
| 1907 | rxdesc = (sca_descriptor *) |
| 1908 | (hc->mem_start + (sc->rxdesc & hc->winmsk)); |
| 1909 | sc->rxhind = 0; |
| 1910 | } |
| 1911 | if (single && (stat == SCA_DESC_EOM)) |
| 1912 | break; |
| 1913 | } |
| 1914 | |
| 1915 | /* |
| 1916 | * Update the eda to the previous descriptor. |
| 1917 | */ |
| 1918 | rxdesc = (sca_descriptor *)sc->rxdesc; |
| 1919 | rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2) % sc->rxmax]; |
| 1920 | |
| 1921 | SRC_PUT16(hc->sca_base, |
| 1922 | hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda, |
| 1923 | (u_short)((u_int)(rxdesc + hc->mem_pstart) & 0xffff)); |
| 1924 | } |
| 1925 | |
| 1926 | /* |
| 1927 | * While there is packets available in the rx buffer, read them out |
| 1928 | * into mbufs and ship them off. |
| 1929 | */ |
| 1930 | static void |
| 1931 | sr_get_packets(struct sr_softc *sc) |
| 1932 | { |
| 1933 | u_char rxstat; /* acquired status byte */ |
| 1934 | int i; |
| 1935 | int pkts; /* count of packets found */ |
| 1936 | int rxndx; /* rcv buffer index */ |
| 1937 | int tries; /* settling time counter */ |
| 1938 | u_int len; /* length of pending packet */ |
| 1939 | struct sr_hardc *hc; /* card-level information */ |
| 1940 | sca_descriptor *rxdesc; /* descriptor in memory */ |
| 1941 | #ifndef NETGRAPH |
| 1942 | struct ifnet *ifp; /* network intf ctl table */ |
| 1943 | #endif /* NETGRAPH */ |
| 1944 | struct mbuf *m = NULL; /* message buffer */ |
| 1945 | |
| 1946 | #if BUGGY > 0 |
| 1947 | kprintf("sr_get_packets(sc=%08x)\n", sc); |
| 1948 | #endif |
| 1949 | |
| 1950 | hc = sc->hc; |
| 1951 | #ifndef NETGRAPH |
| 1952 | ifp = &sc->ifsppp.pp_if; |
| 1953 | #endif /* NETGRAPH */ |
| 1954 | |
| 1955 | pkts = 0; /* reset count of found packets */ |
| 1956 | |
| 1957 | /* |
| 1958 | * for each complete packet in the receiving pool, process each |
| 1959 | * packet... |
| 1960 | */ |
| 1961 | while (sr_packet_avail(sc, &len, &rxstat)) { /* packet pending? */ |
| 1962 | /* |
| 1963 | * I have seen situations where we got the interrupt but the |
| 1964 | * status value wasn't deposited. This code should allow |
| 1965 | * the status byte's value to settle... |
| 1966 | */ |
| 1967 | |
| 1968 | tries = 5; |
| 1969 | |
| 1970 | while ((rxstat == 0x00ff) |
| 1971 | && --tries) |
| 1972 | sr_packet_avail(sc, &len, &rxstat); |
| 1973 | |
| 1974 | #if BUGGY > 1 |
| 1975 | kprintf("sr_packet_avail() returned len=%d, rxstat=%02ux\n", |
| 1976 | len, rxstat); |
| 1977 | #endif |
| 1978 | |
| 1979 | pkts++; |
| 1980 | #ifdef NETGRAPH |
| 1981 | sc->inbytes += len; |
| 1982 | sc->inlast = 0; |
| 1983 | #endif /* NETGRAPH */ |
| 1984 | |
| 1985 | /* |
| 1986 | * OK, we've settled the incoming message status. We can now |
| 1987 | * process it... |
| 1988 | */ |
| 1989 | if (((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) { |
| 1990 | #if BUGGY > 1 |
| 1991 | kprintf("sr%d: sr_get_packet() rxstat=%02x, len=%d\n", |
| 1992 | sc->unit, rxstat, len); |
| 1993 | #endif |
| 1994 | |
| 1995 | MGETHDR(m, MB_DONTWAIT, MT_DATA); |
| 1996 | if (m == NULL) { |
| 1997 | /* |
| 1998 | * eat (flush) packet if get mbuf fail!! |
| 1999 | */ |
| 2000 | sr_eat_packet(sc, 1); |
| 2001 | continue; |
| 2002 | } |
| 2003 | /* |
| 2004 | * construct control information for pass-off |
| 2005 | */ |
| 2006 | #ifndef NETGRAPH |
| 2007 | m->m_pkthdr.rcvif = ifp; |
| 2008 | #else |
| 2009 | m->m_pkthdr.rcvif = NULL; |
| 2010 | #endif /* NETGRAPH */ |
| 2011 | m->m_pkthdr.len = m->m_len = len; |
| 2012 | if (len > MHLEN) { |
| 2013 | MCLGET(m, MB_DONTWAIT); |
| 2014 | if ((m->m_flags & M_EXT) == 0) { |
| 2015 | /* |
| 2016 | * We couldn't get a big enough |
| 2017 | * message packet, so we'll send the |
| 2018 | * packet to /dev/null... |
| 2019 | */ |
| 2020 | m_freem(m); |
| 2021 | sr_eat_packet(sc, 1); |
| 2022 | continue; |
| 2023 | } |
| 2024 | } |
| 2025 | /* |
| 2026 | * OK, we've got a good message buffer. Now we can |
| 2027 | * copy the received message into it |
| 2028 | */ |
| 2029 | sr_copy_rxbuf(m, sc, len); /* copy from DPRAM */ |
| 2030 | |
| 2031 | #ifndef NETGRAPH |
| 2032 | BPF_MTAP(ifp, m); |
| 2033 | |
| 2034 | #if BUGGY > 3 |
| 2035 | { |
| 2036 | u_char *bp; |
| 2037 | |
| 2038 | bp = (u_char *)m; |
| 2039 | kprintf("sr%d: rcvd=%02x%02x%02x%02x%02x%02x\n", |
| 2040 | sc->unit, |
| 2041 | bp[0], bp[1], bp[2], |
| 2042 | bp[4], bp[5], bp[6]); |
| 2043 | } |
| 2044 | #endif |
| 2045 | sppp_input(ifp, m); |
| 2046 | ifp->if_ipackets++; |
| 2047 | |
| 2048 | #else /* NETGRAPH */ |
| 2049 | #if BUGGY > 3 |
| 2050 | { |
| 2051 | u_char *bp; |
| 2052 | |
| 2053 | bp = mtod(m,u_char *); |
| 2054 | kprintf("sr%d: rd=%02x:%02x:%02x:%02x:%02x:%02x", |
| 2055 | sc->unit, |
| 2056 | bp[0], bp[1], bp[2], |
| 2057 | bp[4], bp[5], bp[6]); |
| 2058 | kprintf(":%02x:%02x:%02x:%02x:%02x:%02x\n", |
| 2059 | bp[6], bp[7], bp[8], |
| 2060 | bp[9], bp[10], bp[11]); |
| 2061 | } |
| 2062 | #endif |
| 2063 | ng_queue_data(sc->hook, m, NULL); |
| 2064 | sc->ipackets++; |
| 2065 | #endif /* NETGRAPH */ |
| 2066 | /* |
| 2067 | * Update the eda to the previous descriptor. |
| 2068 | */ |
| 2069 | i = (len + SR_BUF_SIZ - 1) / SR_BUF_SIZ; |
| 2070 | sc->rxhind = (sc->rxhind + i) % sc->rxmax; |
| 2071 | |
| 2072 | rxdesc = (sca_descriptor *)sc->rxdesc; |
| 2073 | rxndx = (sc->rxhind + sc->rxmax - 2) % sc->rxmax; |
| 2074 | rxdesc = &rxdesc[rxndx]; |
| 2075 | |
| 2076 | SRC_PUT16(hc->sca_base, |
| 2077 | hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda, |
| 2078 | (u_short)((u_int)(rxdesc + hc->mem_pstart) |
| 2079 | & 0xffff)); |
| 2080 | |
| 2081 | } else { |
| 2082 | int got_st3, got_cda, got_eda; |
| 2083 | int tries = 5; |
| 2084 | |
| 2085 | while ((rxstat == 0xff) && --tries) |
| 2086 | sr_packet_avail(sc, &len, &rxstat); |
| 2087 | |
| 2088 | /* |
| 2089 | * It look like we get an interrupt early |
| 2090 | * sometimes and then the status is not |
| 2091 | * filled in yet. |
| 2092 | */ |
| 2093 | if (tries && (tries != 5)) |
| 2094 | continue; |
| 2095 | |
| 2096 | /* |
| 2097 | * This chunk of code handles the error packets. |
| 2098 | * We'll log them for posterity... |
| 2099 | */ |
| 2100 | sr_eat_packet(sc, 1); |
| 2101 | |
| 2102 | #ifndef NETGRAPH |
| 2103 | ifp->if_ierrors++; |
| 2104 | #else |
| 2105 | sc->ierrors[0]++; |
| 2106 | #endif /* NETGRAPH */ |
| 2107 | |
| 2108 | got_st3 = SRC_GET8(hc->sca_base, |
| 2109 | hc->sca->msci[sc->scachan].st3); |
| 2110 | got_cda = SRC_GET16(hc->sca_base, |
| 2111 | hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda); |
| 2112 | got_eda = SRC_GET16(hc->sca_base, |
| 2113 | hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda); |
| 2114 | |
| 2115 | #if BUGGY > 0 |
| 2116 | kprintf("sr%d: Receive error chan %d, " |
| 2117 | "stat %02x, msci st3 %02x," |
| 2118 | "rxhind %d, cda %04x, eda %04x.\n", |
| 2119 | sc->unit, sc->scachan, rxstat, |
| 2120 | got_st3, sc->rxhind, got_cda, got_eda); |
| 2121 | #endif |
| 2122 | } |
| 2123 | } |
| 2124 | |
| 2125 | #if BUGGY > 0 |
| 2126 | kprintf("sr%d: sr_get_packets() found %d packet(s)\n", |
| 2127 | sc->unit, pkts); |
| 2128 | #endif |
| 2129 | } |
| 2130 | |
| 2131 | /* |
| 2132 | * All DMA interrupts come here. |
| 2133 | * |
| 2134 | * Each channel has two interrupts. |
| 2135 | * Interrupt A for errors and Interrupt B for normal stuff like end |
| 2136 | * of transmit or receive dmas. |
| 2137 | */ |
| 2138 | static void |
| 2139 | sr_dmac_intr(struct sr_hardc *hc, u_char isr1) |
| 2140 | { |
| 2141 | u_char dsr; /* contents of DMA Stat Reg */ |
| 2142 | u_char dotxstart; /* enables for tranmit part */ |
| 2143 | int mch; /* channel being processed */ |
| 2144 | struct sr_softc *sc; /* channel's softc structure */ |
| 2145 | sca_regs *sca = hc->sca; |
| 2146 | dmac_channel *dmac; /* dma structure of chip */ |
| 2147 | |
| 2148 | #if BUGGY > 0 |
| 2149 | kprintf("sr_dmac_intr(hc=%08x,isr1=%04x)\n", hc, isr1); |
| 2150 | #endif |
| 2151 | |
| 2152 | mch = 0; /* assume chan0 on card */ |
| 2153 | dotxstart = isr1; /* copy for xmitter starts */ |
| 2154 | |
| 2155 | /* |
| 2156 | * Shortcut if there is no interrupts for dma channel 0 or 1. |
| 2157 | * Skip processing for channel 0 if no incoming hit |
| 2158 | */ |
| 2159 | if ((isr1 & 0x0F) == 0) { |
| 2160 | mch = 1; |
| 2161 | isr1 >>= 4; |
| 2162 | } |
| 2163 | do { |
| 2164 | sc = &hc->sc[mch]; |
| 2165 | |
| 2166 | /* |
| 2167 | * Transmit channel - DMA Status Register Evaluation |
| 2168 | */ |
| 2169 | if (isr1 & 0x0C) { |
| 2170 | dmac = &sca->dmac[DMAC_TXCH(mch)]; |
| 2171 | |
| 2172 | /* |
| 2173 | * get the DMA Status Register contents and write |
| 2174 | * back to reset interrupt... |
| 2175 | */ |
| 2176 | dsr = SRC_GET8(hc->sca_base, dmac->dsr); |
| 2177 | SRC_PUT8(hc->sca_base, dmac->dsr, dsr); |
| 2178 | |
| 2179 | /* |
| 2180 | * Check for (& process) a Counter overflow |
| 2181 | */ |
| 2182 | if (dsr & SCA_DSR_COF) { |
| 2183 | kprintf("sr%d: TX DMA Counter overflow, " |
| 2184 | "txpacket no %lu.\n", |
| 2185 | #ifndef NETGRAPH |
| 2186 | sc->unit, sc->ifsppp.pp_if.if_opackets); |
| 2187 | sc->ifsppp.pp_if.if_oerrors++; |
| 2188 | #else |
| 2189 | sc->unit, sc->opackets); |
| 2190 | sc->oerrors++; |
| 2191 | #endif /* NETGRAPH */ |
| 2192 | } |
| 2193 | /* |
| 2194 | * Check for (& process) a Buffer overflow |
| 2195 | */ |
| 2196 | if (dsr & SCA_DSR_BOF) { |
| 2197 | kprintf("sr%d: TX DMA Buffer overflow, " |
| 2198 | "txpacket no %lu, dsr %02x, " |
| 2199 | "cda %04x, eda %04x.\n", |
| 2200 | #ifndef NETGRAPH |
| 2201 | sc->unit, sc->ifsppp.pp_if.if_opackets, |
| 2202 | #else |
| 2203 | sc->unit, sc->opackets, |
| 2204 | #endif /* NETGRAPH */ |
| 2205 | dsr, |
| 2206 | SRC_GET16(hc->sca_base, dmac->cda), |
| 2207 | SRC_GET16(hc->sca_base, dmac->eda)); |
| 2208 | #ifndef NETGRAPH |
| 2209 | sc->ifsppp.pp_if.if_oerrors++; |
| 2210 | #else |
| 2211 | sc->oerrors++; |
| 2212 | #endif /* NETGRAPH */ |
| 2213 | } |
| 2214 | /* |
| 2215 | * Check for (& process) an End of Transfer (OK) |
| 2216 | */ |
| 2217 | if (dsr & SCA_DSR_EOT) { |
| 2218 | /* |
| 2219 | * This should be the most common case. |
| 2220 | * |
| 2221 | * Clear the IFF_OACTIVE flag. |
| 2222 | * |
| 2223 | * Call srstart to start a new transmit if |
| 2224 | * there is data to transmit. |
| 2225 | */ |
| 2226 | #if BUGGY > 0 |
| 2227 | kprintf("sr%d: TX Completed OK\n", sc->unit); |
| 2228 | #endif |
| 2229 | sc->xmit_busy = 0; |
| 2230 | #ifndef NETGRAPH |
| 2231 | sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE; |
| 2232 | sc->ifsppp.pp_if.if_timer = 0; |
| 2233 | #else |
| 2234 | /* XXX may need to mark tx inactive? */ |
| 2235 | sc->out_deficit++; |
| 2236 | sc->out_dog = DOG_HOLDOFF; |
| 2237 | #endif /* NETGRAPH */ |
| 2238 | |
| 2239 | if (sc->txb_inuse && --sc->txb_inuse) |
| 2240 | sr_xmit(sc); |
| 2241 | } |
| 2242 | } |
| 2243 | /* |
| 2244 | * Receive channel processing of DMA Status Register |
| 2245 | */ |
| 2246 | if (isr1 & 0x03) { |
| 2247 | dmac = &sca->dmac[DMAC_RXCH(mch)]; |
| 2248 | |
| 2249 | dsr = SRC_GET8(hc->sca_base, dmac->dsr); |
| 2250 | SRC_PUT8(hc->sca_base, dmac->dsr, dsr); |
| 2251 | |
| 2252 | /* |
| 2253 | * End of frame processing (MSG OK?) |
| 2254 | */ |
| 2255 | if (dsr & SCA_DSR_EOM) { |
| 2256 | #if BUGGY > 0 |
| 2257 | int tt, ind; |
| 2258 | |
| 2259 | #ifndef NETGRAPH |
| 2260 | tt = sc->ifsppp.pp_if.if_ipackets; |
| 2261 | #else /* NETGRAPH */ |
| 2262 | tt = sc->ipackets; |
| 2263 | #endif /* NETGRAPH */ |
| 2264 | ind = sc->rxhind; |
| 2265 | #endif |
| 2266 | |
| 2267 | sr_get_packets(sc); |
| 2268 | #if BUGGY > 0 |
| 2269 | #ifndef NETGRAPH |
| 2270 | if (tt == sc->ifsppp.pp_if.if_ipackets) |
| 2271 | #else /* NETGRAPH */ |
| 2272 | if (tt == sc->ipackets) |
| 2273 | #endif /* NETGRAPH */ |
| 2274 | { |
| 2275 | sca_descriptor *rxdesc; |
| 2276 | int i; |
| 2277 | |
| 2278 | kprintf("SR: RXINTR isr1 %x, dsr %x, " |
| 2279 | "no data %d pkts, orxind %d.\n", |
| 2280 | dotxstart, dsr, tt, ind); |
| 2281 | kprintf("SR: rxdesc %x, rxstart %x, " |
| 2282 | "rxend %x, rxhind %d, " |
| 2283 | "rxmax %d.\n", |
| 2284 | sc->rxdesc, sc->rxstart, |
| 2285 | sc->rxend, sc->rxhind, |
| 2286 | sc->rxmax); |
| 2287 | kprintf("SR: cda %x, eda %x.\n", |
| 2288 | SRC_GET16(hc->sca_base, dmac->cda), |
| 2289 | SRC_GET16(hc->sca_base, dmac->eda)); |
| 2290 | |
| 2291 | rxdesc = (sca_descriptor *) |
| 2292 | (hc->mem_start + |
| 2293 | (sc->rxdesc & hc->winmsk)); |
| 2294 | rxdesc = &rxdesc[sc->rxhind]; |
| 2295 | |
| 2296 | for (i = 0; i < 3; i++, rxdesc++) |
| 2297 | kprintf("SR: rxdesc->stat %x, " |
| 2298 | "len %d.\n", |
| 2299 | rxdesc->stat, |
| 2300 | rxdesc->len); |
| 2301 | } |
| 2302 | #endif /* BUGGY */ |
| 2303 | } |
| 2304 | /* |
| 2305 | * Check for Counter overflow |
| 2306 | */ |
| 2307 | if (dsr & SCA_DSR_COF) { |
| 2308 | kprintf("sr%d: RX DMA Counter overflow, " |
| 2309 | "rxpkts %lu.\n", |
| 2310 | #ifndef NETGRAPH |
| 2311 | sc->unit, sc->ifsppp.pp_if.if_ipackets); |
| 2312 | sc->ifsppp.pp_if.if_ierrors++; |
| 2313 | #else /* NETGRAPH */ |
| 2314 | sc->unit, sc->ipackets); |
| 2315 | sc->ierrors[1]++; |
| 2316 | #endif /* NETGRAPH */ |
| 2317 | } |
| 2318 | /* |
| 2319 | * Check for Buffer overflow |
| 2320 | */ |
| 2321 | if (dsr & SCA_DSR_BOF) { |
| 2322 | kprintf("sr%d: RX DMA Buffer overflow, " |
| 2323 | "rxpkts %lu, rxind %d, " |
| 2324 | "cda %x, eda %x, dsr %x.\n", |
| 2325 | #ifndef NETGRAPH |
| 2326 | sc->unit, sc->ifsppp.pp_if.if_ipackets, |
| 2327 | #else /* NETGRAPH */ |
| 2328 | sc->unit, sc->ipackets, |
| 2329 | #endif /* NETGRAPH */ |
| 2330 | sc->rxhind, |
| 2331 | SRC_GET16(hc->sca_base, dmac->cda), |
| 2332 | SRC_GET16(hc->sca_base, dmac->eda), |
| 2333 | dsr); |
| 2334 | |
| 2335 | /* |
| 2336 | * Make sure we eat as many as possible. |
| 2337 | * Then get the system running again. |
| 2338 | */ |
| 2339 | |
| 2340 | sr_eat_packet(sc, 0); |
| 2341 | #ifndef NETGRAPH |
| 2342 | sc->ifsppp.pp_if.if_ierrors++; |
| 2343 | #else /* NETGRAPH */ |
| 2344 | sc->ierrors[2]++; |
| 2345 | #endif /* NETGRAPH */ |
| 2346 | |
| 2347 | SRC_PUT8(hc->sca_base, |
| 2348 | sca->msci[mch].cmd, |
| 2349 | SCA_CMD_RXMSGREJ); |
| 2350 | |
| 2351 | SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE); |
| 2352 | |
| 2353 | #if BUGGY > 0 |
| 2354 | kprintf("sr%d: RX DMA Buffer overflow, " |
| 2355 | "rxpkts %lu, rxind %d, " |
| 2356 | "cda %x, eda %x, dsr %x. After\n", |
| 2357 | sc->unit, |
| 2358 | #ifndef NETGRAPH |
| 2359 | sc->ipackets, |
| 2360 | #else /* NETGRAPH */ |
| 2361 | sc->ifsppp.pp_if.if_ipackets, |
| 2362 | #endif /* NETGRAPH */ |
| 2363 | sc->rxhind, |
| 2364 | SRC_GET16(hc->sca_base, dmac->cda), |
| 2365 | SRC_GET16(hc->sca_base, dmac->eda), |
| 2366 | SRC_GET8(hc->sca_base, dmac->dsr)); |
| 2367 | #endif |
| 2368 | } |
| 2369 | /* |
| 2370 | * End of Transfer |
| 2371 | */ |
| 2372 | if (dsr & SCA_DSR_EOT) { |
| 2373 | /* |
| 2374 | * If this happen, it means that we are |
| 2375 | * receiving faster than what the processor |
| 2376 | * can handle. |
| 2377 | * |
| 2378 | * XXX We should enable the dma again. |
| 2379 | */ |
| 2380 | kprintf("sr%d: RX End of xfer, rxpkts %lu.\n", |
| 2381 | sc->unit, |
| 2382 | #ifndef NETGRAPH |
| 2383 | sc->ifsppp.pp_if.if_ipackets); |
| 2384 | sc->ifsppp.pp_if.if_ierrors++; |
| 2385 | #else |
| 2386 | sc->ipackets); |
| 2387 | sc->ierrors[3]++; |
| 2388 | #endif /* NETGRAPH */ |
| 2389 | } |
| 2390 | } |
| 2391 | isr1 >>= 4; /* process next half of ISR */ |
| 2392 | mch++; /* and move to next channel */ |
| 2393 | } while ((mch < NCHAN) && isr1); /* loop for each chn */ |
| 2394 | |
| 2395 | /* |
| 2396 | * Now that we have done all the urgent things, see if we can fill |
| 2397 | * the transmit buffers. |
| 2398 | */ |
| 2399 | for (mch = 0; mch < NCHAN; mch++) { |
| 2400 | if (dotxstart & 0x0C) { /* TX initiation enabled? */ |
| 2401 | sc = &hc->sc[mch]; |
| 2402 | #ifndef NETGRAPH |
| 2403 | srstart(&sc->ifsppp.pp_if); |
| 2404 | #else |
| 2405 | srstart(sc); |
| 2406 | #endif /* NETGRAPH */ |
| 2407 | } |
| 2408 | dotxstart >>= 4;/* shift for next channel */ |
| 2409 | } |
| 2410 | } |
| 2411 | #ifndef NETGRAPH |
| 2412 | #ifdef USE_MODEMCK |
| 2413 | /* |
| 2414 | * Perform timeout on an FR channel |
| 2415 | * |
| 2416 | * Establish a periodic check of open N2 ports; If |
| 2417 | * a port is open/active, its DCD state is checked |
| 2418 | * and a loss of DCD is recognized (and eventually |
| 2419 | * processed). |
| 2420 | */ |
| 2421 | static void |
| 2422 | sr_modemck(void *arg) |
| 2423 | { |
| 2424 | int card; /* card index in table */ |
| 2425 | int cards; /* card list index */ |
| 2426 | int mch; /* channel on card */ |
| 2427 | u_char dcd_v; /* Data Carrier Detect */ |
| 2428 | u_char got_st0; /* contents of ST0 */ |
| 2429 | u_char got_st1; /* contents of ST1 */ |
| 2430 | u_char got_st2; /* contents of ST2 */ |
| 2431 | u_char got_st3; /* contents of ST3 */ |
| 2432 | struct sr_hardc *hc; /* card's configuration */ |
| 2433 | struct sr_hardc *Card[16];/* up to 16 cards in system */ |
| 2434 | struct sr_softc *sc; /* channel's softc structure */ |
| 2435 | struct ifnet *ifp; /* interface control table */ |
| 2436 | msci_channel *msci; /* regs specific to channel */ |
| 2437 | |
| 2438 | crit_enter(); |
| 2439 | |
| 2440 | #if 0 |
| 2441 | if (sr_opens == 0) { /* count of "up" channels */ |
| 2442 | sr_watcher = 0; /* indicate no watcher */ |
| 2443 | |
| 2444 | crit_exit(); |
| 2445 | |
| 2446 | return; |
| 2447 | } |
| 2448 | #endif |
| 2449 | |
| 2450 | sr_watcher = 1; /* mark that we're online */ |
| 2451 | |
| 2452 | /* |
| 2453 | * Now we'll need a list of cards to process. Since we can handle |
| 2454 | * both ISA and PCI cards (and I didn't think of making this logic |
| 2455 | * global YET) we'll generate a single table of card table |
| 2456 | * addresses. |
| 2457 | */ |
| 2458 | cards = 0; |
| 2459 | |
| 2460 | for (card = 0; card < NSR; card++) { |
| 2461 | hc = &sr_hardc[card]; |
| 2462 | |
| 2463 | if (hc->sc == NULL) |
| 2464 | continue; |
| 2465 | |
| 2466 | Card[cards++] = hc; |
| 2467 | } |
| 2468 | |
| 2469 | hc = sr_hardc_pci; |
| 2470 | |
| 2471 | while (hc) { |
| 2472 | Card[cards++] = hc; |
| 2473 | hc = hc->next; |
| 2474 | } |
| 2475 | |
| 2476 | /* |
| 2477 | * OK, we've got work we can do. Let's do it... (Please note that |
| 2478 | * this code _only_ deals w/ ISA cards) |
| 2479 | */ |
| 2480 | for (card = 0; card < cards; card++) { |
| 2481 | hc = Card[card];/* get card table */ |
| 2482 | |
| 2483 | for (mch = 0; mch < hc->numports; mch++) { |
| 2484 | sc = &hc->sc[mch]; |
| 2485 | |
| 2486 | ifp = &sc->ifsppp.pp_if; |
| 2487 | |
| 2488 | /* |
| 2489 | * if this channel isn't "up", skip it |
| 2490 | */ |
| 2491 | if ((ifp->if_flags & IFF_UP) == 0) |
| 2492 | continue; |
| 2493 | |
| 2494 | /* |
| 2495 | * OK, now we can go looking at this channel's |
| 2496 | * actual register contents... |
| 2497 | */ |
| 2498 | msci = &hc->sca->msci[sc->scachan]; |
| 2499 | |
| 2500 | /* |
| 2501 | * OK, now we'll look into the actual status of this |
| 2502 | * channel... |
| 2503 | * |
| 2504 | * I suck in more registers than strictly needed |
| 2505 | */ |
| 2506 | got_st0 = SRC_GET8(hc->sca_base, msci->st0); |
| 2507 | got_st1 = SRC_GET8(hc->sca_base, msci->st1); |
| 2508 | got_st2 = SRC_GET8(hc->sca_base, msci->st2); |
| 2509 | got_st3 = SRC_GET8(hc->sca_base, msci->st3); |
| 2510 | |
| 2511 | /* |
| 2512 | * We want to see if the DCD signal is up (DCD is |
| 2513 | * true if zero) |
| 2514 | */ |
| 2515 | dcd_v = (got_st3 & SCA_ST3_DCD) == 0; |
| 2516 | |
| 2517 | if (dcd_v == 0) |
| 2518 | kprintf("sr%d: DCD lost\n", sc->unit); |
| 2519 | } |
| 2520 | } |
| 2521 | |
| 2522 | /* |
| 2523 | * OK, now set up for the next modem signal checking pass... |
| 2524 | */ |
| 2525 | timeout(sr_modemck, NULL, hz); |
| 2526 | |
| 2527 | crit_exit(); |
| 2528 | } |
| 2529 | #endif |
| 2530 | #else /* NETGRAPH */ |
| 2531 | /* |
| 2532 | * If a port is open/active, it's DCD state is checked |
| 2533 | * and a loss of DCD is recognized (and eventually processed?). |
| 2534 | */ |
| 2535 | static void |
| 2536 | sr_modemck(struct sr_softc *sc ) |
| 2537 | { |
| 2538 | u_char got_st3; /* contents of ST3 */ |
| 2539 | struct sr_hardc *hc = sc->hc; /* card's configuration */ |
| 2540 | msci_channel *msci; /* regs specific to channel */ |
| 2541 | |
| 2542 | crit_enter(); |
| 2543 | |
| 2544 | if (sc->running == 0) { |
| 2545 | crit_exit(); |
| 2546 | return; |
| 2547 | } |
| 2548 | |
| 2549 | /* |
| 2550 | * OK, now we can go looking at this channel's register contents... |
| 2551 | */ |
| 2552 | msci = &hc->sca->msci[sc->scachan]; |
| 2553 | got_st3 = SRC_GET8(hc->sca_base, msci->st3); |
| 2554 | |
| 2555 | /* |
| 2556 | * We want to see if the DCD signal is up (DCD is true if zero) |
| 2557 | */ |
| 2558 | sc->dcd = (got_st3 & SCA_ST3_DCD) == 0; |
| 2559 | |
| 2560 | crit_exit(); |
| 2561 | } |
| 2562 | |
| 2563 | #endif /* NETGRAPH */ |
| 2564 | static void |
| 2565 | sr_msci_intr(struct sr_hardc *hc, u_char isr0) |
| 2566 | { |
| 2567 | kprintf("src%d: SRINTR: MSCI\n", hc->cunit); |
| 2568 | } |
| 2569 | |
| 2570 | static void |
| 2571 | sr_timer_intr(struct sr_hardc *hc, u_char isr2) |
| 2572 | { |
| 2573 | kprintf("src%d: SRINTR: TIMER\n", hc->cunit); |
| 2574 | } |
| 2575 | |
| 2576 | #ifdef NETGRAPH |
| 2577 | /***************************************** |
| 2578 | * Device timeout/watchdog routine. |
| 2579 | * called once per second. |
| 2580 | * checks to see that if activity was expected, that it hapenned. |
| 2581 | * At present we only look to see if expected output was completed. |
| 2582 | */ |
| 2583 | static void |
| 2584 | ngsr_watchdog_frame(void * arg) |
| 2585 | { |
| 2586 | struct sr_softc * sc = arg; |
| 2587 | int speed; |
| 2588 | |
| 2589 | crit_enter(); |
| 2590 | |
| 2591 | if (sc->running == 0) { |
| 2592 | crit_enter(); |
| 2593 | return; /* if we are not running let timeouts die */ |
| 2594 | } |
| 2595 | /* |
| 2596 | * calculate the apparent throughputs |
| 2597 | * XXX a real hack |
| 2598 | */ |
| 2599 | |
| 2600 | speed = sc->inbytes - sc->lastinbytes; |
| 2601 | sc->lastinbytes = sc->inbytes; |
| 2602 | if ( sc->inrate < speed ) |
| 2603 | sc->inrate = speed; |
| 2604 | speed = sc->outbytes - sc->lastoutbytes; |
| 2605 | sc->lastoutbytes = sc->outbytes; |
| 2606 | if ( sc->outrate < speed ) |
| 2607 | sc->outrate = speed; |
| 2608 | sc->inlast++; |
| 2609 | |
| 2610 | crit_exit(); |
| 2611 | |
| 2612 | if ((sc->inlast > QUITE_A_WHILE) |
| 2613 | && (sc->out_deficit > LOTS_OF_PACKETS)) { |
| 2614 | log(LOG_ERR, "sr%d: No response from remote end\n", sc->unit); |
| 2615 | |
| 2616 | crit_enter(); |
| 2617 | |
| 2618 | sr_down(sc); |
| 2619 | sr_up(sc); |
| 2620 | sc->inlast = sc->out_deficit = 0; |
| 2621 | |
| 2622 | crit_exit(); |
| 2623 | } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */ |
| 2624 | if (sc->out_dog == 0) { |
| 2625 | log(LOG_ERR, "sr%d: Transmit failure.. no clock?\n", |
| 2626 | sc->unit); |
| 2627 | |
| 2628 | crit_enter(); |
| 2629 | |
| 2630 | srwatchdog(sc); |
| 2631 | #if 0 |
| 2632 | sr_down(sc); |
| 2633 | sr_up(sc); |
| 2634 | #endif |
| 2635 | |
| 2636 | crit_exit(); |
| 2637 | |
| 2638 | sc->inlast = sc->out_deficit = 0; |
| 2639 | } else { |
| 2640 | sc->out_dog--; |
| 2641 | } |
| 2642 | } |
| 2643 | sr_modemck(sc); /* update the DCD status */ |
| 2644 | callout_reset(&sc->sr_timer, hz, ngsr_watchdog_frame, sc); |
| 2645 | } |
| 2646 | |
| 2647 | /*********************************************************************** |
| 2648 | * This section contains the methods for the Netgraph interface |
| 2649 | ***********************************************************************/ |
| 2650 | /* |
| 2651 | * It is not possible or allowable to create a node of this type. |
| 2652 | * If the hardware exists, it will already have created it. |
| 2653 | */ |
| 2654 | static int |
| 2655 | ngsr_constructor(node_p *nodep) |
| 2656 | { |
| 2657 | return (EINVAL); |
| 2658 | } |
| 2659 | |
| 2660 | /* |
| 2661 | * give our ok for a hook to be added... |
| 2662 | * If we are not running this should kick the device into life. |
| 2663 | * The hook's private info points to our stash of info about that |
| 2664 | * channel. |
| 2665 | */ |
| 2666 | static int |
| 2667 | ngsr_newhook(node_p node, hook_p hook, const char *name) |
| 2668 | { |
| 2669 | struct sr_softc * sc = node->private; |
| 2670 | |
| 2671 | /* |
| 2672 | * check if it's our friend the debug hook |
| 2673 | */ |
| 2674 | if (strcmp(name, NG_SR_HOOK_DEBUG) == 0) { |
| 2675 | hook->private = NULL; /* paranoid */ |
| 2676 | sc->debug_hook = hook; |
| 2677 | return (0); |
| 2678 | } |
| 2679 | |
| 2680 | /* |
| 2681 | * Check for raw mode hook. |
| 2682 | */ |
| 2683 | if (strcmp(name, NG_SR_HOOK_RAW) != 0) { |
| 2684 | return (EINVAL); |
| 2685 | } |
| 2686 | hook->private = sc; |
| 2687 | sc->hook = hook; |
| 2688 | sc->datahooks++; |
| 2689 | sr_up(sc); |
| 2690 | return (0); |
| 2691 | } |
| 2692 | |
| 2693 | /* |
| 2694 | * incoming messages. |
| 2695 | * Just respond to the generic TEXT_STATUS message |
| 2696 | */ |
| 2697 | static int |
| 2698 | ngsr_rcvmsg(node_p node, |
| 2699 | struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp) |
| 2700 | { |
| 2701 | struct sr_softc * sc; |
| 2702 | int error = 0; |
| 2703 | |
| 2704 | sc = node->private; |
| 2705 | switch (msg->header.typecookie) { |
| 2706 | case NG_SR_COOKIE: |
| 2707 | error = EINVAL; |
| 2708 | break; |
| 2709 | case NGM_GENERIC_COOKIE: |
| 2710 | switch(msg->header.cmd) { |
| 2711 | case NGM_TEXT_STATUS: { |
| 2712 | char *arg; |
| 2713 | int pos = 0; |
| 2714 | int resplen = sizeof(struct ng_mesg) + 512; |
| 2715 | MALLOC(*resp, struct ng_mesg *, resplen, |
| 2716 | M_NETGRAPH, M_INTWAIT | M_ZERO); |
| 2717 | if (*resp == NULL) { |
| 2718 | error = ENOMEM; |
| 2719 | break; |
| 2720 | } |
| 2721 | arg = (*resp)->data; |
| 2722 | |
| 2723 | /* |
| 2724 | * Put in the throughput information. |
| 2725 | */ |
| 2726 | pos = ksprintf(arg, "%ld bytes in, %ld bytes out\n" |
| 2727 | "highest rate seen: %ld B/S in, %ld B/S out\n", |
| 2728 | sc->inbytes, sc->outbytes, |
| 2729 | sc->inrate, sc->outrate); |
| 2730 | pos += ksprintf(arg + pos, |
| 2731 | "%ld output errors\n", |
| 2732 | sc->oerrors); |
| 2733 | pos += ksprintf(arg + pos, |
| 2734 | "ierrors = %ld, %ld, %ld, %ld, %ld, %ld\n", |
| 2735 | sc->ierrors[0], |
| 2736 | sc->ierrors[1], |
| 2737 | sc->ierrors[2], |
| 2738 | sc->ierrors[3], |
| 2739 | sc->ierrors[4], |
| 2740 | sc->ierrors[5]); |
| 2741 | |
| 2742 | (*resp)->header.version = NG_VERSION; |
| 2743 | (*resp)->header.arglen = strlen(arg) + 1; |
| 2744 | (*resp)->header.token = msg->header.token; |
| 2745 | (*resp)->header.typecookie = NG_SR_COOKIE; |
| 2746 | (*resp)->header.cmd = msg->header.cmd; |
| 2747 | strlcpy((*resp)->header.cmdstr, "status", |
| 2748 | NG_CMDSTRSIZ); |
| 2749 | } |
| 2750 | break; |
| 2751 | default: |
| 2752 | error = EINVAL; |
| 2753 | break; |
| 2754 | } |
| 2755 | break; |
| 2756 | default: |
| 2757 | error = EINVAL; |
| 2758 | break; |
| 2759 | } |
| 2760 | kfree(msg, M_NETGRAPH); |
| 2761 | return (error); |
| 2762 | } |
| 2763 | |
| 2764 | /* |
| 2765 | * get data from another node and transmit it to the correct channel |
| 2766 | */ |
| 2767 | static int |
| 2768 | ngsr_rcvdata(hook_p hook, struct mbuf *m, meta_p meta) |
| 2769 | { |
| 2770 | int error = 0; |
| 2771 | struct sr_softc * sc = hook->node->private; |
| 2772 | struct ifqueue *xmitq_p; |
| 2773 | |
| 2774 | /* |
| 2775 | * data doesn't come in from just anywhere (e.g control hook) |
| 2776 | */ |
| 2777 | if ( hook->private == NULL) { |
| 2778 | error = ENETDOWN; |
| 2779 | goto bad; |
| 2780 | } |
| 2781 | |
| 2782 | /* |
| 2783 | * Now queue the data for when it can be sent |
| 2784 | */ |
| 2785 | if (meta && meta->priority > 0) { |
| 2786 | xmitq_p = (&sc->xmitq_hipri); |
| 2787 | } else { |
| 2788 | xmitq_p = (&sc->xmitq); |
| 2789 | } |
| 2790 | |
| 2791 | crit_enter(); |
| 2792 | |
| 2793 | if (IF_QFULL(xmitq_p)) { |
| 2794 | IF_DROP(xmitq_p); |
| 2795 | |
| 2796 | crit_exit(); |
| 2797 | |
| 2798 | error = ENOBUFS; |
| 2799 | goto bad; |
| 2800 | } |
| 2801 | IF_ENQUEUE(xmitq_p, m); |
| 2802 | srstart(sc); |
| 2803 | |
| 2804 | crit_exit(); |
| 2805 | |
| 2806 | return (0); |
| 2807 | |
| 2808 | bad: |
| 2809 | /* |
| 2810 | * It was an error case. |
| 2811 | * check if we need to free the mbuf, and then return the error |
| 2812 | */ |
| 2813 | NG_FREE_DATA(m, meta); |
| 2814 | return (error); |
| 2815 | } |
| 2816 | |
| 2817 | /* |
| 2818 | * do local shutdown processing.. |
| 2819 | * this node will refuse to go away, unless the hardware says to.. |
| 2820 | * don't unref the node, or remove our name. just clear our links up. |
| 2821 | */ |
| 2822 | static int |
| 2823 | ngsr_rmnode(node_p node) |
| 2824 | { |
| 2825 | struct sr_softc * sc = node->private; |
| 2826 | |
| 2827 | sr_down(sc); |
| 2828 | ng_cutlinks(node); |
| 2829 | node->flags &= ~NG_INVALID; /* bounce back to life */ |
| 2830 | return (0); |
| 2831 | } |
| 2832 | |
| 2833 | /* already linked */ |
| 2834 | static int |
| 2835 | ngsr_connect(hook_p hook) |
| 2836 | { |
| 2837 | /* be really amiable and just say "YUP that's OK by me! " */ |
| 2838 | return (0); |
| 2839 | } |
| 2840 | |
| 2841 | /* |
| 2842 | * notify on hook disconnection (destruction) |
| 2843 | * |
| 2844 | * Invalidate the private data associated with this dlci. |
| 2845 | * For this type, removal of the last link resets tries to destroy the node. |
| 2846 | * As the device still exists, the shutdown method will not actually |
| 2847 | * destroy the node, but reset the device and leave it 'fresh' :) |
| 2848 | * |
| 2849 | * The node removal code will remove all references except that owned by the |
| 2850 | * driver. |
| 2851 | */ |
| 2852 | static int |
| 2853 | ngsr_disconnect(hook_p hook) |
| 2854 | { |
| 2855 | struct sr_softc * sc = hook->node->private; |
| 2856 | /* |
| 2857 | * If it's the data hook, then free resources etc. |
| 2858 | */ |
| 2859 | if (hook->private) { |
| 2860 | crit_enter(); |
| 2861 | |
| 2862 | sc->datahooks--; |
| 2863 | if (sc->datahooks == 0) |
| 2864 | sr_down(sc); |
| 2865 | |
| 2866 | crit_exit(); |
| 2867 | } else { |
| 2868 | sc->debug_hook = NULL; |
| 2869 | } |
| 2870 | return (0); |
| 2871 | } |
| 2872 | |
| 2873 | /* |
| 2874 | * called during bootup |
| 2875 | * or LKM loading to put this type into the list of known modules |
| 2876 | */ |
| 2877 | static void |
| 2878 | ngsr_init(void *ignored) |
| 2879 | { |
| 2880 | if (ng_newtype(&typestruct)) |
| 2881 | kprintf("ngsr install failed\n"); |
| 2882 | ngsr_done_init = 1; |
| 2883 | } |
| 2884 | #endif /* NETGRAPH */ |
| 2885 | |
| 2886 | /* |
| 2887 | ********************************* END ************************************ |
| 2888 | */ |