| 1 | /* |
| 2 | * Product specific probe and attach routines for: |
| 3 | * 3940, 2940, aic7895, aic7890, aic7880, |
| 4 | * aic7870, aic7860 and aic7850 SCSI controllers |
| 5 | * |
| 6 | * Copyright (c) 1994-2001 Justin T. Gibbs. |
| 7 | * Copyright (c) 2000-2001 Adaptec Inc. |
| 8 | * All rights reserved. |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or without |
| 11 | * modification, are permitted provided that the following conditions |
| 12 | * are met: |
| 13 | * 1. Redistributions of source code must retain the above copyright |
| 14 | * notice, this list of conditions, and the following disclaimer, |
| 15 | * without modification. |
| 16 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer |
| 17 | * substantially similar to the "NO WARRANTY" disclaimer below |
| 18 | * ("Disclaimer") and any redistribution must be conditioned upon |
| 19 | * including a substantially similar Disclaimer requirement for further |
| 20 | * binary redistribution. |
| 21 | * 3. Neither the names of the above-listed copyright holders nor the names |
| 22 | * of any contributors may be used to endorse or promote products derived |
| 23 | * from this software without specific prior written permission. |
| 24 | * |
| 25 | * Alternatively, this software may be distributed under the terms of the |
| 26 | * GNU General Public License ("GPL") version 2 as published by the Free |
| 27 | * Software Foundation. |
| 28 | * |
| 29 | * NO WARRANTY |
| 30 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 31 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 32 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR |
| 33 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 34 | * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 35 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 36 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 37 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| 38 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
| 39 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 40 | * POSSIBILITY OF SUCH DAMAGES. |
| 41 | * |
| 42 | * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#78 $ |
| 43 | * |
| 44 | * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.33 2004/08/22 14:02:43 gibbs Exp $ |
| 45 | * $DragonFly: src/sys/dev/disk/aic7xxx/aic7xxx_pci.c,v 1.11 2007/07/06 05:40:41 pavalos Exp $ |
| 46 | */ |
| 47 | |
| 48 | #ifdef __linux__ |
| 49 | #include "aic7xxx_osm.h" |
| 50 | #include "aic7xxx_inline.h" |
| 51 | #include "aic7xxx_93cx6.h" |
| 52 | #else |
| 53 | #include "aic7xxx_osm.h" |
| 54 | #include "aic7xxx_inline.h" |
| 55 | #include "aic7xxx_93cx6.h" |
| 56 | #endif |
| 57 | |
| 58 | #ifdef AHC_PCI_CONFIG |
| 59 | |
| 60 | static __inline uint64_t |
| 61 | ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) |
| 62 | { |
| 63 | uint64_t id; |
| 64 | |
| 65 | id = subvendor |
| 66 | | (subdevice << 16) |
| 67 | | ((uint64_t)vendor << 32) |
| 68 | | ((uint64_t)device << 48); |
| 69 | |
| 70 | return (id); |
| 71 | } |
| 72 | |
| 73 | #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull |
| 74 | #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull |
| 75 | #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull |
| 76 | #define ID_9005_SISL_MASK 0x000FFFFF00000000ull |
| 77 | #define ID_9005_SISL_ID 0x0005900500000000ull |
| 78 | #define ID_AIC7850 0x5078900400000000ull |
| 79 | #define ID_AHA_2902_04_10_15_20C_30C 0x5078900478509004ull |
| 80 | #define ID_AIC7855 0x5578900400000000ull |
| 81 | #define ID_AIC7859 0x3860900400000000ull |
| 82 | #define ID_AHA_2930CU 0x3860900438699004ull |
| 83 | #define ID_AIC7860 0x6078900400000000ull |
| 84 | #define ID_AIC7860C 0x6078900478609004ull |
| 85 | #define ID_AHA_1480A 0x6075900400000000ull |
| 86 | #define ID_AHA_2940AU_0 0x6178900400000000ull |
| 87 | #define ID_AHA_2940AU_1 0x6178900478619004ull |
| 88 | #define ID_AHA_2940AU_CN 0x2178900478219004ull |
| 89 | #define ID_AHA_2930C_VAR 0x6038900438689004ull |
| 90 | |
| 91 | #define ID_AIC7870 0x7078900400000000ull |
| 92 | #define ID_AHA_2940 0x7178900400000000ull |
| 93 | #define ID_AHA_3940 0x7278900400000000ull |
| 94 | #define ID_AHA_398X 0x7378900400000000ull |
| 95 | #define ID_AHA_2944 0x7478900400000000ull |
| 96 | #define ID_AHA_3944 0x7578900400000000ull |
| 97 | #define ID_AHA_4944 0x7678900400000000ull |
| 98 | |
| 99 | #define ID_AIC7880 0x8078900400000000ull |
| 100 | #define ID_AIC7880_B 0x8078900478809004ull |
| 101 | #define ID_AHA_2940U 0x8178900400000000ull |
| 102 | #define ID_AHA_3940U 0x8278900400000000ull |
| 103 | #define ID_AHA_2944U 0x8478900400000000ull |
| 104 | #define ID_AHA_3944U 0x8578900400000000ull |
| 105 | #define ID_AHA_398XU 0x8378900400000000ull |
| 106 | #define ID_AHA_4944U 0x8678900400000000ull |
| 107 | #define ID_AHA_2940UB 0x8178900478819004ull |
| 108 | #define ID_AHA_2930U 0x8878900478889004ull |
| 109 | #define ID_AHA_2940U_PRO 0x8778900478879004ull |
| 110 | #define ID_AHA_2940U_CN 0x0078900478009004ull |
| 111 | |
| 112 | #define ID_AIC7895 0x7895900478959004ull |
| 113 | #define ID_AIC7895_ARO 0x7890900478939004ull |
| 114 | #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull |
| 115 | #define ID_AHA_2940U_DUAL 0x7895900478919004ull |
| 116 | #define ID_AHA_3940AU 0x7895900478929004ull |
| 117 | #define ID_AHA_3944AU 0x7895900478949004ull |
| 118 | |
| 119 | #define ID_AIC7890 0x001F9005000F9005ull |
| 120 | #define ID_AIC7890_ARO 0x00139005000F9005ull |
| 121 | #define ID_AAA_131U2 0x0013900500039005ull |
| 122 | #define ID_AHA_2930U2 0x0011900501819005ull |
| 123 | #define ID_AHA_2940U2B 0x00109005A1009005ull |
| 124 | #define ID_AHA_2940U2_OEM 0x0010900521809005ull |
| 125 | #define ID_AHA_2940U2 0x00109005A1809005ull |
| 126 | #define ID_AHA_2950U2B 0x00109005E1009005ull |
| 127 | |
| 128 | #define ID_AIC7892 0x008F9005FFFF9005ull |
| 129 | #define ID_AIC7892_ARO 0x00839005FFFF9005ull |
| 130 | #define ID_AHA_29160 0x00809005E2A09005ull |
| 131 | #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull |
| 132 | #define ID_AHA_29160N 0x0080900562A09005ull |
| 133 | #define ID_AHA_29160C 0x0080900562209005ull |
| 134 | #define ID_AHA_29160B 0x00809005E2209005ull |
| 135 | #define ID_AHA_19160B 0x0081900562A19005ull |
| 136 | #define ID_AHA_2915_30LP 0x0082900502109005ull |
| 137 | |
| 138 | #define ID_AIC7896 0x005F9005FFFF9005ull |
| 139 | #define ID_AIC7896_ARO 0x00539005FFFF9005ull |
| 140 | #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull |
| 141 | #define ID_AHA_3950U2B_1 0x00509005F5009005ull |
| 142 | #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull |
| 143 | #define ID_AHA_3950U2D_1 0x00519005B5009005ull |
| 144 | |
| 145 | #define ID_AIC7899 0x00CF9005FFFF9005ull |
| 146 | #define ID_AIC7899_ARO 0x00C39005FFFF9005ull |
| 147 | #define ID_AHA_3960D 0x00C09005F6209005ull |
| 148 | #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull |
| 149 | |
| 150 | #define ID_AIC7810 0x1078900400000000ull |
| 151 | #define ID_AIC7815 0x7815900400000000ull |
| 152 | |
| 153 | #define DEVID_9005_TYPE(id) ((id) & 0xF) |
| 154 | #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ |
| 155 | #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ |
| 156 | #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ |
| 157 | #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ |
| 158 | |
| 159 | #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) |
| 160 | #define DEVID_9005_MAXRATE_U160 0x0 |
| 161 | #define DEVID_9005_MAXRATE_ULTRA2 0x1 |
| 162 | #define DEVID_9005_MAXRATE_ULTRA 0x2 |
| 163 | #define DEVID_9005_MAXRATE_FAST 0x3 |
| 164 | |
| 165 | #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) |
| 166 | |
| 167 | #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) |
| 168 | #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ |
| 169 | |
| 170 | #define SUBID_9005_TYPE(id) ((id) & 0xF) |
| 171 | #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ |
| 172 | #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ |
| 173 | #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ |
| 174 | #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ |
| 175 | |
| 176 | #define SUBID_9005_TYPE_KNOWN(id) \ |
| 177 | ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ |
| 178 | || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ |
| 179 | || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ |
| 180 | || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) |
| 181 | |
| 182 | #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) |
| 183 | #define SUBID_9005_MAXRATE_ULTRA2 0x0 |
| 184 | #define SUBID_9005_MAXRATE_ULTRA 0x1 |
| 185 | #define SUBID_9005_MAXRATE_U160 0x2 |
| 186 | #define SUBID_9005_MAXRATE_RESERVED 0x3 |
| 187 | |
| 188 | #define SUBID_9005_SEEPTYPE(id) \ |
| 189 | ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ |
| 190 | ? ((id) & 0xC0) >> 6 \ |
| 191 | : ((id) & 0x300) >> 8) |
| 192 | #define SUBID_9005_SEEPTYPE_NONE 0x0 |
| 193 | #define SUBID_9005_SEEPTYPE_1K 0x1 |
| 194 | #define SUBID_9005_SEEPTYPE_2K_4K 0x2 |
| 195 | #define SUBID_9005_SEEPTYPE_RESERVED 0x3 |
| 196 | #define SUBID_9005_AUTOTERM(id) \ |
| 197 | ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ |
| 198 | ? (((id) & 0x400) >> 10) == 0 \ |
| 199 | : (((id) & 0x40) >> 6) == 0) |
| 200 | |
| 201 | #define SUBID_9005_NUMCHAN(id) \ |
| 202 | ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ |
| 203 | ? ((id) & 0x300) >> 8 \ |
| 204 | : ((id) & 0xC00) >> 10) |
| 205 | |
| 206 | #define SUBID_9005_LEGACYCONN(id) \ |
| 207 | ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ |
| 208 | ? 0 \ |
| 209 | : ((id) & 0x80) >> 7) |
| 210 | |
| 211 | #define SUBID_9005_MFUNCENB(id) \ |
| 212 | ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ |
| 213 | ? ((id) & 0x800) >> 11 \ |
| 214 | : ((id) & 0x1000) >> 12) |
| 215 | /* |
| 216 | * Informational only. Should use chip register to be |
| 217 | * certain, but may be use in identification strings. |
| 218 | */ |
| 219 | #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 |
| 220 | #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 |
| 221 | #define SUBID_9005_CARD_SEDIFF_MASK 0x8000 |
| 222 | |
| 223 | static ahc_device_setup_t ahc_aic785X_setup; |
| 224 | static ahc_device_setup_t ahc_aic7860_setup; |
| 225 | static ahc_device_setup_t ahc_apa1480_setup; |
| 226 | static ahc_device_setup_t ahc_aic7870_setup; |
| 227 | static ahc_device_setup_t ahc_aha394X_setup; |
| 228 | static ahc_device_setup_t ahc_aha494X_setup; |
| 229 | static ahc_device_setup_t ahc_aha398X_setup; |
| 230 | static ahc_device_setup_t ahc_aic7880_setup; |
| 231 | static ahc_device_setup_t ahc_aha2940Pro_setup; |
| 232 | static ahc_device_setup_t ahc_aha394XU_setup; |
| 233 | static ahc_device_setup_t ahc_aha398XU_setup; |
| 234 | static ahc_device_setup_t ahc_aic7890_setup; |
| 235 | static ahc_device_setup_t ahc_aic7892_setup; |
| 236 | static ahc_device_setup_t ahc_aic7895_setup; |
| 237 | static ahc_device_setup_t ahc_aic7896_setup; |
| 238 | static ahc_device_setup_t ahc_aic7899_setup; |
| 239 | static ahc_device_setup_t ahc_aha29160C_setup; |
| 240 | static ahc_device_setup_t ahc_raid_setup; |
| 241 | static ahc_device_setup_t ahc_aha394XX_setup; |
| 242 | static ahc_device_setup_t ahc_aha494XX_setup; |
| 243 | static ahc_device_setup_t ahc_aha398XX_setup; |
| 244 | |
| 245 | struct ahc_pci_identity ahc_pci_ident_table [] = |
| 246 | { |
| 247 | /* aic7850 based controllers */ |
| 248 | { |
| 249 | ID_AHA_2902_04_10_15_20C_30C, |
| 250 | ID_ALL_MASK, |
| 251 | "Adaptec 2902/04/10/15/20C/30C SCSI adapter", |
| 252 | ahc_aic785X_setup |
| 253 | }, |
| 254 | /* aic7860 based controllers */ |
| 255 | { |
| 256 | ID_AHA_2930CU, |
| 257 | ID_ALL_MASK, |
| 258 | "Adaptec 2930CU SCSI adapter", |
| 259 | ahc_aic7860_setup |
| 260 | }, |
| 261 | { |
| 262 | ID_AHA_1480A & ID_DEV_VENDOR_MASK, |
| 263 | ID_DEV_VENDOR_MASK, |
| 264 | "Adaptec 1480A Ultra SCSI adapter", |
| 265 | ahc_apa1480_setup |
| 266 | }, |
| 267 | { |
| 268 | ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, |
| 269 | ID_DEV_VENDOR_MASK, |
| 270 | "Adaptec 2940A Ultra SCSI adapter", |
| 271 | ahc_aic7860_setup |
| 272 | }, |
| 273 | { |
| 274 | ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, |
| 275 | ID_DEV_VENDOR_MASK, |
| 276 | "Adaptec 2940A/CN Ultra SCSI adapter", |
| 277 | ahc_aic7860_setup |
| 278 | }, |
| 279 | { |
| 280 | ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, |
| 281 | ID_DEV_VENDOR_MASK, |
| 282 | "Adaptec 2930C Ultra SCSI adapter (VAR)", |
| 283 | ahc_aic7860_setup |
| 284 | }, |
| 285 | /* aic7870 based controllers */ |
| 286 | { |
| 287 | ID_AHA_2940, |
| 288 | ID_ALL_MASK, |
| 289 | "Adaptec 2940 SCSI adapter", |
| 290 | ahc_aic7870_setup |
| 291 | }, |
| 292 | { |
| 293 | ID_AHA_3940, |
| 294 | ID_ALL_MASK, |
| 295 | "Adaptec 3940 SCSI adapter", |
| 296 | ahc_aha394X_setup |
| 297 | }, |
| 298 | { |
| 299 | ID_AHA_398X, |
| 300 | ID_ALL_MASK, |
| 301 | "Adaptec 398X SCSI RAID adapter", |
| 302 | ahc_aha398X_setup |
| 303 | }, |
| 304 | { |
| 305 | ID_AHA_2944, |
| 306 | ID_ALL_MASK, |
| 307 | "Adaptec 2944 SCSI adapter", |
| 308 | ahc_aic7870_setup |
| 309 | }, |
| 310 | { |
| 311 | ID_AHA_3944, |
| 312 | ID_ALL_MASK, |
| 313 | "Adaptec 3944 SCSI adapter", |
| 314 | ahc_aha394X_setup |
| 315 | }, |
| 316 | { |
| 317 | ID_AHA_4944, |
| 318 | ID_ALL_MASK, |
| 319 | "Adaptec 4944 SCSI adapter", |
| 320 | ahc_aha494X_setup |
| 321 | }, |
| 322 | /* aic7880 based controllers */ |
| 323 | { |
| 324 | ID_AHA_2940U & ID_DEV_VENDOR_MASK, |
| 325 | ID_DEV_VENDOR_MASK, |
| 326 | "Adaptec 2940 Ultra SCSI adapter", |
| 327 | ahc_aic7880_setup |
| 328 | }, |
| 329 | { |
| 330 | ID_AHA_3940U & ID_DEV_VENDOR_MASK, |
| 331 | ID_DEV_VENDOR_MASK, |
| 332 | "Adaptec 3940 Ultra SCSI adapter", |
| 333 | ahc_aha394XU_setup |
| 334 | }, |
| 335 | { |
| 336 | ID_AHA_2944U & ID_DEV_VENDOR_MASK, |
| 337 | ID_DEV_VENDOR_MASK, |
| 338 | "Adaptec 2944 Ultra SCSI adapter", |
| 339 | ahc_aic7880_setup |
| 340 | }, |
| 341 | { |
| 342 | ID_AHA_3944U & ID_DEV_VENDOR_MASK, |
| 343 | ID_DEV_VENDOR_MASK, |
| 344 | "Adaptec 3944 Ultra SCSI adapter", |
| 345 | ahc_aha394XU_setup |
| 346 | }, |
| 347 | { |
| 348 | ID_AHA_398XU & ID_DEV_VENDOR_MASK, |
| 349 | ID_DEV_VENDOR_MASK, |
| 350 | "Adaptec 398X Ultra SCSI RAID adapter", |
| 351 | ahc_aha398XU_setup |
| 352 | }, |
| 353 | { |
| 354 | /* |
| 355 | * XXX Don't know the slot numbers |
| 356 | * so we can't identify channels |
| 357 | */ |
| 358 | ID_AHA_4944U & ID_DEV_VENDOR_MASK, |
| 359 | ID_DEV_VENDOR_MASK, |
| 360 | "Adaptec 4944 Ultra SCSI adapter", |
| 361 | ahc_aic7880_setup |
| 362 | }, |
| 363 | { |
| 364 | ID_AHA_2930U & ID_DEV_VENDOR_MASK, |
| 365 | ID_DEV_VENDOR_MASK, |
| 366 | "Adaptec 2930 Ultra SCSI adapter", |
| 367 | ahc_aic7880_setup |
| 368 | }, |
| 369 | { |
| 370 | ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, |
| 371 | ID_DEV_VENDOR_MASK, |
| 372 | "Adaptec 2940 Pro Ultra SCSI adapter", |
| 373 | ahc_aha2940Pro_setup |
| 374 | }, |
| 375 | { |
| 376 | ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, |
| 377 | ID_DEV_VENDOR_MASK, |
| 378 | "Adaptec 2940/CN Ultra SCSI adapter", |
| 379 | ahc_aic7880_setup |
| 380 | }, |
| 381 | /* Ignore all SISL (AAC on MB) based controllers. */ |
| 382 | { |
| 383 | ID_9005_SISL_ID, |
| 384 | ID_9005_SISL_MASK, |
| 385 | NULL, |
| 386 | NULL |
| 387 | }, |
| 388 | /* aic7890 based controllers */ |
| 389 | { |
| 390 | ID_AHA_2930U2, |
| 391 | ID_ALL_MASK, |
| 392 | "Adaptec 2930 Ultra2 SCSI adapter", |
| 393 | ahc_aic7890_setup |
| 394 | }, |
| 395 | { |
| 396 | ID_AHA_2940U2B, |
| 397 | ID_ALL_MASK, |
| 398 | "Adaptec 2940B Ultra2 SCSI adapter", |
| 399 | ahc_aic7890_setup |
| 400 | }, |
| 401 | { |
| 402 | ID_AHA_2940U2_OEM, |
| 403 | ID_ALL_MASK, |
| 404 | "Adaptec 2940 Ultra2 SCSI adapter (OEM)", |
| 405 | ahc_aic7890_setup |
| 406 | }, |
| 407 | { |
| 408 | ID_AHA_2940U2, |
| 409 | ID_ALL_MASK, |
| 410 | "Adaptec 2940 Ultra2 SCSI adapter", |
| 411 | ahc_aic7890_setup |
| 412 | }, |
| 413 | { |
| 414 | ID_AHA_2950U2B, |
| 415 | ID_ALL_MASK, |
| 416 | "Adaptec 2950 Ultra2 SCSI adapter", |
| 417 | ahc_aic7890_setup |
| 418 | }, |
| 419 | { |
| 420 | ID_AIC7890_ARO, |
| 421 | ID_ALL_MASK, |
| 422 | "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)", |
| 423 | ahc_aic7890_setup |
| 424 | }, |
| 425 | { |
| 426 | ID_AAA_131U2, |
| 427 | ID_ALL_MASK, |
| 428 | "Adaptec AAA-131 Ultra2 RAID adapter", |
| 429 | ahc_aic7890_setup |
| 430 | }, |
| 431 | /* aic7892 based controllers */ |
| 432 | { |
| 433 | ID_AHA_29160, |
| 434 | ID_ALL_MASK, |
| 435 | "Adaptec 29160 Ultra160 SCSI adapter", |
| 436 | ahc_aic7892_setup |
| 437 | }, |
| 438 | { |
| 439 | ID_AHA_29160_CPQ, |
| 440 | ID_ALL_MASK, |
| 441 | "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", |
| 442 | ahc_aic7892_setup |
| 443 | }, |
| 444 | { |
| 445 | ID_AHA_29160N, |
| 446 | ID_ALL_MASK, |
| 447 | "Adaptec 29160N Ultra160 SCSI adapter", |
| 448 | ahc_aic7892_setup |
| 449 | }, |
| 450 | { |
| 451 | ID_AHA_29160C, |
| 452 | ID_ALL_MASK, |
| 453 | "Adaptec 29160C Ultra160 SCSI adapter", |
| 454 | ahc_aha29160C_setup |
| 455 | }, |
| 456 | { |
| 457 | ID_AHA_29160B, |
| 458 | ID_ALL_MASK, |
| 459 | "Adaptec 29160B Ultra160 SCSI adapter", |
| 460 | ahc_aic7892_setup |
| 461 | }, |
| 462 | { |
| 463 | ID_AHA_19160B, |
| 464 | ID_ALL_MASK, |
| 465 | "Adaptec 19160B Ultra160 SCSI adapter", |
| 466 | ahc_aic7892_setup |
| 467 | }, |
| 468 | { |
| 469 | ID_AIC7892_ARO, |
| 470 | ID_ALL_MASK, |
| 471 | "Adaptec aic7892 Ultra160 SCSI adapter (ARO)", |
| 472 | ahc_aic7892_setup |
| 473 | }, |
| 474 | { |
| 475 | ID_AHA_2915_30LP, |
| 476 | ID_ALL_MASK, |
| 477 | "Adaptec 2915/30LP Ultra160 SCSI adapter", |
| 478 | ahc_aic7892_setup |
| 479 | }, |
| 480 | /* aic7895 based controllers */ |
| 481 | { |
| 482 | ID_AHA_2940U_DUAL, |
| 483 | ID_ALL_MASK, |
| 484 | "Adaptec 2940/DUAL Ultra SCSI adapter", |
| 485 | ahc_aic7895_setup |
| 486 | }, |
| 487 | { |
| 488 | ID_AHA_3940AU, |
| 489 | ID_ALL_MASK, |
| 490 | "Adaptec 3940A Ultra SCSI adapter", |
| 491 | ahc_aic7895_setup |
| 492 | }, |
| 493 | { |
| 494 | ID_AHA_3944AU, |
| 495 | ID_ALL_MASK, |
| 496 | "Adaptec 3944A Ultra SCSI adapter", |
| 497 | ahc_aic7895_setup |
| 498 | }, |
| 499 | { |
| 500 | ID_AIC7895_ARO, |
| 501 | ID_AIC7895_ARO_MASK, |
| 502 | "Adaptec aic7895 Ultra SCSI adapter (ARO)", |
| 503 | ahc_aic7895_setup |
| 504 | }, |
| 505 | /* aic7896/97 based controllers */ |
| 506 | { |
| 507 | ID_AHA_3950U2B_0, |
| 508 | ID_ALL_MASK, |
| 509 | "Adaptec 3950B Ultra2 SCSI adapter", |
| 510 | ahc_aic7896_setup |
| 511 | }, |
| 512 | { |
| 513 | ID_AHA_3950U2B_1, |
| 514 | ID_ALL_MASK, |
| 515 | "Adaptec 3950B Ultra2 SCSI adapter", |
| 516 | ahc_aic7896_setup |
| 517 | }, |
| 518 | { |
| 519 | ID_AHA_3950U2D_0, |
| 520 | ID_ALL_MASK, |
| 521 | "Adaptec 3950D Ultra2 SCSI adapter", |
| 522 | ahc_aic7896_setup |
| 523 | }, |
| 524 | { |
| 525 | ID_AHA_3950U2D_1, |
| 526 | ID_ALL_MASK, |
| 527 | "Adaptec 3950D Ultra2 SCSI adapter", |
| 528 | ahc_aic7896_setup |
| 529 | }, |
| 530 | { |
| 531 | ID_AIC7896_ARO, |
| 532 | ID_ALL_MASK, |
| 533 | "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)", |
| 534 | ahc_aic7896_setup |
| 535 | }, |
| 536 | /* aic7899 based controllers */ |
| 537 | { |
| 538 | ID_AHA_3960D, |
| 539 | ID_ALL_MASK, |
| 540 | "Adaptec 3960D Ultra160 SCSI adapter", |
| 541 | ahc_aic7899_setup |
| 542 | }, |
| 543 | { |
| 544 | ID_AHA_3960D_CPQ, |
| 545 | ID_ALL_MASK, |
| 546 | "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", |
| 547 | ahc_aic7899_setup |
| 548 | }, |
| 549 | { |
| 550 | ID_AIC7899_ARO, |
| 551 | ID_ALL_MASK, |
| 552 | "Adaptec aic7899 Ultra160 SCSI adapter (ARO)", |
| 553 | ahc_aic7899_setup |
| 554 | }, |
| 555 | /* Generic chip probes for devices we don't know 'exactly' */ |
| 556 | { |
| 557 | ID_AIC7850 & ID_DEV_VENDOR_MASK, |
| 558 | ID_DEV_VENDOR_MASK, |
| 559 | "Adaptec aic7850 SCSI adapter", |
| 560 | ahc_aic785X_setup |
| 561 | }, |
| 562 | { |
| 563 | ID_AIC7855 & ID_DEV_VENDOR_MASK, |
| 564 | ID_DEV_VENDOR_MASK, |
| 565 | "Adaptec aic7855 SCSI adapter", |
| 566 | ahc_aic785X_setup |
| 567 | }, |
| 568 | { |
| 569 | ID_AIC7859 & ID_DEV_VENDOR_MASK, |
| 570 | ID_DEV_VENDOR_MASK, |
| 571 | "Adaptec aic7859 SCSI adapter", |
| 572 | ahc_aic7860_setup |
| 573 | }, |
| 574 | { |
| 575 | ID_AIC7860 & ID_DEV_VENDOR_MASK, |
| 576 | ID_DEV_VENDOR_MASK, |
| 577 | "Adaptec aic7860 Ultra SCSI adapter", |
| 578 | ahc_aic7860_setup |
| 579 | }, |
| 580 | { |
| 581 | ID_AIC7870 & ID_DEV_VENDOR_MASK, |
| 582 | ID_DEV_VENDOR_MASK, |
| 583 | "Adaptec aic7870 SCSI adapter", |
| 584 | ahc_aic7870_setup |
| 585 | }, |
| 586 | { |
| 587 | ID_AIC7880 & ID_DEV_VENDOR_MASK, |
| 588 | ID_DEV_VENDOR_MASK, |
| 589 | "Adaptec aic7880 Ultra SCSI adapter", |
| 590 | ahc_aic7880_setup |
| 591 | }, |
| 592 | { |
| 593 | ID_AIC7890 & ID_9005_GENERIC_MASK, |
| 594 | ID_9005_GENERIC_MASK, |
| 595 | "Adaptec aic7890/91 Ultra2 SCSI adapter", |
| 596 | ahc_aic7890_setup |
| 597 | }, |
| 598 | { |
| 599 | ID_AIC7892 & ID_9005_GENERIC_MASK, |
| 600 | ID_9005_GENERIC_MASK, |
| 601 | "Adaptec aic7892 Ultra160 SCSI adapter", |
| 602 | ahc_aic7892_setup |
| 603 | }, |
| 604 | { |
| 605 | ID_AIC7895 & ID_DEV_VENDOR_MASK, |
| 606 | ID_DEV_VENDOR_MASK, |
| 607 | "Adaptec aic7895 Ultra SCSI adapter", |
| 608 | ahc_aic7895_setup |
| 609 | }, |
| 610 | { |
| 611 | ID_AIC7896 & ID_9005_GENERIC_MASK, |
| 612 | ID_9005_GENERIC_MASK, |
| 613 | "Adaptec aic7896/97 Ultra2 SCSI adapter", |
| 614 | ahc_aic7896_setup |
| 615 | }, |
| 616 | { |
| 617 | ID_AIC7899 & ID_9005_GENERIC_MASK, |
| 618 | ID_9005_GENERIC_MASK, |
| 619 | "Adaptec aic7899 Ultra160 SCSI adapter", |
| 620 | ahc_aic7899_setup |
| 621 | }, |
| 622 | { |
| 623 | ID_AIC7810 & ID_DEV_VENDOR_MASK, |
| 624 | ID_DEV_VENDOR_MASK, |
| 625 | "Adaptec aic7810 RAID memory controller", |
| 626 | ahc_raid_setup |
| 627 | }, |
| 628 | { |
| 629 | ID_AIC7815 & ID_DEV_VENDOR_MASK, |
| 630 | ID_DEV_VENDOR_MASK, |
| 631 | "Adaptec aic7815 RAID memory controller", |
| 632 | ahc_raid_setup |
| 633 | } |
| 634 | }; |
| 635 | |
| 636 | const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); |
| 637 | |
| 638 | #define AHC_394X_SLOT_CHANNEL_A 4 |
| 639 | #define AHC_394X_SLOT_CHANNEL_B 5 |
| 640 | |
| 641 | #define AHC_398X_SLOT_CHANNEL_A 4 |
| 642 | #define AHC_398X_SLOT_CHANNEL_B 8 |
| 643 | #define AHC_398X_SLOT_CHANNEL_C 12 |
| 644 | |
| 645 | #define AHC_494X_SLOT_CHANNEL_A 4 |
| 646 | #define AHC_494X_SLOT_CHANNEL_B 5 |
| 647 | #define AHC_494X_SLOT_CHANNEL_C 6 |
| 648 | #define AHC_494X_SLOT_CHANNEL_D 7 |
| 649 | |
| 650 | #define DEVCONFIG 0x40 |
| 651 | #define PCIERRGENDIS 0x80000000ul |
| 652 | #define SCBSIZE32 0x00010000ul /* aic789X only */ |
| 653 | #define REXTVALID 0x00001000ul /* ultra cards only */ |
| 654 | #define MPORTMODE 0x00000400ul /* aic7870+ only */ |
| 655 | #define RAMPSM 0x00000200ul /* aic7870+ only */ |
| 656 | #define VOLSENSE 0x00000100ul |
| 657 | #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ |
| 658 | #define SCBRAMSEL 0x00000080ul |
| 659 | #define MRDCEN 0x00000040ul |
| 660 | #define EXTSCBTIME 0x00000020ul /* aic7870 only */ |
| 661 | #define EXTSCBPEN 0x00000010ul /* aic7870 only */ |
| 662 | #define BERREN 0x00000008ul |
| 663 | #define DACEN 0x00000004ul |
| 664 | #define STPWLEVEL 0x00000002ul |
| 665 | #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ |
| 666 | |
| 667 | #define CSIZE_LATTIME 0x0c |
| 668 | #define CACHESIZE 0x0000003ful /* only 5 bits */ |
| 669 | #define LATTIME 0x0000ff00ul |
| 670 | |
| 671 | /* PCI STATUS definitions */ |
| 672 | #define DPE 0x80 |
| 673 | #define SSE 0x40 |
| 674 | #define RMA 0x20 |
| 675 | #define RTA 0x10 |
| 676 | #define STA 0x08 |
| 677 | #define DPR 0x01 |
| 678 | |
| 679 | static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, |
| 680 | uint16_t subvendor, uint16_t subdevice); |
| 681 | static int ahc_ext_scbram_present(struct ahc_softc *ahc); |
| 682 | static void ahc_scbram_config(struct ahc_softc *ahc, int enable, |
| 683 | int pcheck, int fast, int large); |
| 684 | static void ahc_probe_ext_scbram(struct ahc_softc *ahc); |
| 685 | static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); |
| 686 | static void ahc_parse_pci_eeprom(struct ahc_softc *ahc, |
| 687 | struct seeprom_config *sc); |
| 688 | static void configure_termination(struct ahc_softc *ahc, |
| 689 | struct seeprom_descriptor *sd, |
| 690 | u_int adapter_control, |
| 691 | u_int *sxfrctl1); |
| 692 | |
| 693 | static void ahc_new_term_detect(struct ahc_softc *ahc, |
| 694 | int *enableSEC_low, |
| 695 | int *enableSEC_high, |
| 696 | int *enablePRI_low, |
| 697 | int *enablePRI_high, |
| 698 | int *eeprom_present); |
| 699 | static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, |
| 700 | int *internal68_present, |
| 701 | int *externalcable_present, |
| 702 | int *eeprom_present); |
| 703 | static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, |
| 704 | int *externalcable_present, |
| 705 | int *eeprom_present); |
| 706 | static void write_brdctl(struct ahc_softc *ahc, uint8_t value); |
| 707 | static uint8_t read_brdctl(struct ahc_softc *ahc); |
| 708 | static void ahc_pci_intr(struct ahc_softc *ahc); |
| 709 | static int ahc_pci_chip_init(struct ahc_softc *ahc); |
| 710 | static int ahc_pci_suspend(struct ahc_softc *ahc); |
| 711 | static int ahc_pci_resume(struct ahc_softc *ahc); |
| 712 | |
| 713 | static int |
| 714 | ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, |
| 715 | uint16_t subdevice, uint16_t subvendor) |
| 716 | { |
| 717 | int result; |
| 718 | |
| 719 | /* Default to invalid. */ |
| 720 | result = 0; |
| 721 | if (vendor == 0x9005 |
| 722 | && subvendor == 0x9005 |
| 723 | && subdevice != device |
| 724 | && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { |
| 725 | |
| 726 | switch (SUBID_9005_TYPE(subdevice)) { |
| 727 | case SUBID_9005_TYPE_MB: |
| 728 | break; |
| 729 | case SUBID_9005_TYPE_CARD: |
| 730 | case SUBID_9005_TYPE_LCCARD: |
| 731 | /* |
| 732 | * Currently only trust Adaptec cards to |
| 733 | * get the sub device info correct. |
| 734 | */ |
| 735 | if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) |
| 736 | result = 1; |
| 737 | break; |
| 738 | case SUBID_9005_TYPE_RAID: |
| 739 | break; |
| 740 | default: |
| 741 | break; |
| 742 | } |
| 743 | } |
| 744 | return (result); |
| 745 | } |
| 746 | |
| 747 | struct ahc_pci_identity * |
| 748 | ahc_find_pci_device(aic_dev_softc_t pci) |
| 749 | { |
| 750 | uint64_t full_id; |
| 751 | uint16_t device; |
| 752 | uint16_t vendor; |
| 753 | uint16_t subdevice; |
| 754 | uint16_t subvendor; |
| 755 | struct ahc_pci_identity *entry; |
| 756 | u_int i; |
| 757 | |
| 758 | vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); |
| 759 | device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); |
| 760 | subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); |
| 761 | subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); |
| 762 | full_id = ahc_compose_id(device, vendor, subdevice, subvendor); |
| 763 | |
| 764 | /* |
| 765 | * If the second function is not hooked up, ignore it. |
| 766 | * Unfortunately, not all MB vendors implement the |
| 767 | * subdevice ID as per the Adaptec spec, so do our best |
| 768 | * to sanity check it prior to accepting the subdevice |
| 769 | * ID as valid. |
| 770 | */ |
| 771 | if (aic_get_pci_function(pci) > 0 |
| 772 | && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice) |
| 773 | && SUBID_9005_MFUNCENB(subdevice) == 0) |
| 774 | return (NULL); |
| 775 | |
| 776 | for (i = 0; i < ahc_num_pci_devs; i++) { |
| 777 | entry = &ahc_pci_ident_table[i]; |
| 778 | if (entry->full_id == (full_id & entry->id_mask)) { |
| 779 | /* Honor exclusion entries. */ |
| 780 | if (entry->name == NULL) |
| 781 | return (NULL); |
| 782 | return (entry); |
| 783 | } |
| 784 | } |
| 785 | return (NULL); |
| 786 | } |
| 787 | |
| 788 | int |
| 789 | ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry) |
| 790 | { |
| 791 | u_int command; |
| 792 | u_int our_id; |
| 793 | u_int sxfrctl1; |
| 794 | u_int scsiseq; |
| 795 | u_int dscommand0; |
| 796 | uint32_t devconfig; |
| 797 | int error; |
| 798 | uint8_t sblkctl; |
| 799 | |
| 800 | our_id = 0; |
| 801 | error = entry->setup(ahc); |
| 802 | if (error != 0) |
| 803 | return (error); |
| 804 | ahc->chip |= AHC_PCI; |
| 805 | ahc->description = entry->name; |
| 806 | |
| 807 | aic_power_state_change(ahc, AIC_POWER_STATE_D0); |
| 808 | |
| 809 | error = ahc_pci_map_registers(ahc); |
| 810 | if (error != 0) |
| 811 | return (error); |
| 812 | |
| 813 | /* |
| 814 | * Before we continue probing the card, ensure that |
| 815 | * its interrupts are *disabled*. We don't want |
| 816 | * a misstep to hang the machine in an interrupt |
| 817 | * storm. |
| 818 | */ |
| 819 | ahc_intr_enable(ahc, FALSE); |
| 820 | |
| 821 | devconfig = aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); |
| 822 | |
| 823 | /* |
| 824 | * If we need to support high memory, enable dual |
| 825 | * address cycles. This bit must be set to enable |
| 826 | * high address bit generation even if we are on a |
| 827 | * 64bit bus (PCI64BIT set in devconfig). |
| 828 | */ |
| 829 | if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { |
| 830 | |
| 831 | if (bootverbose) |
| 832 | kprintf("%s: Enabling 39Bit Addressing\n", |
| 833 | ahc_name(ahc)); |
| 834 | devconfig |= DACEN; |
| 835 | } |
| 836 | |
| 837 | /* Ensure that pci error generation, a test feature, is disabled. */ |
| 838 | devconfig |= PCIERRGENDIS; |
| 839 | |
| 840 | aic_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); |
| 841 | |
| 842 | /* Ensure busmastering is enabled */ |
| 843 | command = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2); |
| 844 | command |= PCIM_CMD_BUSMASTEREN; |
| 845 | |
| 846 | aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2); |
| 847 | |
| 848 | /* On all PCI adapters, we allow SCB paging */ |
| 849 | ahc->flags |= AHC_PAGESCBS; |
| 850 | |
| 851 | error = ahc_softc_init(ahc); |
| 852 | if (error != 0) |
| 853 | return (error); |
| 854 | |
| 855 | /* |
| 856 | * Disable PCI parity error checking. Users typically |
| 857 | * do this to work around broken PCI chipsets that get |
| 858 | * the parity timing wrong and thus generate lots of spurious |
| 859 | * errors. The chip only allows us to disable *all* parity |
| 860 | * error reporting when doing this, so CIO bus, scb ram, and |
| 861 | * scratch ram parity errors will be ignored too. |
| 862 | */ |
| 863 | if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) |
| 864 | ahc->seqctl |= FAILDIS; |
| 865 | |
| 866 | ahc->bus_intr = ahc_pci_intr; |
| 867 | ahc->bus_chip_init = ahc_pci_chip_init; |
| 868 | ahc->bus_suspend = ahc_pci_suspend; |
| 869 | ahc->bus_resume = ahc_pci_resume; |
| 870 | |
| 871 | /* Remeber how the card was setup in case there is no SEEPROM */ |
| 872 | if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { |
| 873 | ahc_pause(ahc); |
| 874 | if ((ahc->features & AHC_ULTRA2) != 0) |
| 875 | our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; |
| 876 | else |
| 877 | our_id = ahc_inb(ahc, SCSIID) & OID; |
| 878 | sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; |
| 879 | scsiseq = ahc_inb(ahc, SCSISEQ); |
| 880 | } else { |
| 881 | sxfrctl1 = STPWEN; |
| 882 | our_id = 7; |
| 883 | scsiseq = 0; |
| 884 | } |
| 885 | |
| 886 | error = ahc_reset(ahc, /*reinit*/FALSE); |
| 887 | if (error != 0) |
| 888 | return (ENXIO); |
| 889 | |
| 890 | if ((ahc->features & AHC_DT) != 0) { |
| 891 | u_int sfunct; |
| 892 | |
| 893 | /* Perform ALT-Mode Setup */ |
| 894 | sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; |
| 895 | ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); |
| 896 | ahc_outb(ahc, OPTIONMODE, |
| 897 | OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); |
| 898 | ahc_outb(ahc, SFUNCT, sfunct); |
| 899 | |
| 900 | /* Normal mode setup */ |
| 901 | ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN |
| 902 | |TARGCRCENDEN); |
| 903 | } |
| 904 | |
| 905 | dscommand0 = ahc_inb(ahc, DSCOMMAND0); |
| 906 | dscommand0 |= MPARCKEN|CACHETHEN; |
| 907 | if ((ahc->features & AHC_ULTRA2) != 0) { |
| 908 | |
| 909 | /* |
| 910 | * DPARCKEN doesn't work correctly on |
| 911 | * some MBs so don't use it. |
| 912 | */ |
| 913 | dscommand0 &= ~DPARCKEN; |
| 914 | } |
| 915 | |
| 916 | /* |
| 917 | * Handle chips that must have cache line |
| 918 | * streaming (dis/en)abled. |
| 919 | */ |
| 920 | if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) |
| 921 | dscommand0 |= CACHETHEN; |
| 922 | |
| 923 | if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) |
| 924 | dscommand0 &= ~CACHETHEN; |
| 925 | |
| 926 | ahc_outb(ahc, DSCOMMAND0, dscommand0); |
| 927 | |
| 928 | ahc->pci_cachesize = |
| 929 | aic_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, |
| 930 | /*bytes*/1) & CACHESIZE; |
| 931 | ahc->pci_cachesize *= 4; |
| 932 | |
| 933 | if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 |
| 934 | && ahc->pci_cachesize == 4) { |
| 935 | |
| 936 | aic_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, |
| 937 | 0, /*bytes*/1); |
| 938 | ahc->pci_cachesize = 0; |
| 939 | } |
| 940 | |
| 941 | /* |
| 942 | * We cannot perform ULTRA speeds without the presense |
| 943 | * of the external precision resistor. |
| 944 | */ |
| 945 | if ((ahc->features & AHC_ULTRA) != 0) { |
| 946 | uint32_t devconfig; |
| 947 | |
| 948 | devconfig = aic_pci_read_config(ahc->dev_softc, |
| 949 | DEVCONFIG, /*bytes*/4); |
| 950 | if ((devconfig & REXTVALID) == 0) |
| 951 | ahc->features &= ~AHC_ULTRA; |
| 952 | } |
| 953 | |
| 954 | /* See if we have a SEEPROM and perform auto-term */ |
| 955 | check_extport(ahc, &sxfrctl1); |
| 956 | |
| 957 | /* |
| 958 | * Take the LED out of diagnostic mode |
| 959 | */ |
| 960 | sblkctl = ahc_inb(ahc, SBLKCTL); |
| 961 | ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); |
| 962 | |
| 963 | if ((ahc->features & AHC_ULTRA2) != 0) { |
| 964 | ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); |
| 965 | } else { |
| 966 | ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); |
| 967 | } |
| 968 | |
| 969 | if (ahc->flags & AHC_USEDEFAULTS) { |
| 970 | /* |
| 971 | * PCI Adapter default setup |
| 972 | * Should only be used if the adapter does not have |
| 973 | * a SEEPROM. |
| 974 | */ |
| 975 | /* See if someone else set us up already */ |
| 976 | if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 |
| 977 | && scsiseq != 0) { |
| 978 | kprintf("%s: Using left over BIOS settings\n", |
| 979 | ahc_name(ahc)); |
| 980 | ahc->flags &= ~AHC_USEDEFAULTS; |
| 981 | ahc->flags |= AHC_BIOS_ENABLED; |
| 982 | } else { |
| 983 | /* |
| 984 | * Assume only one connector and always turn |
| 985 | * on termination. |
| 986 | */ |
| 987 | our_id = 0x07; |
| 988 | sxfrctl1 = STPWEN; |
| 989 | } |
| 990 | ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); |
| 991 | |
| 992 | ahc->our_id = our_id; |
| 993 | } |
| 994 | |
| 995 | /* |
| 996 | * Take a look to see if we have external SRAM. |
| 997 | * We currently do not attempt to use SRAM that is |
| 998 | * shared among multiple controllers. |
| 999 | */ |
| 1000 | ahc_probe_ext_scbram(ahc); |
| 1001 | |
| 1002 | /* |
| 1003 | * Record our termination setting for the |
| 1004 | * generic initialization routine. |
| 1005 | */ |
| 1006 | if ((sxfrctl1 & STPWEN) != 0) |
| 1007 | ahc->flags |= AHC_TERM_ENB_A; |
| 1008 | |
| 1009 | /* |
| 1010 | * Save chip register configuration data for chip resets |
| 1011 | * that occur during runtime and resume events. |
| 1012 | */ |
| 1013 | ahc->bus_softc.pci_softc.devconfig = |
| 1014 | aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); |
| 1015 | ahc->bus_softc.pci_softc.command = |
| 1016 | aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1); |
| 1017 | ahc->bus_softc.pci_softc.csize_lattime = |
| 1018 | aic_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1); |
| 1019 | ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0); |
| 1020 | ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS); |
| 1021 | if ((ahc->features & AHC_DT) != 0) { |
| 1022 | u_int sfunct; |
| 1023 | |
| 1024 | sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; |
| 1025 | ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); |
| 1026 | ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE); |
| 1027 | ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT); |
| 1028 | ahc_outb(ahc, SFUNCT, sfunct); |
| 1029 | ahc->bus_softc.pci_softc.crccontrol1 = |
| 1030 | ahc_inb(ahc, CRCCONTROL1); |
| 1031 | } |
| 1032 | if ((ahc->features & AHC_MULTI_FUNC) != 0) |
| 1033 | ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR); |
| 1034 | |
| 1035 | if ((ahc->features & AHC_ULTRA2) != 0) |
| 1036 | ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH); |
| 1037 | |
| 1038 | /* Core initialization */ |
| 1039 | error = ahc_init(ahc); |
| 1040 | if (error != 0) |
| 1041 | return (error); |
| 1042 | |
| 1043 | /* |
| 1044 | * Allow interrupts now that we are completely setup. |
| 1045 | */ |
| 1046 | error = ahc_pci_map_int(ahc); |
| 1047 | if (error != 0) |
| 1048 | return (error); |
| 1049 | |
| 1050 | /* |
| 1051 | * Link this softc in with all other ahc instances. |
| 1052 | */ |
| 1053 | ahc_softc_insert(ahc); |
| 1054 | return (0); |
| 1055 | } |
| 1056 | |
| 1057 | /* |
| 1058 | * Test for the presense of external sram in an |
| 1059 | * "unshared" configuration. |
| 1060 | */ |
| 1061 | static int |
| 1062 | ahc_ext_scbram_present(struct ahc_softc *ahc) |
| 1063 | { |
| 1064 | u_int chip; |
| 1065 | int ramps; |
| 1066 | int single_user; |
| 1067 | uint32_t devconfig; |
| 1068 | |
| 1069 | chip = ahc->chip & AHC_CHIPID_MASK; |
| 1070 | devconfig = aic_pci_read_config(ahc->dev_softc, |
| 1071 | DEVCONFIG, /*bytes*/4); |
| 1072 | single_user = (devconfig & MPORTMODE) != 0; |
| 1073 | |
| 1074 | if ((ahc->features & AHC_ULTRA2) != 0) |
| 1075 | ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; |
| 1076 | else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) |
| 1077 | /* |
| 1078 | * External SCBRAM arbitration is flakey |
| 1079 | * on these chips. Unfortunately this means |
| 1080 | * we don't use the extra SCB ram space on the |
| 1081 | * 3940AUW. |
| 1082 | */ |
| 1083 | ramps = 0; |
| 1084 | else if (chip >= AHC_AIC7870) |
| 1085 | ramps = (devconfig & RAMPSM) != 0; |
| 1086 | else |
| 1087 | ramps = 0; |
| 1088 | |
| 1089 | if (ramps && single_user) |
| 1090 | return (1); |
| 1091 | return (0); |
| 1092 | } |
| 1093 | |
| 1094 | /* |
| 1095 | * Enable external scbram. |
| 1096 | */ |
| 1097 | static void |
| 1098 | ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, |
| 1099 | int fast, int large) |
| 1100 | { |
| 1101 | uint32_t devconfig; |
| 1102 | |
| 1103 | if (ahc->features & AHC_MULTI_FUNC) { |
| 1104 | /* |
| 1105 | * Set the SCB Base addr (highest address bit) |
| 1106 | * depending on which channel we are. |
| 1107 | */ |
| 1108 | ahc_outb(ahc, SCBBADDR, aic_get_pci_function(ahc->dev_softc)); |
| 1109 | } |
| 1110 | |
| 1111 | ahc->flags &= ~AHC_LSCBS_ENABLED; |
| 1112 | if (large) |
| 1113 | ahc->flags |= AHC_LSCBS_ENABLED; |
| 1114 | devconfig = aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); |
| 1115 | if ((ahc->features & AHC_ULTRA2) != 0) { |
| 1116 | u_int dscommand0; |
| 1117 | |
| 1118 | dscommand0 = ahc_inb(ahc, DSCOMMAND0); |
| 1119 | if (enable) |
| 1120 | dscommand0 &= ~INTSCBRAMSEL; |
| 1121 | else |
| 1122 | dscommand0 |= INTSCBRAMSEL; |
| 1123 | if (large) |
| 1124 | dscommand0 &= ~USCBSIZE32; |
| 1125 | else |
| 1126 | dscommand0 |= USCBSIZE32; |
| 1127 | ahc_outb(ahc, DSCOMMAND0, dscommand0); |
| 1128 | } else { |
| 1129 | if (fast) |
| 1130 | devconfig &= ~EXTSCBTIME; |
| 1131 | else |
| 1132 | devconfig |= EXTSCBTIME; |
| 1133 | if (enable) |
| 1134 | devconfig &= ~SCBRAMSEL; |
| 1135 | else |
| 1136 | devconfig |= SCBRAMSEL; |
| 1137 | if (large) |
| 1138 | devconfig &= ~SCBSIZE32; |
| 1139 | else |
| 1140 | devconfig |= SCBSIZE32; |
| 1141 | } |
| 1142 | if (pcheck) |
| 1143 | devconfig |= EXTSCBPEN; |
| 1144 | else |
| 1145 | devconfig &= ~EXTSCBPEN; |
| 1146 | |
| 1147 | aic_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); |
| 1148 | } |
| 1149 | |
| 1150 | /* |
| 1151 | * Take a look to see if we have external SRAM. |
| 1152 | * We currently do not attempt to use SRAM that is |
| 1153 | * shared among multiple controllers. |
| 1154 | */ |
| 1155 | static void |
| 1156 | ahc_probe_ext_scbram(struct ahc_softc *ahc) |
| 1157 | { |
| 1158 | int num_scbs; |
| 1159 | int test_num_scbs; |
| 1160 | int enable; |
| 1161 | int pcheck; |
| 1162 | int fast; |
| 1163 | int large; |
| 1164 | |
| 1165 | enable = FALSE; |
| 1166 | pcheck = FALSE; |
| 1167 | fast = FALSE; |
| 1168 | large = FALSE; |
| 1169 | num_scbs = 0; |
| 1170 | |
| 1171 | if (ahc_ext_scbram_present(ahc) == 0) |
| 1172 | goto done; |
| 1173 | |
| 1174 | /* |
| 1175 | * Probe for the best parameters to use. |
| 1176 | */ |
| 1177 | ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); |
| 1178 | num_scbs = ahc_probe_scbs(ahc); |
| 1179 | if (num_scbs == 0) { |
| 1180 | /* The SRAM wasn't really present. */ |
| 1181 | goto done; |
| 1182 | } |
| 1183 | enable = TRUE; |
| 1184 | |
| 1185 | /* |
| 1186 | * Clear any outstanding parity error |
| 1187 | * and ensure that parity error reporting |
| 1188 | * is enabled. |
| 1189 | */ |
| 1190 | ahc_outb(ahc, SEQCTL, 0); |
| 1191 | ahc_outb(ahc, CLRINT, CLRPARERR); |
| 1192 | ahc_outb(ahc, CLRINT, CLRBRKADRINT); |
| 1193 | |
| 1194 | /* Now see if we can do parity */ |
| 1195 | ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); |
| 1196 | num_scbs = ahc_probe_scbs(ahc); |
| 1197 | if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 |
| 1198 | || (ahc_inb(ahc, ERROR) & MPARERR) == 0) |
| 1199 | pcheck = TRUE; |
| 1200 | |
| 1201 | /* Clear any resulting parity error */ |
| 1202 | ahc_outb(ahc, CLRINT, CLRPARERR); |
| 1203 | ahc_outb(ahc, CLRINT, CLRBRKADRINT); |
| 1204 | |
| 1205 | /* Now see if we can do fast timing */ |
| 1206 | ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); |
| 1207 | test_num_scbs = ahc_probe_scbs(ahc); |
| 1208 | if (test_num_scbs == num_scbs |
| 1209 | && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 |
| 1210 | || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) |
| 1211 | fast = TRUE; |
| 1212 | |
| 1213 | /* |
| 1214 | * See if we can use large SCBs and still maintain |
| 1215 | * the same overall count of SCBs. |
| 1216 | */ |
| 1217 | if ((ahc->features & AHC_LARGE_SCBS) != 0) { |
| 1218 | ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); |
| 1219 | test_num_scbs = ahc_probe_scbs(ahc); |
| 1220 | if (test_num_scbs >= num_scbs) { |
| 1221 | large = TRUE; |
| 1222 | num_scbs = test_num_scbs; |
| 1223 | if (num_scbs >= 64) { |
| 1224 | /* |
| 1225 | * We have enough space to move the |
| 1226 | * "busy targets table" into SCB space |
| 1227 | * and make it qualify all the way to the |
| 1228 | * lun level. |
| 1229 | */ |
| 1230 | ahc->flags |= AHC_SCB_BTT; |
| 1231 | } |
| 1232 | } |
| 1233 | } |
| 1234 | done: |
| 1235 | /* |
| 1236 | * Disable parity error reporting until we |
| 1237 | * can load instruction ram. |
| 1238 | */ |
| 1239 | ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); |
| 1240 | /* Clear any latched parity error */ |
| 1241 | ahc_outb(ahc, CLRINT, CLRPARERR); |
| 1242 | ahc_outb(ahc, CLRINT, CLRBRKADRINT); |
| 1243 | if (bootverbose && enable) { |
| 1244 | kprintf("%s: External SRAM, %s access%s, %dbytes/SCB\n", |
| 1245 | ahc_name(ahc), fast ? "fast" : "slow", |
| 1246 | pcheck ? ", parity checking enabled" : "", |
| 1247 | large ? 64 : 32); |
| 1248 | } |
| 1249 | ahc_scbram_config(ahc, enable, pcheck, fast, large); |
| 1250 | } |
| 1251 | |
| 1252 | /* |
| 1253 | * Perform some simple tests that should catch situations where |
| 1254 | * our registers are invalidly mapped. |
| 1255 | */ |
| 1256 | int |
| 1257 | ahc_pci_test_register_access(struct ahc_softc *ahc) |
| 1258 | { |
| 1259 | int error; |
| 1260 | u_int status1; |
| 1261 | uint32_t cmd; |
| 1262 | uint8_t hcntrl; |
| 1263 | |
| 1264 | error = EIO; |
| 1265 | |
| 1266 | /* |
| 1267 | * Enable PCI error interrupt status, but suppress NMIs |
| 1268 | * generated by SERR raised due to target aborts. |
| 1269 | */ |
| 1270 | cmd = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2); |
| 1271 | aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, |
| 1272 | cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); |
| 1273 | |
| 1274 | /* |
| 1275 | * First a simple test to see if any |
| 1276 | * registers can be read. Reading |
| 1277 | * HCNTRL has no side effects and has |
| 1278 | * at least one bit that is guaranteed to |
| 1279 | * be zero so it is a good register to |
| 1280 | * use for this test. |
| 1281 | */ |
| 1282 | hcntrl = ahc_inb(ahc, HCNTRL); |
| 1283 | |
| 1284 | if (hcntrl == 0xFF) |
| 1285 | goto fail; |
| 1286 | |
| 1287 | if ((hcntrl & CHIPRST) != 0) { |
| 1288 | /* |
| 1289 | * The chip has not been initialized since |
| 1290 | * PCI/EISA/VLB bus reset. Don't trust |
| 1291 | * "left over BIOS data". |
| 1292 | */ |
| 1293 | ahc->flags |= AHC_NO_BIOS_INIT; |
| 1294 | } |
| 1295 | |
| 1296 | /* |
| 1297 | * Next create a situation where write combining |
| 1298 | * or read prefetching could be initiated by the |
| 1299 | * CPU or host bridge. Our device does not support |
| 1300 | * either, so look for data corruption and/or flagged |
| 1301 | * PCI errors. First pause without causing another |
| 1302 | * chip reset. |
| 1303 | */ |
| 1304 | hcntrl &= ~CHIPRST; |
| 1305 | ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); |
| 1306 | while (ahc_is_paused(ahc) == 0) |
| 1307 | ; |
| 1308 | |
| 1309 | /* Clear any PCI errors that occurred before our driver attached. */ |
| 1310 | status1 = aic_pci_read_config(ahc->dev_softc, |
| 1311 | PCIR_STATUS + 1, /*bytes*/1); |
| 1312 | aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, |
| 1313 | status1, /*bytes*/1); |
| 1314 | ahc_outb(ahc, CLRINT, CLRPARERR); |
| 1315 | |
| 1316 | ahc_outb(ahc, SEQCTL, PERRORDIS); |
| 1317 | ahc_outb(ahc, SCBPTR, 0); |
| 1318 | ahc_outl(ahc, SCB_BASE, 0x5aa555aa); |
| 1319 | if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa) |
| 1320 | goto fail; |
| 1321 | |
| 1322 | status1 = aic_pci_read_config(ahc->dev_softc, |
| 1323 | PCIR_STATUS + 1, /*bytes*/1); |
| 1324 | if ((status1 & STA) != 0) |
| 1325 | goto fail; |
| 1326 | |
| 1327 | error = 0; |
| 1328 | |
| 1329 | fail: |
| 1330 | /* Silently clear any latched errors. */ |
| 1331 | status1 = aic_pci_read_config(ahc->dev_softc, |
| 1332 | PCIR_STATUS + 1, /*bytes*/1); |
| 1333 | aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, |
| 1334 | status1, /*bytes*/1); |
| 1335 | ahc_outb(ahc, CLRINT, CLRPARERR); |
| 1336 | ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); |
| 1337 | aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); |
| 1338 | return (error); |
| 1339 | } |
| 1340 | |
| 1341 | /* |
| 1342 | * Check the external port logic for a serial eeprom |
| 1343 | * and termination/cable detection contrls. |
| 1344 | */ |
| 1345 | static void |
| 1346 | check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) |
| 1347 | { |
| 1348 | struct seeprom_descriptor sd; |
| 1349 | struct seeprom_config *sc; |
| 1350 | int have_seeprom; |
| 1351 | int have_autoterm; |
| 1352 | |
| 1353 | sd.sd_ahc = ahc; |
| 1354 | sd.sd_control_offset = SEECTL; |
| 1355 | sd.sd_status_offset = SEECTL; |
| 1356 | sd.sd_dataout_offset = SEECTL; |
| 1357 | sc = ahc->seep_config; |
| 1358 | |
| 1359 | /* |
| 1360 | * For some multi-channel devices, the c46 is simply too |
| 1361 | * small to work. For the other controller types, we can |
| 1362 | * get our information from either SEEPROM type. Set the |
| 1363 | * type to start our probe with accordingly. |
| 1364 | */ |
| 1365 | if (ahc->flags & AHC_LARGE_SEEPROM) |
| 1366 | sd.sd_chip = C56_66; |
| 1367 | else |
| 1368 | sd.sd_chip = C46; |
| 1369 | |
| 1370 | sd.sd_MS = SEEMS; |
| 1371 | sd.sd_RDY = SEERDY; |
| 1372 | sd.sd_CS = SEECS; |
| 1373 | sd.sd_CK = SEECK; |
| 1374 | sd.sd_DO = SEEDO; |
| 1375 | sd.sd_DI = SEEDI; |
| 1376 | |
| 1377 | have_seeprom = ahc_acquire_seeprom(ahc, &sd); |
| 1378 | if (have_seeprom) { |
| 1379 | |
| 1380 | if (bootverbose) |
| 1381 | kprintf("%s: Reading SEEPROM...", ahc_name(ahc)); |
| 1382 | |
| 1383 | for (;;) { |
| 1384 | u_int start_addr; |
| 1385 | |
| 1386 | start_addr = 32 * (ahc->channel - 'A'); |
| 1387 | |
| 1388 | have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc, |
| 1389 | start_addr, |
| 1390 | sizeof(*sc)/2); |
| 1391 | |
| 1392 | if (have_seeprom) |
| 1393 | have_seeprom = ahc_verify_cksum(sc); |
| 1394 | |
| 1395 | if (have_seeprom != 0 || sd.sd_chip == C56_66) { |
| 1396 | if (bootverbose) { |
| 1397 | if (have_seeprom == 0) |
| 1398 | kprintf ("checksum error\n"); |
| 1399 | else |
| 1400 | kprintf ("done.\n"); |
| 1401 | } |
| 1402 | break; |
| 1403 | } |
| 1404 | sd.sd_chip = C56_66; |
| 1405 | } |
| 1406 | ahc_release_seeprom(&sd); |
| 1407 | |
| 1408 | /* Remember the SEEPROM type for later */ |
| 1409 | if (sd.sd_chip == C56_66) |
| 1410 | ahc->flags |= AHC_LARGE_SEEPROM; |
| 1411 | } |
| 1412 | |
| 1413 | if (!have_seeprom) { |
| 1414 | /* |
| 1415 | * Pull scratch ram settings and treat them as |
| 1416 | * if they are the contents of an seeprom if |
| 1417 | * the 'ADPT' signature is found in SCB2. |
| 1418 | * We manually compose the data as 16bit values |
| 1419 | * to avoid endian issues. |
| 1420 | */ |
| 1421 | ahc_outb(ahc, SCBPTR, 2); |
| 1422 | if (ahc_inb(ahc, SCB_BASE) == 'A' |
| 1423 | && ahc_inb(ahc, SCB_BASE + 1) == 'D' |
| 1424 | && ahc_inb(ahc, SCB_BASE + 2) == 'P' |
| 1425 | && ahc_inb(ahc, SCB_BASE + 3) == 'T') { |
| 1426 | uint16_t *sc_data; |
| 1427 | int i; |
| 1428 | |
| 1429 | sc_data = (uint16_t *)sc; |
| 1430 | for (i = 0; i < 32; i++, sc_data++) { |
| 1431 | int j; |
| 1432 | |
| 1433 | j = i * 2; |
| 1434 | *sc_data = ahc_inb(ahc, SRAM_BASE + j) |
| 1435 | | ahc_inb(ahc, SRAM_BASE + j + 1) << 8; |
| 1436 | } |
| 1437 | have_seeprom = ahc_verify_cksum(sc); |
| 1438 | if (have_seeprom) |
| 1439 | ahc->flags |= AHC_SCB_CONFIG_USED; |
| 1440 | } |
| 1441 | /* |
| 1442 | * Clear any SCB parity errors in case this data and |
| 1443 | * its associated parity was not initialized by the BIOS |
| 1444 | */ |
| 1445 | ahc_outb(ahc, CLRINT, CLRPARERR); |
| 1446 | ahc_outb(ahc, CLRINT, CLRBRKADRINT); |
| 1447 | } |
| 1448 | |
| 1449 | if (!have_seeprom) { |
| 1450 | if (bootverbose) |
| 1451 | kprintf("%s: No SEEPROM available.\n", ahc_name(ahc)); |
| 1452 | ahc->flags |= AHC_USEDEFAULTS; |
| 1453 | kfree(ahc->seep_config, M_DEVBUF); |
| 1454 | ahc->seep_config = NULL; |
| 1455 | sc = NULL; |
| 1456 | } else { |
| 1457 | ahc_parse_pci_eeprom(ahc, sc); |
| 1458 | } |
| 1459 | |
| 1460 | /* |
| 1461 | * Cards that have the external logic necessary to talk to |
| 1462 | * a SEEPROM, are almost certain to have the remaining logic |
| 1463 | * necessary for auto-termination control. This assumption |
| 1464 | * hasn't failed yet... |
| 1465 | */ |
| 1466 | have_autoterm = have_seeprom; |
| 1467 | |
| 1468 | /* |
| 1469 | * Some low-cost chips have SEEPROM and auto-term control built |
| 1470 | * in, instead of using a GAL. They can tell us directly |
| 1471 | * if the termination logic is enabled. |
| 1472 | */ |
| 1473 | if ((ahc->features & AHC_SPIOCAP) != 0) { |
| 1474 | if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0) |
| 1475 | have_autoterm = FALSE; |
| 1476 | } |
| 1477 | |
| 1478 | if (have_autoterm) { |
| 1479 | ahc->flags |= AHC_HAS_TERM_LOGIC; |
| 1480 | ahc_acquire_seeprom(ahc, &sd); |
| 1481 | configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1); |
| 1482 | ahc_release_seeprom(&sd); |
| 1483 | } else if (have_seeprom) { |
| 1484 | *sxfrctl1 &= ~STPWEN; |
| 1485 | if ((sc->adapter_control & CFSTERM) != 0) |
| 1486 | *sxfrctl1 |= STPWEN; |
| 1487 | if (bootverbose) |
| 1488 | kprintf("%s: Low byte termination %sabled\n", |
| 1489 | ahc_name(ahc), |
| 1490 | (*sxfrctl1 & STPWEN) ? "en" : "dis"); |
| 1491 | } |
| 1492 | } |
| 1493 | |
| 1494 | static void |
| 1495 | ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc) |
| 1496 | { |
| 1497 | /* |
| 1498 | * Put the data we've collected down into SRAM |
| 1499 | * where ahc_init will find it. |
| 1500 | */ |
| 1501 | int i; |
| 1502 | int max_targ = sc->max_targets & CFMAXTARG; |
| 1503 | u_int scsi_conf; |
| 1504 | uint16_t discenable; |
| 1505 | uint16_t ultraenb; |
| 1506 | |
| 1507 | discenable = 0; |
| 1508 | ultraenb = 0; |
| 1509 | if ((sc->adapter_control & CFULTRAEN) != 0) { |
| 1510 | /* |
| 1511 | * Determine if this adapter has a "newstyle" |
| 1512 | * SEEPROM format. |
| 1513 | */ |
| 1514 | for (i = 0; i < max_targ; i++) { |
| 1515 | if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) { |
| 1516 | ahc->flags |= AHC_NEWEEPROM_FMT; |
| 1517 | break; |
| 1518 | } |
| 1519 | } |
| 1520 | } |
| 1521 | |
| 1522 | for (i = 0; i < max_targ; i++) { |
| 1523 | u_int scsirate; |
| 1524 | uint16_t target_mask; |
| 1525 | |
| 1526 | target_mask = 0x01 << i; |
| 1527 | if (sc->device_flags[i] & CFDISC) |
| 1528 | discenable |= target_mask; |
| 1529 | if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { |
| 1530 | if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) |
| 1531 | ultraenb |= target_mask; |
| 1532 | } else if ((sc->adapter_control & CFULTRAEN) != 0) { |
| 1533 | ultraenb |= target_mask; |
| 1534 | } |
| 1535 | if ((sc->device_flags[i] & CFXFER) == 0x04 |
| 1536 | && (ultraenb & target_mask) != 0) { |
| 1537 | /* Treat 10MHz as a non-ultra speed */ |
| 1538 | sc->device_flags[i] &= ~CFXFER; |
| 1539 | ultraenb &= ~target_mask; |
| 1540 | } |
| 1541 | if ((ahc->features & AHC_ULTRA2) != 0) { |
| 1542 | u_int offset; |
| 1543 | |
| 1544 | if (sc->device_flags[i] & CFSYNCH) |
| 1545 | offset = MAX_OFFSET_ULTRA2; |
| 1546 | else |
| 1547 | offset = 0; |
| 1548 | ahc_outb(ahc, TARG_OFFSET + i, offset); |
| 1549 | |
| 1550 | /* |
| 1551 | * The ultra enable bits contain the |
| 1552 | * high bit of the ultra2 sync rate |
| 1553 | * field. |
| 1554 | */ |
| 1555 | scsirate = (sc->device_flags[i] & CFXFER) |
| 1556 | | ((ultraenb & target_mask) ? 0x8 : 0x0); |
| 1557 | if (sc->device_flags[i] & CFWIDEB) |
| 1558 | scsirate |= WIDEXFER; |
| 1559 | } else { |
| 1560 | scsirate = (sc->device_flags[i] & CFXFER) << 4; |
| 1561 | if (sc->device_flags[i] & CFSYNCH) |
| 1562 | scsirate |= SOFS; |
| 1563 | if (sc->device_flags[i] & CFWIDEB) |
| 1564 | scsirate |= WIDEXFER; |
| 1565 | } |
| 1566 | ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); |
| 1567 | } |
| 1568 | ahc->our_id = sc->brtime_id & CFSCSIID; |
| 1569 | |
| 1570 | scsi_conf = (ahc->our_id & 0x7); |
| 1571 | if (sc->adapter_control & CFSPARITY) |
| 1572 | scsi_conf |= ENSPCHK; |
| 1573 | if (sc->adapter_control & CFRESETB) |
| 1574 | scsi_conf |= RESET_SCSI; |
| 1575 | |
| 1576 | ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT; |
| 1577 | |
| 1578 | if (sc->bios_control & CFEXTEND) |
| 1579 | ahc->flags |= AHC_EXTENDED_TRANS_A; |
| 1580 | |
| 1581 | if (sc->bios_control & CFBIOSEN) |
| 1582 | ahc->flags |= AHC_BIOS_ENABLED; |
| 1583 | if (ahc->features & AHC_ULTRA |
| 1584 | && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { |
| 1585 | /* Should we enable Ultra mode? */ |
| 1586 | if (!(sc->adapter_control & CFULTRAEN)) |
| 1587 | /* Treat us as a non-ultra card */ |
| 1588 | ultraenb = 0; |
| 1589 | } |
| 1590 | |
| 1591 | if (sc->signature == CFSIGNATURE |
| 1592 | || sc->signature == CFSIGNATURE2) { |
| 1593 | uint32_t devconfig; |
| 1594 | |
| 1595 | /* Honor the STPWLEVEL settings */ |
| 1596 | devconfig = aic_pci_read_config(ahc->dev_softc, |
| 1597 | DEVCONFIG, /*bytes*/4); |
| 1598 | devconfig &= ~STPWLEVEL; |
| 1599 | if ((sc->bios_control & CFSTPWLEVEL) != 0) |
| 1600 | devconfig |= STPWLEVEL; |
| 1601 | aic_pci_write_config(ahc->dev_softc, DEVCONFIG, |
| 1602 | devconfig, /*bytes*/4); |
| 1603 | } |
| 1604 | /* Set SCSICONF info */ |
| 1605 | ahc_outb(ahc, SCSICONF, scsi_conf); |
| 1606 | ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); |
| 1607 | ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); |
| 1608 | ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); |
| 1609 | ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); |
| 1610 | } |
| 1611 | |
| 1612 | static void |
| 1613 | configure_termination(struct ahc_softc *ahc, |
| 1614 | struct seeprom_descriptor *sd, |
| 1615 | u_int adapter_control, |
| 1616 | u_int *sxfrctl1) |
| 1617 | { |
| 1618 | uint8_t brddat; |
| 1619 | |
| 1620 | brddat = 0; |
| 1621 | |
| 1622 | /* |
| 1623 | * Update the settings in sxfrctl1 to match the |
| 1624 | * termination settings |
| 1625 | */ |
| 1626 | *sxfrctl1 = 0; |
| 1627 | |
| 1628 | /* |
| 1629 | * SEECS must be on for the GALS to latch |
| 1630 | * the data properly. Be sure to leave MS |
| 1631 | * on or we will release the seeprom. |
| 1632 | */ |
| 1633 | SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); |
| 1634 | if ((adapter_control & CFAUTOTERM) != 0 |
| 1635 | || (ahc->features & AHC_NEW_TERMCTL) != 0) { |
| 1636 | int internal50_present; |
| 1637 | int internal68_present; |
| 1638 | int externalcable_present; |
| 1639 | int eeprom_present; |
| 1640 | int enableSEC_low; |
| 1641 | int enableSEC_high; |
| 1642 | int enablePRI_low; |
| 1643 | int enablePRI_high; |
| 1644 | int sum; |
| 1645 | |
| 1646 | enableSEC_low = 0; |
| 1647 | enableSEC_high = 0; |
| 1648 | enablePRI_low = 0; |
| 1649 | enablePRI_high = 0; |
| 1650 | if ((ahc->features & AHC_NEW_TERMCTL) != 0) { |
| 1651 | ahc_new_term_detect(ahc, &enableSEC_low, |
| 1652 | &enableSEC_high, |
| 1653 | &enablePRI_low, |
| 1654 | &enablePRI_high, |
| 1655 | &eeprom_present); |
| 1656 | if ((adapter_control & CFSEAUTOTERM) == 0) { |
| 1657 | if (bootverbose) |
| 1658 | kprintf("%s: Manual SE Termination\n", |
| 1659 | ahc_name(ahc)); |
| 1660 | enableSEC_low = (adapter_control & CFSELOWTERM); |
| 1661 | enableSEC_high = |
| 1662 | (adapter_control & CFSEHIGHTERM); |
| 1663 | } |
| 1664 | if ((adapter_control & CFAUTOTERM) == 0) { |
| 1665 | if (bootverbose) |
| 1666 | kprintf("%s: Manual LVD Termination\n", |
| 1667 | ahc_name(ahc)); |
| 1668 | enablePRI_low = (adapter_control & CFSTERM); |
| 1669 | enablePRI_high = (adapter_control & CFWSTERM); |
| 1670 | } |
| 1671 | /* Make the table calculations below happy */ |
| 1672 | internal50_present = 0; |
| 1673 | internal68_present = 1; |
| 1674 | externalcable_present = 1; |
| 1675 | } else if ((ahc->features & AHC_SPIOCAP) != 0) { |
| 1676 | aic785X_cable_detect(ahc, &internal50_present, |
| 1677 | &externalcable_present, |
| 1678 | &eeprom_present); |
| 1679 | /* Can never support a wide connector. */ |
| 1680 | internal68_present = 0; |
| 1681 | } else { |
| 1682 | aic787X_cable_detect(ahc, &internal50_present, |
| 1683 | &internal68_present, |
| 1684 | &externalcable_present, |
| 1685 | &eeprom_present); |
| 1686 | } |
| 1687 | |
| 1688 | if ((ahc->features & AHC_WIDE) == 0) |
| 1689 | internal68_present = 0; |
| 1690 | |
| 1691 | if (bootverbose |
| 1692 | && (ahc->features & AHC_ULTRA2) == 0) { |
| 1693 | kprintf("%s: internal 50 cable %s present", |
| 1694 | ahc_name(ahc), |
| 1695 | internal50_present ? "is":"not"); |
| 1696 | |
| 1697 | if ((ahc->features & AHC_WIDE) != 0) |
| 1698 | kprintf(", internal 68 cable %s present", |
| 1699 | internal68_present ? "is":"not"); |
| 1700 | kprintf("\n%s: external cable %s present\n", |
| 1701 | ahc_name(ahc), |
| 1702 | externalcable_present ? "is":"not"); |
| 1703 | } |
| 1704 | if (bootverbose) |
| 1705 | kprintf("%s: BIOS eeprom %s present\n", |
| 1706 | ahc_name(ahc), eeprom_present ? "is" : "not"); |
| 1707 | |
| 1708 | if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { |
| 1709 | /* |
| 1710 | * The 50 pin connector is a separate bus, |
| 1711 | * so force it to always be terminated. |
| 1712 | * In the future, perform current sensing |
| 1713 | * to determine if we are in the middle of |
| 1714 | * a properly terminated bus. |
| 1715 | */ |
| 1716 | internal50_present = 0; |
| 1717 | } |
| 1718 | |
| 1719 | /* |
| 1720 | * Now set the termination based on what |
| 1721 | * we found. |
| 1722 | * Flash Enable = BRDDAT7 |
| 1723 | * Secondary High Term Enable = BRDDAT6 |
| 1724 | * Secondary Low Term Enable = BRDDAT5 (7890) |
| 1725 | * Primary High Term Enable = BRDDAT4 (7890) |
| 1726 | */ |
| 1727 | if ((ahc->features & AHC_ULTRA2) == 0 |
| 1728 | && (internal50_present != 0) |
| 1729 | && (internal68_present != 0) |
| 1730 | && (externalcable_present != 0)) { |
| 1731 | kprintf("%s: Illegal cable configuration!!. " |
| 1732 | "Only two connectors on the " |
| 1733 | "adapter may be used at a " |
| 1734 | "time!\n", ahc_name(ahc)); |
| 1735 | |
| 1736 | /* |
| 1737 | * Pretend there are no cables in the hope |
| 1738 | * that having all of the termination on |
| 1739 | * gives us a more stable bus. |
| 1740 | */ |
| 1741 | internal50_present = 0; |
| 1742 | internal68_present = 0; |
| 1743 | externalcable_present = 0; |
| 1744 | } |
| 1745 | |
| 1746 | if ((ahc->features & AHC_WIDE) != 0 |
| 1747 | && ((externalcable_present == 0) |
| 1748 | || (internal68_present == 0) |
| 1749 | || (enableSEC_high != 0))) { |
| 1750 | brddat |= BRDDAT6; |
| 1751 | if (bootverbose) { |
| 1752 | if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) |
| 1753 | kprintf("%s: 68 pin termination " |
| 1754 | "Enabled\n", ahc_name(ahc)); |
| 1755 | else |
| 1756 | kprintf("%s: %sHigh byte termination " |
| 1757 | "Enabled\n", ahc_name(ahc), |
| 1758 | enableSEC_high ? "Secondary " |
| 1759 | : ""); |
| 1760 | } |
| 1761 | } |
| 1762 | |
| 1763 | sum = internal50_present + internal68_present |
| 1764 | + externalcable_present; |
| 1765 | if (sum < 2 || (enableSEC_low != 0)) { |
| 1766 | if ((ahc->features & AHC_ULTRA2) != 0) |
| 1767 | brddat |= BRDDAT5; |
| 1768 | else |
| 1769 | *sxfrctl1 |= STPWEN; |
| 1770 | if (bootverbose) { |
| 1771 | if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) |
| 1772 | kprintf("%s: 50 pin termination " |
| 1773 | "Enabled\n", ahc_name(ahc)); |
| 1774 | else |
| 1775 | kprintf("%s: %sLow byte termination " |
| 1776 | "Enabled\n", ahc_name(ahc), |
| 1777 | enableSEC_low ? "Secondary " |
| 1778 | : ""); |
| 1779 | } |
| 1780 | } |
| 1781 | |
| 1782 | if (enablePRI_low != 0) { |
| 1783 | *sxfrctl1 |= STPWEN; |
| 1784 | if (bootverbose) |
| 1785 | kprintf("%s: Primary Low Byte termination " |
| 1786 | "Enabled\n", ahc_name(ahc)); |
| 1787 | } |
| 1788 | |
| 1789 | /* |
| 1790 | * Setup STPWEN before setting up the rest of |
| 1791 | * the termination per the tech note on the U160 cards. |
| 1792 | */ |
| 1793 | ahc_outb(ahc, SXFRCTL1, *sxfrctl1); |
| 1794 | |
| 1795 | if (enablePRI_high != 0) { |
| 1796 | brddat |= BRDDAT4; |
| 1797 | if (bootverbose) |
| 1798 | kprintf("%s: Primary High Byte " |
| 1799 | "termination Enabled\n", |
| 1800 | ahc_name(ahc)); |
| 1801 | } |
| 1802 | |
| 1803 | write_brdctl(ahc, brddat); |
| 1804 | |
| 1805 | } else { |
| 1806 | if ((adapter_control & CFSTERM) != 0) { |
| 1807 | *sxfrctl1 |= STPWEN; |
| 1808 | |
| 1809 | if (bootverbose) |
| 1810 | kprintf("%s: %sLow byte termination Enabled\n", |
| 1811 | ahc_name(ahc), |
| 1812 | (ahc->features & AHC_ULTRA2) ? "Primary " |
| 1813 | : ""); |
| 1814 | } |
| 1815 | |
| 1816 | if ((adapter_control & CFWSTERM) != 0 |
| 1817 | && (ahc->features & AHC_WIDE) != 0) { |
| 1818 | brddat |= BRDDAT6; |
| 1819 | if (bootverbose) |
| 1820 | kprintf("%s: %sHigh byte termination Enabled\n", |
| 1821 | ahc_name(ahc), |
| 1822 | (ahc->features & AHC_ULTRA2) |
| 1823 | ? "Secondary " : ""); |
| 1824 | } |
| 1825 | |
| 1826 | /* |
| 1827 | * Setup STPWEN before setting up the rest of |
| 1828 | * the termination per the tech note on the U160 cards. |
| 1829 | */ |
| 1830 | ahc_outb(ahc, SXFRCTL1, *sxfrctl1); |
| 1831 | |
| 1832 | if ((ahc->features & AHC_WIDE) != 0) |
| 1833 | write_brdctl(ahc, brddat); |
| 1834 | } |
| 1835 | SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ |
| 1836 | } |
| 1837 | |
| 1838 | static void |
| 1839 | ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, |
| 1840 | int *enableSEC_high, int *enablePRI_low, |
| 1841 | int *enablePRI_high, int *eeprom_present) |
| 1842 | { |
| 1843 | uint8_t brdctl; |
| 1844 | |
| 1845 | /* |
| 1846 | * BRDDAT7 = Eeprom |
| 1847 | * BRDDAT6 = Enable Secondary High Byte termination |
| 1848 | * BRDDAT5 = Enable Secondary Low Byte termination |
| 1849 | * BRDDAT4 = Enable Primary high byte termination |
| 1850 | * BRDDAT3 = Enable Primary low byte termination |
| 1851 | */ |
| 1852 | brdctl = read_brdctl(ahc); |
| 1853 | *eeprom_present = brdctl & BRDDAT7; |
| 1854 | *enableSEC_high = (brdctl & BRDDAT6); |
| 1855 | *enableSEC_low = (brdctl & BRDDAT5); |
| 1856 | *enablePRI_high = (brdctl & BRDDAT4); |
| 1857 | *enablePRI_low = (brdctl & BRDDAT3); |
| 1858 | } |
| 1859 | |
| 1860 | static void |
| 1861 | aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, |
| 1862 | int *internal68_present, int *externalcable_present, |
| 1863 | int *eeprom_present) |
| 1864 | { |
| 1865 | uint8_t brdctl; |
| 1866 | |
| 1867 | /* |
| 1868 | * First read the status of our cables. |
| 1869 | * Set the rom bank to 0 since the |
| 1870 | * bank setting serves as a multiplexor |
| 1871 | * for the cable detection logic. |
| 1872 | * BRDDAT5 controls the bank switch. |
| 1873 | */ |
| 1874 | write_brdctl(ahc, 0); |
| 1875 | |
| 1876 | /* |
| 1877 | * Now read the state of the internal |
| 1878 | * connectors. BRDDAT6 is INT50 and |
| 1879 | * BRDDAT7 is INT68. |
| 1880 | */ |
| 1881 | brdctl = read_brdctl(ahc); |
| 1882 | *internal50_present = (brdctl & BRDDAT6) ? 0 : 1; |
| 1883 | *internal68_present = (brdctl & BRDDAT7) ? 0 : 1; |
| 1884 | |
| 1885 | /* |
| 1886 | * Set the rom bank to 1 and determine |
| 1887 | * the other signals. |
| 1888 | */ |
| 1889 | write_brdctl(ahc, BRDDAT5); |
| 1890 | |
| 1891 | /* |
| 1892 | * Now read the state of the external |
| 1893 | * connectors. BRDDAT6 is EXT68 and |
| 1894 | * BRDDAT7 is EPROMPS. |
| 1895 | */ |
| 1896 | brdctl = read_brdctl(ahc); |
| 1897 | *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; |
| 1898 | *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0; |
| 1899 | } |
| 1900 | |
| 1901 | static void |
| 1902 | aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, |
| 1903 | int *externalcable_present, int *eeprom_present) |
| 1904 | { |
| 1905 | uint8_t brdctl; |
| 1906 | uint8_t spiocap; |
| 1907 | |
| 1908 | spiocap = ahc_inb(ahc, SPIOCAP); |
| 1909 | spiocap &= ~SOFTCMDEN; |
| 1910 | spiocap |= EXT_BRDCTL; |
| 1911 | ahc_outb(ahc, SPIOCAP, spiocap); |
| 1912 | ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); |
| 1913 | ahc_flush_device_writes(ahc); |
| 1914 | aic_delay(500); |
| 1915 | ahc_outb(ahc, BRDCTL, 0); |
| 1916 | ahc_flush_device_writes(ahc); |
| 1917 | aic_delay(500); |
| 1918 | brdctl = ahc_inb(ahc, BRDCTL); |
| 1919 | *internal50_present = (brdctl & BRDDAT5) ? 0 : 1; |
| 1920 | *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; |
| 1921 | *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0; |
| 1922 | } |
| 1923 | |
| 1924 | int |
| 1925 | ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) |
| 1926 | { |
| 1927 | int wait; |
| 1928 | |
| 1929 | if ((ahc->features & AHC_SPIOCAP) != 0 |
| 1930 | && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) |
| 1931 | return (0); |
| 1932 | |
| 1933 | /* |
| 1934 | * Request access of the memory port. When access is |
| 1935 | * granted, SEERDY will go high. We use a 1 second |
| 1936 | * timeout which should be near 1 second more than |
| 1937 | * is needed. Reason: after the chip reset, there |
| 1938 | * should be no contention. |
| 1939 | */ |
| 1940 | SEEPROM_OUTB(sd, sd->sd_MS); |
| 1941 | wait = 1000; /* 1 second timeout in msec */ |
| 1942 | while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { |
| 1943 | aic_delay(1000); /* delay 1 msec */ |
| 1944 | } |
| 1945 | if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { |
| 1946 | SEEPROM_OUTB(sd, 0); |
| 1947 | return (0); |
| 1948 | } |
| 1949 | return(1); |
| 1950 | } |
| 1951 | |
| 1952 | void |
| 1953 | ahc_release_seeprom(struct seeprom_descriptor *sd) |
| 1954 | { |
| 1955 | /* Release access to the memory port and the serial EEPROM. */ |
| 1956 | SEEPROM_OUTB(sd, 0); |
| 1957 | } |
| 1958 | |
| 1959 | static void |
| 1960 | write_brdctl(struct ahc_softc *ahc, uint8_t value) |
| 1961 | { |
| 1962 | uint8_t brdctl; |
| 1963 | |
| 1964 | if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { |
| 1965 | brdctl = BRDSTB; |
| 1966 | if (ahc->channel == 'B') |
| 1967 | brdctl |= BRDCS; |
| 1968 | } else if ((ahc->features & AHC_ULTRA2) != 0) { |
| 1969 | brdctl = 0; |
| 1970 | } else { |
| 1971 | brdctl = BRDSTB|BRDCS; |
| 1972 | } |
| 1973 | ahc_outb(ahc, BRDCTL, brdctl); |
| 1974 | ahc_flush_device_writes(ahc); |
| 1975 | brdctl |= value; |
| 1976 | ahc_outb(ahc, BRDCTL, brdctl); |
| 1977 | ahc_flush_device_writes(ahc); |
| 1978 | if ((ahc->features & AHC_ULTRA2) != 0) |
| 1979 | brdctl |= BRDSTB_ULTRA2; |
| 1980 | else |
| 1981 | brdctl &= ~BRDSTB; |
| 1982 | ahc_outb(ahc, BRDCTL, brdctl); |
| 1983 | ahc_flush_device_writes(ahc); |
| 1984 | if ((ahc->features & AHC_ULTRA2) != 0) |
| 1985 | brdctl = 0; |
| 1986 | else |
| 1987 | brdctl &= ~BRDCS; |
| 1988 | ahc_outb(ahc, BRDCTL, brdctl); |
| 1989 | } |
| 1990 | |
| 1991 | static uint8_t |
| 1992 | read_brdctl(struct ahc_softc *ahc) |
| 1993 | { |
| 1994 | uint8_t brdctl; |
| 1995 | uint8_t value; |
| 1996 | |
| 1997 | if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { |
| 1998 | brdctl = BRDRW; |
| 1999 | if (ahc->channel == 'B') |
| 2000 | brdctl |= BRDCS; |
| 2001 | } else if ((ahc->features & AHC_ULTRA2) != 0) { |
| 2002 | brdctl = BRDRW_ULTRA2; |
| 2003 | } else { |
| 2004 | brdctl = BRDRW|BRDCS; |
| 2005 | } |
| 2006 | ahc_outb(ahc, BRDCTL, brdctl); |
| 2007 | ahc_flush_device_writes(ahc); |
| 2008 | value = ahc_inb(ahc, BRDCTL); |
| 2009 | ahc_outb(ahc, BRDCTL, 0); |
| 2010 | return (value); |
| 2011 | } |
| 2012 | |
| 2013 | static void |
| 2014 | ahc_pci_intr(struct ahc_softc *ahc) |
| 2015 | { |
| 2016 | u_int error; |
| 2017 | u_int status1; |
| 2018 | |
| 2019 | error = ahc_inb(ahc, ERROR); |
| 2020 | if ((error & PCIERRSTAT) == 0) |
| 2021 | return; |
| 2022 | |
| 2023 | status1 = aic_pci_read_config(ahc->dev_softc, |
| 2024 | PCIR_STATUS + 1, /*bytes*/1); |
| 2025 | |
| 2026 | kprintf("%s: PCI error Interrupt at seqaddr = 0x%x\n", |
| 2027 | ahc_name(ahc), |
| 2028 | ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); |
| 2029 | |
| 2030 | if (status1 & DPE) { |
| 2031 | ahc->pci_target_perr_count++; |
| 2032 | kprintf("%s: Data Parity Error Detected during address " |
| 2033 | "or write data phase\n", ahc_name(ahc)); |
| 2034 | } |
| 2035 | if (status1 & SSE) { |
| 2036 | kprintf("%s: Signal System Error Detected\n", ahc_name(ahc)); |
| 2037 | } |
| 2038 | if (status1 & RMA) { |
| 2039 | kprintf("%s: Received a Master Abort\n", ahc_name(ahc)); |
| 2040 | } |
| 2041 | if (status1 & RTA) { |
| 2042 | kprintf("%s: Received a Target Abort\n", ahc_name(ahc)); |
| 2043 | } |
| 2044 | if (status1 & STA) { |
| 2045 | kprintf("%s: Signaled a Target Abort\n", ahc_name(ahc)); |
| 2046 | } |
| 2047 | if (status1 & DPR) { |
| 2048 | kprintf("%s: Data Parity Error has been reported via PERR#\n", |
| 2049 | ahc_name(ahc)); |
| 2050 | } |
| 2051 | |
| 2052 | /* Clear latched errors. */ |
| 2053 | aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, |
| 2054 | status1, /*bytes*/1); |
| 2055 | |
| 2056 | if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { |
| 2057 | kprintf("%s: Latched PCIERR interrupt with " |
| 2058 | "no status bits set\n", ahc_name(ahc)); |
| 2059 | } else { |
| 2060 | ahc_outb(ahc, CLRINT, CLRPARERR); |
| 2061 | } |
| 2062 | |
| 2063 | if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH) { |
| 2064 | kprintf( |
| 2065 | "%s: WARNING WARNING WARNING WARNING\n" |
| 2066 | "%s: Too many PCI parity errors observed as a target.\n" |
| 2067 | "%s: Some device on this bus is generating bad parity.\n" |
| 2068 | "%s: This is an error *observed by*, not *generated by*, this controller.\n" |
| 2069 | "%s: PCI parity error checking has been disabled.\n" |
| 2070 | "%s: WARNING WARNING WARNING WARNING\n", |
| 2071 | ahc_name(ahc), ahc_name(ahc), ahc_name(ahc), |
| 2072 | ahc_name(ahc), ahc_name(ahc), ahc_name(ahc)); |
| 2073 | ahc->seqctl |= FAILDIS; |
| 2074 | ahc_outb(ahc, SEQCTL, ahc->seqctl); |
| 2075 | } |
| 2076 | ahc_unpause(ahc); |
| 2077 | } |
| 2078 | |
| 2079 | static int |
| 2080 | ahc_pci_chip_init(struct ahc_softc *ahc) |
| 2081 | { |
| 2082 | ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0); |
| 2083 | ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus); |
| 2084 | if ((ahc->features & AHC_DT) != 0) { |
| 2085 | u_int sfunct; |
| 2086 | |
| 2087 | sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; |
| 2088 | ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); |
| 2089 | ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode); |
| 2090 | ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt); |
| 2091 | ahc_outb(ahc, SFUNCT, sfunct); |
| 2092 | ahc_outb(ahc, CRCCONTROL1, |
| 2093 | ahc->bus_softc.pci_softc.crccontrol1); |
| 2094 | } |
| 2095 | if ((ahc->features & AHC_MULTI_FUNC) != 0) |
| 2096 | ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr); |
| 2097 | |
| 2098 | if ((ahc->features & AHC_ULTRA2) != 0) |
| 2099 | ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh); |
| 2100 | |
| 2101 | return (ahc_chip_init(ahc)); |
| 2102 | } |
| 2103 | |
| 2104 | static int |
| 2105 | ahc_pci_suspend(struct ahc_softc *ahc) |
| 2106 | { |
| 2107 | return (ahc_suspend(ahc)); |
| 2108 | } |
| 2109 | |
| 2110 | static int |
| 2111 | ahc_pci_resume(struct ahc_softc *ahc) |
| 2112 | { |
| 2113 | |
| 2114 | aic_power_state_change(ahc, AIC_POWER_STATE_D0); |
| 2115 | |
| 2116 | /* |
| 2117 | * We assume that the OS has restored our register |
| 2118 | * mappings, etc. Just update the config space registers |
| 2119 | * that the OS doesn't know about and rely on our chip |
| 2120 | * reset handler to handle the rest. |
| 2121 | */ |
| 2122 | aic_pci_write_config(ahc->dev_softc, DEVCONFIG, |
| 2123 | ahc->bus_softc.pci_softc.devconfig, /*bytes*/4); |
| 2124 | aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, |
| 2125 | ahc->bus_softc.pci_softc.command, /*bytes*/1); |
| 2126 | aic_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, |
| 2127 | ahc->bus_softc.pci_softc.csize_lattime, |
| 2128 | /*bytes*/1); |
| 2129 | if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) { |
| 2130 | struct seeprom_descriptor sd; |
| 2131 | u_int sxfrctl1; |
| 2132 | |
| 2133 | sd.sd_ahc = ahc; |
| 2134 | sd.sd_control_offset = SEECTL; |
| 2135 | sd.sd_status_offset = SEECTL; |
| 2136 | sd.sd_dataout_offset = SEECTL; |
| 2137 | |
| 2138 | ahc_acquire_seeprom(ahc, &sd); |
| 2139 | configure_termination(ahc, &sd, |
| 2140 | ahc->seep_config->adapter_control, |
| 2141 | &sxfrctl1); |
| 2142 | ahc_release_seeprom(&sd); |
| 2143 | } |
| 2144 | return (ahc_resume(ahc)); |
| 2145 | } |
| 2146 | |
| 2147 | static int |
| 2148 | ahc_aic785X_setup(struct ahc_softc *ahc) |
| 2149 | { |
| 2150 | aic_dev_softc_t pci; |
| 2151 | uint8_t rev; |
| 2152 | |
| 2153 | pci = ahc->dev_softc; |
| 2154 | ahc->channel = 'A'; |
| 2155 | ahc->chip = AHC_AIC7850; |
| 2156 | ahc->features = AHC_AIC7850_FE; |
| 2157 | ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; |
| 2158 | rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1); |
| 2159 | if (rev >= 1) |
| 2160 | ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; |
| 2161 | ahc->instruction_ram_size = 512; |
| 2162 | return (0); |
| 2163 | } |
| 2164 | |
| 2165 | static int |
| 2166 | ahc_aic7860_setup(struct ahc_softc *ahc) |
| 2167 | { |
| 2168 | aic_dev_softc_t pci; |
| 2169 | uint8_t rev; |
| 2170 | |
| 2171 | pci = ahc->dev_softc; |
| 2172 | ahc->channel = 'A'; |
| 2173 | ahc->chip = AHC_AIC7860; |
| 2174 | ahc->features = AHC_AIC7860_FE; |
| 2175 | ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; |
| 2176 | rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1); |
| 2177 | if (rev >= 1) |
| 2178 | ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; |
| 2179 | ahc->instruction_ram_size = 512; |
| 2180 | return (0); |
| 2181 | } |
| 2182 | |
| 2183 | static int |
| 2184 | ahc_apa1480_setup(struct ahc_softc *ahc) |
| 2185 | { |
| 2186 | int error; |
| 2187 | |
| 2188 | error = ahc_aic7860_setup(ahc); |
| 2189 | if (error != 0) |
| 2190 | return (error); |
| 2191 | ahc->features |= AHC_REMOVABLE; |
| 2192 | return (0); |
| 2193 | } |
| 2194 | |
| 2195 | static int |
| 2196 | ahc_aic7870_setup(struct ahc_softc *ahc) |
| 2197 | { |
| 2198 | |
| 2199 | ahc->channel = 'A'; |
| 2200 | ahc->chip = AHC_AIC7870; |
| 2201 | ahc->features = AHC_AIC7870_FE; |
| 2202 | ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; |
| 2203 | ahc->instruction_ram_size = 512; |
| 2204 | return (0); |
| 2205 | } |
| 2206 | |
| 2207 | static int |
| 2208 | ahc_aha394X_setup(struct ahc_softc *ahc) |
| 2209 | { |
| 2210 | int error; |
| 2211 | |
| 2212 | error = ahc_aic7870_setup(ahc); |
| 2213 | if (error == 0) |
| 2214 | error = ahc_aha394XX_setup(ahc); |
| 2215 | return (error); |
| 2216 | } |
| 2217 | |
| 2218 | static int |
| 2219 | ahc_aha398X_setup(struct ahc_softc *ahc) |
| 2220 | { |
| 2221 | int error; |
| 2222 | |
| 2223 | error = ahc_aic7870_setup(ahc); |
| 2224 | if (error == 0) |
| 2225 | error = ahc_aha398XX_setup(ahc); |
| 2226 | return (error); |
| 2227 | } |
| 2228 | |
| 2229 | static int |
| 2230 | ahc_aha494X_setup(struct ahc_softc *ahc) |
| 2231 | { |
| 2232 | int error; |
| 2233 | |
| 2234 | error = ahc_aic7870_setup(ahc); |
| 2235 | if (error == 0) |
| 2236 | error = ahc_aha494XX_setup(ahc); |
| 2237 | return (error); |
| 2238 | } |
| 2239 | |
| 2240 | static int |
| 2241 | ahc_aic7880_setup(struct ahc_softc *ahc) |
| 2242 | { |
| 2243 | aic_dev_softc_t pci; |
| 2244 | uint8_t rev; |
| 2245 | |
| 2246 | pci = ahc->dev_softc; |
| 2247 | ahc->channel = 'A'; |
| 2248 | ahc->chip = AHC_AIC7880; |
| 2249 | ahc->features = AHC_AIC7880_FE; |
| 2250 | ahc->bugs |= AHC_TMODE_WIDEODD_BUG; |
| 2251 | rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1); |
| 2252 | if (rev >= 1) { |
| 2253 | ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; |
| 2254 | } else { |
| 2255 | ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; |
| 2256 | } |
| 2257 | ahc->instruction_ram_size = 512; |
| 2258 | return (0); |
| 2259 | } |
| 2260 | |
| 2261 | static int |
| 2262 | ahc_aha2940Pro_setup(struct ahc_softc *ahc) |
| 2263 | { |
| 2264 | |
| 2265 | ahc->flags |= AHC_INT50_SPEEDFLEX; |
| 2266 | return (ahc_aic7880_setup(ahc)); |
| 2267 | } |
| 2268 | |
| 2269 | static int |
| 2270 | ahc_aha394XU_setup(struct ahc_softc *ahc) |
| 2271 | { |
| 2272 | int error; |
| 2273 | |
| 2274 | error = ahc_aic7880_setup(ahc); |
| 2275 | if (error == 0) |
| 2276 | error = ahc_aha394XX_setup(ahc); |
| 2277 | return (error); |
| 2278 | } |
| 2279 | |
| 2280 | static int |
| 2281 | ahc_aha398XU_setup(struct ahc_softc *ahc) |
| 2282 | { |
| 2283 | int error; |
| 2284 | |
| 2285 | error = ahc_aic7880_setup(ahc); |
| 2286 | if (error == 0) |
| 2287 | error = ahc_aha398XX_setup(ahc); |
| 2288 | return (error); |
| 2289 | } |
| 2290 | |
| 2291 | static int |
| 2292 | ahc_aic7890_setup(struct ahc_softc *ahc) |
| 2293 | { |
| 2294 | aic_dev_softc_t pci; |
| 2295 | uint8_t rev; |
| 2296 | |
| 2297 | pci = ahc->dev_softc; |
| 2298 | ahc->channel = 'A'; |
| 2299 | ahc->chip = AHC_AIC7890; |
| 2300 | ahc->features = AHC_AIC7890_FE; |
| 2301 | ahc->flags |= AHC_NEWEEPROM_FMT; |
| 2302 | rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1); |
| 2303 | if (rev == 0) |
| 2304 | ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; |
| 2305 | ahc->instruction_ram_size = 768; |
| 2306 | return (0); |
| 2307 | } |
| 2308 | |
| 2309 | static int |
| 2310 | ahc_aic7892_setup(struct ahc_softc *ahc) |
| 2311 | { |
| 2312 | |
| 2313 | ahc->channel = 'A'; |
| 2314 | ahc->chip = AHC_AIC7892; |
| 2315 | ahc->features = AHC_AIC7892_FE; |
| 2316 | ahc->flags |= AHC_NEWEEPROM_FMT; |
| 2317 | ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; |
| 2318 | ahc->instruction_ram_size = 1024; |
| 2319 | return (0); |
| 2320 | } |
| 2321 | |
| 2322 | static int |
| 2323 | ahc_aic7895_setup(struct ahc_softc *ahc) |
| 2324 | { |
| 2325 | aic_dev_softc_t pci; |
| 2326 | uint8_t rev; |
| 2327 | |
| 2328 | pci = ahc->dev_softc; |
| 2329 | ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A'; |
| 2330 | /* |
| 2331 | * The 'C' revision of the aic7895 has a few additional features. |
| 2332 | */ |
| 2333 | rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1); |
| 2334 | if (rev >= 4) { |
| 2335 | ahc->chip = AHC_AIC7895C; |
| 2336 | ahc->features = AHC_AIC7895C_FE; |
| 2337 | } else { |
| 2338 | u_int command; |
| 2339 | |
| 2340 | ahc->chip = AHC_AIC7895; |
| 2341 | ahc->features = AHC_AIC7895_FE; |
| 2342 | |
| 2343 | /* |
| 2344 | * The BIOS disables the use of MWI transactions |
| 2345 | * since it does not have the MWI bug work around |
| 2346 | * we have. Disabling MWI reduces performance, so |
| 2347 | * turn it on again. |
| 2348 | */ |
| 2349 | command = aic_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1); |
| 2350 | command |= PCIM_CMD_MWRICEN; |
| 2351 | aic_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1); |
| 2352 | ahc->bugs |= AHC_PCI_MWI_BUG; |
| 2353 | } |
| 2354 | /* |
| 2355 | * XXX Does CACHETHEN really not work??? What about PCI retry? |
| 2356 | * on C level chips. Need to test, but for now, play it safe. |
| 2357 | */ |
| 2358 | ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG |
| 2359 | | AHC_CACHETHEN_BUG; |
| 2360 | |
| 2361 | #if 0 |
| 2362 | uint32_t devconfig; |
| 2363 | |
| 2364 | /* |
| 2365 | * Cachesize must also be zero due to stray DAC |
| 2366 | * problem when sitting behind some bridges. |
| 2367 | */ |
| 2368 | aic_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1); |
| 2369 | devconfig = aic_pci_read_config(pci, DEVCONFIG, /*bytes*/1); |
| 2370 | devconfig |= MRDCEN; |
| 2371 | aic_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1); |
| 2372 | #endif |
| 2373 | ahc->flags |= AHC_NEWEEPROM_FMT; |
| 2374 | ahc->instruction_ram_size = 512; |
| 2375 | return (0); |
| 2376 | } |
| 2377 | |
| 2378 | static int |
| 2379 | ahc_aic7896_setup(struct ahc_softc *ahc) |
| 2380 | { |
| 2381 | aic_dev_softc_t pci; |
| 2382 | |
| 2383 | pci = ahc->dev_softc; |
| 2384 | ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A'; |
| 2385 | ahc->chip = AHC_AIC7896; |
| 2386 | ahc->features = AHC_AIC7896_FE; |
| 2387 | ahc->flags |= AHC_NEWEEPROM_FMT; |
| 2388 | ahc->bugs |= AHC_CACHETHEN_DIS_BUG; |
| 2389 | ahc->instruction_ram_size = 768; |
| 2390 | return (0); |
| 2391 | } |
| 2392 | |
| 2393 | static int |
| 2394 | ahc_aic7899_setup(struct ahc_softc *ahc) |
| 2395 | { |
| 2396 | aic_dev_softc_t pci; |
| 2397 | |
| 2398 | pci = ahc->dev_softc; |
| 2399 | ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A'; |
| 2400 | ahc->chip = AHC_AIC7899; |
| 2401 | ahc->features = AHC_AIC7899_FE; |
| 2402 | ahc->flags |= AHC_NEWEEPROM_FMT; |
| 2403 | ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; |
| 2404 | ahc->instruction_ram_size = 1024; |
| 2405 | return (0); |
| 2406 | } |
| 2407 | |
| 2408 | static int |
| 2409 | ahc_aha29160C_setup(struct ahc_softc *ahc) |
| 2410 | { |
| 2411 | int error; |
| 2412 | |
| 2413 | error = ahc_aic7899_setup(ahc); |
| 2414 | if (error != 0) |
| 2415 | return (error); |
| 2416 | ahc->features |= AHC_REMOVABLE; |
| 2417 | return (0); |
| 2418 | } |
| 2419 | |
| 2420 | static int |
| 2421 | ahc_raid_setup(struct ahc_softc *ahc) |
| 2422 | { |
| 2423 | kprintf("RAID functionality unsupported\n"); |
| 2424 | return (ENXIO); |
| 2425 | } |
| 2426 | |
| 2427 | static int |
| 2428 | ahc_aha394XX_setup(struct ahc_softc *ahc) |
| 2429 | { |
| 2430 | aic_dev_softc_t pci; |
| 2431 | |
| 2432 | pci = ahc->dev_softc; |
| 2433 | switch (aic_get_pci_slot(pci)) { |
| 2434 | case AHC_394X_SLOT_CHANNEL_A: |
| 2435 | ahc->channel = 'A'; |
| 2436 | break; |
| 2437 | case AHC_394X_SLOT_CHANNEL_B: |
| 2438 | ahc->channel = 'B'; |
| 2439 | break; |
| 2440 | default: |
| 2441 | kprintf("adapter at unexpected slot %d\n" |
| 2442 | "unable to map to a channel\n", |
| 2443 | aic_get_pci_slot(pci)); |
| 2444 | ahc->channel = 'A'; |
| 2445 | } |
| 2446 | return (0); |
| 2447 | } |
| 2448 | |
| 2449 | static int |
| 2450 | ahc_aha398XX_setup(struct ahc_softc *ahc) |
| 2451 | { |
| 2452 | aic_dev_softc_t pci; |
| 2453 | |
| 2454 | pci = ahc->dev_softc; |
| 2455 | switch (aic_get_pci_slot(pci)) { |
| 2456 | case AHC_398X_SLOT_CHANNEL_A: |
| 2457 | ahc->channel = 'A'; |
| 2458 | break; |
| 2459 | case AHC_398X_SLOT_CHANNEL_B: |
| 2460 | ahc->channel = 'B'; |
| 2461 | break; |
| 2462 | case AHC_398X_SLOT_CHANNEL_C: |
| 2463 | ahc->channel = 'C'; |
| 2464 | break; |
| 2465 | default: |
| 2466 | kprintf("adapter at unexpected slot %d\n" |
| 2467 | "unable to map to a channel\n", |
| 2468 | aic_get_pci_slot(pci)); |
| 2469 | ahc->channel = 'A'; |
| 2470 | break; |
| 2471 | } |
| 2472 | ahc->flags |= AHC_LARGE_SEEPROM; |
| 2473 | return (0); |
| 2474 | } |
| 2475 | |
| 2476 | static int |
| 2477 | ahc_aha494XX_setup(struct ahc_softc *ahc) |
| 2478 | { |
| 2479 | aic_dev_softc_t pci; |
| 2480 | |
| 2481 | pci = ahc->dev_softc; |
| 2482 | switch (aic_get_pci_slot(pci)) { |
| 2483 | case AHC_494X_SLOT_CHANNEL_A: |
| 2484 | ahc->channel = 'A'; |
| 2485 | break; |
| 2486 | case AHC_494X_SLOT_CHANNEL_B: |
| 2487 | ahc->channel = 'B'; |
| 2488 | break; |
| 2489 | case AHC_494X_SLOT_CHANNEL_C: |
| 2490 | ahc->channel = 'C'; |
| 2491 | break; |
| 2492 | case AHC_494X_SLOT_CHANNEL_D: |
| 2493 | ahc->channel = 'D'; |
| 2494 | break; |
| 2495 | default: |
| 2496 | kprintf("adapter at unexpected slot %d\n" |
| 2497 | "unable to map to a channel\n", |
| 2498 | aic_get_pci_slot(pci)); |
| 2499 | ahc->channel = 'A'; |
| 2500 | } |
| 2501 | ahc->flags |= AHC_LARGE_SEEPROM; |
| 2502 | return (0); |
| 2503 | } |
| 2504 | |
| 2505 | #endif |