| 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | |
| 29 | #ifndef __RADEON_OBJECT_H__ |
| 30 | #define __RADEON_OBJECT_H__ |
| 31 | |
| 32 | #include <drm/radeon_drm.h> |
| 33 | #include "radeon.h" |
| 34 | |
| 35 | /** |
| 36 | * radeon_mem_type_to_domain - return domain corresponding to mem_type |
| 37 | * @mem_type: ttm memory type |
| 38 | * |
| 39 | * Returns corresponding domain of the ttm mem_type |
| 40 | */ |
| 41 | static inline unsigned radeon_mem_type_to_domain(u32 mem_type) |
| 42 | { |
| 43 | switch (mem_type) { |
| 44 | case TTM_PL_VRAM: |
| 45 | return RADEON_GEM_DOMAIN_VRAM; |
| 46 | case TTM_PL_TT: |
| 47 | return RADEON_GEM_DOMAIN_GTT; |
| 48 | case TTM_PL_SYSTEM: |
| 49 | return RADEON_GEM_DOMAIN_CPU; |
| 50 | default: |
| 51 | break; |
| 52 | } |
| 53 | return 0; |
| 54 | } |
| 55 | |
| 56 | int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr); |
| 57 | |
| 58 | static inline void radeon_bo_unreserve(struct radeon_bo *bo) |
| 59 | { |
| 60 | ttm_bo_unreserve(&bo->tbo); |
| 61 | } |
| 62 | |
| 63 | /** |
| 64 | * radeon_bo_gpu_offset - return GPU offset of bo |
| 65 | * @bo: radeon object for which we query the offset |
| 66 | * |
| 67 | * Returns current GPU offset of the object. |
| 68 | * |
| 69 | * Note: object should either be pinned or reserved when calling this |
| 70 | * function, it might be useful to add check for this for debugging. |
| 71 | */ |
| 72 | static inline u64 radeon_bo_gpu_offset(struct radeon_bo *bo) |
| 73 | { |
| 74 | return bo->tbo.offset; |
| 75 | } |
| 76 | |
| 77 | static inline unsigned long radeon_bo_size(struct radeon_bo *bo) |
| 78 | { |
| 79 | return bo->tbo.num_pages << PAGE_SHIFT; |
| 80 | } |
| 81 | |
| 82 | static inline unsigned radeon_bo_ngpu_pages(struct radeon_bo *bo) |
| 83 | { |
| 84 | return (bo->tbo.num_pages << PAGE_SHIFT) / RADEON_GPU_PAGE_SIZE; |
| 85 | } |
| 86 | |
| 87 | static inline unsigned radeon_bo_gpu_page_alignment(struct radeon_bo *bo) |
| 88 | { |
| 89 | return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / RADEON_GPU_PAGE_SIZE; |
| 90 | } |
| 91 | |
| 92 | /** |
| 93 | * radeon_bo_mmap_offset - return mmap offset of bo |
| 94 | * @bo: radeon object for which we query the offset |
| 95 | * |
| 96 | * Returns mmap offset of the object. |
| 97 | */ |
| 98 | static inline u64 radeon_bo_mmap_offset(struct radeon_bo *bo) |
| 99 | { |
| 100 | return drm_vma_node_offset_addr(&bo->tbo.vma_node); |
| 101 | } |
| 102 | |
| 103 | extern int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, |
| 104 | bool no_wait); |
| 105 | |
| 106 | extern int radeon_bo_create(struct radeon_device *rdev, |
| 107 | unsigned long size, int byte_align, |
| 108 | bool kernel, u32 domain, u32 flags, |
| 109 | struct sg_table *sg, |
| 110 | struct radeon_bo **bo_ptr); |
| 111 | extern int radeon_bo_kmap(struct radeon_bo *bo, void **ptr); |
| 112 | extern void radeon_bo_kunmap(struct radeon_bo *bo); |
| 113 | extern struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo); |
| 114 | extern void radeon_bo_unref(struct radeon_bo **bo); |
| 115 | extern int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr); |
| 116 | extern int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, |
| 117 | u64 max_offset, u64 *gpu_addr); |
| 118 | extern int radeon_bo_unpin(struct radeon_bo *bo); |
| 119 | extern int radeon_bo_evict_vram(struct radeon_device *rdev); |
| 120 | extern void radeon_bo_force_delete(struct radeon_device *rdev); |
| 121 | extern int radeon_bo_init(struct radeon_device *rdev); |
| 122 | extern void radeon_bo_fini(struct radeon_device *rdev); |
| 123 | extern int radeon_bo_list_validate(struct radeon_device *rdev, |
| 124 | struct ww_acquire_ctx *ticket, |
| 125 | struct list_head *head, int ring); |
| 126 | extern int radeon_bo_set_tiling_flags(struct radeon_bo *bo, |
| 127 | u32 tiling_flags, u32 pitch); |
| 128 | extern void radeon_bo_get_tiling_flags(struct radeon_bo *bo, |
| 129 | u32 *tiling_flags, u32 *pitch); |
| 130 | extern int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, |
| 131 | bool force_drop); |
| 132 | extern void radeon_bo_move_notify(struct ttm_buffer_object *bo, |
| 133 | struct ttm_mem_reg *new_mem); |
| 134 | extern int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo); |
| 135 | extern int radeon_bo_get_surface_reg(struct radeon_bo *bo); |
| 136 | |
| 137 | /* |
| 138 | * sub allocation |
| 139 | */ |
| 140 | |
| 141 | static inline uint64_t radeon_sa_bo_gpu_addr(struct radeon_sa_bo *sa_bo) |
| 142 | { |
| 143 | return sa_bo->manager->gpu_addr + sa_bo->soffset; |
| 144 | } |
| 145 | |
| 146 | static inline void * radeon_sa_bo_cpu_addr(struct radeon_sa_bo *sa_bo) |
| 147 | { |
| 148 | return (char *)sa_bo->manager->cpu_ptr + sa_bo->soffset; |
| 149 | } |
| 150 | |
| 151 | extern int radeon_sa_bo_manager_init(struct radeon_device *rdev, |
| 152 | struct radeon_sa_manager *sa_manager, |
| 153 | unsigned size, u32 align, u32 domain, |
| 154 | u32 flags); |
| 155 | extern void radeon_sa_bo_manager_fini(struct radeon_device *rdev, |
| 156 | struct radeon_sa_manager *sa_manager); |
| 157 | extern int radeon_sa_bo_manager_start(struct radeon_device *rdev, |
| 158 | struct radeon_sa_manager *sa_manager); |
| 159 | extern int radeon_sa_bo_manager_suspend(struct radeon_device *rdev, |
| 160 | struct radeon_sa_manager *sa_manager); |
| 161 | extern int radeon_sa_bo_new(struct radeon_device *rdev, |
| 162 | struct radeon_sa_manager *sa_manager, |
| 163 | struct radeon_sa_bo **sa_bo, |
| 164 | unsigned size, unsigned align); |
| 165 | extern void radeon_sa_bo_free(struct radeon_device *rdev, |
| 166 | struct radeon_sa_bo **sa_bo, |
| 167 | struct radeon_fence *fence); |
| 168 | #if defined(CONFIG_DEBUG_FS) |
| 169 | extern void radeon_sa_bo_dump_debug_info(struct radeon_sa_manager *sa_manager, |
| 170 | struct seq_file *m); |
| 171 | #endif |
| 172 | |
| 173 | |
| 174 | #endif |