| 1 | /*- |
| 2 | * Copyright (c) 1995, David Greenman |
| 3 | * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> |
| 4 | * All rights reserved. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice unmodified, this list of conditions, and the following |
| 11 | * disclaimer. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 17 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 20 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 21 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 22 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 26 | * SUCH DAMAGE. |
| 27 | * |
| 28 | * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $ |
| 29 | * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.35 2005/06/15 11:15:37 joerg Exp $ |
| 30 | */ |
| 31 | |
| 32 | /* |
| 33 | * Intel EtherExpress Pro/100B PCI Fast Ethernet driver |
| 34 | */ |
| 35 | |
| 36 | #include <sys/param.h> |
| 37 | #include <sys/systm.h> |
| 38 | #include <sys/mbuf.h> |
| 39 | #include <sys/malloc.h> |
| 40 | #include <sys/kernel.h> |
| 41 | #include <sys/socket.h> |
| 42 | #include <sys/sysctl.h> |
| 43 | #include <sys/thread2.h> |
| 44 | |
| 45 | #include <net/if.h> |
| 46 | #include <net/ifq_var.h> |
| 47 | #include <net/if_dl.h> |
| 48 | #include <net/if_media.h> |
| 49 | |
| 50 | #ifdef NS |
| 51 | #include <netns/ns.h> |
| 52 | #include <netns/ns_if.h> |
| 53 | #endif |
| 54 | |
| 55 | #include <net/bpf.h> |
| 56 | #include <sys/sockio.h> |
| 57 | #include <sys/bus.h> |
| 58 | #include <machine/bus.h> |
| 59 | #include <sys/rman.h> |
| 60 | #include <machine/resource.h> |
| 61 | |
| 62 | #include <net/ethernet.h> |
| 63 | #include <net/if_arp.h> |
| 64 | |
| 65 | #include <vm/vm.h> /* for vtophys */ |
| 66 | #include <vm/pmap.h> /* for vtophys */ |
| 67 | |
| 68 | #include <net/if_types.h> |
| 69 | #include <net/vlan/if_vlan_var.h> |
| 70 | |
| 71 | #include <bus/pci/pcivar.h> |
| 72 | #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */ |
| 73 | |
| 74 | #include "../mii_layer/mii.h" |
| 75 | #include "../mii_layer/miivar.h" |
| 76 | |
| 77 | #include "if_fxpreg.h" |
| 78 | #include "if_fxpvar.h" |
| 79 | #include "rcvbundl.h" |
| 80 | |
| 81 | #include "miibus_if.h" |
| 82 | |
| 83 | /* |
| 84 | * NOTE! On the Alpha, we have an alignment constraint. The |
| 85 | * card DMAs the packet immediately following the RFA. However, |
| 86 | * the first thing in the packet is a 14-byte Ethernet header. |
| 87 | * This means that the packet is misaligned. To compensate, |
| 88 | * we actually offset the RFA 2 bytes into the cluster. This |
| 89 | * alignes the packet after the Ethernet header at a 32-bit |
| 90 | * boundary. HOWEVER! This means that the RFA is misaligned! |
| 91 | */ |
| 92 | #define RFA_ALIGNMENT_FUDGE 2 |
| 93 | |
| 94 | /* |
| 95 | * Set initial transmit threshold at 64 (512 bytes). This is |
| 96 | * increased by 64 (512 bytes) at a time, to maximum of 192 |
| 97 | * (1536 bytes), if an underrun occurs. |
| 98 | */ |
| 99 | static int tx_threshold = 64; |
| 100 | |
| 101 | /* |
| 102 | * The configuration byte map has several undefined fields which |
| 103 | * must be one or must be zero. Set up a template for these bits |
| 104 | * only, (assuming a 82557 chip) leaving the actual configuration |
| 105 | * to fxp_init. |
| 106 | * |
| 107 | * See struct fxp_cb_config for the bit definitions. |
| 108 | */ |
| 109 | static u_char fxp_cb_config_template[] = { |
| 110 | 0x0, 0x0, /* cb_status */ |
| 111 | 0x0, 0x0, /* cb_command */ |
| 112 | 0x0, 0x0, 0x0, 0x0, /* link_addr */ |
| 113 | 0x0, /* 0 */ |
| 114 | 0x0, /* 1 */ |
| 115 | 0x0, /* 2 */ |
| 116 | 0x0, /* 3 */ |
| 117 | 0x0, /* 4 */ |
| 118 | 0x0, /* 5 */ |
| 119 | 0x32, /* 6 */ |
| 120 | 0x0, /* 7 */ |
| 121 | 0x0, /* 8 */ |
| 122 | 0x0, /* 9 */ |
| 123 | 0x6, /* 10 */ |
| 124 | 0x0, /* 11 */ |
| 125 | 0x0, /* 12 */ |
| 126 | 0x0, /* 13 */ |
| 127 | 0xf2, /* 14 */ |
| 128 | 0x48, /* 15 */ |
| 129 | 0x0, /* 16 */ |
| 130 | 0x40, /* 17 */ |
| 131 | 0xf0, /* 18 */ |
| 132 | 0x0, /* 19 */ |
| 133 | 0x3f, /* 20 */ |
| 134 | 0x5 /* 21 */ |
| 135 | }; |
| 136 | |
| 137 | struct fxp_ident { |
| 138 | u_int16_t devid; |
| 139 | int16_t revid; /* -1 matches anything */ |
| 140 | char *name; |
| 141 | }; |
| 142 | |
| 143 | /* |
| 144 | * Claim various Intel PCI device identifiers for this driver. The |
| 145 | * sub-vendor and sub-device field are extensively used to identify |
| 146 | * particular variants, but we don't currently differentiate between |
| 147 | * them. |
| 148 | */ |
| 149 | static struct fxp_ident fxp_ident_table[] = { |
| 150 | { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, |
| 151 | { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, |
| 152 | { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, |
| 153 | { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, |
| 154 | { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, |
| 155 | { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, |
| 156 | { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, |
| 157 | { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, |
| 158 | { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, |
| 159 | { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, |
| 160 | { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, |
| 161 | { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, |
| 162 | { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, |
| 163 | { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, |
| 164 | { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, |
| 165 | { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, |
| 166 | { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, |
| 167 | { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, |
| 168 | { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, |
| 169 | { 0x1064, -1, "Intel 82562ET/EZ/GT/GZ (ICH6/ICH6R) Pro/100 VE Ethernet" }, |
| 170 | { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, |
| 171 | { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, |
| 172 | { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, |
| 173 | { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, |
| 174 | { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, |
| 175 | { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, |
| 176 | { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, |
| 177 | { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, |
| 178 | { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, |
| 179 | { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, |
| 180 | { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, |
| 181 | { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, |
| 182 | { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, |
| 183 | { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, |
| 184 | { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, |
| 185 | { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, |
| 186 | { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, |
| 187 | { 0, -1, NULL }, |
| 188 | }; |
| 189 | |
| 190 | static int fxp_probe(device_t dev); |
| 191 | static int fxp_attach(device_t dev); |
| 192 | static int fxp_detach(device_t dev); |
| 193 | static int fxp_shutdown(device_t dev); |
| 194 | static int fxp_suspend(device_t dev); |
| 195 | static int fxp_resume(device_t dev); |
| 196 | |
| 197 | static void fxp_intr(void *xsc); |
| 198 | static void fxp_intr_body(struct fxp_softc *sc, |
| 199 | u_int8_t statack, int count); |
| 200 | |
| 201 | static void fxp_init(void *xsc); |
| 202 | static void fxp_tick(void *xsc); |
| 203 | static void fxp_powerstate_d0(device_t dev); |
| 204 | static void fxp_start(struct ifnet *ifp); |
| 205 | static void fxp_stop(struct fxp_softc *sc); |
| 206 | static void fxp_release(device_t dev); |
| 207 | static int fxp_ioctl(struct ifnet *ifp, u_long command, |
| 208 | caddr_t data, struct ucred *); |
| 209 | static void fxp_watchdog(struct ifnet *ifp); |
| 210 | static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); |
| 211 | static int fxp_mc_addrs(struct fxp_softc *sc); |
| 212 | static void fxp_mc_setup(struct fxp_softc *sc); |
| 213 | static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, |
| 214 | int autosize); |
| 215 | static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, |
| 216 | u_int16_t data); |
| 217 | static void fxp_autosize_eeprom(struct fxp_softc *sc); |
| 218 | static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, |
| 219 | int offset, int words); |
| 220 | static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, |
| 221 | int offset, int words); |
| 222 | static int fxp_ifmedia_upd(struct ifnet *ifp); |
| 223 | static void fxp_ifmedia_sts(struct ifnet *ifp, |
| 224 | struct ifmediareq *ifmr); |
| 225 | static int fxp_serial_ifmedia_upd(struct ifnet *ifp); |
| 226 | static void fxp_serial_ifmedia_sts(struct ifnet *ifp, |
| 227 | struct ifmediareq *ifmr); |
| 228 | static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); |
| 229 | static void fxp_miibus_writereg(device_t dev, int phy, int reg, |
| 230 | int value); |
| 231 | static void fxp_load_ucode(struct fxp_softc *sc); |
| 232 | static int sysctl_int_range(SYSCTL_HANDLER_ARGS, |
| 233 | int low, int high); |
| 234 | static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); |
| 235 | static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); |
| 236 | #ifdef DEVICE_POLLING |
| 237 | static poll_handler_t fxp_poll; |
| 238 | #endif |
| 239 | |
| 240 | static void fxp_lwcopy(volatile u_int32_t *src, |
| 241 | volatile u_int32_t *dst); |
| 242 | static void fxp_scb_wait(struct fxp_softc *sc); |
| 243 | static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); |
| 244 | static void fxp_dma_wait(volatile u_int16_t *status, |
| 245 | struct fxp_softc *sc); |
| 246 | |
| 247 | static device_method_t fxp_methods[] = { |
| 248 | /* Device interface */ |
| 249 | DEVMETHOD(device_probe, fxp_probe), |
| 250 | DEVMETHOD(device_attach, fxp_attach), |
| 251 | DEVMETHOD(device_detach, fxp_detach), |
| 252 | DEVMETHOD(device_shutdown, fxp_shutdown), |
| 253 | DEVMETHOD(device_suspend, fxp_suspend), |
| 254 | DEVMETHOD(device_resume, fxp_resume), |
| 255 | |
| 256 | /* MII interface */ |
| 257 | DEVMETHOD(miibus_readreg, fxp_miibus_readreg), |
| 258 | DEVMETHOD(miibus_writereg, fxp_miibus_writereg), |
| 259 | |
| 260 | { 0, 0 } |
| 261 | }; |
| 262 | |
| 263 | static driver_t fxp_driver = { |
| 264 | "fxp", |
| 265 | fxp_methods, |
| 266 | sizeof(struct fxp_softc), |
| 267 | }; |
| 268 | |
| 269 | static devclass_t fxp_devclass; |
| 270 | |
| 271 | DECLARE_DUMMY_MODULE(if_fxp); |
| 272 | MODULE_DEPEND(if_fxp, miibus, 1, 1, 1); |
| 273 | DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); |
| 274 | DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); |
| 275 | DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); |
| 276 | |
| 277 | static int fxp_rnr; |
| 278 | SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); |
| 279 | |
| 280 | /* |
| 281 | * Copy a 16-bit aligned 32-bit quantity. |
| 282 | */ |
| 283 | static void |
| 284 | fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) |
| 285 | { |
| 286 | #ifdef __i386__ |
| 287 | *dst = *src; |
| 288 | #else |
| 289 | volatile u_int16_t *a = (volatile u_int16_t *)src; |
| 290 | volatile u_int16_t *b = (volatile u_int16_t *)dst; |
| 291 | |
| 292 | b[0] = a[0]; |
| 293 | b[1] = a[1]; |
| 294 | #endif |
| 295 | } |
| 296 | |
| 297 | /* |
| 298 | * Wait for the previous command to be accepted (but not necessarily |
| 299 | * completed). |
| 300 | */ |
| 301 | static void |
| 302 | fxp_scb_wait(struct fxp_softc *sc) |
| 303 | { |
| 304 | int i = 10000; |
| 305 | |
| 306 | while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) |
| 307 | DELAY(2); |
| 308 | if (i == 0) { |
| 309 | if_printf(&sc->arpcom.ac_if, |
| 310 | "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", |
| 311 | CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), |
| 312 | CSR_READ_1(sc, FXP_CSR_SCB_STATACK), |
| 313 | CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), |
| 314 | CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); |
| 315 | } |
| 316 | } |
| 317 | |
| 318 | static void |
| 319 | fxp_scb_cmd(struct fxp_softc *sc, int cmd) |
| 320 | { |
| 321 | |
| 322 | if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { |
| 323 | CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); |
| 324 | fxp_scb_wait(sc); |
| 325 | } |
| 326 | CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); |
| 327 | } |
| 328 | |
| 329 | static void |
| 330 | fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) |
| 331 | { |
| 332 | int i = 10000; |
| 333 | |
| 334 | while (!(*status & FXP_CB_STATUS_C) && --i) |
| 335 | DELAY(2); |
| 336 | if (i == 0) |
| 337 | if_printf(&sc->arpcom.ac_if, "DMA timeout\n"); |
| 338 | } |
| 339 | |
| 340 | /* |
| 341 | * Return identification string if this is device is ours. |
| 342 | */ |
| 343 | static int |
| 344 | fxp_probe(device_t dev) |
| 345 | { |
| 346 | u_int16_t devid; |
| 347 | u_int8_t revid; |
| 348 | struct fxp_ident *ident; |
| 349 | |
| 350 | if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { |
| 351 | devid = pci_get_device(dev); |
| 352 | revid = pci_get_revid(dev); |
| 353 | for (ident = fxp_ident_table; ident->name != NULL; ident++) { |
| 354 | if (ident->devid == devid && |
| 355 | (ident->revid == revid || ident->revid == -1)) { |
| 356 | device_set_desc(dev, ident->name); |
| 357 | return (0); |
| 358 | } |
| 359 | } |
| 360 | } |
| 361 | return (ENXIO); |
| 362 | } |
| 363 | |
| 364 | static void |
| 365 | fxp_powerstate_d0(device_t dev) |
| 366 | { |
| 367 | u_int32_t iobase, membase, irq; |
| 368 | |
| 369 | if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { |
| 370 | /* Save important PCI config data. */ |
| 371 | iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); |
| 372 | membase = pci_read_config(dev, FXP_PCI_MMBA, 4); |
| 373 | irq = pci_read_config(dev, PCIR_INTLINE, 4); |
| 374 | |
| 375 | /* Reset the power state. */ |
| 376 | device_printf(dev, "chip is in D%d power mode " |
| 377 | "-- setting to D0\n", pci_get_powerstate(dev)); |
| 378 | |
| 379 | pci_set_powerstate(dev, PCI_POWERSTATE_D0); |
| 380 | |
| 381 | /* Restore PCI config data. */ |
| 382 | pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); |
| 383 | pci_write_config(dev, FXP_PCI_MMBA, membase, 4); |
| 384 | pci_write_config(dev, PCIR_INTLINE, irq, 4); |
| 385 | } |
| 386 | } |
| 387 | |
| 388 | static int |
| 389 | fxp_attach(device_t dev) |
| 390 | { |
| 391 | int error = 0; |
| 392 | struct fxp_softc *sc = device_get_softc(dev); |
| 393 | struct ifnet *ifp; |
| 394 | u_int32_t val; |
| 395 | u_int16_t data; |
| 396 | int i, rid, m1, m2, prefer_iomap; |
| 397 | |
| 398 | callout_init(&sc->fxp_stat_timer); |
| 399 | sysctl_ctx_init(&sc->sysctl_ctx); |
| 400 | |
| 401 | /* |
| 402 | * Enable bus mastering. Enable memory space too, in case |
| 403 | * BIOS/Prom forgot about it. |
| 404 | */ |
| 405 | pci_enable_busmaster(dev); |
| 406 | pci_enable_io(dev, SYS_RES_MEMORY); |
| 407 | val = pci_read_config(dev, PCIR_COMMAND, 2); |
| 408 | |
| 409 | fxp_powerstate_d0(dev); |
| 410 | |
| 411 | /* |
| 412 | * Figure out which we should try first - memory mapping or i/o mapping? |
| 413 | * We default to memory mapping. Then we accept an override from the |
| 414 | * command line. Then we check to see which one is enabled. |
| 415 | */ |
| 416 | m1 = PCIM_CMD_MEMEN; |
| 417 | m2 = PCIM_CMD_PORTEN; |
| 418 | prefer_iomap = 0; |
| 419 | if (resource_int_value(device_get_name(dev), device_get_unit(dev), |
| 420 | "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { |
| 421 | m1 = PCIM_CMD_PORTEN; |
| 422 | m2 = PCIM_CMD_MEMEN; |
| 423 | } |
| 424 | |
| 425 | if (val & m1) { |
| 426 | sc->rtp = |
| 427 | (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; |
| 428 | sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; |
| 429 | sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, |
| 430 | RF_ACTIVE); |
| 431 | } |
| 432 | if (sc->mem == NULL && (val & m2)) { |
| 433 | sc->rtp = |
| 434 | (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; |
| 435 | sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; |
| 436 | sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, |
| 437 | RF_ACTIVE); |
| 438 | } |
| 439 | |
| 440 | if (!sc->mem) { |
| 441 | device_printf(dev, "could not map device registers\n"); |
| 442 | error = ENXIO; |
| 443 | goto fail; |
| 444 | } |
| 445 | if (bootverbose) { |
| 446 | device_printf(dev, "using %s space register mapping\n", |
| 447 | sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); |
| 448 | } |
| 449 | |
| 450 | sc->sc_st = rman_get_bustag(sc->mem); |
| 451 | sc->sc_sh = rman_get_bushandle(sc->mem); |
| 452 | |
| 453 | /* |
| 454 | * Allocate our interrupt. |
| 455 | */ |
| 456 | rid = 0; |
| 457 | sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, |
| 458 | RF_SHAREABLE | RF_ACTIVE); |
| 459 | if (sc->irq == NULL) { |
| 460 | device_printf(dev, "could not map interrupt\n"); |
| 461 | error = ENXIO; |
| 462 | goto fail; |
| 463 | } |
| 464 | |
| 465 | /* |
| 466 | * Reset to a stable state. |
| 467 | */ |
| 468 | CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); |
| 469 | DELAY(10); |
| 470 | |
| 471 | sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, |
| 472 | M_DEVBUF, M_WAITOK | M_ZERO); |
| 473 | |
| 474 | sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, |
| 475 | M_WAITOK | M_ZERO); |
| 476 | |
| 477 | sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK); |
| 478 | |
| 479 | /* |
| 480 | * Pre-allocate our receive buffers. |
| 481 | */ |
| 482 | for (i = 0; i < FXP_NRFABUFS; i++) { |
| 483 | if (fxp_add_rfabuf(sc, NULL) != 0) { |
| 484 | goto failmem; |
| 485 | } |
| 486 | } |
| 487 | |
| 488 | /* |
| 489 | * Find out how large of an SEEPROM we have. |
| 490 | */ |
| 491 | fxp_autosize_eeprom(sc); |
| 492 | |
| 493 | /* |
| 494 | * Determine whether we must use the 503 serial interface. |
| 495 | */ |
| 496 | fxp_read_eeprom(sc, &data, 6, 1); |
| 497 | if ((data & FXP_PHY_DEVICE_MASK) != 0 && |
| 498 | (data & FXP_PHY_SERIAL_ONLY)) |
| 499 | sc->flags |= FXP_FLAG_SERIAL_MEDIA; |
| 500 | |
| 501 | /* |
| 502 | * Create the sysctl tree |
| 503 | */ |
| 504 | sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, |
| 505 | SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, |
| 506 | device_get_nameunit(dev), CTLFLAG_RD, 0, ""); |
| 507 | if (sc->sysctl_tree == NULL) |
| 508 | goto fail; |
| 509 | SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), |
| 510 | OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, |
| 511 | &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", |
| 512 | "FXP driver receive interrupt microcode bundling delay"); |
| 513 | SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), |
| 514 | OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, |
| 515 | &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", |
| 516 | "FXP driver receive interrupt microcode bundle size limit"); |
| 517 | |
| 518 | /* |
| 519 | * Pull in device tunables. |
| 520 | */ |
| 521 | sc->tunable_int_delay = TUNABLE_INT_DELAY; |
| 522 | sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; |
| 523 | (void) resource_int_value(device_get_name(dev), device_get_unit(dev), |
| 524 | "int_delay", &sc->tunable_int_delay); |
| 525 | (void) resource_int_value(device_get_name(dev), device_get_unit(dev), |
| 526 | "bundle_max", &sc->tunable_bundle_max); |
| 527 | |
| 528 | /* |
| 529 | * Find out the chip revision; lump all 82557 revs together. |
| 530 | */ |
| 531 | fxp_read_eeprom(sc, &data, 5, 1); |
| 532 | if ((data >> 8) == 1) |
| 533 | sc->revision = FXP_REV_82557; |
| 534 | else |
| 535 | sc->revision = pci_get_revid(dev); |
| 536 | |
| 537 | /* |
| 538 | * Enable workarounds for certain chip revision deficiencies. |
| 539 | * |
| 540 | * Systems based on the ICH2/ICH2-M chip from Intel, and possibly |
| 541 | * some systems based a normal 82559 design, have a defect where |
| 542 | * the chip can cause a PCI protocol violation if it receives |
| 543 | * a CU_RESUME command when it is entering the IDLE state. The |
| 544 | * workaround is to disable Dynamic Standby Mode, so the chip never |
| 545 | * deasserts CLKRUN#, and always remains in an active state. |
| 546 | * |
| 547 | * See Intel 82801BA/82801BAM Specification Update, Errata #30. |
| 548 | */ |
| 549 | i = pci_get_device(dev); |
| 550 | if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || |
| 551 | sc->revision >= FXP_REV_82559_A0) { |
| 552 | fxp_read_eeprom(sc, &data, 10, 1); |
| 553 | if (data & 0x02) { /* STB enable */ |
| 554 | u_int16_t cksum; |
| 555 | int i; |
| 556 | |
| 557 | device_printf(dev, |
| 558 | "Disabling dynamic standby mode in EEPROM\n"); |
| 559 | data &= ~0x02; |
| 560 | fxp_write_eeprom(sc, &data, 10, 1); |
| 561 | device_printf(dev, "New EEPROM ID: 0x%x\n", data); |
| 562 | cksum = 0; |
| 563 | for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { |
| 564 | fxp_read_eeprom(sc, &data, i, 1); |
| 565 | cksum += data; |
| 566 | } |
| 567 | i = (1 << sc->eeprom_size) - 1; |
| 568 | cksum = 0xBABA - cksum; |
| 569 | fxp_read_eeprom(sc, &data, i, 1); |
| 570 | fxp_write_eeprom(sc, &cksum, i, 1); |
| 571 | device_printf(dev, |
| 572 | "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", |
| 573 | i, data, cksum); |
| 574 | #if 1 |
| 575 | /* |
| 576 | * If the user elects to continue, try the software |
| 577 | * workaround, as it is better than nothing. |
| 578 | */ |
| 579 | sc->flags |= FXP_FLAG_CU_RESUME_BUG; |
| 580 | #endif |
| 581 | } |
| 582 | } |
| 583 | |
| 584 | /* |
| 585 | * If we are not a 82557 chip, we can enable extended features. |
| 586 | */ |
| 587 | if (sc->revision != FXP_REV_82557) { |
| 588 | /* |
| 589 | * If MWI is enabled in the PCI configuration, and there |
| 590 | * is a valid cacheline size (8 or 16 dwords), then tell |
| 591 | * the board to turn on MWI. |
| 592 | */ |
| 593 | if (val & PCIM_CMD_MWRICEN && |
| 594 | pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) |
| 595 | sc->flags |= FXP_FLAG_MWI_ENABLE; |
| 596 | |
| 597 | /* turn on the extended TxCB feature */ |
| 598 | sc->flags |= FXP_FLAG_EXT_TXCB; |
| 599 | |
| 600 | /* enable reception of long frames for VLAN */ |
| 601 | sc->flags |= FXP_FLAG_LONG_PKT_EN; |
| 602 | } |
| 603 | |
| 604 | /* |
| 605 | * Read MAC address. |
| 606 | */ |
| 607 | fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); |
| 608 | if (sc->flags & FXP_FLAG_SERIAL_MEDIA) |
| 609 | device_printf(dev, "10Mbps\n"); |
| 610 | if (bootverbose) { |
| 611 | device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", |
| 612 | pci_get_vendor(dev), pci_get_device(dev), |
| 613 | pci_get_subvendor(dev), pci_get_subdevice(dev), |
| 614 | pci_get_revid(dev)); |
| 615 | fxp_read_eeprom(sc, &data, 10, 1); |
| 616 | device_printf(dev, "Dynamic Standby mode is %s\n", |
| 617 | data & 0x02 ? "enabled" : "disabled"); |
| 618 | } |
| 619 | |
| 620 | /* |
| 621 | * If this is only a 10Mbps device, then there is no MII, and |
| 622 | * the PHY will use a serial interface instead. |
| 623 | * |
| 624 | * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter |
| 625 | * doesn't have a programming interface of any sort. The |
| 626 | * media is sensed automatically based on how the link partner |
| 627 | * is configured. This is, in essence, manual configuration. |
| 628 | */ |
| 629 | if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { |
| 630 | ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, |
| 631 | fxp_serial_ifmedia_sts); |
| 632 | ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); |
| 633 | ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); |
| 634 | } else { |
| 635 | if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, |
| 636 | fxp_ifmedia_sts)) { |
| 637 | device_printf(dev, "MII without any PHY!\n"); |
| 638 | error = ENXIO; |
| 639 | goto fail; |
| 640 | } |
| 641 | } |
| 642 | |
| 643 | ifp = &sc->arpcom.ac_if; |
| 644 | if_initname(ifp, device_get_name(dev), device_get_unit(dev)); |
| 645 | ifp->if_baudrate = 100000000; |
| 646 | ifp->if_init = fxp_init; |
| 647 | ifp->if_softc = sc; |
| 648 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; |
| 649 | ifp->if_ioctl = fxp_ioctl; |
| 650 | ifp->if_start = fxp_start; |
| 651 | #ifdef DEVICE_POLLING |
| 652 | ifp->if_poll = fxp_poll; |
| 653 | #endif |
| 654 | ifp->if_watchdog = fxp_watchdog; |
| 655 | |
| 656 | /* |
| 657 | * Attach the interface. |
| 658 | */ |
| 659 | ether_ifattach(ifp, sc->arpcom.ac_enaddr); |
| 660 | |
| 661 | /* |
| 662 | * Tell the upper layer(s) we support long frames. |
| 663 | */ |
| 664 | ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); |
| 665 | |
| 666 | /* |
| 667 | * Let the system queue as many packets as we have available |
| 668 | * TX descriptors. |
| 669 | */ |
| 670 | ifq_set_maxlen(&ifp->if_snd, FXP_NTXCB - 1); |
| 671 | ifq_set_ready(&ifp->if_snd); |
| 672 | |
| 673 | error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, |
| 674 | fxp_intr, sc, &sc->ih, NULL); |
| 675 | if (error) { |
| 676 | ether_ifdetach(ifp); |
| 677 | if (sc->flags & FXP_FLAG_SERIAL_MEDIA) |
| 678 | ifmedia_removeall(&sc->sc_media); |
| 679 | device_printf(dev, "could not setup irq\n"); |
| 680 | goto fail; |
| 681 | } |
| 682 | |
| 683 | return (0); |
| 684 | |
| 685 | failmem: |
| 686 | device_printf(dev, "Failed to malloc memory\n"); |
| 687 | error = ENOMEM; |
| 688 | fail: |
| 689 | fxp_release(dev); |
| 690 | return (error); |
| 691 | } |
| 692 | |
| 693 | /* |
| 694 | * release all resources |
| 695 | */ |
| 696 | static void |
| 697 | fxp_release(device_t dev) |
| 698 | { |
| 699 | struct fxp_softc *sc = device_get_softc(dev); |
| 700 | |
| 701 | if (sc->miibus) |
| 702 | device_delete_child(dev, sc->miibus); |
| 703 | bus_generic_detach(dev); |
| 704 | |
| 705 | if (sc->cbl_base) |
| 706 | free(sc->cbl_base, M_DEVBUF); |
| 707 | if (sc->fxp_stats) |
| 708 | free(sc->fxp_stats, M_DEVBUF); |
| 709 | if (sc->mcsp) |
| 710 | free(sc->mcsp, M_DEVBUF); |
| 711 | if (sc->rfa_headm) |
| 712 | m_freem(sc->rfa_headm); |
| 713 | |
| 714 | if (sc->irq) |
| 715 | bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); |
| 716 | if (sc->mem) |
| 717 | bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem); |
| 718 | |
| 719 | sysctl_ctx_free(&sc->sysctl_ctx); |
| 720 | } |
| 721 | |
| 722 | /* |
| 723 | * Detach interface. |
| 724 | */ |
| 725 | static int |
| 726 | fxp_detach(device_t dev) |
| 727 | { |
| 728 | struct fxp_softc *sc = device_get_softc(dev); |
| 729 | |
| 730 | /* disable interrupts */ |
| 731 | CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); |
| 732 | |
| 733 | crit_enter(); |
| 734 | |
| 735 | /* |
| 736 | * Stop DMA and drop transmit queue. |
| 737 | */ |
| 738 | fxp_stop(sc); |
| 739 | |
| 740 | /* |
| 741 | * Close down routes etc. |
| 742 | */ |
| 743 | ether_ifdetach(&sc->arpcom.ac_if); |
| 744 | |
| 745 | /* |
| 746 | * Free all media structures. |
| 747 | */ |
| 748 | if (sc->flags & FXP_FLAG_SERIAL_MEDIA) |
| 749 | ifmedia_removeall(&sc->sc_media); |
| 750 | |
| 751 | if (sc->ih) |
| 752 | bus_teardown_intr(dev, sc->irq, sc->ih); |
| 753 | |
| 754 | crit_exit(); |
| 755 | |
| 756 | /* Release our allocated resources. */ |
| 757 | fxp_release(dev); |
| 758 | |
| 759 | return (0); |
| 760 | } |
| 761 | |
| 762 | /* |
| 763 | * Device shutdown routine. Called at system shutdown after sync. The |
| 764 | * main purpose of this routine is to shut off receiver DMA so that |
| 765 | * kernel memory doesn't get clobbered during warmboot. |
| 766 | */ |
| 767 | static int |
| 768 | fxp_shutdown(device_t dev) |
| 769 | { |
| 770 | /* |
| 771 | * Make sure that DMA is disabled prior to reboot. Not doing |
| 772 | * do could allow DMA to corrupt kernel memory during the |
| 773 | * reboot before the driver initializes. |
| 774 | */ |
| 775 | fxp_stop((struct fxp_softc *) device_get_softc(dev)); |
| 776 | return (0); |
| 777 | } |
| 778 | |
| 779 | /* |
| 780 | * Device suspend routine. Stop the interface and save some PCI |
| 781 | * settings in case the BIOS doesn't restore them properly on |
| 782 | * resume. |
| 783 | */ |
| 784 | static int |
| 785 | fxp_suspend(device_t dev) |
| 786 | { |
| 787 | struct fxp_softc *sc = device_get_softc(dev); |
| 788 | int i; |
| 789 | |
| 790 | crit_enter(); |
| 791 | |
| 792 | fxp_stop(sc); |
| 793 | |
| 794 | for (i = 0; i < 5; i++) |
| 795 | sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); |
| 796 | sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); |
| 797 | sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); |
| 798 | sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); |
| 799 | sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); |
| 800 | |
| 801 | sc->suspended = 1; |
| 802 | |
| 803 | crit_exit(); |
| 804 | return (0); |
| 805 | } |
| 806 | |
| 807 | /* |
| 808 | * Device resume routine. Restore some PCI settings in case the BIOS |
| 809 | * doesn't, re-enable busmastering, and restart the interface if |
| 810 | * appropriate. |
| 811 | */ |
| 812 | static int |
| 813 | fxp_resume(device_t dev) |
| 814 | { |
| 815 | struct fxp_softc *sc = device_get_softc(dev); |
| 816 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 817 | int i; |
| 818 | |
| 819 | crit_enter(); |
| 820 | |
| 821 | fxp_powerstate_d0(dev); |
| 822 | |
| 823 | /* better way to do this? */ |
| 824 | for (i = 0; i < 5; i++) |
| 825 | pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); |
| 826 | pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); |
| 827 | pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); |
| 828 | pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); |
| 829 | pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); |
| 830 | |
| 831 | /* reenable busmastering and memory space */ |
| 832 | pci_enable_busmaster(dev); |
| 833 | pci_enable_io(dev, SYS_RES_MEMORY); |
| 834 | |
| 835 | CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); |
| 836 | DELAY(10); |
| 837 | |
| 838 | /* reinitialize interface if necessary */ |
| 839 | if (ifp->if_flags & IFF_UP) |
| 840 | fxp_init(sc); |
| 841 | |
| 842 | sc->suspended = 0; |
| 843 | |
| 844 | crit_exit(); |
| 845 | return (0); |
| 846 | } |
| 847 | |
| 848 | static void |
| 849 | fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) |
| 850 | { |
| 851 | u_int16_t reg; |
| 852 | int x; |
| 853 | |
| 854 | /* |
| 855 | * Shift in data. |
| 856 | */ |
| 857 | for (x = 1 << (length - 1); x; x >>= 1) { |
| 858 | if (data & x) |
| 859 | reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; |
| 860 | else |
| 861 | reg = FXP_EEPROM_EECS; |
| 862 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); |
| 863 | DELAY(1); |
| 864 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); |
| 865 | DELAY(1); |
| 866 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); |
| 867 | DELAY(1); |
| 868 | } |
| 869 | } |
| 870 | |
| 871 | /* |
| 872 | * Read from the serial EEPROM. Basically, you manually shift in |
| 873 | * the read opcode (one bit at a time) and then shift in the address, |
| 874 | * and then you shift out the data (all of this one bit at a time). |
| 875 | * The word size is 16 bits, so you have to provide the address for |
| 876 | * every 16 bits of data. |
| 877 | */ |
| 878 | static u_int16_t |
| 879 | fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) |
| 880 | { |
| 881 | u_int16_t reg, data; |
| 882 | int x; |
| 883 | |
| 884 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); |
| 885 | /* |
| 886 | * Shift in read opcode. |
| 887 | */ |
| 888 | fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); |
| 889 | /* |
| 890 | * Shift in address. |
| 891 | */ |
| 892 | data = 0; |
| 893 | for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { |
| 894 | if (offset & x) |
| 895 | reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; |
| 896 | else |
| 897 | reg = FXP_EEPROM_EECS; |
| 898 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); |
| 899 | DELAY(1); |
| 900 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); |
| 901 | DELAY(1); |
| 902 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); |
| 903 | DELAY(1); |
| 904 | reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; |
| 905 | data++; |
| 906 | if (autosize && reg == 0) { |
| 907 | sc->eeprom_size = data; |
| 908 | break; |
| 909 | } |
| 910 | } |
| 911 | /* |
| 912 | * Shift out data. |
| 913 | */ |
| 914 | data = 0; |
| 915 | reg = FXP_EEPROM_EECS; |
| 916 | for (x = 1 << 15; x; x >>= 1) { |
| 917 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); |
| 918 | DELAY(1); |
| 919 | if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) |
| 920 | data |= x; |
| 921 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); |
| 922 | DELAY(1); |
| 923 | } |
| 924 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); |
| 925 | DELAY(1); |
| 926 | |
| 927 | return (data); |
| 928 | } |
| 929 | |
| 930 | static void |
| 931 | fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) |
| 932 | { |
| 933 | int i; |
| 934 | |
| 935 | /* |
| 936 | * Erase/write enable. |
| 937 | */ |
| 938 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); |
| 939 | fxp_eeprom_shiftin(sc, 0x4, 3); |
| 940 | fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); |
| 941 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); |
| 942 | DELAY(1); |
| 943 | /* |
| 944 | * Shift in write opcode, address, data. |
| 945 | */ |
| 946 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); |
| 947 | fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); |
| 948 | fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); |
| 949 | fxp_eeprom_shiftin(sc, data, 16); |
| 950 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); |
| 951 | DELAY(1); |
| 952 | /* |
| 953 | * Wait for EEPROM to finish up. |
| 954 | */ |
| 955 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); |
| 956 | DELAY(1); |
| 957 | for (i = 0; i < 1000; i++) { |
| 958 | if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) |
| 959 | break; |
| 960 | DELAY(50); |
| 961 | } |
| 962 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); |
| 963 | DELAY(1); |
| 964 | /* |
| 965 | * Erase/write disable. |
| 966 | */ |
| 967 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); |
| 968 | fxp_eeprom_shiftin(sc, 0x4, 3); |
| 969 | fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); |
| 970 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); |
| 971 | DELAY(1); |
| 972 | } |
| 973 | |
| 974 | /* |
| 975 | * From NetBSD: |
| 976 | * |
| 977 | * Figure out EEPROM size. |
| 978 | * |
| 979 | * 559's can have either 64-word or 256-word EEPROMs, the 558 |
| 980 | * datasheet only talks about 64-word EEPROMs, and the 557 datasheet |
| 981 | * talks about the existance of 16 to 256 word EEPROMs. |
| 982 | * |
| 983 | * The only known sizes are 64 and 256, where the 256 version is used |
| 984 | * by CardBus cards to store CIS information. |
| 985 | * |
| 986 | * The address is shifted in msb-to-lsb, and after the last |
| 987 | * address-bit the EEPROM is supposed to output a `dummy zero' bit, |
| 988 | * after which follows the actual data. We try to detect this zero, by |
| 989 | * probing the data-out bit in the EEPROM control register just after |
| 990 | * having shifted in a bit. If the bit is zero, we assume we've |
| 991 | * shifted enough address bits. The data-out should be tri-state, |
| 992 | * before this, which should translate to a logical one. |
| 993 | */ |
| 994 | static void |
| 995 | fxp_autosize_eeprom(struct fxp_softc *sc) |
| 996 | { |
| 997 | |
| 998 | /* guess maximum size of 256 words */ |
| 999 | sc->eeprom_size = 8; |
| 1000 | |
| 1001 | /* autosize */ |
| 1002 | (void) fxp_eeprom_getword(sc, 0, 1); |
| 1003 | } |
| 1004 | |
| 1005 | static void |
| 1006 | fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) |
| 1007 | { |
| 1008 | int i; |
| 1009 | |
| 1010 | for (i = 0; i < words; i++) |
| 1011 | data[i] = fxp_eeprom_getword(sc, offset + i, 0); |
| 1012 | } |
| 1013 | |
| 1014 | static void |
| 1015 | fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) |
| 1016 | { |
| 1017 | int i; |
| 1018 | |
| 1019 | for (i = 0; i < words; i++) |
| 1020 | fxp_eeprom_putword(sc, offset + i, data[i]); |
| 1021 | } |
| 1022 | |
| 1023 | /* |
| 1024 | * Start packet transmission on the interface. |
| 1025 | */ |
| 1026 | static void |
| 1027 | fxp_start(struct ifnet *ifp) |
| 1028 | { |
| 1029 | struct fxp_softc *sc = ifp->if_softc; |
| 1030 | struct fxp_cb_tx *txp; |
| 1031 | |
| 1032 | /* |
| 1033 | * See if we need to suspend xmit until the multicast filter |
| 1034 | * has been reprogrammed (which can only be done at the head |
| 1035 | * of the command chain). |
| 1036 | */ |
| 1037 | if (sc->need_mcsetup) { |
| 1038 | return; |
| 1039 | } |
| 1040 | |
| 1041 | txp = NULL; |
| 1042 | |
| 1043 | /* |
| 1044 | * We're finished if there is nothing more to add to the list or if |
| 1045 | * we're all filled up with buffers to transmit. |
| 1046 | * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add |
| 1047 | * a NOP command when needed. |
| 1048 | */ |
| 1049 | while (!ifq_is_empty(&ifp->if_snd) && sc->tx_queued < FXP_NTXCB - 1) { |
| 1050 | struct mbuf *m, *mb_head; |
| 1051 | int segment, ntries = 0; |
| 1052 | |
| 1053 | /* |
| 1054 | * Grab a packet to transmit. The packet is dequeued, |
| 1055 | * once we are sure that we have enough free descriptors. |
| 1056 | */ |
| 1057 | mb_head = ifq_poll(&ifp->if_snd); |
| 1058 | if (mb_head == NULL) |
| 1059 | break; |
| 1060 | |
| 1061 | /* |
| 1062 | * Get pointer to next available tx desc. |
| 1063 | */ |
| 1064 | txp = sc->cbl_last->next; |
| 1065 | |
| 1066 | /* |
| 1067 | * Go through each of the mbufs in the chain and initialize |
| 1068 | * the transmit buffer descriptors with the physical address |
| 1069 | * and size of the mbuf. |
| 1070 | */ |
| 1071 | tbdinit: |
| 1072 | for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { |
| 1073 | if (m->m_len != 0) { |
| 1074 | if (segment == FXP_NTXSEG) |
| 1075 | break; |
| 1076 | txp->tbd[segment].tb_addr = |
| 1077 | vtophys(mtod(m, vm_offset_t)); |
| 1078 | txp->tbd[segment].tb_size = m->m_len; |
| 1079 | segment++; |
| 1080 | } |
| 1081 | } |
| 1082 | if (m != NULL) { |
| 1083 | struct mbuf *mn; |
| 1084 | |
| 1085 | /* |
| 1086 | * We ran out of segments. We have to recopy this |
| 1087 | * mbuf chain first. Bail out if we can't get the |
| 1088 | * new buffers. |
| 1089 | */ |
| 1090 | if (ntries > 0) |
| 1091 | break; |
| 1092 | mn = m_dup(mb_head, MB_DONTWAIT); |
| 1093 | if (mn == NULL) |
| 1094 | break; |
| 1095 | /* We can transmit the packet, dequeue it. */ |
| 1096 | mb_head = ifq_dequeue(&ifp->if_snd); |
| 1097 | m_freem(mb_head); |
| 1098 | mb_head = mn; |
| 1099 | ntries = 1; |
| 1100 | goto tbdinit; |
| 1101 | } else { |
| 1102 | /* Nothing to worry about, just dequeue. */ |
| 1103 | mb_head = ifq_dequeue(&ifp->if_snd); |
| 1104 | } |
| 1105 | |
| 1106 | txp->tbd_number = segment; |
| 1107 | txp->mb_head = mb_head; |
| 1108 | txp->cb_status = 0; |
| 1109 | if (sc->tx_queued != FXP_CXINT_THRESH - 1) { |
| 1110 | txp->cb_command = |
| 1111 | FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | |
| 1112 | FXP_CB_COMMAND_S; |
| 1113 | } else { |
| 1114 | txp->cb_command = |
| 1115 | FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | |
| 1116 | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; |
| 1117 | /* |
| 1118 | * Set a 5 second timer just in case we don't hear |
| 1119 | * from the card again. |
| 1120 | */ |
| 1121 | ifp->if_timer = 5; |
| 1122 | } |
| 1123 | txp->tx_threshold = tx_threshold; |
| 1124 | |
| 1125 | /* |
| 1126 | * Advance the end of list forward. |
| 1127 | */ |
| 1128 | |
| 1129 | sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; |
| 1130 | sc->cbl_last = txp; |
| 1131 | |
| 1132 | /* |
| 1133 | * Advance the beginning of the list forward if there are |
| 1134 | * no other packets queued (when nothing is queued, cbl_first |
| 1135 | * sits on the last TxCB that was sent out). |
| 1136 | */ |
| 1137 | if (sc->tx_queued == 0) |
| 1138 | sc->cbl_first = txp; |
| 1139 | |
| 1140 | sc->tx_queued++; |
| 1141 | |
| 1142 | BPF_MTAP(ifp, mb_head); |
| 1143 | } |
| 1144 | |
| 1145 | /* |
| 1146 | * We're finished. If we added to the list, issue a RESUME to get DMA |
| 1147 | * going again if suspended. |
| 1148 | */ |
| 1149 | if (txp != NULL) { |
| 1150 | fxp_scb_wait(sc); |
| 1151 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); |
| 1152 | } |
| 1153 | } |
| 1154 | |
| 1155 | #ifdef DEVICE_POLLING |
| 1156 | |
| 1157 | static void |
| 1158 | fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) |
| 1159 | { |
| 1160 | struct fxp_softc *sc = ifp->if_softc; |
| 1161 | u_int8_t statack; |
| 1162 | |
| 1163 | switch(cmd) { |
| 1164 | case POLL_REGISTER: |
| 1165 | /* disable interrupts */ |
| 1166 | CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); |
| 1167 | break; |
| 1168 | case POLL_DEREGISTER: |
| 1169 | /* enable interrupts */ |
| 1170 | CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); |
| 1171 | break; |
| 1172 | default: |
| 1173 | statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | |
| 1174 | FXP_SCB_STATACK_FR; |
| 1175 | if (cmd == POLL_AND_CHECK_STATUS) { |
| 1176 | u_int8_t tmp; |
| 1177 | |
| 1178 | tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); |
| 1179 | if (tmp == 0xff || tmp == 0) |
| 1180 | return; /* nothing to do */ |
| 1181 | tmp &= ~statack; |
| 1182 | /* ack what we can */ |
| 1183 | if (tmp != 0) |
| 1184 | CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); |
| 1185 | statack |= tmp; |
| 1186 | } |
| 1187 | fxp_intr_body(sc, statack, count); |
| 1188 | break; |
| 1189 | } |
| 1190 | } |
| 1191 | |
| 1192 | #endif /* DEVICE_POLLING */ |
| 1193 | |
| 1194 | /* |
| 1195 | * Process interface interrupts. |
| 1196 | */ |
| 1197 | static void |
| 1198 | fxp_intr(void *xsc) |
| 1199 | { |
| 1200 | struct fxp_softc *sc = xsc; |
| 1201 | u_int8_t statack; |
| 1202 | |
| 1203 | if (sc->suspended) { |
| 1204 | return; |
| 1205 | } |
| 1206 | |
| 1207 | while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { |
| 1208 | /* |
| 1209 | * It should not be possible to have all bits set; the |
| 1210 | * FXP_SCB_INTR_SWI bit always returns 0 on a read. If |
| 1211 | * all bits are set, this may indicate that the card has |
| 1212 | * been physically ejected, so ignore it. |
| 1213 | */ |
| 1214 | if (statack == 0xff) |
| 1215 | return; |
| 1216 | |
| 1217 | /* |
| 1218 | * First ACK all the interrupts in this pass. |
| 1219 | */ |
| 1220 | CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); |
| 1221 | fxp_intr_body(sc, statack, -1); |
| 1222 | } |
| 1223 | } |
| 1224 | |
| 1225 | static void |
| 1226 | fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) |
| 1227 | { |
| 1228 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 1229 | struct mbuf *m; |
| 1230 | struct fxp_rfa *rfa; |
| 1231 | int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; |
| 1232 | |
| 1233 | if (rnr) |
| 1234 | fxp_rnr++; |
| 1235 | #ifdef DEVICE_POLLING |
| 1236 | /* Pick up a deferred RNR condition if `count' ran out last time. */ |
| 1237 | if (sc->flags & FXP_FLAG_DEFERRED_RNR) { |
| 1238 | sc->flags &= ~FXP_FLAG_DEFERRED_RNR; |
| 1239 | rnr = 1; |
| 1240 | } |
| 1241 | #endif |
| 1242 | |
| 1243 | /* |
| 1244 | * Free any finished transmit mbuf chains. |
| 1245 | * |
| 1246 | * Handle the CNA event likt a CXTNO event. It used to |
| 1247 | * be that this event (control unit not ready) was not |
| 1248 | * encountered, but it is now with the SMPng modifications. |
| 1249 | * The exact sequence of events that occur when the interface |
| 1250 | * is brought up are different now, and if this event |
| 1251 | * goes unhandled, the configuration/rxfilter setup sequence |
| 1252 | * can stall for several seconds. The result is that no |
| 1253 | * packets go out onto the wire for about 5 to 10 seconds |
| 1254 | * after the interface is ifconfig'ed for the first time. |
| 1255 | */ |
| 1256 | if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { |
| 1257 | struct fxp_cb_tx *txp; |
| 1258 | |
| 1259 | for (txp = sc->cbl_first; sc->tx_queued && |
| 1260 | (txp->cb_status & FXP_CB_STATUS_C) != 0; |
| 1261 | txp = txp->next) { |
| 1262 | if ((m = txp->mb_head) != NULL) { |
| 1263 | txp->mb_head = NULL; |
| 1264 | sc->tx_queued--; |
| 1265 | m_freem(m); |
| 1266 | } else { |
| 1267 | sc->tx_queued--; |
| 1268 | } |
| 1269 | } |
| 1270 | sc->cbl_first = txp; |
| 1271 | ifp->if_timer = 0; |
| 1272 | if (sc->tx_queued == 0) { |
| 1273 | if (sc->need_mcsetup) |
| 1274 | fxp_mc_setup(sc); |
| 1275 | } |
| 1276 | /* |
| 1277 | * Try to start more packets transmitting. |
| 1278 | */ |
| 1279 | if (!ifq_is_empty(&ifp->if_snd)) |
| 1280 | (*ifp->if_start)(ifp); |
| 1281 | } |
| 1282 | |
| 1283 | /* |
| 1284 | * Just return if nothing happened on the receive side. |
| 1285 | */ |
| 1286 | if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) |
| 1287 | return; |
| 1288 | |
| 1289 | /* |
| 1290 | * Process receiver interrupts. If a no-resource (RNR) |
| 1291 | * condition exists, get whatever packets we can and |
| 1292 | * re-start the receiver. |
| 1293 | * |
| 1294 | * When using polling, we do not process the list to completion, |
| 1295 | * so when we get an RNR interrupt we must defer the restart |
| 1296 | * until we hit the last buffer with the C bit set. |
| 1297 | * If we run out of cycles and rfa_headm has the C bit set, |
| 1298 | * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so |
| 1299 | * that the info will be used in the subsequent polling cycle. |
| 1300 | */ |
| 1301 | for (;;) { |
| 1302 | m = sc->rfa_headm; |
| 1303 | rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + |
| 1304 | RFA_ALIGNMENT_FUDGE); |
| 1305 | |
| 1306 | #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ |
| 1307 | if (count >= 0 && count-- == 0) { |
| 1308 | if (rnr) { |
| 1309 | /* Defer RNR processing until the next time. */ |
| 1310 | sc->flags |= FXP_FLAG_DEFERRED_RNR; |
| 1311 | rnr = 0; |
| 1312 | } |
| 1313 | break; |
| 1314 | } |
| 1315 | #endif /* DEVICE_POLLING */ |
| 1316 | |
| 1317 | if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) |
| 1318 | break; |
| 1319 | |
| 1320 | /* |
| 1321 | * Remove first packet from the chain. |
| 1322 | */ |
| 1323 | sc->rfa_headm = m->m_next; |
| 1324 | m->m_next = NULL; |
| 1325 | |
| 1326 | /* |
| 1327 | * Add a new buffer to the receive chain. |
| 1328 | * If this fails, the old buffer is recycled |
| 1329 | * instead. |
| 1330 | */ |
| 1331 | if (fxp_add_rfabuf(sc, m) == 0) { |
| 1332 | int total_len; |
| 1333 | |
| 1334 | /* |
| 1335 | * Fetch packet length (the top 2 bits of |
| 1336 | * actual_size are flags set by the controller |
| 1337 | * upon completion), and drop the packet in case |
| 1338 | * of bogus length or CRC errors. |
| 1339 | */ |
| 1340 | total_len = rfa->actual_size & 0x3fff; |
| 1341 | if (total_len < sizeof(struct ether_header) || |
| 1342 | total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - |
| 1343 | sizeof(struct fxp_rfa) || |
| 1344 | rfa->rfa_status & FXP_RFA_STATUS_CRC) { |
| 1345 | m_freem(m); |
| 1346 | continue; |
| 1347 | } |
| 1348 | m->m_pkthdr.len = m->m_len = total_len; |
| 1349 | (*ifp->if_input)(ifp, m); |
| 1350 | } |
| 1351 | } |
| 1352 | if (rnr) { |
| 1353 | fxp_scb_wait(sc); |
| 1354 | CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, |
| 1355 | vtophys(sc->rfa_headm->m_ext.ext_buf) + |
| 1356 | RFA_ALIGNMENT_FUDGE); |
| 1357 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); |
| 1358 | } |
| 1359 | } |
| 1360 | |
| 1361 | /* |
| 1362 | * Update packet in/out/collision statistics. The i82557 doesn't |
| 1363 | * allow you to access these counters without doing a fairly |
| 1364 | * expensive DMA to get _all_ of the statistics it maintains, so |
| 1365 | * we do this operation here only once per second. The statistics |
| 1366 | * counters in the kernel are updated from the previous dump-stats |
| 1367 | * DMA and then a new dump-stats DMA is started. The on-chip |
| 1368 | * counters are zeroed when the DMA completes. If we can't start |
| 1369 | * the DMA immediately, we don't wait - we just prepare to read |
| 1370 | * them again next time. |
| 1371 | */ |
| 1372 | static void |
| 1373 | fxp_tick(void *xsc) |
| 1374 | { |
| 1375 | struct fxp_softc *sc = xsc; |
| 1376 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 1377 | struct fxp_stats *sp = sc->fxp_stats; |
| 1378 | struct fxp_cb_tx *txp; |
| 1379 | struct mbuf *m; |
| 1380 | |
| 1381 | ifp->if_opackets += sp->tx_good; |
| 1382 | ifp->if_collisions += sp->tx_total_collisions; |
| 1383 | if (sp->rx_good) { |
| 1384 | ifp->if_ipackets += sp->rx_good; |
| 1385 | sc->rx_idle_secs = 0; |
| 1386 | } else { |
| 1387 | /* |
| 1388 | * Receiver's been idle for another second. |
| 1389 | */ |
| 1390 | sc->rx_idle_secs++; |
| 1391 | } |
| 1392 | ifp->if_ierrors += |
| 1393 | sp->rx_crc_errors + |
| 1394 | sp->rx_alignment_errors + |
| 1395 | sp->rx_rnr_errors + |
| 1396 | sp->rx_overrun_errors; |
| 1397 | /* |
| 1398 | * If any transmit underruns occured, bump up the transmit |
| 1399 | * threshold by another 512 bytes (64 * 8). |
| 1400 | */ |
| 1401 | if (sp->tx_underruns) { |
| 1402 | ifp->if_oerrors += sp->tx_underruns; |
| 1403 | if (tx_threshold < 192) |
| 1404 | tx_threshold += 64; |
| 1405 | } |
| 1406 | |
| 1407 | crit_enter(); |
| 1408 | |
| 1409 | /* |
| 1410 | * Release any xmit buffers that have completed DMA. This isn't |
| 1411 | * strictly necessary to do here, but it's advantagous for mbufs |
| 1412 | * with external storage to be released in a timely manner rather |
| 1413 | * than being defered for a potentially long time. This limits |
| 1414 | * the delay to a maximum of one second. |
| 1415 | */ |
| 1416 | for (txp = sc->cbl_first; sc->tx_queued && |
| 1417 | (txp->cb_status & FXP_CB_STATUS_C) != 0; |
| 1418 | txp = txp->next) { |
| 1419 | if ((m = txp->mb_head) != NULL) { |
| 1420 | txp->mb_head = NULL; |
| 1421 | sc->tx_queued--; |
| 1422 | m_freem(m); |
| 1423 | } else { |
| 1424 | sc->tx_queued--; |
| 1425 | } |
| 1426 | } |
| 1427 | sc->cbl_first = txp; |
| 1428 | /* |
| 1429 | * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, |
| 1430 | * then assume the receiver has locked up and attempt to clear |
| 1431 | * the condition by reprogramming the multicast filter. This is |
| 1432 | * a work-around for a bug in the 82557 where the receiver locks |
| 1433 | * up if it gets certain types of garbage in the syncronization |
| 1434 | * bits prior to the packet header. This bug is supposed to only |
| 1435 | * occur in 10Mbps mode, but has been seen to occur in 100Mbps |
| 1436 | * mode as well (perhaps due to a 10/100 speed transition). |
| 1437 | */ |
| 1438 | if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { |
| 1439 | sc->rx_idle_secs = 0; |
| 1440 | fxp_mc_setup(sc); |
| 1441 | } |
| 1442 | /* |
| 1443 | * If there is no pending command, start another stats |
| 1444 | * dump. Otherwise punt for now. |
| 1445 | */ |
| 1446 | if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { |
| 1447 | /* |
| 1448 | * Start another stats dump. |
| 1449 | */ |
| 1450 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); |
| 1451 | } else { |
| 1452 | /* |
| 1453 | * A previous command is still waiting to be accepted. |
| 1454 | * Just zero our copy of the stats and wait for the |
| 1455 | * next timer event to update them. |
| 1456 | */ |
| 1457 | sp->tx_good = 0; |
| 1458 | sp->tx_underruns = 0; |
| 1459 | sp->tx_total_collisions = 0; |
| 1460 | |
| 1461 | sp->rx_good = 0; |
| 1462 | sp->rx_crc_errors = 0; |
| 1463 | sp->rx_alignment_errors = 0; |
| 1464 | sp->rx_rnr_errors = 0; |
| 1465 | sp->rx_overrun_errors = 0; |
| 1466 | } |
| 1467 | if (sc->miibus != NULL) |
| 1468 | mii_tick(device_get_softc(sc->miibus)); |
| 1469 | /* |
| 1470 | * Schedule another timeout one second from now. |
| 1471 | */ |
| 1472 | callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); |
| 1473 | |
| 1474 | crit_exit(); |
| 1475 | } |
| 1476 | |
| 1477 | /* |
| 1478 | * Stop the interface. Cancels the statistics updater and resets |
| 1479 | * the interface. |
| 1480 | */ |
| 1481 | static void |
| 1482 | fxp_stop(struct fxp_softc *sc) |
| 1483 | { |
| 1484 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 1485 | struct fxp_cb_tx *txp; |
| 1486 | int i; |
| 1487 | |
| 1488 | ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); |
| 1489 | ifp->if_timer = 0; |
| 1490 | |
| 1491 | /* |
| 1492 | * Cancel stats updater. |
| 1493 | */ |
| 1494 | callout_stop(&sc->fxp_stat_timer); |
| 1495 | |
| 1496 | /* |
| 1497 | * Issue software reset, which also unloads the microcode. |
| 1498 | */ |
| 1499 | sc->flags &= ~FXP_FLAG_UCODE; |
| 1500 | CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); |
| 1501 | DELAY(50); |
| 1502 | |
| 1503 | /* |
| 1504 | * Release any xmit buffers. |
| 1505 | */ |
| 1506 | txp = sc->cbl_base; |
| 1507 | if (txp != NULL) { |
| 1508 | for (i = 0; i < FXP_NTXCB; i++) { |
| 1509 | if (txp[i].mb_head != NULL) { |
| 1510 | m_freem(txp[i].mb_head); |
| 1511 | txp[i].mb_head = NULL; |
| 1512 | } |
| 1513 | } |
| 1514 | } |
| 1515 | sc->tx_queued = 0; |
| 1516 | |
| 1517 | /* |
| 1518 | * Free all the receive buffers then reallocate/reinitialize |
| 1519 | */ |
| 1520 | if (sc->rfa_headm != NULL) |
| 1521 | m_freem(sc->rfa_headm); |
| 1522 | sc->rfa_headm = NULL; |
| 1523 | sc->rfa_tailm = NULL; |
| 1524 | for (i = 0; i < FXP_NRFABUFS; i++) { |
| 1525 | if (fxp_add_rfabuf(sc, NULL) != 0) { |
| 1526 | /* |
| 1527 | * This "can't happen" - we're at splimp() |
| 1528 | * and we just freed all the buffers we need |
| 1529 | * above. |
| 1530 | */ |
| 1531 | panic("fxp_stop: no buffers!"); |
| 1532 | } |
| 1533 | } |
| 1534 | } |
| 1535 | |
| 1536 | /* |
| 1537 | * Watchdog/transmission transmit timeout handler. Called when a |
| 1538 | * transmission is started on the interface, but no interrupt is |
| 1539 | * received before the timeout. This usually indicates that the |
| 1540 | * card has wedged for some reason. |
| 1541 | */ |
| 1542 | static void |
| 1543 | fxp_watchdog(struct ifnet *ifp) |
| 1544 | { |
| 1545 | if_printf(ifp, "device timeout\n"); |
| 1546 | ifp->if_oerrors++; |
| 1547 | fxp_init(ifp->if_softc); |
| 1548 | } |
| 1549 | |
| 1550 | static void |
| 1551 | fxp_init(void *xsc) |
| 1552 | { |
| 1553 | struct fxp_softc *sc = xsc; |
| 1554 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 1555 | struct fxp_cb_config *cbp; |
| 1556 | struct fxp_cb_ias *cb_ias; |
| 1557 | struct fxp_cb_tx *txp; |
| 1558 | struct fxp_cb_mcs *mcsp; |
| 1559 | int i, prm; |
| 1560 | |
| 1561 | crit_enter(); |
| 1562 | |
| 1563 | /* |
| 1564 | * Cancel any pending I/O |
| 1565 | */ |
| 1566 | fxp_stop(sc); |
| 1567 | |
| 1568 | prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; |
| 1569 | |
| 1570 | /* |
| 1571 | * Initialize base of CBL and RFA memory. Loading with zero |
| 1572 | * sets it up for regular linear addressing. |
| 1573 | */ |
| 1574 | CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); |
| 1575 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); |
| 1576 | |
| 1577 | fxp_scb_wait(sc); |
| 1578 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); |
| 1579 | |
| 1580 | /* |
| 1581 | * Initialize base of dump-stats buffer. |
| 1582 | */ |
| 1583 | fxp_scb_wait(sc); |
| 1584 | CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); |
| 1585 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); |
| 1586 | |
| 1587 | /* |
| 1588 | * Attempt to load microcode if requested. |
| 1589 | */ |
| 1590 | if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) |
| 1591 | fxp_load_ucode(sc); |
| 1592 | |
| 1593 | /* |
| 1594 | * Initialize the multicast address list. |
| 1595 | */ |
| 1596 | if (fxp_mc_addrs(sc)) { |
| 1597 | mcsp = sc->mcsp; |
| 1598 | mcsp->cb_status = 0; |
| 1599 | mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; |
| 1600 | mcsp->link_addr = -1; |
| 1601 | /* |
| 1602 | * Start the multicast setup command. |
| 1603 | */ |
| 1604 | fxp_scb_wait(sc); |
| 1605 | CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); |
| 1606 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); |
| 1607 | /* ...and wait for it to complete. */ |
| 1608 | fxp_dma_wait(&mcsp->cb_status, sc); |
| 1609 | } |
| 1610 | |
| 1611 | /* |
| 1612 | * We temporarily use memory that contains the TxCB list to |
| 1613 | * construct the config CB. The TxCB list memory is rebuilt |
| 1614 | * later. |
| 1615 | */ |
| 1616 | cbp = (struct fxp_cb_config *) sc->cbl_base; |
| 1617 | |
| 1618 | /* |
| 1619 | * This bcopy is kind of disgusting, but there are a bunch of must be |
| 1620 | * zero and must be one bits in this structure and this is the easiest |
| 1621 | * way to initialize them all to proper values. |
| 1622 | */ |
| 1623 | bcopy(fxp_cb_config_template, |
| 1624 | (void *)(uintptr_t)(volatile void *)&cbp->cb_status, |
| 1625 | sizeof(fxp_cb_config_template)); |
| 1626 | |
| 1627 | cbp->cb_status = 0; |
| 1628 | cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; |
| 1629 | cbp->link_addr = -1; /* (no) next command */ |
| 1630 | cbp->byte_count = 22; /* (22) bytes to config */ |
| 1631 | cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ |
| 1632 | cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ |
| 1633 | cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ |
| 1634 | cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; |
| 1635 | cbp->type_enable = 0; /* actually reserved */ |
| 1636 | cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; |
| 1637 | cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; |
| 1638 | cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ |
| 1639 | cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ |
| 1640 | cbp->dma_mbce = 0; /* (disable) dma max counters */ |
| 1641 | cbp->late_scb = 0; /* (don't) defer SCB update */ |
| 1642 | cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ |
| 1643 | cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ |
| 1644 | cbp->ci_int = 1; /* interrupt on CU idle */ |
| 1645 | cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; |
| 1646 | cbp->ext_stats_dis = 1; /* disable extended counters */ |
| 1647 | cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ |
| 1648 | cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; |
| 1649 | cbp->disc_short_rx = !prm; /* discard short packets */ |
| 1650 | cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ |
| 1651 | cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ |
| 1652 | cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ |
| 1653 | cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; |
| 1654 | cbp->csma_dis = 0; /* (don't) disable link */ |
| 1655 | cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ |
| 1656 | cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ |
| 1657 | cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ |
| 1658 | cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ |
| 1659 | cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ |
| 1660 | cbp->nsai = 1; /* (don't) disable source addr insert */ |
| 1661 | cbp->preamble_length = 2; /* (7 byte) preamble */ |
| 1662 | cbp->loopback = 0; /* (don't) loopback */ |
| 1663 | cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ |
| 1664 | cbp->linear_pri_mode = 0; /* (wait after xmit only) */ |
| 1665 | cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ |
| 1666 | cbp->promiscuous = prm; /* promiscuous mode */ |
| 1667 | cbp->bcast_disable = 0; /* (don't) disable broadcasts */ |
| 1668 | cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ |
| 1669 | cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ |
| 1670 | cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ |
| 1671 | cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; |
| 1672 | |
| 1673 | cbp->stripping = !prm; /* truncate rx packet to byte count */ |
| 1674 | cbp->padding = 1; /* (do) pad short tx packets */ |
| 1675 | cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ |
| 1676 | cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; |
| 1677 | cbp->ia_wake_en = 0; /* (don't) wake up on address match */ |
| 1678 | cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ |
| 1679 | /* must set wake_en in PMCSR also */ |
| 1680 | cbp->force_fdx = 0; /* (don't) force full duplex */ |
| 1681 | cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ |
| 1682 | cbp->multi_ia = 0; /* (don't) accept multiple IAs */ |
| 1683 | cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; |
| 1684 | |
| 1685 | if (sc->revision == FXP_REV_82557) { |
| 1686 | /* |
| 1687 | * The 82557 has no hardware flow control, the values |
| 1688 | * below are the defaults for the chip. |
| 1689 | */ |
| 1690 | cbp->fc_delay_lsb = 0; |
| 1691 | cbp->fc_delay_msb = 0x40; |
| 1692 | cbp->pri_fc_thresh = 3; |
| 1693 | cbp->tx_fc_dis = 0; |
| 1694 | cbp->rx_fc_restop = 0; |
| 1695 | cbp->rx_fc_restart = 0; |
| 1696 | cbp->fc_filter = 0; |
| 1697 | cbp->pri_fc_loc = 1; |
| 1698 | } else { |
| 1699 | cbp->fc_delay_lsb = 0x1f; |
| 1700 | cbp->fc_delay_msb = 0x01; |
| 1701 | cbp->pri_fc_thresh = 3; |
| 1702 | cbp->tx_fc_dis = 0; /* enable transmit FC */ |
| 1703 | cbp->rx_fc_restop = 1; /* enable FC restop frames */ |
| 1704 | cbp->rx_fc_restart = 1; /* enable FC restart frames */ |
| 1705 | cbp->fc_filter = !prm; /* drop FC frames to host */ |
| 1706 | cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ |
| 1707 | } |
| 1708 | |
| 1709 | /* |
| 1710 | * Start the config command/DMA. |
| 1711 | */ |
| 1712 | fxp_scb_wait(sc); |
| 1713 | CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); |
| 1714 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); |
| 1715 | /* ...and wait for it to complete. */ |
| 1716 | fxp_dma_wait(&cbp->cb_status, sc); |
| 1717 | |
| 1718 | /* |
| 1719 | * Now initialize the station address. Temporarily use the TxCB |
| 1720 | * memory area like we did above for the config CB. |
| 1721 | */ |
| 1722 | cb_ias = (struct fxp_cb_ias *) sc->cbl_base; |
| 1723 | cb_ias->cb_status = 0; |
| 1724 | cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; |
| 1725 | cb_ias->link_addr = -1; |
| 1726 | bcopy(sc->arpcom.ac_enaddr, |
| 1727 | (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, |
| 1728 | sizeof(sc->arpcom.ac_enaddr)); |
| 1729 | |
| 1730 | /* |
| 1731 | * Start the IAS (Individual Address Setup) command/DMA. |
| 1732 | */ |
| 1733 | fxp_scb_wait(sc); |
| 1734 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); |
| 1735 | /* ...and wait for it to complete. */ |
| 1736 | fxp_dma_wait(&cb_ias->cb_status, sc); |
| 1737 | |
| 1738 | /* |
| 1739 | * Initialize transmit control block (TxCB) list. |
| 1740 | */ |
| 1741 | |
| 1742 | txp = sc->cbl_base; |
| 1743 | bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); |
| 1744 | for (i = 0; i < FXP_NTXCB; i++) { |
| 1745 | txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; |
| 1746 | txp[i].cb_command = FXP_CB_COMMAND_NOP; |
| 1747 | txp[i].link_addr = |
| 1748 | vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); |
| 1749 | if (sc->flags & FXP_FLAG_EXT_TXCB) |
| 1750 | txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); |
| 1751 | else |
| 1752 | txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); |
| 1753 | txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; |
| 1754 | } |
| 1755 | /* |
| 1756 | * Set the suspend flag on the first TxCB and start the control |
| 1757 | * unit. It will execute the NOP and then suspend. |
| 1758 | */ |
| 1759 | txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; |
| 1760 | sc->cbl_first = sc->cbl_last = txp; |
| 1761 | sc->tx_queued = 1; |
| 1762 | |
| 1763 | fxp_scb_wait(sc); |
| 1764 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); |
| 1765 | |
| 1766 | /* |
| 1767 | * Initialize receiver buffer area - RFA. |
| 1768 | */ |
| 1769 | fxp_scb_wait(sc); |
| 1770 | CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, |
| 1771 | vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); |
| 1772 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); |
| 1773 | |
| 1774 | /* |
| 1775 | * Set current media. |
| 1776 | */ |
| 1777 | if (sc->miibus != NULL) |
| 1778 | mii_mediachg(device_get_softc(sc->miibus)); |
| 1779 | |
| 1780 | ifp->if_flags |= IFF_RUNNING; |
| 1781 | ifp->if_flags &= ~IFF_OACTIVE; |
| 1782 | |
| 1783 | /* |
| 1784 | * Enable interrupts. |
| 1785 | */ |
| 1786 | #ifdef DEVICE_POLLING |
| 1787 | /* |
| 1788 | * ... but only do that if we are not polling. And because (presumably) |
| 1789 | * the default is interrupts on, we need to disable them explicitly! |
| 1790 | */ |
| 1791 | if ( ifp->if_flags & IFF_POLLING ) |
| 1792 | CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); |
| 1793 | else |
| 1794 | #endif /* DEVICE_POLLING */ |
| 1795 | CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); |
| 1796 | |
| 1797 | /* |
| 1798 | * Start stats updater. |
| 1799 | */ |
| 1800 | callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); |
| 1801 | |
| 1802 | crit_exit(); |
| 1803 | } |
| 1804 | |
| 1805 | static int |
| 1806 | fxp_serial_ifmedia_upd(struct ifnet *ifp) |
| 1807 | { |
| 1808 | |
| 1809 | return (0); |
| 1810 | } |
| 1811 | |
| 1812 | static void |
| 1813 | fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) |
| 1814 | { |
| 1815 | |
| 1816 | ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; |
| 1817 | } |
| 1818 | |
| 1819 | /* |
| 1820 | * Change media according to request. |
| 1821 | */ |
| 1822 | static int |
| 1823 | fxp_ifmedia_upd(struct ifnet *ifp) |
| 1824 | { |
| 1825 | struct fxp_softc *sc = ifp->if_softc; |
| 1826 | struct mii_data *mii; |
| 1827 | |
| 1828 | mii = device_get_softc(sc->miibus); |
| 1829 | mii_mediachg(mii); |
| 1830 | return (0); |
| 1831 | } |
| 1832 | |
| 1833 | /* |
| 1834 | * Notify the world which media we're using. |
| 1835 | */ |
| 1836 | static void |
| 1837 | fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) |
| 1838 | { |
| 1839 | struct fxp_softc *sc = ifp->if_softc; |
| 1840 | struct mii_data *mii; |
| 1841 | |
| 1842 | mii = device_get_softc(sc->miibus); |
| 1843 | mii_pollstat(mii); |
| 1844 | ifmr->ifm_active = mii->mii_media_active; |
| 1845 | ifmr->ifm_status = mii->mii_media_status; |
| 1846 | |
| 1847 | if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) |
| 1848 | sc->cu_resume_bug = 1; |
| 1849 | else |
| 1850 | sc->cu_resume_bug = 0; |
| 1851 | } |
| 1852 | |
| 1853 | /* |
| 1854 | * Add a buffer to the end of the RFA buffer list. |
| 1855 | * Return 0 if successful, 1 for failure. A failure results in |
| 1856 | * adding the 'oldm' (if non-NULL) on to the end of the list - |
| 1857 | * tossing out its old contents and recycling it. |
| 1858 | * The RFA struct is stuck at the beginning of mbuf cluster and the |
| 1859 | * data pointer is fixed up to point just past it. |
| 1860 | */ |
| 1861 | static int |
| 1862 | fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) |
| 1863 | { |
| 1864 | u_int32_t v; |
| 1865 | struct mbuf *m; |
| 1866 | struct fxp_rfa *rfa, *p_rfa; |
| 1867 | |
| 1868 | m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); |
| 1869 | if (m == NULL) { /* try to recycle the old mbuf instead */ |
| 1870 | if (oldm == NULL) |
| 1871 | return 1; |
| 1872 | m = oldm; |
| 1873 | m->m_data = m->m_ext.ext_buf; |
| 1874 | } |
| 1875 | |
| 1876 | /* |
| 1877 | * Move the data pointer up so that the incoming data packet |
| 1878 | * will be 32-bit aligned. |
| 1879 | */ |
| 1880 | m->m_data += RFA_ALIGNMENT_FUDGE; |
| 1881 | |
| 1882 | /* |
| 1883 | * Get a pointer to the base of the mbuf cluster and move |
| 1884 | * data start past it. |
| 1885 | */ |
| 1886 | rfa = mtod(m, struct fxp_rfa *); |
| 1887 | m->m_data += sizeof(struct fxp_rfa); |
| 1888 | rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); |
| 1889 | |
| 1890 | /* |
| 1891 | * Initialize the rest of the RFA. Note that since the RFA |
| 1892 | * is misaligned, we cannot store values directly. Instead, |
| 1893 | * we use an optimized, inline copy. |
| 1894 | */ |
| 1895 | |
| 1896 | rfa->rfa_status = 0; |
| 1897 | rfa->rfa_control = FXP_RFA_CONTROL_EL; |
| 1898 | rfa->actual_size = 0; |
| 1899 | |
| 1900 | v = -1; |
| 1901 | fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); |
| 1902 | fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); |
| 1903 | |
| 1904 | /* |
| 1905 | * If there are other buffers already on the list, attach this |
| 1906 | * one to the end by fixing up the tail to point to this one. |
| 1907 | */ |
| 1908 | if (sc->rfa_headm != NULL) { |
| 1909 | p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + |
| 1910 | RFA_ALIGNMENT_FUDGE); |
| 1911 | sc->rfa_tailm->m_next = m; |
| 1912 | v = vtophys(rfa); |
| 1913 | fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); |
| 1914 | p_rfa->rfa_control = 0; |
| 1915 | } else { |
| 1916 | sc->rfa_headm = m; |
| 1917 | } |
| 1918 | sc->rfa_tailm = m; |
| 1919 | |
| 1920 | return (m == oldm); |
| 1921 | } |
| 1922 | |
| 1923 | static volatile int |
| 1924 | fxp_miibus_readreg(device_t dev, int phy, int reg) |
| 1925 | { |
| 1926 | struct fxp_softc *sc = device_get_softc(dev); |
| 1927 | int count = 10000; |
| 1928 | int value; |
| 1929 | |
| 1930 | CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, |
| 1931 | (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); |
| 1932 | |
| 1933 | while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 |
| 1934 | && count--) |
| 1935 | DELAY(10); |
| 1936 | |
| 1937 | if (count <= 0) |
| 1938 | device_printf(dev, "fxp_miibus_readreg: timed out\n"); |
| 1939 | |
| 1940 | return (value & 0xffff); |
| 1941 | } |
| 1942 | |
| 1943 | static void |
| 1944 | fxp_miibus_writereg(device_t dev, int phy, int reg, int value) |
| 1945 | { |
| 1946 | struct fxp_softc *sc = device_get_softc(dev); |
| 1947 | int count = 10000; |
| 1948 | |
| 1949 | CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, |
| 1950 | (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | |
| 1951 | (value & 0xffff)); |
| 1952 | |
| 1953 | while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && |
| 1954 | count--) |
| 1955 | DELAY(10); |
| 1956 | |
| 1957 | if (count <= 0) |
| 1958 | device_printf(dev, "fxp_miibus_writereg: timed out\n"); |
| 1959 | } |
| 1960 | |
| 1961 | static int |
| 1962 | fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) |
| 1963 | { |
| 1964 | struct fxp_softc *sc = ifp->if_softc; |
| 1965 | struct ifreq *ifr = (struct ifreq *)data; |
| 1966 | struct mii_data *mii; |
| 1967 | int error = 0; |
| 1968 | |
| 1969 | crit_enter(); |
| 1970 | |
| 1971 | switch (command) { |
| 1972 | |
| 1973 | case SIOCSIFFLAGS: |
| 1974 | if (ifp->if_flags & IFF_ALLMULTI) |
| 1975 | sc->flags |= FXP_FLAG_ALL_MCAST; |
| 1976 | else |
| 1977 | sc->flags &= ~FXP_FLAG_ALL_MCAST; |
| 1978 | |
| 1979 | /* |
| 1980 | * If interface is marked up and not running, then start it. |
| 1981 | * If it is marked down and running, stop it. |
| 1982 | * XXX If it's up then re-initialize it. This is so flags |
| 1983 | * such as IFF_PROMISC are handled. |
| 1984 | */ |
| 1985 | if (ifp->if_flags & IFF_UP) { |
| 1986 | fxp_init(sc); |
| 1987 | } else { |
| 1988 | if (ifp->if_flags & IFF_RUNNING) |
| 1989 | fxp_stop(sc); |
| 1990 | } |
| 1991 | break; |
| 1992 | |
| 1993 | case SIOCADDMULTI: |
| 1994 | case SIOCDELMULTI: |
| 1995 | if (ifp->if_flags & IFF_ALLMULTI) |
| 1996 | sc->flags |= FXP_FLAG_ALL_MCAST; |
| 1997 | else |
| 1998 | sc->flags &= ~FXP_FLAG_ALL_MCAST; |
| 1999 | /* |
| 2000 | * Multicast list has changed; set the hardware filter |
| 2001 | * accordingly. |
| 2002 | */ |
| 2003 | if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) |
| 2004 | fxp_mc_setup(sc); |
| 2005 | /* |
| 2006 | * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it |
| 2007 | * again rather than else {}. |
| 2008 | */ |
| 2009 | if (sc->flags & FXP_FLAG_ALL_MCAST) |
| 2010 | fxp_init(sc); |
| 2011 | error = 0; |
| 2012 | break; |
| 2013 | |
| 2014 | case SIOCSIFMEDIA: |
| 2015 | case SIOCGIFMEDIA: |
| 2016 | if (sc->miibus != NULL) { |
| 2017 | mii = device_get_softc(sc->miibus); |
| 2018 | error = ifmedia_ioctl(ifp, ifr, |
| 2019 | &mii->mii_media, command); |
| 2020 | } else { |
| 2021 | error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); |
| 2022 | } |
| 2023 | break; |
| 2024 | |
| 2025 | default: |
| 2026 | error = ether_ioctl(ifp, command, data); |
| 2027 | break; |
| 2028 | } |
| 2029 | |
| 2030 | crit_exit(); |
| 2031 | |
| 2032 | return (error); |
| 2033 | } |
| 2034 | |
| 2035 | /* |
| 2036 | * Fill in the multicast address list and return number of entries. |
| 2037 | */ |
| 2038 | static int |
| 2039 | fxp_mc_addrs(struct fxp_softc *sc) |
| 2040 | { |
| 2041 | struct fxp_cb_mcs *mcsp = sc->mcsp; |
| 2042 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 2043 | struct ifmultiaddr *ifma; |
| 2044 | int nmcasts; |
| 2045 | |
| 2046 | nmcasts = 0; |
| 2047 | if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { |
| 2048 | LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { |
| 2049 | if (ifma->ifma_addr->sa_family != AF_LINK) |
| 2050 | continue; |
| 2051 | if (nmcasts >= MAXMCADDR) { |
| 2052 | sc->flags |= FXP_FLAG_ALL_MCAST; |
| 2053 | nmcasts = 0; |
| 2054 | break; |
| 2055 | } |
| 2056 | bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), |
| 2057 | (void *)(uintptr_t)(volatile void *) |
| 2058 | &sc->mcsp->mc_addr[nmcasts][0], 6); |
| 2059 | nmcasts++; |
| 2060 | } |
| 2061 | } |
| 2062 | mcsp->mc_cnt = nmcasts * 6; |
| 2063 | return (nmcasts); |
| 2064 | } |
| 2065 | |
| 2066 | /* |
| 2067 | * Program the multicast filter. |
| 2068 | * |
| 2069 | * We have an artificial restriction that the multicast setup command |
| 2070 | * must be the first command in the chain, so we take steps to ensure |
| 2071 | * this. By requiring this, it allows us to keep up the performance of |
| 2072 | * the pre-initialized command ring (esp. link pointers) by not actually |
| 2073 | * inserting the mcsetup command in the ring - i.e. its link pointer |
| 2074 | * points to the TxCB ring, but the mcsetup descriptor itself is not part |
| 2075 | * of it. We then can do 'CU_START' on the mcsetup descriptor and have it |
| 2076 | * lead into the regular TxCB ring when it completes. |
| 2077 | * |
| 2078 | * This function must be called at splimp. |
| 2079 | */ |
| 2080 | static void |
| 2081 | fxp_mc_setup(struct fxp_softc *sc) |
| 2082 | { |
| 2083 | struct fxp_cb_mcs *mcsp = sc->mcsp; |
| 2084 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 2085 | int count; |
| 2086 | |
| 2087 | /* |
| 2088 | * If there are queued commands, we must wait until they are all |
| 2089 | * completed. If we are already waiting, then add a NOP command |
| 2090 | * with interrupt option so that we're notified when all commands |
| 2091 | * have been completed - fxp_start() ensures that no additional |
| 2092 | * TX commands will be added when need_mcsetup is true. |
| 2093 | */ |
| 2094 | if (sc->tx_queued) { |
| 2095 | struct fxp_cb_tx *txp; |
| 2096 | |
| 2097 | /* |
| 2098 | * need_mcsetup will be true if we are already waiting for the |
| 2099 | * NOP command to be completed (see below). In this case, bail. |
| 2100 | */ |
| 2101 | if (sc->need_mcsetup) |
| 2102 | return; |
| 2103 | sc->need_mcsetup = 1; |
| 2104 | |
| 2105 | /* |
| 2106 | * Add a NOP command with interrupt so that we are notified |
| 2107 | * when all TX commands have been processed. |
| 2108 | */ |
| 2109 | txp = sc->cbl_last->next; |
| 2110 | txp->mb_head = NULL; |
| 2111 | txp->cb_status = 0; |
| 2112 | txp->cb_command = FXP_CB_COMMAND_NOP | |
| 2113 | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; |
| 2114 | /* |
| 2115 | * Advance the end of list forward. |
| 2116 | */ |
| 2117 | sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; |
| 2118 | sc->cbl_last = txp; |
| 2119 | sc->tx_queued++; |
| 2120 | /* |
| 2121 | * Issue a resume in case the CU has just suspended. |
| 2122 | */ |
| 2123 | fxp_scb_wait(sc); |
| 2124 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); |
| 2125 | /* |
| 2126 | * Set a 5 second timer just in case we don't hear from the |
| 2127 | * card again. |
| 2128 | */ |
| 2129 | ifp->if_timer = 5; |
| 2130 | |
| 2131 | return; |
| 2132 | } |
| 2133 | sc->need_mcsetup = 0; |
| 2134 | |
| 2135 | /* |
| 2136 | * Initialize multicast setup descriptor. |
| 2137 | */ |
| 2138 | mcsp->next = sc->cbl_base; |
| 2139 | mcsp->mb_head = NULL; |
| 2140 | mcsp->cb_status = 0; |
| 2141 | mcsp->cb_command = FXP_CB_COMMAND_MCAS | |
| 2142 | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; |
| 2143 | mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); |
| 2144 | (void) fxp_mc_addrs(sc); |
| 2145 | sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; |
| 2146 | sc->tx_queued = 1; |
| 2147 | |
| 2148 | /* |
| 2149 | * Wait until command unit is not active. This should never |
| 2150 | * be the case when nothing is queued, but make sure anyway. |
| 2151 | */ |
| 2152 | count = 100; |
| 2153 | while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == |
| 2154 | FXP_SCB_CUS_ACTIVE && --count) |
| 2155 | DELAY(10); |
| 2156 | if (count == 0) { |
| 2157 | if_printf(&sc->arpcom.ac_if, "command queue timeout\n"); |
| 2158 | return; |
| 2159 | } |
| 2160 | |
| 2161 | /* |
| 2162 | * Start the multicast setup command. |
| 2163 | */ |
| 2164 | fxp_scb_wait(sc); |
| 2165 | CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); |
| 2166 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); |
| 2167 | |
| 2168 | ifp->if_timer = 2; |
| 2169 | return; |
| 2170 | } |
| 2171 | |
| 2172 | static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; |
| 2173 | static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; |
| 2174 | static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; |
| 2175 | static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; |
| 2176 | static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; |
| 2177 | static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; |
| 2178 | |
| 2179 | #define UCODE(x) x, sizeof(x) |
| 2180 | |
| 2181 | struct ucode { |
| 2182 | u_int32_t revision; |
| 2183 | u_int32_t *ucode; |
| 2184 | int length; |
| 2185 | u_short int_delay_offset; |
| 2186 | u_short bundle_max_offset; |
| 2187 | } ucode_table[] = { |
| 2188 | { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, |
| 2189 | { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, |
| 2190 | { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), |
| 2191 | D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, |
| 2192 | { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), |
| 2193 | D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, |
| 2194 | { FXP_REV_82550, UCODE(fxp_ucode_d102), |
| 2195 | D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, |
| 2196 | { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), |
| 2197 | D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, |
| 2198 | { 0, NULL, 0, 0, 0 } |
| 2199 | }; |
| 2200 | |
| 2201 | static void |
| 2202 | fxp_load_ucode(struct fxp_softc *sc) |
| 2203 | { |
| 2204 | struct ucode *uc; |
| 2205 | struct fxp_cb_ucode *cbp; |
| 2206 | |
| 2207 | for (uc = ucode_table; uc->ucode != NULL; uc++) |
| 2208 | if (sc->revision == uc->revision) |
| 2209 | break; |
| 2210 | if (uc->ucode == NULL) |
| 2211 | return; |
| 2212 | cbp = (struct fxp_cb_ucode *)sc->cbl_base; |
| 2213 | cbp->cb_status = 0; |
| 2214 | cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; |
| 2215 | cbp->link_addr = -1; /* (no) next command */ |
| 2216 | memcpy(cbp->ucode, uc->ucode, uc->length); |
| 2217 | if (uc->int_delay_offset) |
| 2218 | *(u_short *)&cbp->ucode[uc->int_delay_offset] = |
| 2219 | sc->tunable_int_delay + sc->tunable_int_delay / 2; |
| 2220 | if (uc->bundle_max_offset) |
| 2221 | *(u_short *)&cbp->ucode[uc->bundle_max_offset] = |
| 2222 | sc->tunable_bundle_max; |
| 2223 | /* |
| 2224 | * Download the ucode to the chip. |
| 2225 | */ |
| 2226 | fxp_scb_wait(sc); |
| 2227 | CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); |
| 2228 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); |
| 2229 | /* ...and wait for it to complete. */ |
| 2230 | fxp_dma_wait(&cbp->cb_status, sc); |
| 2231 | if_printf(&sc->arpcom.ac_if, |
| 2232 | "Microcode loaded, int_delay: %d usec bundle_max: %d\n", |
| 2233 | sc->tunable_int_delay, |
| 2234 | uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); |
| 2235 | sc->flags |= FXP_FLAG_UCODE; |
| 2236 | } |
| 2237 | |
| 2238 | static int |
| 2239 | sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) |
| 2240 | { |
| 2241 | int error, value; |
| 2242 | |
| 2243 | value = *(int *)arg1; |
| 2244 | error = sysctl_handle_int(oidp, &value, 0, req); |
| 2245 | if (error || !req->newptr) |
| 2246 | return (error); |
| 2247 | if (value < low || value > high) |
| 2248 | return (EINVAL); |
| 2249 | *(int *)arg1 = value; |
| 2250 | return (0); |
| 2251 | } |
| 2252 | |
| 2253 | /* |
| 2254 | * Interrupt delay is expressed in microseconds, a multiplier is used |
| 2255 | * to convert this to the appropriate clock ticks before using. |
| 2256 | */ |
| 2257 | static int |
| 2258 | sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) |
| 2259 | { |
| 2260 | return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); |
| 2261 | } |
| 2262 | |
| 2263 | static int |
| 2264 | sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) |
| 2265 | { |
| 2266 | return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); |
| 2267 | } |