| 1 | /*- |
| 2 | * Copyright (c) 1995 - 2001 John Hay. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions |
| 6 | * are met: |
| 7 | * 1. Redistributions of source code must retain the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer. |
| 9 | * 2. Redistributions in binary form must reproduce the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer in the |
| 11 | * documentation and/or other materials provided with the distribution. |
| 12 | * 3. Neither the name of the author nor the names of any co-contributors |
| 13 | * may be used to endorse or promote products derived from this software |
| 14 | * without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY John Hay ``AS IS'' AND |
| 17 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL John Hay BE LIABLE |
| 20 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 21 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 22 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 26 | * SUCH DAMAGE. |
| 27 | * |
| 28 | * $FreeBSD: src/sys/dev/ar/if_ar.c,v 1.66 2005/01/06 01:42:28 imp Exp $ |
| 29 | * $DragonFly: src/sys/dev/netif/ar/if_ar.c,v 1.16 2005/06/13 20:36:45 joerg Exp $ |
| 30 | */ |
| 31 | |
| 32 | /* |
| 33 | * Programming assumptions and other issues. |
| 34 | * |
| 35 | * The descriptors of a DMA channel will fit in a 16K memory window. |
| 36 | * |
| 37 | * The buffers of a transmit DMA channel will fit in a 16K memory window. |
| 38 | * |
| 39 | * Only the ISA bus cards with X.21 and V.35 is tested. |
| 40 | * |
| 41 | * When interface is going up, handshaking is set and it is only cleared |
| 42 | * when the interface is down'ed. |
| 43 | * |
| 44 | * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE, |
| 45 | * internal/external clock, etc..... |
| 46 | */ |
| 47 | |
| 48 | #include "opt_netgraph.h" |
| 49 | |
| 50 | #include <sys/param.h> |
| 51 | #include <sys/systm.h> |
| 52 | #include <sys/kernel.h> |
| 53 | #include <sys/malloc.h> |
| 54 | #include <sys/mbuf.h> |
| 55 | #include <sys/socket.h> |
| 56 | #include <sys/sockio.h> |
| 57 | #include <sys/module.h> |
| 58 | #include <sys/thread2.h> |
| 59 | #include <sys/bus.h> |
| 60 | #include <machine/bus.h> |
| 61 | #include <machine/resource.h> |
| 62 | #include <machine/bus_pio.h> |
| 63 | #include <machine/bus_memio.h> |
| 64 | #include <sys/rman.h> |
| 65 | |
| 66 | #include <net/if.h> |
| 67 | #ifdef NETGRAPH |
| 68 | #include <netgraph/ng_message.h> |
| 69 | #include <netgraph/netgraph.h> |
| 70 | #include <sys/syslog.h> |
| 71 | #include <dev/netif/ar/if_ar.h> |
| 72 | #else /* NETGRAPH */ |
| 73 | #include <net/sppp/if_sppp.h> |
| 74 | #include <net/bpf.h> |
| 75 | #endif /* NETGRAPH */ |
| 76 | |
| 77 | #include <machine/md_var.h> |
| 78 | |
| 79 | #include <dev/netif/ic_layer/hd64570.h> |
| 80 | #include <dev/netif/ar/if_arregs.h> |
| 81 | |
| 82 | #ifdef TRACE |
| 83 | #define TRC(x) x |
| 84 | #else |
| 85 | #define TRC(x) |
| 86 | #endif |
| 87 | |
| 88 | #define TRCL(x) x |
| 89 | |
| 90 | #define PPP_HEADER_LEN 4 |
| 91 | |
| 92 | devclass_t ar_devclass; |
| 93 | |
| 94 | struct ar_softc { |
| 95 | #ifndef NETGRAPH |
| 96 | struct sppp ifsppp; |
| 97 | #endif /* NETGRAPH */ |
| 98 | int unit; /* With regards to all ar devices */ |
| 99 | int subunit; /* With regards to this card */ |
| 100 | struct ar_hardc *hc; |
| 101 | |
| 102 | struct buf_block { |
| 103 | u_int txdesc; /* On card address */ |
| 104 | u_int txstart; /* On card address */ |
| 105 | u_int txend; /* On card address */ |
| 106 | u_int txtail; /* Index of first unused buffer */ |
| 107 | u_int txmax; /* number of usable buffers/descriptors */ |
| 108 | u_int txeda; /* Error descriptor addresses */ |
| 109 | }block[AR_TX_BLOCKS]; |
| 110 | |
| 111 | char xmit_busy; /* Transmitter is busy */ |
| 112 | char txb_inuse; /* Number of tx blocks currently in use */ |
| 113 | u_char txb_new; /* Index to where new buffer will be added */ |
| 114 | u_char txb_next_tx; /* Index to next block ready to tx */ |
| 115 | |
| 116 | u_int rxdesc; /* On card address */ |
| 117 | u_int rxstart; /* On card address */ |
| 118 | u_int rxend; /* On card address */ |
| 119 | u_int rxhind; /* Index to the head of the rx buffers. */ |
| 120 | u_int rxmax; /* number of usable buffers/descriptors */ |
| 121 | |
| 122 | int scano; |
| 123 | int scachan; |
| 124 | sca_regs *sca; |
| 125 | #ifdef NETGRAPH |
| 126 | int running; /* something is attached so we are running */ |
| 127 | int dcd; /* do we have dcd? */ |
| 128 | /* ---netgraph bits --- */ |
| 129 | char nodename[NG_NODELEN + 1]; /* store our node name */ |
| 130 | int datahooks; /* number of data hooks attached */ |
| 131 | node_p node; /* netgraph node */ |
| 132 | hook_p hook; /* data hook */ |
| 133 | hook_p debug_hook; |
| 134 | struct ifqueue xmitq_hipri; /* hi-priority transmit queue */ |
| 135 | struct ifqueue xmitq; /* transmit queue */ |
| 136 | int flags; /* state */ |
| 137 | #define SCF_RUNNING 0x01 /* board is active */ |
| 138 | #define SCF_OACTIVE 0x02 /* output is active */ |
| 139 | int out_dog; /* watchdog cycles output count-down */ |
| 140 | struct callout timer; /* watchdog timer */ |
| 141 | u_long inbytes, outbytes; /* stats */ |
| 142 | u_long lastinbytes, lastoutbytes; /* a second ago */ |
| 143 | u_long inrate, outrate; /* highest rate seen */ |
| 144 | u_long inlast; /* last input N secs ago */ |
| 145 | u_long out_deficit; /* output since last input */ |
| 146 | u_long oerrors, ierrors[6]; |
| 147 | u_long opackets, ipackets; |
| 148 | #endif /* NETGRAPH */ |
| 149 | }; |
| 150 | |
| 151 | static int next_ar_unit = 0; |
| 152 | |
| 153 | #ifdef NETGRAPH |
| 154 | #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */ |
| 155 | #define QUITE_A_WHILE 300 /* 5 MINUTES */ |
| 156 | #define LOTS_OF_PACKETS 100 |
| 157 | #endif /* NETGRAPH */ |
| 158 | |
| 159 | /* |
| 160 | * This translate from irq numbers to |
| 161 | * the value that the arnet card needs |
| 162 | * in the lower part of the AR_INT_SEL |
| 163 | * register. |
| 164 | */ |
| 165 | static int irqtable[16] = { |
| 166 | 0, /* 0 */ |
| 167 | 0, /* 1 */ |
| 168 | 0, /* 2 */ |
| 169 | 1, /* 3 */ |
| 170 | 0, /* 4 */ |
| 171 | 2, /* 5 */ |
| 172 | 0, /* 6 */ |
| 173 | 3, /* 7 */ |
| 174 | 0, /* 8 */ |
| 175 | 0, /* 9 */ |
| 176 | 4, /* 10 */ |
| 177 | 5, /* 11 */ |
| 178 | 6, /* 12 */ |
| 179 | 0, /* 13 */ |
| 180 | 0, /* 14 */ |
| 181 | 7 /* 15 */ |
| 182 | }; |
| 183 | |
| 184 | #ifndef NETGRAPH |
| 185 | DECLARE_DUMMY_MODULE(if_ar); |
| 186 | MODULE_DEPEND(if_ar, sppp, 1, 1, 1); |
| 187 | #else |
| 188 | MODULE_DEPEND(ng_sync_ar, netgraph, 1, 1, 1); |
| 189 | #endif |
| 190 | |
| 191 | static void arintr(void *arg); |
| 192 | static void ar_xmit(struct ar_softc *sc); |
| 193 | #ifndef NETGRAPH |
| 194 | static void arstart(struct ifnet *ifp); |
| 195 | static int arioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *); |
| 196 | static void arwatchdog(struct ifnet *ifp); |
| 197 | #else /* NETGRAPH */ |
| 198 | static void arstart(struct ar_softc *sc); |
| 199 | static void arwatchdog(struct ar_softc *sc); |
| 200 | #endif /* NETGRAPH */ |
| 201 | static int ar_packet_avail(struct ar_softc *sc, int *len, u_char *rxstat); |
| 202 | static void ar_copy_rxbuf(struct mbuf *m, struct ar_softc *sc, int len); |
| 203 | static void ar_eat_packet(struct ar_softc *sc, int single); |
| 204 | static void ar_get_packets(struct ar_softc *sc); |
| 205 | |
| 206 | static int ar_read_pim_iface(volatile struct ar_hardc *hc, int channel); |
| 207 | static void ar_up(struct ar_softc *sc); |
| 208 | static void ar_down(struct ar_softc *sc); |
| 209 | static void arc_init(struct ar_hardc *hc); |
| 210 | static void ar_init_sca(struct ar_hardc *hc, int scano); |
| 211 | static void ar_init_msci(struct ar_softc *sc); |
| 212 | static void ar_init_rx_dmac(struct ar_softc *sc); |
| 213 | static void ar_init_tx_dmac(struct ar_softc *sc); |
| 214 | static void ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr); |
| 215 | static void ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr); |
| 216 | static void ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr); |
| 217 | |
| 218 | #ifdef NETGRAPH |
| 219 | static void ngar_watchdog_frame(void * arg); |
| 220 | static void ngar_init(void* ignored); |
| 221 | |
| 222 | static ng_constructor_t ngar_constructor; |
| 223 | static ng_rcvmsg_t ngar_rcvmsg; |
| 224 | static ng_shutdown_t ngar_shutdown; |
| 225 | static ng_newhook_t ngar_newhook; |
| 226 | /*static ng_findhook_t ngar_findhook; */ |
| 227 | static ng_connect_t ngar_connect; |
| 228 | static ng_rcvdata_t ngar_rcvdata; |
| 229 | static ng_disconnect_t ngar_disconnect; |
| 230 | |
| 231 | static struct ng_type typestruct = { |
| 232 | NG_VERSION, |
| 233 | NG_AR_NODE_TYPE, |
| 234 | NULL, |
| 235 | ngar_constructor, |
| 236 | ngar_rcvmsg, |
| 237 | ngar_shutdown, |
| 238 | ngar_newhook, |
| 239 | NULL, |
| 240 | ngar_connect, |
| 241 | ngar_rcvdata, |
| 242 | ngar_rcvdata, |
| 243 | ngar_disconnect, |
| 244 | NULL |
| 245 | }; |
| 246 | |
| 247 | static int ngar_done_init = 0; |
| 248 | #endif /* NETGRAPH */ |
| 249 | |
| 250 | int |
| 251 | ar_attach(device_t device) |
| 252 | { |
| 253 | struct ar_hardc *hc; |
| 254 | struct ar_softc *sc; |
| 255 | #ifndef NETGRAPH |
| 256 | struct ifnet *ifp; |
| 257 | char *iface; |
| 258 | #endif /* NETGRAPH */ |
| 259 | int unit; |
| 260 | int error; |
| 261 | |
| 262 | hc = (struct ar_hardc *)device_get_softc(device); |
| 263 | |
| 264 | printf("arc%d: %uK RAM, %u ports, rev %u.\n", |
| 265 | hc->cunit, |
| 266 | hc->memsize/1024, |
| 267 | hc->numports, |
| 268 | hc->revision); |
| 269 | |
| 270 | arc_init(hc); |
| 271 | |
| 272 | error = BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq, |
| 273 | INTR_TYPE_NET, arintr, hc, |
| 274 | &hc->intr_cookie, NULL); |
| 275 | if (error) |
| 276 | return (1); |
| 277 | |
| 278 | sc = hc->sc; |
| 279 | |
| 280 | for(unit=0;unit<hc->numports;unit+=NCHAN) |
| 281 | ar_init_sca(hc, unit / NCHAN); |
| 282 | |
| 283 | /* |
| 284 | * Now configure each port on the card. |
| 285 | */ |
| 286 | for(unit=0;unit<hc->numports;sc++,unit++) { |
| 287 | sc->hc = hc; |
| 288 | sc->subunit = unit; |
| 289 | sc->unit = next_ar_unit; |
| 290 | next_ar_unit++; |
| 291 | sc->scano = unit / NCHAN; |
| 292 | sc->scachan = unit%NCHAN; |
| 293 | |
| 294 | ar_init_rx_dmac(sc); |
| 295 | ar_init_tx_dmac(sc); |
| 296 | ar_init_msci(sc); |
| 297 | |
| 298 | #ifndef NETGRAPH |
| 299 | ifp = &sc->ifsppp.pp_if; |
| 300 | |
| 301 | ifp->if_softc = sc; |
| 302 | if_initname(ifp, device_get_name(device), sc->unit); |
| 303 | ifp->if_mtu = PP_MTU; |
| 304 | ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST; |
| 305 | ifp->if_ioctl = arioctl; |
| 306 | ifp->if_start = arstart; |
| 307 | ifp->if_watchdog = arwatchdog; |
| 308 | |
| 309 | sc->ifsppp.pp_flags = PP_KEEPALIVE; |
| 310 | |
| 311 | switch(hc->interface[unit]) { |
| 312 | default: iface = "UNKNOWN"; break; |
| 313 | case AR_IFACE_EIA_232: iface = "EIA-232"; break; |
| 314 | case AR_IFACE_V_35: iface = "EIA-232 or V.35"; break; |
| 315 | case AR_IFACE_EIA_530: iface = "EIA-530"; break; |
| 316 | case AR_IFACE_X_21: iface = "X.21"; break; |
| 317 | case AR_IFACE_COMBO: iface = "COMBO X.21 / EIA-530"; break; |
| 318 | } |
| 319 | |
| 320 | printf("ar%d: Adapter %d, port %d, interface %s.\n", |
| 321 | sc->unit, |
| 322 | hc->cunit, |
| 323 | sc->subunit, |
| 324 | iface); |
| 325 | |
| 326 | sppp_attach((struct ifnet *)&sc->ifsppp); |
| 327 | if_attach(ifp); |
| 328 | |
| 329 | bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN); |
| 330 | #else /* NETGRAPH */ |
| 331 | /* |
| 332 | * we have found a node, make sure our 'type' is availabe. |
| 333 | */ |
| 334 | if (ngar_done_init == 0) ngar_init(NULL); |
| 335 | if (ng_make_node_common(&typestruct, &sc->node) != 0) |
| 336 | return (1); |
| 337 | sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit); |
| 338 | if (ng_name_node(sc->node, sc->nodename)) { |
| 339 | NG_NODE_UNREF(sc->node); /* drop it again */ |
| 340 | return (1); |
| 341 | } |
| 342 | NG_NODE_SET_PRIVATE(sc->node, sc); |
| 343 | callout_init(&sc->timer); |
| 344 | sc->xmitq.ifq_maxlen = IFQ_MAXLEN; |
| 345 | sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN; |
| 346 | sc->running = 0; |
| 347 | #endif /* NETGRAPH */ |
| 348 | } |
| 349 | |
| 350 | if(hc->bustype == AR_BUS_ISA) |
| 351 | ARC_SET_OFF(hc); |
| 352 | |
| 353 | return (0); |
| 354 | } |
| 355 | |
| 356 | int |
| 357 | ar_detach(device_t device) |
| 358 | { |
| 359 | device_t parent = device_get_parent(device); |
| 360 | struct ar_hardc *hc = device_get_softc(device); |
| 361 | |
| 362 | if (hc->intr_cookie != NULL) { |
| 363 | if (BUS_TEARDOWN_INTR(parent, device, |
| 364 | hc->res_irq, hc->intr_cookie) != 0) { |
| 365 | printf("intr teardown failed.. continuing\n"); |
| 366 | } |
| 367 | hc->intr_cookie = NULL; |
| 368 | } |
| 369 | |
| 370 | /* |
| 371 | * deallocate any system resources we may have |
| 372 | * allocated on behalf of this driver. |
| 373 | */ |
| 374 | FREE(hc->sc, M_DEVBUF); |
| 375 | hc->sc = NULL; |
| 376 | hc->mem_start = NULL; |
| 377 | return (ar_deallocate_resources(device)); |
| 378 | } |
| 379 | |
| 380 | int |
| 381 | ar_allocate_ioport(device_t device, int rid, u_long size) |
| 382 | { |
| 383 | struct ar_hardc *hc = device_get_softc(device); |
| 384 | |
| 385 | hc->rid_ioport = rid; |
| 386 | hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT, |
| 387 | &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE); |
| 388 | if (hc->res_ioport == NULL) { |
| 389 | goto errexit; |
| 390 | } |
| 391 | hc->bt = rman_get_bustag(hc->res_ioport); |
| 392 | hc->bh = rman_get_bushandle(hc->res_ioport); |
| 393 | |
| 394 | return (0); |
| 395 | |
| 396 | errexit: |
| 397 | ar_deallocate_resources(device); |
| 398 | return (ENXIO); |
| 399 | } |
| 400 | |
| 401 | int |
| 402 | ar_allocate_irq(device_t device, int rid, u_long size) |
| 403 | { |
| 404 | struct ar_hardc *hc = device_get_softc(device); |
| 405 | |
| 406 | hc->rid_irq = rid; |
| 407 | hc->res_irq = bus_alloc_resource_any(device, SYS_RES_IRQ, |
| 408 | &hc->rid_irq, RF_SHAREABLE|RF_ACTIVE); |
| 409 | if (hc->res_irq == NULL) { |
| 410 | goto errexit; |
| 411 | } |
| 412 | return (0); |
| 413 | |
| 414 | errexit: |
| 415 | ar_deallocate_resources(device); |
| 416 | return (ENXIO); |
| 417 | } |
| 418 | |
| 419 | int |
| 420 | ar_allocate_memory(device_t device, int rid, u_long size) |
| 421 | { |
| 422 | struct ar_hardc *hc = device_get_softc(device); |
| 423 | |
| 424 | hc->rid_memory = rid; |
| 425 | hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY, |
| 426 | &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE); |
| 427 | if (hc->res_memory == NULL) { |
| 428 | goto errexit; |
| 429 | } |
| 430 | return (0); |
| 431 | |
| 432 | errexit: |
| 433 | ar_deallocate_resources(device); |
| 434 | return (ENXIO); |
| 435 | } |
| 436 | |
| 437 | int |
| 438 | ar_allocate_plx_memory(device_t device, int rid, u_long size) |
| 439 | { |
| 440 | struct ar_hardc *hc = device_get_softc(device); |
| 441 | |
| 442 | hc->rid_plx_memory = rid; |
| 443 | hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY, |
| 444 | &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE); |
| 445 | if (hc->res_plx_memory == NULL) { |
| 446 | goto errexit; |
| 447 | } |
| 448 | return (0); |
| 449 | |
| 450 | errexit: |
| 451 | ar_deallocate_resources(device); |
| 452 | return (ENXIO); |
| 453 | } |
| 454 | |
| 455 | int |
| 456 | ar_deallocate_resources(device_t device) |
| 457 | { |
| 458 | struct ar_hardc *hc = device_get_softc(device); |
| 459 | |
| 460 | if (hc->res_irq != 0) { |
| 461 | bus_deactivate_resource(device, SYS_RES_IRQ, |
| 462 | hc->rid_irq, hc->res_irq); |
| 463 | bus_release_resource(device, SYS_RES_IRQ, |
| 464 | hc->rid_irq, hc->res_irq); |
| 465 | hc->res_irq = 0; |
| 466 | } |
| 467 | if (hc->res_ioport != 0) { |
| 468 | bus_deactivate_resource(device, SYS_RES_IOPORT, |
| 469 | hc->rid_ioport, hc->res_ioport); |
| 470 | bus_release_resource(device, SYS_RES_IOPORT, |
| 471 | hc->rid_ioport, hc->res_ioport); |
| 472 | hc->res_ioport = 0; |
| 473 | } |
| 474 | if (hc->res_memory != 0) { |
| 475 | bus_deactivate_resource(device, SYS_RES_MEMORY, |
| 476 | hc->rid_memory, hc->res_memory); |
| 477 | bus_release_resource(device, SYS_RES_MEMORY, |
| 478 | hc->rid_memory, hc->res_memory); |
| 479 | hc->res_memory = 0; |
| 480 | } |
| 481 | if (hc->res_plx_memory != 0) { |
| 482 | bus_deactivate_resource(device, SYS_RES_MEMORY, |
| 483 | hc->rid_plx_memory, hc->res_plx_memory); |
| 484 | bus_release_resource(device, SYS_RES_MEMORY, |
| 485 | hc->rid_plx_memory, hc->res_plx_memory); |
| 486 | hc->res_plx_memory = 0; |
| 487 | } |
| 488 | return (0); |
| 489 | } |
| 490 | |
| 491 | /* |
| 492 | * First figure out which SCA gave the interrupt. |
| 493 | * Process it. |
| 494 | * See if there is other interrupts pending. |
| 495 | * Repeat until there is no more interrupts. |
| 496 | */ |
| 497 | static void |
| 498 | arintr(void *arg) |
| 499 | { |
| 500 | struct ar_hardc *hc = (struct ar_hardc *)arg; |
| 501 | sca_regs *sca; |
| 502 | u_char isr0, isr1, isr2, arisr; |
| 503 | int scano; |
| 504 | |
| 505 | /* XXX Use the PCI interrupt score board register later */ |
| 506 | if(hc->bustype == AR_BUS_PCI) |
| 507 | arisr = hc->orbase[AR_ISTAT * 4]; |
| 508 | else |
| 509 | arisr = ar_inb(hc, AR_ISTAT); |
| 510 | |
| 511 | while(arisr & AR_BD_INT) { |
| 512 | TRC(printf("arisr = %x\n", arisr)); |
| 513 | if(arisr & AR_INT_0) |
| 514 | scano = 0; |
| 515 | else if(arisr & AR_INT_1) |
| 516 | scano = 1; |
| 517 | else { |
| 518 | /* XXX Oops this shouldn't happen. */ |
| 519 | printf("arc%d: Interrupted with no interrupt.\n", |
| 520 | hc->cunit); |
| 521 | return; |
| 522 | } |
| 523 | sca = hc->sca[scano]; |
| 524 | |
| 525 | if(hc->bustype == AR_BUS_ISA) |
| 526 | ARC_SET_SCA(hc, scano); |
| 527 | |
| 528 | isr0 = sca->isr0; |
| 529 | isr1 = sca->isr1; |
| 530 | isr2 = sca->isr2; |
| 531 | |
| 532 | TRC(printf("arc%d: ARINTR isr0 %x, isr1 %x, isr2 %x\n", |
| 533 | hc->cunit, |
| 534 | isr0, |
| 535 | isr1, |
| 536 | isr2)); |
| 537 | if(isr0) |
| 538 | ar_msci_intr(hc, scano, isr0); |
| 539 | |
| 540 | if(isr1) |
| 541 | ar_dmac_intr(hc, scano, isr1); |
| 542 | |
| 543 | if(isr2) |
| 544 | ar_timer_intr(hc, scano, isr2); |
| 545 | |
| 546 | /* |
| 547 | * Proccess the second sca's interrupt if available. |
| 548 | * Else see if there are any new interrupts. |
| 549 | */ |
| 550 | if((arisr & AR_INT_0) && (arisr & AR_INT_1)) |
| 551 | arisr &= ~AR_INT_0; |
| 552 | else { |
| 553 | if(hc->bustype == AR_BUS_PCI) |
| 554 | arisr = hc->orbase[AR_ISTAT * 4]; |
| 555 | else |
| 556 | arisr = ar_inb(hc, AR_ISTAT); |
| 557 | } |
| 558 | } |
| 559 | |
| 560 | if(hc->bustype == AR_BUS_ISA) |
| 561 | ARC_SET_OFF(hc); |
| 562 | } |
| 563 | |
| 564 | |
| 565 | /* |
| 566 | * This will only start the transmitter. It is assumed that the data |
| 567 | * is already there. It is normally called from arstart() or ar_dmac_intr(). |
| 568 | * |
| 569 | */ |
| 570 | static void |
| 571 | ar_xmit(struct ar_softc *sc) |
| 572 | { |
| 573 | #ifndef NETGRAPH |
| 574 | struct ifnet *ifp; |
| 575 | #endif /* NETGRAPH */ |
| 576 | dmac_channel *dmac; |
| 577 | |
| 578 | #ifndef NETGRAPH |
| 579 | ifp = &sc->ifsppp.pp_if; |
| 580 | #endif /* NETGRAPH */ |
| 581 | dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)]; |
| 582 | |
| 583 | if(sc->hc->bustype == AR_BUS_ISA) |
| 584 | ARC_SET_SCA(sc->hc, sc->scano); |
| 585 | dmac->cda = (u_short)(sc->block[sc->txb_next_tx].txdesc & 0xffff); |
| 586 | |
| 587 | dmac->eda = (u_short)(sc->block[sc->txb_next_tx].txeda & 0xffff); |
| 588 | dmac->dsr = SCA_DSR_DE; |
| 589 | |
| 590 | sc->xmit_busy = 1; |
| 591 | |
| 592 | sc->txb_next_tx++; |
| 593 | if(sc->txb_next_tx == AR_TX_BLOCKS) |
| 594 | sc->txb_next_tx = 0; |
| 595 | |
| 596 | #ifndef NETGRAPH |
| 597 | ifp->if_timer = 2; /* Value in seconds. */ |
| 598 | #else /* NETGRAPH */ |
| 599 | sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/ |
| 600 | #endif /* NETGRAPH */ |
| 601 | if(sc->hc->bustype == AR_BUS_ISA) |
| 602 | ARC_SET_OFF(sc->hc); |
| 603 | } |
| 604 | |
| 605 | /* |
| 606 | * This function will be called from the upper level when a user add a |
| 607 | * packet to be send, and from the interrupt handler after a finished |
| 608 | * transmit. |
| 609 | * |
| 610 | * This function only place the data in the oncard buffers. It does not |
| 611 | * start the transmition. ar_xmit() does that. |
| 612 | * |
| 613 | * Transmitter idle state is indicated by the IFF_OACTIVE flag. The function |
| 614 | * that clears that should ensure that the transmitter and its DMA is |
| 615 | * in a "good" idle state. |
| 616 | */ |
| 617 | #ifndef NETGRAPH |
| 618 | static void |
| 619 | arstart(struct ifnet *ifp) |
| 620 | { |
| 621 | struct ar_softc *sc = ifp->if_softc; |
| 622 | #else /* NETGRAPH */ |
| 623 | static void |
| 624 | arstart(struct ar_softc *sc) |
| 625 | { |
| 626 | #endif /* NETGRAPH */ |
| 627 | int i, len, tlen; |
| 628 | struct mbuf *mtx; |
| 629 | u_char *txdata; |
| 630 | sca_descriptor *txdesc; |
| 631 | struct buf_block *blkp; |
| 632 | |
| 633 | #ifndef NETGRAPH |
| 634 | if(!(ifp->if_flags & IFF_RUNNING)) |
| 635 | return; |
| 636 | #else /* NETGRAPH */ |
| 637 | /* XXX */ |
| 638 | #endif /* NETGRAPH */ |
| 639 | |
| 640 | top_arstart: |
| 641 | |
| 642 | /* |
| 643 | * See if we have space for more packets. |
| 644 | */ |
| 645 | if(sc->txb_inuse == AR_TX_BLOCKS) { |
| 646 | #ifndef NETGRAPH |
| 647 | ifp->if_flags |= IFF_OACTIVE; /* yes, mark active */ |
| 648 | #else /* NETGRAPH */ |
| 649 | /*XXX*/ /*ifp->if_flags |= IFF_OACTIVE;*/ /* yes, mark active */ |
| 650 | #endif /* NETGRAPH */ |
| 651 | return; |
| 652 | } |
| 653 | |
| 654 | #ifndef NETGRAPH |
| 655 | mtx = sppp_dequeue(ifp); |
| 656 | #else /* NETGRAPH */ |
| 657 | IF_DEQUEUE(&sc->xmitq_hipri, mtx); |
| 658 | if (mtx == NULL) { |
| 659 | IF_DEQUEUE(&sc->xmitq, mtx); |
| 660 | } |
| 661 | #endif /* NETGRAPH */ |
| 662 | if(!mtx) |
| 663 | return; |
| 664 | |
| 665 | /* |
| 666 | * It is OK to set the memory window outside the loop because |
| 667 | * all tx buffers and descriptors are assumed to be in the same |
| 668 | * 16K window. |
| 669 | */ |
| 670 | if(sc->hc->bustype == AR_BUS_ISA) |
| 671 | ARC_SET_MEM(sc->hc, sc->block[0].txdesc); |
| 672 | |
| 673 | /* |
| 674 | * We stay in this loop until there is nothing in the |
| 675 | * TX queue left or the tx buffer is full. |
| 676 | */ |
| 677 | i = 0; |
| 678 | blkp = &sc->block[sc->txb_new]; |
| 679 | txdesc = (sca_descriptor *) |
| 680 | (sc->hc->mem_start + (blkp->txdesc & sc->hc->winmsk)); |
| 681 | txdata = (u_char *)(sc->hc->mem_start + (blkp->txstart & sc->hc->winmsk)); |
| 682 | for(;;) { |
| 683 | len = mtx->m_pkthdr.len; |
| 684 | |
| 685 | TRC(printf("ar%d: ARstart len %u\n", sc->unit, len)); |
| 686 | |
| 687 | /* |
| 688 | * We can do this because the tx buffers don't wrap. |
| 689 | */ |
| 690 | m_copydata(mtx, 0, len, txdata); |
| 691 | tlen = len; |
| 692 | while(tlen > AR_BUF_SIZ) { |
| 693 | txdesc->stat = 0; |
| 694 | txdesc->len = AR_BUF_SIZ; |
| 695 | tlen -= AR_BUF_SIZ; |
| 696 | txdesc++; |
| 697 | txdata += AR_BUF_SIZ; |
| 698 | i++; |
| 699 | } |
| 700 | /* XXX Move into the loop? */ |
| 701 | txdesc->stat = SCA_DESC_EOM; |
| 702 | txdesc->len = tlen; |
| 703 | txdesc++; |
| 704 | txdata += AR_BUF_SIZ; |
| 705 | i++; |
| 706 | |
| 707 | #ifndef NETGRAPH |
| 708 | BPF_MTAP(ifp, mtx); |
| 709 | m_freem(mtx); |
| 710 | ++sc->ifsppp.pp_if.if_opackets; |
| 711 | #else /* NETGRAPH */ |
| 712 | m_freem(mtx); |
| 713 | sc->outbytes += len; |
| 714 | ++sc->opackets; |
| 715 | #endif /* NETGRAPH */ |
| 716 | |
| 717 | /* |
| 718 | * Check if we have space for another mbuf. |
| 719 | * XXX This is hardcoded. A packet won't be larger |
| 720 | * than 3 buffers (3 x 512). |
| 721 | */ |
| 722 | if((i + 3) >= blkp->txmax) |
| 723 | break; |
| 724 | |
| 725 | #ifndef NETGRAPH |
| 726 | mtx = sppp_dequeue(ifp); |
| 727 | #else /* NETGRAPH */ |
| 728 | IF_DEQUEUE(&sc->xmitq_hipri, mtx); |
| 729 | if (mtx == NULL) { |
| 730 | IF_DEQUEUE(&sc->xmitq, mtx); |
| 731 | } |
| 732 | #endif /* NETGRAPH */ |
| 733 | if(!mtx) |
| 734 | break; |
| 735 | } |
| 736 | |
| 737 | blkp->txtail = i; |
| 738 | |
| 739 | /* |
| 740 | * Mark the last descriptor, so that the SCA know where |
| 741 | * to stop. |
| 742 | */ |
| 743 | txdesc--; |
| 744 | txdesc->stat |= SCA_DESC_EOT; |
| 745 | |
| 746 | txdesc = (sca_descriptor *)blkp->txdesc; |
| 747 | blkp->txeda = (u_short)((u_int)&txdesc[i]); |
| 748 | |
| 749 | #if 0 |
| 750 | printf("ARstart: %p desc->cp %x\n", &txdesc->cp, txdesc->cp); |
| 751 | printf("ARstart: %p desc->bp %x\n", &txdesc->bp, txdesc->bp); |
| 752 | printf("ARstart: %p desc->bpb %x\n", &txdesc->bpb, txdesc->bpb); |
| 753 | printf("ARstart: %p desc->len %x\n", &txdesc->len, txdesc->len); |
| 754 | printf("ARstart: %p desc->stat %x\n", &txdesc->stat, txdesc->stat); |
| 755 | #endif |
| 756 | |
| 757 | sc->txb_inuse++; |
| 758 | sc->txb_new++; |
| 759 | if(sc->txb_new == AR_TX_BLOCKS) |
| 760 | sc->txb_new = 0; |
| 761 | |
| 762 | if(sc->xmit_busy == 0) |
| 763 | ar_xmit(sc); |
| 764 | |
| 765 | if(sc->hc->bustype == AR_BUS_ISA) |
| 766 | ARC_SET_OFF(sc->hc); |
| 767 | |
| 768 | goto top_arstart; |
| 769 | } |
| 770 | |
| 771 | #ifndef NETGRAPH |
| 772 | static int |
| 773 | arioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) |
| 774 | { |
| 775 | int error; |
| 776 | int was_up, should_be_up; |
| 777 | struct ar_softc *sc = ifp->if_softc; |
| 778 | |
| 779 | TRC(if_printf(ifp, "arioctl.\n");) |
| 780 | |
| 781 | was_up = ifp->if_flags & IFF_RUNNING; |
| 782 | |
| 783 | error = sppp_ioctl(ifp, cmd, data); |
| 784 | TRC(if_printf(ifp, "ioctl: ifsppp.pp_flags = %x, if_flags %x.\n", |
| 785 | ((struct sppp *)ifp)->pp_flags, ifp->if_flags);) |
| 786 | if(error) |
| 787 | return (error); |
| 788 | |
| 789 | if((cmd != SIOCSIFFLAGS) && cmd != (SIOCSIFADDR)) |
| 790 | return (0); |
| 791 | |
| 792 | TRC(if_printf(ifp, "arioctl %s.\n", |
| 793 | (cmd == SIOCSIFFLAGS) ? "SIOCSIFFLAGS" : "SIOCSIFADDR");) |
| 794 | |
| 795 | crit_enter(); |
| 796 | |
| 797 | should_be_up = ifp->if_flags & IFF_RUNNING; |
| 798 | |
| 799 | if(!was_up && should_be_up) { |
| 800 | /* Interface should be up -- start it. */ |
| 801 | ar_up(sc); |
| 802 | arstart(ifp); |
| 803 | /* XXX Maybe clear the IFF_UP flag so that the link |
| 804 | * will only go up after sppp lcp and ipcp negotiation. |
| 805 | */ |
| 806 | } else if(was_up && !should_be_up) { |
| 807 | /* Interface should be down -- stop it. */ |
| 808 | ar_down(sc); |
| 809 | sppp_flush(ifp); |
| 810 | } |
| 811 | |
| 812 | crit_exit(); |
| 813 | return (0); |
| 814 | } |
| 815 | #endif /* NETGRAPH */ |
| 816 | |
| 817 | /* |
| 818 | * This is to catch lost tx interrupts. |
| 819 | */ |
| 820 | static void |
| 821 | #ifndef NETGRAPH |
| 822 | arwatchdog(struct ifnet *ifp) |
| 823 | { |
| 824 | struct ar_softc *sc = ifp->if_softc; |
| 825 | #else /* NETGRAPH */ |
| 826 | arwatchdog(struct ar_softc *sc) |
| 827 | { |
| 828 | #endif /* NETGRAPH */ |
| 829 | msci_channel *msci = &sc->sca->msci[sc->scachan]; |
| 830 | |
| 831 | #ifndef NETGRAPH |
| 832 | if(!(ifp->if_flags & IFF_RUNNING)) |
| 833 | return; |
| 834 | #endif /* NETGRAPH */ |
| 835 | |
| 836 | if(sc->hc->bustype == AR_BUS_ISA) |
| 837 | ARC_SET_SCA(sc->hc, sc->scano); |
| 838 | |
| 839 | /* XXX if(sc->ifsppp.pp_if.if_flags & IFF_DEBUG) */ |
| 840 | printf("ar%d: transmit failed, " |
| 841 | "ST0 %x, ST1 %x, ST3 %x, DSR %x.\n", |
| 842 | sc->unit, |
| 843 | msci->st0, |
| 844 | msci->st1, |
| 845 | msci->st3, |
| 846 | sc->sca->dmac[DMAC_TXCH(sc->scachan)].dsr); |
| 847 | |
| 848 | if(msci->st1 & SCA_ST1_UDRN) { |
| 849 | msci->cmd = SCA_CMD_TXABORT; |
| 850 | msci->cmd = SCA_CMD_TXENABLE; |
| 851 | msci->st1 = SCA_ST1_UDRN; |
| 852 | } |
| 853 | |
| 854 | sc->xmit_busy = 0; |
| 855 | #ifndef NETGRAPH |
| 856 | ifp->if_flags &= ~IFF_OACTIVE; |
| 857 | #else /* NETGRAPH */ |
| 858 | /* XXX ifp->if_flags &= ~IFF_OACTIVE; */ |
| 859 | #endif /* NETGRAPH */ |
| 860 | |
| 861 | if(sc->txb_inuse && --sc->txb_inuse) |
| 862 | ar_xmit(sc); |
| 863 | |
| 864 | #ifndef NETGRAPH |
| 865 | arstart(ifp); |
| 866 | #else /* NETGRAPH */ |
| 867 | arstart(sc); |
| 868 | #endif /* NETGRAPH */ |
| 869 | } |
| 870 | |
| 871 | static void |
| 872 | ar_up(struct ar_softc *sc) |
| 873 | { |
| 874 | sca_regs *sca; |
| 875 | msci_channel *msci; |
| 876 | |
| 877 | sca = sc->sca; |
| 878 | msci = &sca->msci[sc->scachan]; |
| 879 | |
| 880 | TRC(printf("ar%d: sca %p, msci %p, ch %d\n", |
| 881 | sc->unit, sca, msci, sc->scachan)); |
| 882 | |
| 883 | /* |
| 884 | * Enable transmitter and receiver. |
| 885 | * Raise DTR and RTS. |
| 886 | * Enable interrupts. |
| 887 | */ |
| 888 | if(sc->hc->bustype == AR_BUS_ISA) |
| 889 | ARC_SET_SCA(sc->hc, sc->scano); |
| 890 | |
| 891 | /* XXX |
| 892 | * What about using AUTO mode in msci->md0 ??? |
| 893 | * And what about CTS/DCD etc... ? |
| 894 | */ |
| 895 | if(sc->hc->handshake & AR_SHSK_RTS) |
| 896 | msci->ctl &= ~SCA_CTL_RTS; |
| 897 | if(sc->hc->handshake & AR_SHSK_DTR) { |
| 898 | sc->hc->txc_dtr[sc->scano] &= sc->scachan ? |
| 899 | ~AR_TXC_DTR_DTR1 : ~AR_TXC_DTR_DTR0; |
| 900 | if(sc->hc->bustype == AR_BUS_PCI) |
| 901 | sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] = |
| 902 | sc->hc->txc_dtr[sc->scano]; |
| 903 | else |
| 904 | ar_outb(sc->hc, sc->hc->txc_dtr_off[sc->scano], |
| 905 | sc->hc->txc_dtr[sc->scano]); |
| 906 | } |
| 907 | |
| 908 | if(sc->scachan == 0) { |
| 909 | sca->ier0 |= 0x0F; |
| 910 | sca->ier1 |= 0x0F; |
| 911 | } else { |
| 912 | sca->ier0 |= 0xF0; |
| 913 | sca->ier1 |= 0xF0; |
| 914 | } |
| 915 | |
| 916 | msci->cmd = SCA_CMD_RXENABLE; |
| 917 | if(sc->hc->bustype == AR_BUS_ISA) |
| 918 | ar_inb(sc->hc, AR_ID_5); /* XXX slow it down a bit. */ |
| 919 | msci->cmd = SCA_CMD_TXENABLE; |
| 920 | |
| 921 | if(sc->hc->bustype == AR_BUS_ISA) |
| 922 | ARC_SET_OFF(sc->hc); |
| 923 | #ifdef NETGRAPH |
| 924 | callout_reset(&sc->timer, hz, ngar_watchdog_frame, sc); |
| 925 | sc->running = 1; |
| 926 | #endif /* NETGRAPH */ |
| 927 | } |
| 928 | |
| 929 | static void |
| 930 | ar_down(struct ar_softc *sc) |
| 931 | { |
| 932 | sca_regs *sca; |
| 933 | msci_channel *msci; |
| 934 | |
| 935 | sca = sc->sca; |
| 936 | msci = &sca->msci[sc->scachan]; |
| 937 | |
| 938 | #ifdef NETGRAPH |
| 939 | callout_stop(&sc->timer); |
| 940 | sc->running = 0; |
| 941 | #endif /* NETGRAPH */ |
| 942 | /* |
| 943 | * Disable transmitter and receiver. |
| 944 | * Lower DTR and RTS. |
| 945 | * Disable interrupts. |
| 946 | */ |
| 947 | if(sc->hc->bustype == AR_BUS_ISA) |
| 948 | ARC_SET_SCA(sc->hc, sc->scano); |
| 949 | msci->cmd = SCA_CMD_RXDISABLE; |
| 950 | if(sc->hc->bustype == AR_BUS_ISA) |
| 951 | ar_inb(sc->hc, AR_ID_5); /* XXX slow it down a bit. */ |
| 952 | msci->cmd = SCA_CMD_TXDISABLE; |
| 953 | |
| 954 | if(sc->hc->handshake & AR_SHSK_RTS) |
| 955 | msci->ctl |= SCA_CTL_RTS; |
| 956 | if(sc->hc->handshake & AR_SHSK_DTR) { |
| 957 | sc->hc->txc_dtr[sc->scano] |= sc->scachan ? |
| 958 | AR_TXC_DTR_DTR1 : AR_TXC_DTR_DTR0; |
| 959 | if(sc->hc->bustype == AR_BUS_PCI) |
| 960 | sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] = |
| 961 | sc->hc->txc_dtr[sc->scano]; |
| 962 | else |
| 963 | ar_outb(sc->hc, sc->hc->txc_dtr_off[sc->scano], |
| 964 | sc->hc->txc_dtr[sc->scano]); |
| 965 | } |
| 966 | |
| 967 | if(sc->scachan == 0) { |
| 968 | sca->ier0 &= ~0x0F; |
| 969 | sca->ier1 &= ~0x0F; |
| 970 | } else { |
| 971 | sca->ier0 &= ~0xF0; |
| 972 | sca->ier1 &= ~0xF0; |
| 973 | } |
| 974 | |
| 975 | if(sc->hc->bustype == AR_BUS_ISA) |
| 976 | ARC_SET_OFF(sc->hc); |
| 977 | } |
| 978 | |
| 979 | static int |
| 980 | ar_read_pim_iface(volatile struct ar_hardc *hc, int channel) |
| 981 | { |
| 982 | int ctype, i, val, x; |
| 983 | volatile u_char *pimctrl; |
| 984 | |
| 985 | ctype = 0; |
| 986 | val = 0; |
| 987 | |
| 988 | pimctrl = hc->orbase + AR_PIMCTRL; |
| 989 | |
| 990 | /* Reset the PIM */ |
| 991 | *pimctrl = 0x00; |
| 992 | *pimctrl = AR_PIM_STROBE; |
| 993 | |
| 994 | /* Check if there is a PIM */ |
| 995 | *pimctrl = 0x00; |
| 996 | *pimctrl = AR_PIM_READ; |
| 997 | x = *pimctrl; |
| 998 | TRC(printf("x = %x", x)); |
| 999 | if(x & AR_PIM_DATA) { |
| 1000 | printf("No PIM installed\n"); |
| 1001 | return (AR_IFACE_UNKNOWN); |
| 1002 | } |
| 1003 | |
| 1004 | x = (x >> 1) & 0x01; |
| 1005 | val |= x << 0; |
| 1006 | |
| 1007 | /* Now read the next 15 bits */ |
| 1008 | for(i = 1; i < 16; i++) { |
| 1009 | *pimctrl = AR_PIM_READ; |
| 1010 | *pimctrl = AR_PIM_READ | AR_PIM_STROBE; |
| 1011 | x = *pimctrl; |
| 1012 | TRC(printf(" %x ", x)); |
| 1013 | x = (x >> 1) & 0x01; |
| 1014 | val |= x << i; |
| 1015 | if(i == 8 && (val & 0x000f) == 0x0004) { |
| 1016 | int ii; |
| 1017 | |
| 1018 | /* Start bit */ |
| 1019 | *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE; |
| 1020 | *pimctrl = AR_PIM_A2D_DOUT; |
| 1021 | |
| 1022 | /* Mode bit */ |
| 1023 | *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE; |
| 1024 | *pimctrl = AR_PIM_A2D_DOUT; |
| 1025 | |
| 1026 | /* Sign bit */ |
| 1027 | *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE; |
| 1028 | *pimctrl = AR_PIM_A2D_DOUT; |
| 1029 | |
| 1030 | /* Select channel */ |
| 1031 | *pimctrl = AR_PIM_A2D_STROBE | ((channel & 2) << 2); |
| 1032 | *pimctrl = ((channel & 2) << 2); |
| 1033 | *pimctrl = AR_PIM_A2D_STROBE | ((channel & 1) << 3); |
| 1034 | *pimctrl = ((channel & 1) << 3); |
| 1035 | |
| 1036 | *pimctrl = AR_PIM_A2D_STROBE; |
| 1037 | |
| 1038 | x = *pimctrl; |
| 1039 | if(x & AR_PIM_DATA) |
| 1040 | printf("\nOops A2D start bit not zero (%X)\n", x); |
| 1041 | |
| 1042 | for(ii = 7; ii >= 0; ii--) { |
| 1043 | *pimctrl = 0x00; |
| 1044 | *pimctrl = AR_PIM_A2D_STROBE; |
| 1045 | x = *pimctrl; |
| 1046 | if(x & AR_PIM_DATA) |
| 1047 | ctype |= 1 << ii; |
| 1048 | } |
| 1049 | } |
| 1050 | } |
| 1051 | TRC(printf("\nPIM val %x, ctype %x, %d\n", val, ctype, ctype)); |
| 1052 | *pimctrl = AR_PIM_MODEG; |
| 1053 | *pimctrl = AR_PIM_MODEG | AR_PIM_AUTO_LED; |
| 1054 | if(ctype > 255) |
| 1055 | return (AR_IFACE_UNKNOWN); |
| 1056 | if(ctype > 239) |
| 1057 | return (AR_IFACE_V_35); |
| 1058 | if(ctype > 207) |
| 1059 | return (AR_IFACE_EIA_232); |
| 1060 | if(ctype > 178) |
| 1061 | return (AR_IFACE_X_21); |
| 1062 | if(ctype > 150) |
| 1063 | return (AR_IFACE_EIA_530); |
| 1064 | if(ctype > 25) |
| 1065 | return (AR_IFACE_UNKNOWN); |
| 1066 | if(ctype > 7) |
| 1067 | return (AR_IFACE_LOOPBACK); |
| 1068 | return (AR_IFACE_UNKNOWN); |
| 1069 | } |
| 1070 | |
| 1071 | /* |
| 1072 | * Initialize the card, allocate memory for the ar_softc structures |
| 1073 | * and fill in the pointers. |
| 1074 | */ |
| 1075 | static void |
| 1076 | arc_init(struct ar_hardc *hc) |
| 1077 | { |
| 1078 | struct ar_softc *sc; |
| 1079 | int x; |
| 1080 | u_int chanmem; |
| 1081 | u_int bufmem; |
| 1082 | u_int next; |
| 1083 | u_int descneeded; |
| 1084 | u_char isr, mar; |
| 1085 | u_long memst; |
| 1086 | |
| 1087 | MALLOC(sc, struct ar_softc *, hc->numports * sizeof(struct ar_softc), |
| 1088 | M_DEVBUF, M_WAITOK | M_ZERO); |
| 1089 | if (sc == NULL) |
| 1090 | return; |
| 1091 | hc->sc = sc; |
| 1092 | |
| 1093 | hc->txc_dtr[0] = AR_TXC_DTR_NOTRESET | |
| 1094 | AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1; |
| 1095 | hc->txc_dtr[1] = AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1; |
| 1096 | hc->txc_dtr_off[0] = AR_TXC_DTR0; |
| 1097 | hc->txc_dtr_off[1] = AR_TXC_DTR2; |
| 1098 | if(hc->bustype == AR_BUS_PCI) { |
| 1099 | hc->txc_dtr_off[0] *= 4; |
| 1100 | hc->txc_dtr_off[1] *= 4; |
| 1101 | } |
| 1102 | |
| 1103 | /* |
| 1104 | * reset the card and wait at least 1uS. |
| 1105 | */ |
| 1106 | if(hc->bustype == AR_BUS_PCI) |
| 1107 | hc->orbase[AR_TXC_DTR0 * 4] = ~AR_TXC_DTR_NOTRESET & |
| 1108 | hc->txc_dtr[0]; |
| 1109 | else |
| 1110 | ar_outb(hc, AR_TXC_DTR0, ~AR_TXC_DTR_NOTRESET & |
| 1111 | hc->txc_dtr[0]); |
| 1112 | DELAY(2); |
| 1113 | if(hc->bustype == AR_BUS_PCI) |
| 1114 | hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0]; |
| 1115 | else |
| 1116 | ar_outb(hc, AR_TXC_DTR0, hc->txc_dtr[0]); |
| 1117 | |
| 1118 | if(hc->bustype == AR_BUS_ISA) { |
| 1119 | /* |
| 1120 | * Configure the card. |
| 1121 | * Mem address, irq, |
| 1122 | */ |
| 1123 | memst = rman_get_start(hc->res_memory); |
| 1124 | mar = memst >> 16; |
| 1125 | isr = irqtable[hc->isa_irq] << 1; |
| 1126 | if(isr == 0) |
| 1127 | printf("ar%d: Warning illegal interrupt %d\n", |
| 1128 | hc->cunit, hc->isa_irq); |
| 1129 | isr = isr | ((memst & 0xc000) >> 10); |
| 1130 | |
| 1131 | hc->sca[0] = (sca_regs *)hc->mem_start; |
| 1132 | hc->sca[1] = (sca_regs *)hc->mem_start; |
| 1133 | |
| 1134 | ar_outb(hc, AR_MEM_SEL, mar); |
| 1135 | ar_outb(hc, AR_INT_SEL, isr | AR_INTS_CEN); |
| 1136 | } |
| 1137 | |
| 1138 | if(hc->bustype == AR_BUS_PCI && hc->interface[0] == AR_IFACE_PIM) |
| 1139 | for(x = 0; x < hc->numports; x++) |
| 1140 | hc->interface[x] = ar_read_pim_iface(hc, x); |
| 1141 | |
| 1142 | /* |
| 1143 | * Set the TX clock direction and enable TX. |
| 1144 | */ |
| 1145 | for(x=0;x<hc->numports;x++) { |
| 1146 | switch(hc->interface[x]) { |
| 1147 | case AR_IFACE_V_35: |
| 1148 | hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ? |
| 1149 | AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1; |
| 1150 | hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ? |
| 1151 | AR_TXC_DTR_TXCS0 : AR_TXC_DTR_TXCS1; |
| 1152 | break; |
| 1153 | case AR_IFACE_EIA_530: |
| 1154 | case AR_IFACE_COMBO: |
| 1155 | case AR_IFACE_X_21: |
| 1156 | hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ? |
| 1157 | AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1; |
| 1158 | break; |
| 1159 | } |
| 1160 | } |
| 1161 | |
| 1162 | if(hc->bustype == AR_BUS_PCI) |
| 1163 | hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0]; |
| 1164 | else |
| 1165 | ar_outb(hc, AR_TXC_DTR0, hc->txc_dtr[0]); |
| 1166 | if(hc->numports > NCHAN) { |
| 1167 | if(hc->bustype == AR_BUS_PCI) |
| 1168 | hc->orbase[AR_TXC_DTR2 * 4] = hc->txc_dtr[1]; |
| 1169 | else |
| 1170 | ar_outb(hc, AR_TXC_DTR2, hc->txc_dtr[1]); |
| 1171 | } |
| 1172 | |
| 1173 | chanmem = hc->memsize / hc->numports; |
| 1174 | next = 0; |
| 1175 | |
| 1176 | for(x=0;x<hc->numports;x++, sc++) { |
| 1177 | int blk; |
| 1178 | |
| 1179 | sc->sca = hc->sca[x / NCHAN]; |
| 1180 | |
| 1181 | for(blk = 0; blk < AR_TX_BLOCKS; blk++) { |
| 1182 | sc->block[blk].txdesc = next; |
| 1183 | bufmem = (16 * 1024) / AR_TX_BLOCKS; |
| 1184 | descneeded = bufmem / AR_BUF_SIZ; |
| 1185 | sc->block[blk].txstart = sc->block[blk].txdesc + |
| 1186 | ((((descneeded * sizeof(sca_descriptor)) / |
| 1187 | AR_BUF_SIZ) + 1) * AR_BUF_SIZ); |
| 1188 | sc->block[blk].txend = next + bufmem; |
| 1189 | sc->block[blk].txmax = |
| 1190 | (sc->block[blk].txend - sc->block[blk].txstart) |
| 1191 | / AR_BUF_SIZ; |
| 1192 | next += bufmem; |
| 1193 | |
| 1194 | TRC(printf("ar%d: blk %d: txdesc %x, txstart %x, " |
| 1195 | "txend %x, txmax %d\n", |
| 1196 | x, |
| 1197 | blk, |
| 1198 | sc->block[blk].txdesc, |
| 1199 | sc->block[blk].txstart, |
| 1200 | sc->block[blk].txend, |
| 1201 | sc->block[blk].txmax)); |
| 1202 | } |
| 1203 | |
| 1204 | sc->rxdesc = next; |
| 1205 | bufmem = chanmem - (bufmem * AR_TX_BLOCKS); |
| 1206 | descneeded = bufmem / AR_BUF_SIZ; |
| 1207 | sc->rxstart = sc->rxdesc + |
| 1208 | ((((descneeded * sizeof(sca_descriptor)) / |
| 1209 | AR_BUF_SIZ) + 1) * AR_BUF_SIZ); |
| 1210 | sc->rxend = next + bufmem; |
| 1211 | sc->rxmax = (sc->rxend - sc->rxstart) / AR_BUF_SIZ; |
| 1212 | next += bufmem; |
| 1213 | TRC(printf("ar%d: rxdesc %x, rxstart %x, " |
| 1214 | "rxend %x, rxmax %d\n", |
| 1215 | x, sc->rxdesc, sc->rxstart, sc->rxend, sc->rxmax)); |
| 1216 | } |
| 1217 | |
| 1218 | if(hc->bustype == AR_BUS_PCI) |
| 1219 | hc->orbase[AR_PIMCTRL] = AR_PIM_MODEG | AR_PIM_AUTO_LED; |
| 1220 | } |
| 1221 | |
| 1222 | |
| 1223 | /* |
| 1224 | * The things done here are channel independent. |
| 1225 | * |
| 1226 | * Configure the sca waitstates. |
| 1227 | * Configure the global interrupt registers. |
| 1228 | * Enable master dma enable. |
| 1229 | */ |
| 1230 | static void |
| 1231 | ar_init_sca(struct ar_hardc *hc, int scano) |
| 1232 | { |
| 1233 | sca_regs *sca; |
| 1234 | |
| 1235 | sca = hc->sca[scano]; |
| 1236 | if(hc->bustype == AR_BUS_ISA) |
| 1237 | ARC_SET_SCA(hc, scano); |
| 1238 | |
| 1239 | /* |
| 1240 | * Do the wait registers. |
| 1241 | * Set everything to 0 wait states. |
| 1242 | */ |
| 1243 | sca->pabr0 = 0; |
| 1244 | sca->pabr1 = 0; |
| 1245 | sca->wcrl = 0; |
| 1246 | sca->wcrm = 0; |
| 1247 | sca->wcrh = 0; |
| 1248 | |
| 1249 | /* |
| 1250 | * Configure the interrupt registers. |
| 1251 | * Most are cleared until the interface is configured. |
| 1252 | */ |
| 1253 | sca->ier0 = 0x00; /* MSCI interrupts... Not used with dma. */ |
| 1254 | sca->ier1 = 0x00; /* DMAC interrupts */ |
| 1255 | sca->ier2 = 0x00; /* TIMER interrupts... Not used yet. */ |
| 1256 | sca->itcr = 0x00; /* Use ivr and no intr ack */ |
| 1257 | sca->ivr = 0x40; /* Fill in the interrupt vector. */ |
| 1258 | sca->imvr = 0x40; |
| 1259 | |
| 1260 | /* |
| 1261 | * Configure the timers. |
| 1262 | * XXX Later |
| 1263 | */ |
| 1264 | |
| 1265 | |
| 1266 | /* |
| 1267 | * Set the DMA channel priority to rotate between |
| 1268 | * all four channels. |
| 1269 | * |
| 1270 | * Enable all dma channels. |
| 1271 | */ |
| 1272 | if(hc->bustype == AR_BUS_PCI) { |
| 1273 | u_char *t; |
| 1274 | |
| 1275 | /* |
| 1276 | * Stupid problem with the PCI interface chip that break |
| 1277 | * things. |
| 1278 | * XXX |
| 1279 | */ |
| 1280 | t = (u_char *)sca; |
| 1281 | t[AR_PCI_SCA_PCR] = SCA_PCR_PR2; |
| 1282 | t[AR_PCI_SCA_DMER] = SCA_DMER_EN; |
| 1283 | } else { |
| 1284 | sca->pcr = SCA_PCR_PR2; |
| 1285 | sca->dmer = SCA_DMER_EN; |
| 1286 | } |
| 1287 | } |
| 1288 | |
| 1289 | |
| 1290 | /* |
| 1291 | * Configure the msci |
| 1292 | * |
| 1293 | * NOTE: The serial port configuration is hardcoded at the moment. |
| 1294 | */ |
| 1295 | static void |
| 1296 | ar_init_msci(struct ar_softc *sc) |
| 1297 | { |
| 1298 | msci_channel *msci; |
| 1299 | |
| 1300 | msci = &sc->sca->msci[sc->scachan]; |
| 1301 | |
| 1302 | if(sc->hc->bustype == AR_BUS_ISA) |
| 1303 | ARC_SET_SCA(sc->hc, sc->scano); |
| 1304 | |
| 1305 | msci->cmd = SCA_CMD_RESET; |
| 1306 | |
| 1307 | msci->md0 = SCA_MD0_CRC_1 | |
| 1308 | SCA_MD0_CRC_CCITT | |
| 1309 | SCA_MD0_CRC_ENABLE | |
| 1310 | SCA_MD0_MODE_HDLC; |
| 1311 | msci->md1 = SCA_MD1_NOADDRCHK; |
| 1312 | msci->md2 = SCA_MD2_DUPLEX | SCA_MD2_NRZ; |
| 1313 | |
| 1314 | /* |
| 1315 | * Acording to the manual I should give a reset after changing the |
| 1316 | * mode registers. |
| 1317 | */ |
| 1318 | msci->cmd = SCA_CMD_RXRESET; |
| 1319 | msci->ctl = SCA_CTL_IDLPAT | SCA_CTL_UDRNC | SCA_CTL_RTS; |
| 1320 | |
| 1321 | /* |
| 1322 | * For now all interfaces are programmed to use the RX clock for |
| 1323 | * the TX clock. |
| 1324 | */ |
| 1325 | switch(sc->hc->interface[sc->subunit]) { |
| 1326 | case AR_IFACE_V_35: |
| 1327 | msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1; |
| 1328 | msci->txs = SCA_TXS_CLK_TXC | SCA_TXS_DIV1; |
| 1329 | break; |
| 1330 | case AR_IFACE_X_21: |
| 1331 | case AR_IFACE_EIA_530: |
| 1332 | case AR_IFACE_COMBO: |
| 1333 | msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1; |
| 1334 | msci->txs = SCA_TXS_CLK_RX | SCA_TXS_DIV1; |
| 1335 | } |
| 1336 | |
| 1337 | msci->tmc = 153; /* This give 64k for loopback */ |
| 1338 | |
| 1339 | /* XXX |
| 1340 | * Disable all interrupts for now. I think if you are using |
| 1341 | * the dmac you don't use these interrupts. |
| 1342 | */ |
| 1343 | msci->ie0 = 0; |
| 1344 | msci->ie1 = 0x0C; /* XXX CTS and DCD (DSR on 570I) level change. */ |
| 1345 | msci->ie2 = 0; |
| 1346 | msci->fie = 0; |
| 1347 | |
| 1348 | msci->sa0 = 0; |
| 1349 | msci->sa1 = 0; |
| 1350 | |
| 1351 | msci->idl = 0x7E; /* XXX This is what cisco does. */ |
| 1352 | |
| 1353 | /* |
| 1354 | * This is what the ARNET diags use. |
| 1355 | */ |
| 1356 | msci->rrc = 0x0E; |
| 1357 | msci->trc0 = 0x12; |
| 1358 | msci->trc1 = 0x1F; |
| 1359 | } |
| 1360 | |
| 1361 | /* |
| 1362 | * Configure the rx dma controller. |
| 1363 | */ |
| 1364 | static void |
| 1365 | ar_init_rx_dmac(struct ar_softc *sc) |
| 1366 | { |
| 1367 | dmac_channel *dmac; |
| 1368 | sca_descriptor *rxd; |
| 1369 | u_int rxbuf; |
| 1370 | u_int rxda; |
| 1371 | u_int rxda_d; |
| 1372 | int x = 0; |
| 1373 | |
| 1374 | dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)]; |
| 1375 | |
| 1376 | if(sc->hc->bustype == AR_BUS_ISA) |
| 1377 | ARC_SET_MEM(sc->hc, sc->rxdesc); |
| 1378 | |
| 1379 | rxd = (sca_descriptor *)(sc->hc->mem_start + (sc->rxdesc&sc->hc->winmsk)); |
| 1380 | rxda_d = (u_int)sc->hc->mem_start - (sc->rxdesc & ~sc->hc->winmsk); |
| 1381 | |
| 1382 | for(rxbuf=sc->rxstart;rxbuf<sc->rxend;rxbuf += AR_BUF_SIZ, rxd++) { |
| 1383 | rxda = (u_int)&rxd[1] - rxda_d; |
| 1384 | rxd->cp = (u_short)(rxda & 0xfffful); |
| 1385 | |
| 1386 | x++; |
| 1387 | if(x < 6) |
| 1388 | TRC(printf("Descrp %p, data pt %x, data %x, ", |
| 1389 | rxd, rxda, rxbuf)); |
| 1390 | |
| 1391 | rxd->bp = (u_short)(rxbuf & 0xfffful); |
| 1392 | rxd->bpb = (u_char)((rxbuf >> 16) & 0xff); |
| 1393 | rxd->len = 0; |
| 1394 | rxd->stat = 0xff; /* The sca write here when it is finished. */ |
| 1395 | |
| 1396 | if(x < 6) |
| 1397 | TRC(printf("bpb %x, bp %x.\n", rxd->bpb, rxd->bp)); |
| 1398 | } |
| 1399 | rxd--; |
| 1400 | rxd->cp = (u_short)(sc->rxdesc & 0xfffful); |
| 1401 | |
| 1402 | sc->rxhind = 0; |
| 1403 | |
| 1404 | if(sc->hc->bustype == AR_BUS_ISA) |
| 1405 | ARC_SET_SCA(sc->hc, sc->scano); |
| 1406 | |
| 1407 | dmac->dsr = 0; /* Disable DMA transfer */ |
| 1408 | dmac->dcr = SCA_DCR_ABRT; |
| 1409 | |
| 1410 | /* XXX maybe also SCA_DMR_CNTE */ |
| 1411 | dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF; |
| 1412 | dmac->bfl = AR_BUF_SIZ; |
| 1413 | |
| 1414 | dmac->cda = (u_short)(sc->rxdesc & 0xffff); |
| 1415 | dmac->sarb = (u_char)((sc->rxdesc >> 16) & 0xff); |
| 1416 | |
| 1417 | rxd = (sca_descriptor *)sc->rxstart; |
| 1418 | dmac->eda = (u_short)((u_int)&rxd[sc->rxmax - 1] & 0xffff); |
| 1419 | |
| 1420 | dmac->dir = 0xF0; |
| 1421 | |
| 1422 | dmac->dsr = SCA_DSR_DE; |
| 1423 | } |
| 1424 | |
| 1425 | /* |
| 1426 | * Configure the TX DMA descriptors. |
| 1427 | * Initialize the needed values and chain the descriptors. |
| 1428 | */ |
| 1429 | static void |
| 1430 | ar_init_tx_dmac(struct ar_softc *sc) |
| 1431 | { |
| 1432 | dmac_channel *dmac; |
| 1433 | struct buf_block *blkp; |
| 1434 | int blk; |
| 1435 | sca_descriptor *txd; |
| 1436 | u_int txbuf; |
| 1437 | u_int txda; |
| 1438 | u_int txda_d; |
| 1439 | |
| 1440 | dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)]; |
| 1441 | |
| 1442 | if(sc->hc->bustype == AR_BUS_ISA) |
| 1443 | ARC_SET_MEM(sc->hc, sc->block[0].txdesc); |
| 1444 | |
| 1445 | for(blk = 0; blk < AR_TX_BLOCKS; blk++) { |
| 1446 | blkp = &sc->block[blk]; |
| 1447 | txd = (sca_descriptor *)(sc->hc->mem_start + |
| 1448 | (blkp->txdesc&sc->hc->winmsk)); |
| 1449 | txda_d = (u_int)sc->hc->mem_start - |
| 1450 | (blkp->txdesc & ~sc->hc->winmsk); |
| 1451 | |
| 1452 | txbuf=blkp->txstart; |
| 1453 | for(;txbuf<blkp->txend;txbuf += AR_BUF_SIZ, txd++) { |
| 1454 | txda = (u_int)&txd[1] - txda_d; |
| 1455 | txd->cp = (u_short)(txda & 0xfffful); |
| 1456 | |
| 1457 | txd->bp = (u_short)(txbuf & 0xfffful); |
| 1458 | txd->bpb = (u_char)((txbuf >> 16) & 0xff); |
| 1459 | TRC(printf("ar%d: txbuf %x, bpb %x, bp %x\n", |
| 1460 | sc->unit, txbuf, txd->bpb, txd->bp)); |
| 1461 | txd->len = 0; |
| 1462 | txd->stat = 0; |
| 1463 | } |
| 1464 | txd--; |
| 1465 | txd->cp = (u_short)(blkp->txdesc & 0xfffful); |
| 1466 | |
| 1467 | blkp->txtail = (u_int)txd - (u_int)sc->hc->mem_start; |
| 1468 | TRC(printf("TX Descriptors start %x, end %x.\n", |
| 1469 | blkp->txdesc, |
| 1470 | blkp->txtail)); |
| 1471 | } |
| 1472 | |
| 1473 | if(sc->hc->bustype == AR_BUS_ISA) |
| 1474 | ARC_SET_SCA(sc->hc, sc->scano); |
| 1475 | |
| 1476 | dmac->dsr = 0; /* Disable DMA */ |
| 1477 | dmac->dcr = SCA_DCR_ABRT; |
| 1478 | dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF; |
| 1479 | dmac->dir = SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF; |
| 1480 | |
| 1481 | dmac->sarb = (u_char)((sc->block[0].txdesc >> 16) & 0xff); |
| 1482 | } |
| 1483 | |
| 1484 | |
| 1485 | /* |
| 1486 | * Look through the descriptors to see if there is a complete packet |
| 1487 | * available. Stop if we get to where the sca is busy. |
| 1488 | * |
| 1489 | * Return the length and status of the packet. |
| 1490 | * Return nonzero if there is a packet available. |
| 1491 | * |
| 1492 | * NOTE: |
| 1493 | * It seems that we get the interrupt a bit early. The updateing of |
| 1494 | * descriptor values is not always completed when this is called. |
| 1495 | */ |
| 1496 | static int |
| 1497 | ar_packet_avail(struct ar_softc *sc, |
| 1498 | int *len, |
| 1499 | u_char *rxstat) |
| 1500 | { |
| 1501 | dmac_channel *dmac; |
| 1502 | sca_descriptor *rxdesc; |
| 1503 | sca_descriptor *endp; |
| 1504 | sca_descriptor *cda; |
| 1505 | |
| 1506 | if(sc->hc->bustype == AR_BUS_ISA) |
| 1507 | ARC_SET_SCA(sc->hc, sc->scano); |
| 1508 | dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)]; |
| 1509 | cda = (sca_descriptor *)(sc->hc->mem_start + |
| 1510 | ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk)); |
| 1511 | |
| 1512 | if(sc->hc->bustype == AR_BUS_ISA) |
| 1513 | ARC_SET_MEM(sc->hc, sc->rxdesc); |
| 1514 | rxdesc = (sca_descriptor *) |
| 1515 | (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); |
| 1516 | endp = rxdesc; |
| 1517 | rxdesc = &rxdesc[sc->rxhind]; |
| 1518 | endp = &endp[sc->rxmax]; |
| 1519 | |
| 1520 | *len = 0; |
| 1521 | |
| 1522 | while(rxdesc != cda) { |
| 1523 | *len += rxdesc->len; |
| 1524 | |
| 1525 | if(rxdesc->stat & SCA_DESC_EOM) { |
| 1526 | *rxstat = rxdesc->stat; |
| 1527 | TRC(printf("ar%d: PKT AVAIL len %d, %x.\n", |
| 1528 | sc->unit, *len, *rxstat)); |
| 1529 | return (1); |
| 1530 | } |
| 1531 | |
| 1532 | rxdesc++; |
| 1533 | if(rxdesc == endp) |
| 1534 | rxdesc = (sca_descriptor *) |
| 1535 | (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); |
| 1536 | } |
| 1537 | |
| 1538 | *len = 0; |
| 1539 | *rxstat = 0; |
| 1540 | return (0); |
| 1541 | } |
| 1542 | |
| 1543 | |
| 1544 | /* |
| 1545 | * Copy a packet from the on card memory into a provided mbuf. |
| 1546 | * Take into account that buffers wrap and that a packet may |
| 1547 | * be larger than a buffer. |
| 1548 | */ |
| 1549 | static void |
| 1550 | ar_copy_rxbuf(struct mbuf *m, |
| 1551 | struct ar_softc *sc, |
| 1552 | int len) |
| 1553 | { |
| 1554 | sca_descriptor *rxdesc; |
| 1555 | u_int rxdata; |
| 1556 | u_int rxmax; |
| 1557 | u_int off = 0; |
| 1558 | u_int tlen; |
| 1559 | |
| 1560 | rxdata = sc->rxstart + (sc->rxhind * AR_BUF_SIZ); |
| 1561 | rxmax = sc->rxstart + (sc->rxmax * AR_BUF_SIZ); |
| 1562 | |
| 1563 | rxdesc = (sca_descriptor *) |
| 1564 | (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); |
| 1565 | rxdesc = &rxdesc[sc->rxhind]; |
| 1566 | |
| 1567 | while(len) { |
| 1568 | tlen = (len < AR_BUF_SIZ) ? len : AR_BUF_SIZ; |
| 1569 | if(sc->hc->bustype == AR_BUS_ISA) |
| 1570 | ARC_SET_MEM(sc->hc, rxdata); |
| 1571 | bcopy(sc->hc->mem_start + (rxdata & sc->hc->winmsk), |
| 1572 | mtod(m, caddr_t) + off, |
| 1573 | tlen); |
| 1574 | |
| 1575 | off += tlen; |
| 1576 | len -= tlen; |
| 1577 | |
| 1578 | if(sc->hc->bustype == AR_BUS_ISA) |
| 1579 | ARC_SET_MEM(sc->hc, sc->rxdesc); |
| 1580 | rxdesc->len = 0; |
| 1581 | rxdesc->stat = 0xff; |
| 1582 | |
| 1583 | rxdata += AR_BUF_SIZ; |
| 1584 | rxdesc++; |
| 1585 | if(rxdata == rxmax) { |
| 1586 | rxdata = sc->rxstart; |
| 1587 | rxdesc = (sca_descriptor *) |
| 1588 | (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); |
| 1589 | } |
| 1590 | } |
| 1591 | } |
| 1592 | |
| 1593 | /* |
| 1594 | * If single is set, just eat a packet. Otherwise eat everything up to |
| 1595 | * where cda points. Update pointers to point to the next packet. |
| 1596 | */ |
| 1597 | static void |
| 1598 | ar_eat_packet(struct ar_softc *sc, int single) |
| 1599 | { |
| 1600 | dmac_channel *dmac; |
| 1601 | sca_descriptor *rxdesc; |
| 1602 | sca_descriptor *endp; |
| 1603 | sca_descriptor *cda; |
| 1604 | int loopcnt = 0; |
| 1605 | u_char stat; |
| 1606 | |
| 1607 | if(sc->hc->bustype == AR_BUS_ISA) |
| 1608 | ARC_SET_SCA(sc->hc, sc->scano); |
| 1609 | dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)]; |
| 1610 | cda = (sca_descriptor *)(sc->hc->mem_start + |
| 1611 | ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk)); |
| 1612 | |
| 1613 | /* |
| 1614 | * Loop until desc->stat == (0xff || EOM) |
| 1615 | * Clear the status and length in the descriptor. |
| 1616 | * Increment the descriptor. |
| 1617 | */ |
| 1618 | if(sc->hc->bustype == AR_BUS_ISA) |
| 1619 | ARC_SET_MEM(sc->hc, sc->rxdesc); |
| 1620 | rxdesc = (sca_descriptor *) |
| 1621 | (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); |
| 1622 | endp = rxdesc; |
| 1623 | rxdesc = &rxdesc[sc->rxhind]; |
| 1624 | endp = &endp[sc->rxmax]; |
| 1625 | |
| 1626 | while(rxdesc != cda) { |
| 1627 | loopcnt++; |
| 1628 | if(loopcnt > sc->rxmax) { |
| 1629 | printf("ar%d: eat pkt %d loop, cda %p, " |
| 1630 | "rxdesc %p, stat %x.\n", |
| 1631 | sc->unit, |
| 1632 | loopcnt, |
| 1633 | (void *)cda, |
| 1634 | (void *)rxdesc, |
| 1635 | rxdesc->stat); |
| 1636 | break; |
| 1637 | } |
| 1638 | |
| 1639 | stat = rxdesc->stat; |
| 1640 | |
| 1641 | rxdesc->len = 0; |
| 1642 | rxdesc->stat = 0xff; |
| 1643 | |
| 1644 | rxdesc++; |
| 1645 | sc->rxhind++; |
| 1646 | if(rxdesc == endp) { |
| 1647 | rxdesc = (sca_descriptor *) |
| 1648 | (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); |
| 1649 | sc->rxhind = 0; |
| 1650 | } |
| 1651 | |
| 1652 | if(single && (stat == SCA_DESC_EOM)) |
| 1653 | break; |
| 1654 | } |
| 1655 | |
| 1656 | /* |
| 1657 | * Update the eda to the previous descriptor. |
| 1658 | */ |
| 1659 | if(sc->hc->bustype == AR_BUS_ISA) |
| 1660 | ARC_SET_SCA(sc->hc, sc->scano); |
| 1661 | |
| 1662 | rxdesc = (sca_descriptor *)sc->rxdesc; |
| 1663 | rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax]; |
| 1664 | |
| 1665 | sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda = |
| 1666 | (u_short)((u_int)rxdesc & 0xffff); |
| 1667 | } |
| 1668 | |
| 1669 | |
| 1670 | /* |
| 1671 | * While there is packets available in the rx buffer, read them out |
| 1672 | * into mbufs and ship them off. |
| 1673 | */ |
| 1674 | static void |
| 1675 | ar_get_packets(struct ar_softc *sc) |
| 1676 | { |
| 1677 | sca_descriptor *rxdesc; |
| 1678 | struct mbuf *m = NULL; |
| 1679 | int i; |
| 1680 | int len; |
| 1681 | u_char rxstat; |
| 1682 | #ifdef NETGRAPH |
| 1683 | int error; |
| 1684 | #endif |
| 1685 | |
| 1686 | while(ar_packet_avail(sc, &len, &rxstat)) { |
| 1687 | TRC(printf("apa: len %d, rxstat %x\n", len, rxstat)); |
| 1688 | if(((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) { |
| 1689 | m = m_getl(len, MB_DONTWAIT, MT_DATA, M_PKTHDR, NULL); |
| 1690 | if(m == NULL) { |
| 1691 | /* eat packet if get mbuf fail!! */ |
| 1692 | ar_eat_packet(sc, 1); |
| 1693 | continue; |
| 1694 | } |
| 1695 | #ifdef NETGRAPH |
| 1696 | m->m_pkthdr.rcvif = NULL; |
| 1697 | sc->inbytes += len; |
| 1698 | sc->inlast = 0; |
| 1699 | #else |
| 1700 | m->m_pkthdr.rcvif = &sc->ifsppp.pp_if; |
| 1701 | #endif |
| 1702 | m->m_pkthdr.len = m->m_len = len; |
| 1703 | ar_copy_rxbuf(m, sc, len); |
| 1704 | #ifdef NETGRAPH |
| 1705 | NG_SEND_DATA_ONLY(error, sc->hook, m); |
| 1706 | sc->ipackets++; |
| 1707 | #else |
| 1708 | BPF_MTAP(&sc->ifsppp.pp_if, m); |
| 1709 | sppp_input(&sc->ifsppp.pp_if, m); |
| 1710 | sc->ifsppp.pp_if.if_ipackets++; |
| 1711 | #endif |
| 1712 | /* |
| 1713 | * Update the eda to the previous descriptor. |
| 1714 | */ |
| 1715 | i = (len + AR_BUF_SIZ - 1) / AR_BUF_SIZ; |
| 1716 | sc->rxhind = (sc->rxhind + i) % sc->rxmax; |
| 1717 | |
| 1718 | if(sc->hc->bustype == AR_BUS_ISA) |
| 1719 | ARC_SET_SCA(sc->hc, sc->scano); |
| 1720 | |
| 1721 | rxdesc = (sca_descriptor *)sc->rxdesc; |
| 1722 | rxdesc = |
| 1723 | &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax]; |
| 1724 | |
| 1725 | sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda = |
| 1726 | (u_short)((u_int)rxdesc & 0xffff); |
| 1727 | } else { |
| 1728 | int tries = 5; |
| 1729 | |
| 1730 | while((rxstat == 0xff) && --tries) |
| 1731 | ar_packet_avail(sc, &len, &rxstat); |
| 1732 | |
| 1733 | /* |
| 1734 | * It look like we get an interrupt early |
| 1735 | * sometimes and then the status is not |
| 1736 | * filled in yet. |
| 1737 | */ |
| 1738 | if(tries && (tries != 5)) |
| 1739 | continue; |
| 1740 | |
| 1741 | ar_eat_packet(sc, 1); |
| 1742 | |
| 1743 | #ifndef NETGRAPH |
| 1744 | sc->ifsppp.pp_if.if_ierrors++; |
| 1745 | #else /* NETGRAPH */ |
| 1746 | sc->ierrors[0]++; |
| 1747 | #endif /* NETGRAPH */ |
| 1748 | |
| 1749 | if(sc->hc->bustype == AR_BUS_ISA) |
| 1750 | ARC_SET_SCA(sc->hc, sc->scano); |
| 1751 | |
| 1752 | TRCL(printf("ar%d: Receive error chan %d, " |
| 1753 | "stat %x, msci st3 %x," |
| 1754 | "rxhind %d, cda %x, eda %x.\n", |
| 1755 | sc->unit, |
| 1756 | sc->scachan, |
| 1757 | rxstat, |
| 1758 | sc->sca->msci[sc->scachan].st3, |
| 1759 | sc->rxhind, |
| 1760 | sc->sca->dmac[ |
| 1761 | DMAC_RXCH(sc->scachan)].cda, |
| 1762 | sc->sca->dmac[ |
| 1763 | DMAC_RXCH(sc->scachan)].eda)); |
| 1764 | } |
| 1765 | } |
| 1766 | } |
| 1767 | |
| 1768 | |
| 1769 | /* |
| 1770 | * All DMA interrupts come here. |
| 1771 | * |
| 1772 | * Each channel has two interrupts. |
| 1773 | * Interrupt A for errors and Interrupt B for normal stuff like end |
| 1774 | * of transmit or receive dmas. |
| 1775 | */ |
| 1776 | static void |
| 1777 | ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr1) |
| 1778 | { |
| 1779 | u_char dsr; |
| 1780 | u_char dotxstart = isr1; |
| 1781 | int mch; |
| 1782 | struct ar_softc *sc; |
| 1783 | sca_regs *sca; |
| 1784 | dmac_channel *dmac; |
| 1785 | |
| 1786 | sca = hc->sca[scano]; |
| 1787 | mch = 0; |
| 1788 | /* |
| 1789 | * Shortcut if there is no interrupts for dma channel 0 or 1 |
| 1790 | */ |
| 1791 | if((isr1 & 0x0F) == 0) { |
| 1792 | mch = 1; |
| 1793 | isr1 >>= 4; |
| 1794 | } |
| 1795 | |
| 1796 | do { |
| 1797 | sc = &hc->sc[mch + (NCHAN * scano)]; |
| 1798 | |
| 1799 | /* |
| 1800 | * Transmit channel |
| 1801 | */ |
| 1802 | if(isr1 & 0x0C) { |
| 1803 | dmac = &sca->dmac[DMAC_TXCH(mch)]; |
| 1804 | |
| 1805 | if(hc->bustype == AR_BUS_ISA) |
| 1806 | ARC_SET_SCA(hc, scano); |
| 1807 | |
| 1808 | dsr = dmac->dsr; |
| 1809 | dmac->dsr = dsr; |
| 1810 | |
| 1811 | /* Counter overflow */ |
| 1812 | if(dsr & SCA_DSR_COF) { |
| 1813 | printf("ar%d: TX DMA Counter overflow, " |
| 1814 | "txpacket no %lu.\n", |
| 1815 | sc->unit, |
| 1816 | #ifndef NETGRAPH |
| 1817 | sc->ifsppp.pp_if.if_opackets); |
| 1818 | sc->ifsppp.pp_if.if_oerrors++; |
| 1819 | #else /* NETGRAPH */ |
| 1820 | sc->opackets); |
| 1821 | sc->oerrors++; |
| 1822 | #endif /* NETGRAPH */ |
| 1823 | } |
| 1824 | |
| 1825 | /* Buffer overflow */ |
| 1826 | if(dsr & SCA_DSR_BOF) { |
| 1827 | printf("ar%d: TX DMA Buffer overflow, " |
| 1828 | "txpacket no %lu, dsr %02x, " |
| 1829 | "cda %04x, eda %04x.\n", |
| 1830 | sc->unit, |
| 1831 | #ifndef NETGRAPH |
| 1832 | sc->ifsppp.pp_if.if_opackets, |
| 1833 | #else /* NETGRAPH */ |
| 1834 | sc->opackets, |
| 1835 | #endif /* NETGRAPH */ |
| 1836 | dsr, |
| 1837 | dmac->cda, |
| 1838 | dmac->eda); |
| 1839 | #ifndef NETGRAPH |
| 1840 | sc->ifsppp.pp_if.if_oerrors++; |
| 1841 | #else /* NETGRAPH */ |
| 1842 | sc->oerrors++; |
| 1843 | #endif /* NETGRAPH */ |
| 1844 | } |
| 1845 | |
| 1846 | /* End of Transfer */ |
| 1847 | if(dsr & SCA_DSR_EOT) { |
| 1848 | /* |
| 1849 | * This should be the most common case. |
| 1850 | * |
| 1851 | * Clear the IFF_OACTIVE flag. |
| 1852 | * |
| 1853 | * Call arstart to start a new transmit if |
| 1854 | * there is data to transmit. |
| 1855 | */ |
| 1856 | sc->xmit_busy = 0; |
| 1857 | #ifndef NETGRAPH |
| 1858 | sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE; |
| 1859 | sc->ifsppp.pp_if.if_timer = 0; |
| 1860 | #else /* NETGRAPH */ |
| 1861 | /* XXX c->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE; */ |
| 1862 | sc->out_dog = 0; /* XXX */ |
| 1863 | #endif /* NETGRAPH */ |
| 1864 | |
| 1865 | if(sc->txb_inuse && --sc->txb_inuse) |
| 1866 | ar_xmit(sc); |
| 1867 | } |
| 1868 | } |
| 1869 | |
| 1870 | /* |
| 1871 | * Receive channel |
| 1872 | */ |
| 1873 | if(isr1 & 0x03) { |
| 1874 | dmac = &sca->dmac[DMAC_RXCH(mch)]; |
| 1875 | |
| 1876 | if(hc->bustype == AR_BUS_ISA) |
| 1877 | ARC_SET_SCA(hc, scano); |
| 1878 | |
| 1879 | dsr = dmac->dsr; |
| 1880 | dmac->dsr = dsr; |
| 1881 | |
| 1882 | TRC(printf("AR: RX DSR %x\n", dsr)); |
| 1883 | |
| 1884 | /* End of frame */ |
| 1885 | if(dsr & SCA_DSR_EOM) { |
| 1886 | TRC(int tt = sc->ifsppp.pp_if.if_ipackets;) |
| 1887 | TRC(int ind = sc->rxhind;) |
| 1888 | |
| 1889 | ar_get_packets(sc); |
| 1890 | #ifndef NETGRAPH |
| 1891 | #define IPACKETS sc->ifsppp.pp_if.if_ipackets |
| 1892 | #else /* NETGRAPH */ |
| 1893 | #define IPACKETS sc->ipackets |
| 1894 | #endif /* NETGRAPH */ |
| 1895 | TRC(if(tt == IPACKETS) { |
| 1896 | sca_descriptor *rxdesc; |
| 1897 | int i; |
| 1898 | |
| 1899 | if(hc->bustype == AR_BUS_ISA) |
| 1900 | ARC_SET_SCA(hc, scano); |
| 1901 | printf("AR: RXINTR isr1 %x, dsr %x, " |
| 1902 | "no data %d pkts, orxhind %d.\n", |
| 1903 | dotxstart, |
| 1904 | dsr, |
| 1905 | tt, |
| 1906 | ind); |
| 1907 | printf("AR: rxdesc %x, rxstart %x, " |
| 1908 | "rxend %x, rxhind %d, " |
| 1909 | "rxmax %d.\n", |
| 1910 | sc->rxdesc, |
| 1911 | sc->rxstart, |
| 1912 | sc->rxend, |
| 1913 | sc->rxhind, |
| 1914 | sc->rxmax); |
| 1915 | printf("AR: cda %x, eda %x.\n", |
| 1916 | dmac->cda, |
| 1917 | dmac->eda); |
| 1918 | |
| 1919 | if(sc->hc->bustype == AR_BUS_ISA) |
| 1920 | ARC_SET_MEM(sc->hc, |
| 1921 | sc->rxdesc); |
| 1922 | rxdesc = (sca_descriptor *) |
| 1923 | (sc->hc->mem_start + |
| 1924 | (sc->rxdesc & sc->hc->winmsk)); |
| 1925 | rxdesc = &rxdesc[sc->rxhind]; |
| 1926 | for(i=0;i<3;i++,rxdesc++) |
| 1927 | printf("AR: rxdesc->stat %x, " |
| 1928 | "len %d.\n", |
| 1929 | rxdesc->stat, |
| 1930 | rxdesc->len); |
| 1931 | }) |
| 1932 | } |
| 1933 | |
| 1934 | /* Counter overflow */ |
| 1935 | if(dsr & SCA_DSR_COF) { |
| 1936 | printf("ar%d: RX DMA Counter overflow, " |
| 1937 | "rxpkts %lu.\n", |
| 1938 | sc->unit, |
| 1939 | #ifndef NETGRAPH |
| 1940 | sc->ifsppp.pp_if.if_ipackets); |
| 1941 | sc->ifsppp.pp_if.if_ierrors++; |
| 1942 | #else /* NETGRAPH */ |
| 1943 | sc->ipackets); |
| 1944 | sc->ierrors[1]++; |
| 1945 | #endif /* NETGRAPH */ |
| 1946 | } |
| 1947 | |
| 1948 | /* Buffer overflow */ |
| 1949 | if(dsr & SCA_DSR_BOF) { |
| 1950 | if(hc->bustype == AR_BUS_ISA) |
| 1951 | ARC_SET_SCA(hc, scano); |
| 1952 | printf("ar%d: RX DMA Buffer overflow, " |
| 1953 | "rxpkts %lu, rxind %d, " |
| 1954 | "cda %x, eda %x, dsr %x.\n", |
| 1955 | sc->unit, |
| 1956 | #ifndef NETGRAPH |
| 1957 | sc->ifsppp.pp_if.if_ipackets, |
| 1958 | #else /* NETGRAPH */ |
| 1959 | sc->ipackets, |
| 1960 | #endif /* NETGRAPH */ |
| 1961 | sc->rxhind, |
| 1962 | dmac->cda, |
| 1963 | dmac->eda, |
| 1964 | dsr); |
| 1965 | /* |
| 1966 | * Make sure we eat as many as possible. |
| 1967 | * Then get the system running again. |
| 1968 | */ |
| 1969 | ar_eat_packet(sc, 0); |
| 1970 | #ifndef NETGRAPH |
| 1971 | sc->ifsppp.pp_if.if_ierrors++; |
| 1972 | #else /* NETGRAPH */ |
| 1973 | sc->ierrors[2]++; |
| 1974 | #endif /* NETGRAPH */ |
| 1975 | if(hc->bustype == AR_BUS_ISA) |
| 1976 | ARC_SET_SCA(hc, scano); |
| 1977 | sca->msci[mch].cmd = SCA_CMD_RXMSGREJ; |
| 1978 | dmac->dsr = SCA_DSR_DE; |
| 1979 | |
| 1980 | TRC(printf("ar%d: RX DMA Buffer overflow, " |
| 1981 | "rxpkts %lu, rxind %d, " |
| 1982 | "cda %x, eda %x, dsr %x. After\n", |
| 1983 | sc->unit, |
| 1984 | sc->ifsppp.pp_if.if_ipackets, |
| 1985 | sc->rxhind, |
| 1986 | dmac->cda, |
| 1987 | dmac->eda, |
| 1988 | dmac->dsr);) |
| 1989 | } |
| 1990 | |
| 1991 | /* End of Transfer */ |
| 1992 | if(dsr & SCA_DSR_EOT) { |
| 1993 | /* |
| 1994 | * If this happen, it means that we are |
| 1995 | * receiving faster than what the processor |
| 1996 | * can handle. |
| 1997 | * |
| 1998 | * XXX We should enable the dma again. |
| 1999 | */ |
| 2000 | printf("ar%d: RX End of transfer, rxpkts %lu.\n", |
| 2001 | sc->unit, |
| 2002 | #ifndef NETGRAPH |
| 2003 | sc->ifsppp.pp_if.if_ipackets); |
| 2004 | sc->ifsppp.pp_if.if_ierrors++; |
| 2005 | #else /* NETGRAPH */ |
| 2006 | sc->ipackets); |
| 2007 | sc->ierrors[3]++; |
| 2008 | #endif /* NETGRAPH */ |
| 2009 | } |
| 2010 | } |
| 2011 | |
| 2012 | isr1 >>= 4; |
| 2013 | |
| 2014 | mch++; |
| 2015 | }while((mch<NCHAN) && isr1); |
| 2016 | |
| 2017 | /* |
| 2018 | * Now that we have done all the urgent things, see if we |
| 2019 | * can fill the transmit buffers. |
| 2020 | */ |
| 2021 | for(mch = 0; mch < NCHAN; mch++) { |
| 2022 | if(dotxstart & 0x0C) { |
| 2023 | sc = &hc->sc[mch + (NCHAN * scano)]; |
| 2024 | #ifndef NETGRAPH |
| 2025 | arstart(&sc->ifsppp.pp_if); |
| 2026 | #else /* NETGRAPH */ |
| 2027 | arstart(sc); |
| 2028 | #endif /* NETGRAPH */ |
| 2029 | } |
| 2030 | dotxstart >>= 4; |
| 2031 | } |
| 2032 | } |
| 2033 | |
| 2034 | static void |
| 2035 | ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr0) |
| 2036 | { |
| 2037 | printf("arc%d: ARINTR: MSCI\n", hc->cunit); |
| 2038 | } |
| 2039 | |
| 2040 | static void |
| 2041 | ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr2) |
| 2042 | { |
| 2043 | printf("arc%d: ARINTR: TIMER\n", hc->cunit); |
| 2044 | } |
| 2045 | |
| 2046 | |
| 2047 | #ifdef NETGRAPH |
| 2048 | /***************************************** |
| 2049 | * Device timeout/watchdog routine. |
| 2050 | * called once per second. |
| 2051 | * checks to see that if activity was expected, that it hapenned. |
| 2052 | * At present we only look to see if expected output was completed. |
| 2053 | */ |
| 2054 | static void |
| 2055 | ngar_watchdog_frame(void * arg) |
| 2056 | { |
| 2057 | struct ar_softc * sc = arg; |
| 2058 | int speed; |
| 2059 | |
| 2060 | crit_enter(); |
| 2061 | |
| 2062 | if (sc->running == 0) { |
| 2063 | crit_exit(); |
| 2064 | return; /* if we are not running let timeouts die */ |
| 2065 | } |
| 2066 | |
| 2067 | /* |
| 2068 | * calculate the apparent throughputs |
| 2069 | * XXX a real hack |
| 2070 | */ |
| 2071 | speed = sc->inbytes - sc->lastinbytes; |
| 2072 | sc->lastinbytes = sc->inbytes; |
| 2073 | if ( sc->inrate < speed ) |
| 2074 | sc->inrate = speed; |
| 2075 | speed = sc->outbytes - sc->lastoutbytes; |
| 2076 | sc->lastoutbytes = sc->outbytes; |
| 2077 | if ( sc->outrate < speed ) |
| 2078 | sc->outrate = speed; |
| 2079 | sc->inlast++; |
| 2080 | |
| 2081 | crit_exit(); |
| 2082 | |
| 2083 | if ((sc->inlast > QUITE_A_WHILE) |
| 2084 | && (sc->out_deficit > LOTS_OF_PACKETS)) { |
| 2085 | log(LOG_ERR, "ar%d: No response from remote end\n", sc->unit); |
| 2086 | |
| 2087 | crit_enter(); |
| 2088 | |
| 2089 | ar_down(sc); |
| 2090 | ar_up(sc); |
| 2091 | sc->inlast = sc->out_deficit = 0; |
| 2092 | |
| 2093 | crit_exit(); |
| 2094 | } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */ |
| 2095 | if (sc->out_dog == 0) { |
| 2096 | log(LOG_ERR, "ar%d: Transmit failure.. no clock?\n", |
| 2097 | sc->unit); |
| 2098 | |
| 2099 | crit_enter(); |
| 2100 | |
| 2101 | arwatchdog(sc); |
| 2102 | #if 0 |
| 2103 | ar_down(sc); |
| 2104 | ar_up(sc); |
| 2105 | #endif |
| 2106 | |
| 2107 | crit_exit(); |
| 2108 | |
| 2109 | sc->inlast = sc->out_deficit = 0; |
| 2110 | } else { |
| 2111 | sc->out_dog--; |
| 2112 | } |
| 2113 | } |
| 2114 | callout_reset(&sc->timer, hz, ngar_watchdog_frame, sc); |
| 2115 | } |
| 2116 | |
| 2117 | /*********************************************************************** |
| 2118 | * This section contains the methods for the Netgraph interface |
| 2119 | ***********************************************************************/ |
| 2120 | /* |
| 2121 | * It is not possible or allowable to create a node of this type. |
| 2122 | * If the hardware exists, it will already have created it. |
| 2123 | */ |
| 2124 | static int |
| 2125 | ngar_constructor(node_p *nodep) |
| 2126 | { |
| 2127 | return (EINVAL); |
| 2128 | } |
| 2129 | |
| 2130 | /* |
| 2131 | * give our ok for a hook to be added... |
| 2132 | * If we are not running this should kick the device into life. |
| 2133 | * The hook's private info points to our stash of info about that |
| 2134 | * channel. |
| 2135 | */ |
| 2136 | static int |
| 2137 | ngar_newhook(node_p node, hook_p hook, const char *name) |
| 2138 | { |
| 2139 | struct ar_softc * sc = NG_NODE_PRIVATE(node); |
| 2140 | |
| 2141 | /* |
| 2142 | * check if it's our friend the debug hook |
| 2143 | */ |
| 2144 | if (strcmp(name, NG_AR_HOOK_DEBUG) == 0) { |
| 2145 | NG_HOOK_SET_PRIVATE(hook, NULL); /* paranoid */ |
| 2146 | sc->debug_hook = hook; |
| 2147 | return (0); |
| 2148 | } |
| 2149 | |
| 2150 | /* |
| 2151 | * Check for raw mode hook. |
| 2152 | */ |
| 2153 | if (strcmp(name, NG_AR_HOOK_RAW) != 0) { |
| 2154 | return (EINVAL); |
| 2155 | } |
| 2156 | NG_HOOK_SET_PRIVATE(hook, sc); |
| 2157 | sc->hook = hook; |
| 2158 | sc->datahooks++; |
| 2159 | ar_up(sc); |
| 2160 | return (0); |
| 2161 | } |
| 2162 | |
| 2163 | /* |
| 2164 | * incoming messages. |
| 2165 | * Just respond to the generic TEXT_STATUS message |
| 2166 | */ |
| 2167 | static int |
| 2168 | ngar_rcvmsg(node_p node, struct ng_mesg *msg, const char *retaddr, |
| 2169 | struct ng_mesg **rptr) |
| 2170 | { |
| 2171 | struct ar_softc *sc; |
| 2172 | int error = 0; |
| 2173 | struct ng_mesg *resp = NULL; |
| 2174 | |
| 2175 | sc = NG_NODE_PRIVATE(node); |
| 2176 | switch (msg->header.typecookie) { |
| 2177 | case NG_AR_COOKIE: |
| 2178 | error = EINVAL; |
| 2179 | break; |
| 2180 | case NGM_GENERIC_COOKIE: |
| 2181 | switch(msg->header.cmd) { |
| 2182 | case NGM_TEXT_STATUS: { |
| 2183 | char *arg; |
| 2184 | int pos = 0; |
| 2185 | |
| 2186 | int resplen = sizeof(struct ng_mesg) + 512; |
| 2187 | NG_MKRESPONSE(resp, msg, resplen, M_INTWAIT); |
| 2188 | if (resp == NULL) { |
| 2189 | error = ENOMEM; |
| 2190 | break; |
| 2191 | } |
| 2192 | arg = (resp)->data; |
| 2193 | pos = sprintf(arg, "%ld bytes in, %ld bytes out\n" |
| 2194 | "highest rate seen: %ld B/S in, %ld B/S out\n", |
| 2195 | sc->inbytes, sc->outbytes, |
| 2196 | sc->inrate, sc->outrate); |
| 2197 | pos += sprintf(arg + pos, |
| 2198 | "%ld output errors\n", |
| 2199 | sc->oerrors); |
| 2200 | pos += sprintf(arg + pos, |
| 2201 | "ierrors = %ld, %ld, %ld, %ld\n", |
| 2202 | sc->ierrors[0], |
| 2203 | sc->ierrors[1], |
| 2204 | sc->ierrors[2], |
| 2205 | sc->ierrors[3]); |
| 2206 | |
| 2207 | (resp)->header.arglen = pos + 1; |
| 2208 | break; |
| 2209 | } |
| 2210 | default: |
| 2211 | error = EINVAL; |
| 2212 | break; |
| 2213 | } |
| 2214 | break; |
| 2215 | default: |
| 2216 | error = EINVAL; |
| 2217 | break; |
| 2218 | } |
| 2219 | /* Take care of synchronous response, if any */ |
| 2220 | NG_RESPOND_MSG(error, node, retaddr, resp, rptr); |
| 2221 | NG_FREE_MSG(msg); |
| 2222 | return (error); |
| 2223 | } |
| 2224 | |
| 2225 | /* |
| 2226 | * get data from another node and transmit it to the correct channel |
| 2227 | */ |
| 2228 | static int |
| 2229 | ngar_rcvdata(hook_p hook, struct mbuf *m, meta_p meta) |
| 2230 | { |
| 2231 | int error = 0; |
| 2232 | struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook)); |
| 2233 | struct ifqueue *xmitq_p; |
| 2234 | |
| 2235 | /* |
| 2236 | * data doesn't come in from just anywhere (e.g control hook) |
| 2237 | */ |
| 2238 | if ( NG_HOOK_PRIVATE(hook) == NULL) { |
| 2239 | error = ENETDOWN; |
| 2240 | goto bad; |
| 2241 | } |
| 2242 | |
| 2243 | /* |
| 2244 | * Now queue the data for when it can be sent |
| 2245 | */ |
| 2246 | if (meta && meta->priority > 0) |
| 2247 | xmitq_p = (&sc->xmitq_hipri); |
| 2248 | else |
| 2249 | xmitq_p = (&sc->xmitq); |
| 2250 | |
| 2251 | crit_enter(); |
| 2252 | |
| 2253 | if (IF_QFULL(xmitq_p)) { |
| 2254 | IF_DROP(xmitq_p); |
| 2255 | |
| 2256 | crit_exit(); |
| 2257 | |
| 2258 | error = ENOBUFS; |
| 2259 | goto bad; |
| 2260 | } |
| 2261 | IF_ENQUEUE(xmitq_p, m); |
| 2262 | arstart(sc); |
| 2263 | |
| 2264 | crit_exit(); |
| 2265 | return (0); |
| 2266 | |
| 2267 | bad: |
| 2268 | /* |
| 2269 | * It was an error case. |
| 2270 | * check if we need to free the mbuf, and then return the error |
| 2271 | */ |
| 2272 | NG_FREE_DATA(m, meta); |
| 2273 | return (error); |
| 2274 | } |
| 2275 | |
| 2276 | /* |
| 2277 | * do local shutdown processing.. |
| 2278 | * this node will refuse to go away, unless the hardware says to.. |
| 2279 | * don't unref the node, or remove our name. just clear our links up. |
| 2280 | */ |
| 2281 | static int |
| 2282 | ngar_shutdown(node_p node) |
| 2283 | { |
| 2284 | struct ar_softc * sc = NG_NODE_PRIVATE(node); |
| 2285 | |
| 2286 | ar_down(sc); |
| 2287 | NG_NODE_UNREF(node); |
| 2288 | /* XXX need to drain the output queues! */ |
| 2289 | |
| 2290 | /* The node is dead, long live the node! */ |
| 2291 | /* stolen from the attach routine */ |
| 2292 | if (ng_make_node_common(&typestruct, &sc->node) != 0) |
| 2293 | return (0); |
| 2294 | sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit); |
| 2295 | if (ng_name_node(sc->node, sc->nodename)) { |
| 2296 | sc->node = NULL; |
| 2297 | printf("node naming failed\n"); |
| 2298 | NG_NODE_UNREF(sc->node); /* node dissappears */ |
| 2299 | return (0); |
| 2300 | } |
| 2301 | NG_NODE_SET_PRIVATE(sc->node, sc); |
| 2302 | sc->running = 0; |
| 2303 | return (0); |
| 2304 | } |
| 2305 | |
| 2306 | /* already linked */ |
| 2307 | static int |
| 2308 | ngar_connect(hook_p hook) |
| 2309 | { |
| 2310 | /* be really amiable and just say "YUP that's OK by me! " */ |
| 2311 | return (0); |
| 2312 | } |
| 2313 | |
| 2314 | /* |
| 2315 | * notify on hook disconnection (destruction) |
| 2316 | * |
| 2317 | * Invalidate the private data associated with this dlci. |
| 2318 | * For this type, removal of the last link resets tries to destroy the node. |
| 2319 | * As the device still exists, the shutdown method will not actually |
| 2320 | * destroy the node, but reset the device and leave it 'fresh' :) |
| 2321 | * |
| 2322 | * The node removal code will remove all references except that owned by the |
| 2323 | * driver. |
| 2324 | */ |
| 2325 | static int |
| 2326 | ngar_disconnect(hook_p hook) |
| 2327 | { |
| 2328 | struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook)); |
| 2329 | |
| 2330 | /* |
| 2331 | * If it's the data hook, then free resources etc. |
| 2332 | */ |
| 2333 | if (NG_HOOK_PRIVATE(hook)) { |
| 2334 | crit_enter(); |
| 2335 | |
| 2336 | sc->datahooks--; |
| 2337 | if (sc->datahooks == 0) |
| 2338 | ar_down(sc); |
| 2339 | |
| 2340 | crit_exit(); |
| 2341 | } else { |
| 2342 | sc->debug_hook = NULL; |
| 2343 | } |
| 2344 | return (0); |
| 2345 | } |
| 2346 | |
| 2347 | /* |
| 2348 | * called during bootup |
| 2349 | * or LKM loading to put this type into the list of known modules |
| 2350 | */ |
| 2351 | static void |
| 2352 | ngar_init(void *ignored) |
| 2353 | { |
| 2354 | if (ng_newtype(&typestruct)) |
| 2355 | printf("ngar install failed\n"); |
| 2356 | ngar_done_init = 1; |
| 2357 | } |
| 2358 | #endif /* NETGRAPH */ |
| 2359 | |
| 2360 | /* |
| 2361 | ********************************* END ************************************ |
| 2362 | */ |