2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 2008 The DragonFly Project.
8 * This code is derived from software contributed to Berkeley by
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
22 * California, Berkeley and its contributors.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
43 //#include "use_npx.h"
45 #include "opt_compat.h"
48 #include "opt_directio.h"
50 #include "opt_msgbuf.h"
53 #include <sys/param.h>
54 #include <sys/systm.h>
55 #include <sys/sysproto.h>
56 #include <sys/signalvar.h>
57 #include <sys/kernel.h>
58 #include <sys/linker.h>
59 #include <sys/malloc.h>
63 #include <sys/reboot.h>
65 #include <sys/msgbuf.h>
66 #include <sys/sysent.h>
67 #include <sys/sysctl.h>
68 #include <sys/vmmeter.h>
70 #include <sys/usched.h>
73 #include <sys/ctype.h>
74 #include <sys/serialize.h>
75 #include <sys/systimer.h>
78 #include <vm/vm_param.h>
80 #include <vm/vm_kern.h>
81 #include <vm/vm_object.h>
82 #include <vm/vm_page.h>
83 #include <vm/vm_map.h>
84 #include <vm/vm_pager.h>
85 #include <vm/vm_extern.h>
87 #include <sys/thread2.h>
88 #include <sys/mplock2.h>
89 #include <sys/mutex2.h>
99 #include <machine/cpu.h>
100 #include <machine/clock.h>
101 #include <machine/specialreg.h>
103 #include <machine/bootinfo.h>
105 #include <machine/md_var.h>
106 #include <machine/metadata.h>
107 #include <machine/pc/bios.h>
108 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
109 #include <machine/globaldata.h> /* CPU_prvspace */
110 #include <machine/smp.h>
112 #include <machine/perfmon.h>
114 #include <machine/cputypes.h>
115 #include <machine/intr_machdep.h>
116 #include <machine/framebuffer.h>
119 #include <bus/isa/isa_device.h>
121 #include <machine_base/isa/isa_intr.h>
122 #include <bus/isa/rtc.h>
123 #include <sys/random.h>
124 #include <sys/ptrace.h>
125 #include <machine/sigframe.h>
127 #include <sys/machintr.h>
128 #include <machine_base/icu/icu_abi.h>
129 #include <machine_base/icu/elcr_var.h>
130 #include <machine_base/apic/lapic.h>
131 #include <machine_base/apic/ioapic.h>
132 #include <machine_base/apic/ioapic_abi.h>
133 #include <machine/mptable.h>
135 #define PHYSMAP_ENTRIES 10
137 extern u_int64_t hammer_time(u_int64_t, u_int64_t);
139 extern void printcpuinfo(void); /* XXX header file */
140 extern void identify_cpu(void);
142 extern void finishidentcpu(void);
144 extern void panicifcpuunsupported(void);
146 static void cpu_startup(void *);
147 static void pic_finish(void *);
148 static void cpu_finish(void *);
150 static void set_fpregs_xmm(struct save87 *, struct savexmm *);
151 static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
153 extern void ffs_rawread_setup(void);
154 #endif /* DIRECTIO */
155 static void init_locks(void);
157 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
158 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL);
159 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL);
162 extern vm_offset_t ksym_start, ksym_end;
165 struct privatespace CPU_prvspace_bsp __aligned(4096);
166 struct privatespace *CPU_prvspace[MAXCPU] = { &CPU_prvspace_bsp };
168 int _udatasel, _ucodesel, _ucode32sel;
170 int64_t tsc_offsets[MAXCPU];
172 static int cpu_mwait_halt_global; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */
174 #if defined(SWTCH_OPTIM_STATS)
175 extern int swtch_optim_stats;
176 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
177 CTLFLAG_RD, &swtch_optim_stats, 0, "");
178 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
179 CTLFLAG_RD, &tlb_flush_count, 0, "");
181 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt,
182 CTLFLAG_RD, &cpu_mwait_halt_global, 0, "");
183 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_spin, CTLFLAG_RD, &cpu_mwait_spin, 0,
184 "monitor/mwait target state");
186 #define CPU_MWAIT_HAS_CX \
187 ((cpu_feature2 & CPUID2_MON) && \
188 (cpu_mwait_feature & CPUID_MWAIT_EXT))
190 #define CPU_MWAIT_CX_NAMELEN 16
192 #define CPU_MWAIT_C1 1
193 #define CPU_MWAIT_C2 2
194 #define CPU_MWAIT_C3 3
195 #define CPU_MWAIT_CX_MAX 8
197 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */
198 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */
200 SYSCTL_NODE(_machdep, OID_AUTO, mwait, CTLFLAG_RW, 0, "MWAIT features");
201 SYSCTL_NODE(_machdep_mwait, OID_AUTO, CX, CTLFLAG_RW, 0, "MWAIT Cx settings");
203 struct cpu_mwait_cx {
206 struct sysctl_ctx_list sysctl_ctx;
207 struct sysctl_oid *sysctl_tree;
209 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX];
210 static char cpu_mwait_cx_supported[256];
212 static int cpu_mwait_c1_hints_cnt;
213 static int cpu_mwait_hints_cnt;
214 static int *cpu_mwait_hints;
216 static int cpu_mwait_deep_hints_cnt;
217 static int *cpu_mwait_deep_hints;
219 #define CPU_IDLE_REPEAT_DEFAULT 750
221 static u_int cpu_idle_repeat = CPU_IDLE_REPEAT_DEFAULT;
222 static u_long cpu_idle_repeat_max = CPU_IDLE_REPEAT_DEFAULT;
223 static u_int cpu_mwait_repeat_shift = 1;
225 #define CPU_MWAIT_C3_PREAMBLE_BM_ARB 0x1
226 #define CPU_MWAIT_C3_PREAMBLE_BM_STS 0x2
228 static int cpu_mwait_c3_preamble =
229 CPU_MWAIT_C3_PREAMBLE_BM_ARB |
230 CPU_MWAIT_C3_PREAMBLE_BM_STS;
232 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD,
233 cpu_mwait_cx_supported, 0, "MWAIT supported C states");
234 SYSCTL_INT(_machdep_mwait_CX, OID_AUTO, c3_preamble, CTLFLAG_RD,
235 &cpu_mwait_c3_preamble, 0, "C3+ preamble mask");
237 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS,
239 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS);
240 static int cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS);
241 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS);
243 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW,
244 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", "");
245 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW,
246 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", "");
247 SYSCTL_UINT(_machdep_mwait_CX, OID_AUTO, repeat_shift, CTLFLAG_RW,
248 &cpu_mwait_repeat_shift, 0, "");
252 u_long ebda_addr = 0;
254 int imcr_present = 0;
256 int naps = 0; /* # of Applications processors */
259 struct mtx dt_lock; /* lock for GDT and LDT */
262 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
264 u_long pmem = ctob(physmem);
266 int error = sysctl_handle_long(oidp, &pmem, 0, req);
270 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
271 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
274 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
276 int error = sysctl_handle_int(oidp, 0,
277 ctob(physmem - vmstats.v_wire_count), req);
281 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
282 0, 0, sysctl_hw_usermem, "IU", "");
285 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
287 int error = sysctl_handle_int(oidp, 0,
288 x86_64_btop(avail_end - avail_start), req);
292 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
293 0, 0, sysctl_hw_availpages, "I", "");
299 * The number of PHYSMAP entries must be one less than the number of
300 * PHYSSEG entries because the PHYSMAP entry that spans the largest
301 * physical address that is accessible by ISA DMA is split into two
304 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
306 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2];
307 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2];
309 /* must be 2 less so 0 0 can signal end of chunks */
310 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 2)
311 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 2)
313 static vm_offset_t buffer_sva, buffer_eva;
314 vm_offset_t clean_sva, clean_eva;
315 static vm_offset_t pager_sva, pager_eva;
316 static struct trapframe proc0_tf;
319 cpu_startup(void *dummy)
323 vm_offset_t firstaddr;
326 * Good {morning,afternoon,evening,night}.
328 kprintf("%s", version);
331 panicifcpuunsupported();
335 kprintf("real memory = %ju (%ju MB)\n",
337 (intmax_t)Realmem / 1024 / 1024);
339 * Display any holes after the first chunk of extended memory.
344 kprintf("Physical memory chunk(s):\n");
345 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
346 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
348 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
349 (intmax_t)phys_avail[indx],
350 (intmax_t)phys_avail[indx + 1] - 1,
352 (intmax_t)(size1 / PAGE_SIZE));
357 * Allocate space for system data structures.
358 * The first available kernel virtual address is in "v".
359 * As pages of kernel virtual memory are allocated, "v" is incremented.
360 * As pages of memory are allocated and cleared,
361 * "firstaddr" is incremented.
362 * An index into the kernel page table corresponding to the
363 * virtual memory address maintained in "v" is kept in "mapaddr".
367 * Make two passes. The first pass calculates how much memory is
368 * needed and allocates it. The second pass assigns virtual
369 * addresses to the various data structures.
373 v = (caddr_t)firstaddr;
375 #define valloc(name, type, num) \
376 (name) = (type *)v; v = (caddr_t)((name)+(num))
377 #define valloclim(name, type, num, lim) \
378 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
381 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
382 * For the first 64MB of ram nominally allocate sufficient buffers to
383 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
384 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
385 * the buffer cache we limit the eventual kva reservation to
388 * factor represents the 1/4 x ram conversion.
391 long factor = 4 * BKVASIZE / 1024;
392 long kbytes = physmem * (PAGE_SIZE / 1024);
396 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
398 nbuf += (kbytes - 65536) * 2 / (factor * 5);
399 if (maxbcache && nbuf > maxbcache / BKVASIZE)
400 nbuf = maxbcache / BKVASIZE;
404 * Do not allow the buffer_map to be more then 1/2 the size of the
407 if (nbuf > (virtual_end - virtual_start +
408 virtual2_end - virtual2_start) / (BKVASIZE * 2)) {
409 nbuf = (virtual_end - virtual_start +
410 virtual2_end - virtual2_start) / (BKVASIZE * 2);
411 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf);
415 * Do not allow the buffer_map to use more than 50% of available
416 * physical-equivalent memory. Since the VM pages which back
417 * individual buffers are typically wired, having too many bufs
418 * can prevent the system from paging properly.
420 if (nbuf > physmem * PAGE_SIZE / (BKVASIZE * 2)) {
421 nbuf = physmem * PAGE_SIZE / (BKVASIZE * 2);
422 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf);
426 * Do not allow the sizeof(struct buf) * nbuf to exceed half of
427 * the valloc space which is just the virtual_end - virtual_start
428 * section. We use valloc() to allocate the buf header array.
430 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 2) {
431 nbuf = (virtual_end - virtual_start) /
432 sizeof(struct buf) / 2;
433 kprintf("Warning: nbufs capped at %ld due to valloc "
434 "considerations", nbuf);
437 nswbuf = lmax(lmin(nbuf / 4, 256), 16);
439 if (nswbuf < NSWBUF_MIN)
446 valloc(swbuf, struct buf, nswbuf);
447 valloc(buf, struct buf, nbuf);
450 * End of first pass, size has been calculated so allocate memory
452 if (firstaddr == 0) {
453 size = (vm_size_t)(v - firstaddr);
454 firstaddr = kmem_alloc(&kernel_map, round_page(size));
456 panic("startup: no room for tables");
461 * End of second pass, addresses have been assigned
463 * nbuf is an int, make sure we don't overflow the field.
465 * On 64-bit systems we always reserve maximal allocations for
466 * buffer cache buffers and there are no fragmentation issues,
467 * so the KVA segment does not have to be excessively oversized.
469 if ((vm_size_t)(v - firstaddr) != size)
470 panic("startup: table size inconsistency");
472 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
473 ((vm_offset_t)(nbuf + 16) * BKVASIZE) +
474 (nswbuf * MAXPHYS) + pager_map_size);
475 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
476 ((vm_offset_t)(nbuf + 16) * BKVASIZE));
477 buffer_map.system_map = 1;
478 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
479 ((vm_offset_t)nswbuf * MAXPHYS) + pager_map_size);
480 pager_map.system_map = 1;
481 kprintf("avail memory = %ju (%ju MB)\n",
482 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages),
483 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) /
487 struct cpu_idle_stat {
495 u_long mwait_cx[CPU_MWAIT_CX_MAX];
498 #define CPU_IDLE_STAT_HALT -1
499 #define CPU_IDLE_STAT_SPIN -2
501 static struct cpu_idle_stat cpu_idle_stats[MAXCPU];
504 sysctl_cpu_idle_cnt(SYSCTL_HANDLER_ARGS)
506 int idx = arg2, cpu, error;
509 if (idx == CPU_IDLE_STAT_HALT) {
510 for (cpu = 0; cpu < ncpus; ++cpu)
511 val += cpu_idle_stats[cpu].halt;
512 } else if (idx == CPU_IDLE_STAT_SPIN) {
513 for (cpu = 0; cpu < ncpus; ++cpu)
514 val += cpu_idle_stats[cpu].spin;
516 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX,
517 ("invalid index %d", idx));
518 for (cpu = 0; cpu < ncpus; ++cpu)
519 val += cpu_idle_stats[cpu].mwait_cx[idx];
522 error = sysctl_handle_quad(oidp, &val, 0, req);
523 if (error || req->newptr == NULL)
526 if (idx == CPU_IDLE_STAT_HALT) {
527 for (cpu = 0; cpu < ncpus; ++cpu)
528 cpu_idle_stats[cpu].halt = 0;
529 cpu_idle_stats[0].halt = val;
530 } else if (idx == CPU_IDLE_STAT_SPIN) {
531 for (cpu = 0; cpu < ncpus; ++cpu)
532 cpu_idle_stats[cpu].spin = 0;
533 cpu_idle_stats[0].spin = val;
535 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX,
536 ("invalid index %d", idx));
537 for (cpu = 0; cpu < ncpus; ++cpu)
538 cpu_idle_stats[cpu].mwait_cx[idx] = 0;
539 cpu_idle_stats[0].mwait_cx[idx] = val;
545 cpu_mwait_attach(void)
550 if (!CPU_MWAIT_HAS_CX)
553 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
554 (CPUID_TO_FAMILY(cpu_id) > 0xf ||
555 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
556 CPUID_TO_MODEL(cpu_id) >= 0xf))) {
560 * Pentium dual-core, Core 2 and beyond do not need any
561 * additional activities to enter deep C-state, i.e. C3(+).
563 cpu_mwait_cx_no_bmarb();
565 TUNABLE_INT_FETCH("machdep.cpu.mwait.bm_sts", &bm_sts);
567 cpu_mwait_cx_no_bmsts();
570 sbuf_new(&sb, cpu_mwait_cx_supported,
571 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN);
573 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) {
574 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i];
577 ksnprintf(cx->name, sizeof(cx->name), "C%d", i);
579 sysctl_ctx_init(&cx->sysctl_ctx);
580 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx,
581 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO,
582 cx->name, CTLFLAG_RW, NULL, "Cx control/info");
583 if (cx->sysctl_tree == NULL)
586 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i);
587 SYSCTL_ADD_INT(&cx->sysctl_ctx,
588 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
589 "subcnt", CTLFLAG_RD, &cx->subcnt, 0,
591 SYSCTL_ADD_PROC(&cx->sysctl_ctx,
592 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
593 "entered", (CTLTYPE_QUAD | CTLFLAG_RW), 0,
594 i, sysctl_cpu_idle_cnt, "Q", "# of times entered");
596 for (sub = 0; sub < cx->subcnt; ++sub)
597 sbuf_printf(&sb, "C%d/%d ", i, sub);
605 cpu_mwait_c1_hints_cnt = cpu_mwait_cx_info[CPU_MWAIT_C1].subcnt;
606 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i)
607 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt;
608 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt,
612 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) {
615 subcnt = cpu_mwait_cx_info[i].subcnt;
616 for (j = 0; j < subcnt; ++j) {
617 KASSERT(hint_idx < cpu_mwait_hints_cnt,
618 ("invalid mwait hint index %d", hint_idx));
619 cpu_mwait_hints[hint_idx] = MWAIT_EAX_HINT(i, j);
623 KASSERT(hint_idx == cpu_mwait_hints_cnt,
624 ("mwait hint count %d != index %d",
625 cpu_mwait_hints_cnt, hint_idx));
628 kprintf("MWAIT hints (%d C1 hints):\n", cpu_mwait_c1_hints_cnt);
629 for (i = 0; i < cpu_mwait_hints_cnt; ++i) {
630 int hint = cpu_mwait_hints[i];
632 kprintf(" C%d/%d hint 0x%04x\n",
633 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint),
641 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i)
642 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt;
643 cpu_mwait_deep_hints = kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt,
647 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) {
650 subcnt = cpu_mwait_cx_info[i].subcnt;
651 for (j = 0; j < subcnt; ++j) {
652 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt,
653 ("invalid mwait deep hint index %d", hint_idx));
654 cpu_mwait_deep_hints[hint_idx] = MWAIT_EAX_HINT(i, j);
658 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt,
659 ("mwait deep hint count %d != index %d",
660 cpu_mwait_deep_hints_cnt, hint_idx));
663 kprintf("MWAIT deep hints:\n");
664 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) {
665 int hint = cpu_mwait_deep_hints[i];
667 kprintf(" C%d/%d hint 0x%04x\n",
668 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint),
672 cpu_idle_repeat_max = 256 * cpu_mwait_deep_hints_cnt;
674 for (i = 0; i < ncpus; ++i) {
677 ksnprintf(name, sizeof(name), "idle%d", i);
678 SYSCTL_ADD_PROC(NULL,
679 SYSCTL_STATIC_CHILDREN(_machdep_mwait_CX), OID_AUTO,
680 name, (CTLTYPE_STRING | CTLFLAG_RW), &cpu_idle_stats[i],
681 0, cpu_mwait_cx_pcpu_idle_sysctl, "A", "");
686 cpu_finish(void *dummy __unused)
693 pic_finish(void *dummy __unused)
695 /* Log ELCR information */
698 /* Log MPTABLE information */
699 mptable_pci_int_dump();
702 MachIntrABI.finalize();
706 * Send an interrupt to process.
708 * Stack is set up to allow sigcode stored
709 * at top to call routine, followed by kcall
710 * to sigreturn routine below. After sigreturn
711 * resets the signal mask, the stack, and the
712 * frame pointer, it returns to the user
716 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
718 struct lwp *lp = curthread->td_lwp;
719 struct proc *p = lp->lwp_proc;
720 struct trapframe *regs;
721 struct sigacts *psp = p->p_sigacts;
722 struct sigframe sf, *sfp;
726 regs = lp->lwp_md.md_regs;
727 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
729 /* Save user context */
730 bzero(&sf, sizeof(struct sigframe));
731 sf.sf_uc.uc_sigmask = *mask;
732 sf.sf_uc.uc_stack = lp->lwp_sigstk;
733 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
734 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0);
735 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe));
737 /* Make the size of the saved context visible to userland */
738 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
740 /* Allocate and validate space for the signal handler context. */
741 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack &&
742 SIGISMEMBER(psp->ps_sigonstack, sig)) {
743 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size -
744 sizeof(struct sigframe));
745 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
747 /* We take red zone into account */
748 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128;
752 * XXX AVX needs 64-byte alignment but sigframe has other fields and
753 * the embedded ucontext is not at the front, so aligning this won't
754 * help us. Fortunately we bcopy in/out of the sigframe, so the
757 * The problem though is if userland winds up trying to use the
760 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF);
762 /* Translate the signal is appropriate */
763 if (p->p_sysent->sv_sigtbl) {
764 if (sig <= p->p_sysent->sv_sigsize)
765 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
769 * Build the argument list for the signal handler.
771 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx)
773 regs->tf_rdi = sig; /* argument 1 */
774 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */
776 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
778 * Signal handler installed with SA_SIGINFO.
780 * action(signo, siginfo, ucontext)
782 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */
783 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
784 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
786 /* fill siginfo structure */
787 sf.sf_si.si_signo = sig;
788 sf.sf_si.si_code = code;
789 sf.sf_si.si_addr = (void *)regs->tf_addr;
792 * Old FreeBSD-style arguments.
794 * handler (signo, code, [uc], addr)
796 regs->tf_rsi = (register_t)code; /* argument 2 */
797 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
798 sf.sf_ahu.sf_handler = catcher;
802 * If we're a vm86 process, we want to save the segment registers.
803 * We also change eflags to be our emulated eflags, not the actual
807 if (regs->tf_eflags & PSL_VM) {
808 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
809 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
811 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
812 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
813 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
814 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
816 if (vm86->vm86_has_vme == 0)
817 sf.sf_uc.uc_mcontext.mc_eflags =
818 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
819 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
822 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
823 * syscalls made by the signal handler. This just avoids
824 * wasting time for our lazy fixup of such faults. PSL_NT
825 * does nothing in vm86 mode, but vm86 programs can set it
826 * almost legitimately in probes for old cpu types.
828 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
833 * Save the FPU state and reinit the FP unit
835 npxpush(&sf.sf_uc.uc_mcontext);
838 * Copy the sigframe out to the user's stack.
840 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
842 * Something is wrong with the stack pointer.
843 * ...Kill the process.
848 regs->tf_rsp = (register_t)sfp;
849 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
852 * i386 abi specifies that the direction flag must be cleared
855 regs->tf_rflags &= ~(PSL_T|PSL_D);
858 * 64 bit mode has a code and stack selector but
859 * no data or extra selector. %fs and %gs are not
862 regs->tf_cs = _ucodesel;
863 regs->tf_ss = _udatasel;
868 * Sanitize the trapframe for a virtual kernel passing control to a custom
869 * VM context. Remove any items that would otherwise create a privilage
872 * XXX at the moment we allow userland to set the resume flag. Is this a
876 cpu_sanitize_frame(struct trapframe *frame)
878 frame->tf_cs = _ucodesel;
879 frame->tf_ss = _udatasel;
880 /* XXX VM (8086) mode not supported? */
881 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP);
882 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I;
888 * Sanitize the tls so loading the descriptor does not blow up
889 * on us. For x86_64 we don't have to do anything.
892 cpu_sanitize_tls(struct savetls *tls)
898 * sigreturn(ucontext_t *sigcntxp)
900 * System call to cleanup state after a signal
901 * has been taken. Reset signal mask and
902 * stack state from context left by sendsig (above).
903 * Return to previous pc and psl as specified by
904 * context left by sendsig. Check carefully to
905 * make sure that the user has not modified the
906 * state to gain improper privileges.
910 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
911 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
914 sys_sigreturn(struct sigreturn_args *uap)
916 struct lwp *lp = curthread->td_lwp;
917 struct trapframe *regs;
925 * We have to copy the information into kernel space so userland
926 * can't modify it while we are sniffing it.
928 regs = lp->lwp_md.md_regs;
929 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
933 rflags = ucp->uc_mcontext.mc_rflags;
935 /* VM (8086) mode not supported */
936 rflags &= ~PSL_VM_UNSUPP;
939 if (eflags & PSL_VM) {
940 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
941 struct vm86_kernel *vm86;
944 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
945 * set up the vm86 area, and we can't enter vm86 mode.
947 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
949 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
950 if (vm86->vm86_inited == 0)
953 /* go back to user mode if both flags are set */
954 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
955 trapsignal(lp, SIGBUS, 0);
957 if (vm86->vm86_has_vme) {
958 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
959 (eflags & VME_USERCHANGE) | PSL_VM;
961 vm86->vm86_eflags = eflags; /* save VIF, VIP */
962 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
963 (eflags & VM_USERCHANGE) | PSL_VM;
965 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
966 tf->tf_eflags = eflags;
967 tf->tf_vm86_ds = tf->tf_ds;
968 tf->tf_vm86_es = tf->tf_es;
969 tf->tf_vm86_fs = tf->tf_fs;
970 tf->tf_vm86_gs = tf->tf_gs;
971 tf->tf_ds = _udatasel;
972 tf->tf_es = _udatasel;
973 tf->tf_fs = _udatasel;
974 tf->tf_gs = _udatasel;
979 * Don't allow users to change privileged or reserved flags.
982 * XXX do allow users to change the privileged flag PSL_RF.
983 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
984 * should sometimes set it there too. tf_eflags is kept in
985 * the signal context during signal handling and there is no
986 * other place to remember it, so the PSL_RF bit may be
987 * corrupted by the signal handler without us knowing.
988 * Corruption of the PSL_RF bit at worst causes one more or
989 * one less debugger trap, so allowing it is fairly harmless.
991 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) {
992 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags);
997 * Don't allow users to load a valid privileged %cs. Let the
998 * hardware check for invalid selectors, excess privilege in
999 * other selectors, invalid %eip's and invalid %esp's.
1001 cs = ucp->uc_mcontext.mc_cs;
1002 if (!CS_SECURE(cs)) {
1003 kprintf("sigreturn: cs = 0x%x\n", cs);
1004 trapsignal(lp, SIGBUS, T_PROTFLT);
1007 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe));
1011 * Restore the FPU state from the frame
1014 npxpop(&ucp->uc_mcontext);
1016 if (ucp->uc_mcontext.mc_onstack & 1)
1017 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
1019 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
1021 lp->lwp_sigmask = ucp->uc_sigmask;
1022 SIG_CANTMASK(lp->lwp_sigmask);
1025 return(EJUSTRETURN);
1029 * Machine dependent boot() routine
1031 * I haven't seen anything to put here yet
1032 * Possibly some stuff might be grafted back here from boot()
1040 * Shutdown the CPU as much as possible
1046 __asm__ __volatile("hlt");
1050 * cpu_idle() represents the idle LWKT. You cannot return from this function
1051 * (unless you want to blow things up!). Instead we look for runnable threads
1052 * and loop or halt as appropriate. Giant is not held on entry to the thread.
1054 * The main loop is entered with a critical section held, we must release
1055 * the critical section before doing anything else. lwkt_switch() will
1056 * check for pending interrupts due to entering and exiting its own
1059 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
1060 * However, there are cases where the idlethread will be entered with
1061 * the possibility that no IPI will occur and in such cases
1062 * lwkt_switch() sets TDF_IDLE_NOHLT.
1064 * NOTE: cpu_idle_repeat determines how many entries into the idle thread
1065 * must occur before it starts using ACPI halt.
1067 * NOTE: Value overridden in hammer_time().
1069 static int cpu_idle_hlt = 2;
1070 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
1071 &cpu_idle_hlt, 0, "Idle loop HLT enable");
1072 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
1073 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
1075 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_hltcnt, (CTLTYPE_QUAD | CTLFLAG_RW),
1076 0, CPU_IDLE_STAT_HALT, sysctl_cpu_idle_cnt, "Q", "Idle loop entry halts");
1077 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_spincnt, (CTLTYPE_QUAD | CTLFLAG_RW),
1078 0, CPU_IDLE_STAT_SPIN, sysctl_cpu_idle_cnt, "Q", "Idle loop entry spins");
1081 cpu_idle_default_hook(void)
1084 * We must guarentee that hlt is exactly the instruction
1085 * following the sti.
1087 __asm __volatile("sti; hlt");
1090 /* Other subsystems (e.g., ACPI) can hook this later. */
1091 void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
1094 cpu_mwait_cx_hint(struct cpu_idle_stat *stat)
1103 idx = (stat->repeat + stat->repeat_last + stat->repeat_delta) >>
1104 cpu_mwait_repeat_shift;
1105 if (idx >= cpu_mwait_c1_hints_cnt) {
1106 /* Step up faster, once we walked through all C1 states */
1107 stat->repeat_delta += 1 << (cpu_mwait_repeat_shift + 1);
1109 if (hint == CPU_MWAIT_HINT_AUTODEEP) {
1110 if (idx >= cpu_mwait_deep_hints_cnt)
1111 idx = cpu_mwait_deep_hints_cnt - 1;
1112 hint = cpu_mwait_deep_hints[idx];
1114 if (idx >= cpu_mwait_hints_cnt)
1115 idx = cpu_mwait_hints_cnt - 1;
1116 hint = cpu_mwait_hints[idx];
1119 cx_idx = MWAIT_EAX_TO_CX(hint);
1120 if (cx_idx >= 0 && cx_idx < CPU_MWAIT_CX_MAX)
1121 stat->mwait_cx[cx_idx]++;
1128 globaldata_t gd = mycpu;
1129 struct cpu_idle_stat *stat = &cpu_idle_stats[gd->gd_cpuid];
1130 struct thread *td __debugvar = gd->gd_curthread;
1134 stat->repeat = stat->repeat_last = cpu_idle_repeat_max;
1137 KKASSERT(td->td_critcount == 0);
1141 * See if there are any LWKTs ready to go.
1146 * When halting inside a cli we must check for reqflags
1147 * races, particularly [re]schedule requests. Running
1148 * splz() does the job.
1151 * 0 Never halt, just spin
1153 * 1 Always use HLT (or MONITOR/MWAIT if avail).
1155 * Better default for modern (Haswell+) Intel
1158 * 2 Use HLT/MONITOR/MWAIT up to a point and then
1159 * use the ACPI halt (default). This is a hybrid
1160 * approach. See machdep.cpu_idle_repeat.
1162 * Better default for modern AMD cpus and older
1165 * 3 Always use the ACPI halt. This typically
1166 * eats the least amount of power but the cpu
1167 * will be slow waking up. Slows down e.g.
1168 * compiles and other pipe/event oriented stuff.
1172 * NOTE: Interrupts are enabled and we are not in a critical
1175 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
1176 * don't bother capping gd_idle_repeat, it is ok if
1179 if (gd->gd_idle_repeat == 0) {
1180 stat->repeat = (stat->repeat + stat->repeat_last) >> 1;
1181 if (stat->repeat > cpu_idle_repeat_max)
1182 stat->repeat = cpu_idle_repeat_max;
1183 stat->repeat_last = 0;
1184 stat->repeat_delta = 0;
1186 ++stat->repeat_last;
1188 ++gd->gd_idle_repeat;
1189 reqflags = gd->gd_reqflags;
1190 quick = (cpu_idle_hlt == 1) ||
1191 (cpu_idle_hlt < 3 &&
1192 gd->gd_idle_repeat < cpu_idle_repeat);
1194 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
1195 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1197 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags,
1198 cpu_mwait_cx_hint(stat), 0);
1200 } else if (cpu_idle_hlt) {
1201 __asm __volatile("cli");
1203 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1205 cpu_idle_default_hook();
1209 __asm __volatile("sti");
1213 __asm __volatile("sti");
1220 * This routine is called if a spinlock has been held through the
1221 * exponential backoff period and is seriously contested. On a real cpu
1225 cpu_spinlock_contested(void)
1231 * Clear registers on exec
1234 exec_setregs(u_long entry, u_long stack, u_long ps_strings)
1236 struct thread *td = curthread;
1237 struct lwp *lp = td->td_lwp;
1238 struct pcb *pcb = td->td_pcb;
1239 struct trapframe *regs = lp->lwp_md.md_regs;
1241 /* was i386_user_cleanup() in NetBSD */
1245 bzero((char *)regs, sizeof(struct trapframe));
1246 regs->tf_rip = entry;
1247 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */
1248 regs->tf_rdi = stack; /* argv */
1249 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T);
1250 regs->tf_ss = _udatasel;
1251 regs->tf_cs = _ucodesel;
1252 regs->tf_rbx = ps_strings;
1255 * Reset the hardware debug registers if they were in use.
1256 * They won't have any meaning for the newly exec'd process.
1258 if (pcb->pcb_flags & PCB_DBREGS) {
1264 pcb->pcb_dr7 = 0; /* JG set bit 10? */
1265 if (pcb == td->td_pcb) {
1267 * Clear the debug registers on the running
1268 * CPU, otherwise they will end up affecting
1269 * the next process we switch to.
1273 pcb->pcb_flags &= ~PCB_DBREGS;
1277 * Initialize the math emulator (if any) for the current process.
1278 * Actually, just clear the bit that says that the emulator has
1279 * been initialized. Initialization is delayed until the process
1280 * traps to the emulator (if it is done at all) mainly because
1281 * emulators don't provide an entry point for initialization.
1283 pcb->pcb_flags &= ~FP_SOFTFP;
1286 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing
1287 * gd_npxthread. Otherwise a preemptive interrupt thread
1288 * may panic in npxdna().
1291 load_cr0(rcr0() | CR0_MP);
1294 * NOTE: The MSR values must be correct so we can return to
1295 * userland. gd_user_fs/gs must be correct so the switch
1296 * code knows what the current MSR values are.
1298 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */
1299 pcb->pcb_gsbase = 0;
1300 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */
1301 mdcpu->gd_user_gs = 0;
1302 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */
1303 wrmsr(MSR_KGSBASE, 0);
1305 /* Initialize the npx (if any) for the current process. */
1309 pcb->pcb_ds = _udatasel;
1310 pcb->pcb_es = _udatasel;
1311 pcb->pcb_fs = _udatasel;
1312 pcb->pcb_gs = _udatasel;
1321 cr0 |= CR0_NE; /* Done by npxinit() */
1322 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
1323 cr0 |= CR0_WP | CR0_AM;
1329 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1332 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1334 if (!error && req->newptr)
1339 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1340 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1342 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1343 CTLFLAG_RW, &disable_rtc_set, 0, "");
1346 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1347 CTLFLAG_RD, &bootinfo, bootinfo, "");
1350 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1351 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1353 extern u_long bootdev; /* not a cdev_t - encoding is different */
1354 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
1355 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
1358 * Initialize 386 and configure to run kernel
1362 * Initialize segments & interrupt table
1366 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1367 struct gate_descriptor idt_arr[MAXCPU][NIDT];
1369 union descriptor ldt[NLDT]; /* local descriptor table */
1372 /* table descriptors - used to load tables by cpu */
1373 struct region_descriptor r_gdt;
1374 struct region_descriptor r_idt_arr[MAXCPU];
1376 /* JG proc0paddr is a virtual address */
1379 char proc0paddr_buff[LWKT_THREAD_STACK];
1382 /* software prototypes -- in more palatable form */
1383 struct soft_segment_descriptor gdt_segs[] = {
1384 /* GNULL_SEL 0 Null Descriptor */
1385 { 0x0, /* segment base address */
1387 0, /* segment type */
1388 0, /* segment descriptor priority level */
1389 0, /* segment descriptor present */
1391 0, /* default 32 vs 16 bit size */
1392 0 /* limit granularity (byte/page units)*/ },
1393 /* GCODE_SEL 1 Code Descriptor for kernel */
1394 { 0x0, /* segment base address */
1395 0xfffff, /* length - all address space */
1396 SDT_MEMERA, /* segment type */
1397 SEL_KPL, /* segment descriptor priority level */
1398 1, /* segment descriptor present */
1400 0, /* default 32 vs 16 bit size */
1401 1 /* limit granularity (byte/page units)*/ },
1402 /* GDATA_SEL 2 Data Descriptor for kernel */
1403 { 0x0, /* segment base address */
1404 0xfffff, /* length - all address space */
1405 SDT_MEMRWA, /* segment type */
1406 SEL_KPL, /* segment descriptor priority level */
1407 1, /* segment descriptor present */
1409 0, /* default 32 vs 16 bit size */
1410 1 /* limit granularity (byte/page units)*/ },
1411 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */
1412 { 0x0, /* segment base address */
1413 0xfffff, /* length - all address space */
1414 SDT_MEMERA, /* segment type */
1415 SEL_UPL, /* segment descriptor priority level */
1416 1, /* segment descriptor present */
1418 1, /* default 32 vs 16 bit size */
1419 1 /* limit granularity (byte/page units)*/ },
1420 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */
1421 { 0x0, /* segment base address */
1422 0xfffff, /* length - all address space */
1423 SDT_MEMRWA, /* segment type */
1424 SEL_UPL, /* segment descriptor priority level */
1425 1, /* segment descriptor present */
1427 1, /* default 32 vs 16 bit size */
1428 1 /* limit granularity (byte/page units)*/ },
1429 /* GUCODE_SEL 5 64 bit Code Descriptor for user */
1430 { 0x0, /* segment base address */
1431 0xfffff, /* length - all address space */
1432 SDT_MEMERA, /* segment type */
1433 SEL_UPL, /* segment descriptor priority level */
1434 1, /* segment descriptor present */
1436 0, /* default 32 vs 16 bit size */
1437 1 /* limit granularity (byte/page units)*/ },
1438 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */
1440 0x0, /* segment base address */
1441 sizeof(struct x86_64tss)-1,/* length - all address space */
1442 SDT_SYSTSS, /* segment type */
1443 SEL_KPL, /* segment descriptor priority level */
1444 1, /* segment descriptor present */
1446 0, /* unused - default 32 vs 16 bit size */
1447 0 /* limit granularity (byte/page units)*/ },
1448 /* Actually, the TSS is a system descriptor which is double size */
1449 { 0x0, /* segment base address */
1451 0, /* segment type */
1452 0, /* segment descriptor priority level */
1453 0, /* segment descriptor present */
1455 0, /* default 32 vs 16 bit size */
1456 0 /* limit granularity (byte/page units)*/ },
1457 /* GUGS32_SEL 8 32 bit GS Descriptor for user */
1458 { 0x0, /* segment base address */
1459 0xfffff, /* length - all address space */
1460 SDT_MEMRWA, /* segment type */
1461 SEL_UPL, /* segment descriptor priority level */
1462 1, /* segment descriptor present */
1464 1, /* default 32 vs 16 bit size */
1465 1 /* limit granularity (byte/page units)*/ },
1469 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist)
1473 for (cpu = 0; cpu < MAXCPU; ++cpu) {
1474 struct gate_descriptor *ip = &idt_arr[cpu][idx];
1476 ip->gd_looffset = (uintptr_t)func;
1477 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1483 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1488 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu)
1490 struct gate_descriptor *ip;
1492 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu));
1494 ip = &idt_arr[cpu][idx];
1495 ip->gd_looffset = (uintptr_t)func;
1496 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1502 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1505 #define IDTVEC(name) __CONCAT(X,name)
1508 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1509 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1510 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
1511 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
1512 IDTVEC(xmm), IDTVEC(dblfault),
1513 IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
1516 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd)
1518 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1519 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1520 ssd->ssd_type = sd->sd_type;
1521 ssd->ssd_dpl = sd->sd_dpl;
1522 ssd->ssd_p = sd->sd_p;
1523 ssd->ssd_def32 = sd->sd_def32;
1524 ssd->ssd_gran = sd->sd_gran;
1528 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd)
1531 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1532 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff;
1533 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1534 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1535 sd->sd_type = ssd->ssd_type;
1536 sd->sd_dpl = ssd->ssd_dpl;
1537 sd->sd_p = ssd->ssd_p;
1538 sd->sd_long = ssd->ssd_long;
1539 sd->sd_def32 = ssd->ssd_def32;
1540 sd->sd_gran = ssd->ssd_gran;
1544 ssdtosyssd(struct soft_segment_descriptor *ssd,
1545 struct system_segment_descriptor *sd)
1548 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1549 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful;
1550 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1551 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1552 sd->sd_type = ssd->ssd_type;
1553 sd->sd_dpl = ssd->ssd_dpl;
1554 sd->sd_p = ssd->ssd_p;
1555 sd->sd_gran = ssd->ssd_gran;
1559 * Populate the (physmap) array with base/bound pairs describing the
1560 * available physical memory in the system, then test this memory and
1561 * build the phys_avail array describing the actually-available memory.
1563 * If we cannot accurately determine the physical memory map, then use
1564 * value from the 0xE801 call, and failing that, the RTC.
1566 * Total memory size may be set by the kernel environment variable
1567 * hw.physmem or the compile-time define MAXMEM.
1569 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple
1570 * of PAGE_SIZE. This also greatly reduces the memory test time
1571 * which would otherwise be excessive on machines with > 8G of ram.
1573 * XXX first should be vm_paddr_t.
1576 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024)
1577 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1)
1578 vm_paddr_t physmap[PHYSMAP_SIZE];
1579 struct bios_smap *smapbase, *smap, *smapend;
1580 struct efi_map_header *efihdrbase;
1584 add_smap_entries(int *physmap_idx)
1588 smapsize = *((u_int32_t *)smapbase - 1);
1589 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
1591 for (smap = smapbase; smap < smapend; smap++) {
1592 if (boothowto & RB_VERBOSE)
1593 kprintf("SMAP type=%02x base=%016lx len=%016lx\n",
1594 smap->type, smap->base, smap->length);
1596 if (smap->type != SMAP_TYPE_MEMORY)
1599 if (smap->length == 0)
1602 for (i = 0; i <= *physmap_idx; i += 2) {
1603 if (smap->base < physmap[i + 1]) {
1604 if (boothowto & RB_VERBOSE) {
1605 kprintf("Overlapping or non-monotonic "
1606 "memory region, ignoring "
1612 if (i <= *physmap_idx)
1615 Realmem += smap->length;
1617 if (smap->base == physmap[*physmap_idx + 1]) {
1618 physmap[*physmap_idx + 1] += smap->length;
1623 if (*physmap_idx == PHYSMAP_SIZE) {
1624 kprintf("Too many segments in the physical "
1625 "address map, giving up\n");
1628 physmap[*physmap_idx] = smap->base;
1629 physmap[*physmap_idx + 1] = smap->base + smap->length;
1633 #define efi_next_descriptor(ptr, size) \
1634 ((struct efi_md *)(((uint8_t *) ptr) + size))
1637 add_efi_map_entries(int *physmap_idx)
1639 struct efi_md *map, *p;
1644 static const char *types[] = {
1650 "RuntimeServicesCode",
1651 "RuntimeServicesData",
1652 "ConventionalMemory",
1654 "ACPIReclaimMemory",
1657 "MemoryMappedIOPortSpace",
1662 * Memory map data provided by UEFI via the GetMemoryMap
1663 * Boot Services API.
1665 efisz = (sizeof(struct efi_map_header) + 0xf) & ~0xf;
1666 map = (struct efi_md *)((uint8_t *)efihdrbase + efisz);
1668 if (efihdrbase->descriptor_size == 0)
1670 ndesc = efihdrbase->memory_size / efihdrbase->descriptor_size;
1672 if (boothowto & RB_VERBOSE)
1673 kprintf("%23s %12s %12s %8s %4s\n",
1674 "Type", "Physical", "Virtual", "#Pages", "Attr");
1676 for (i = 0, p = map; i < ndesc; i++,
1677 p = efi_next_descriptor(p, efihdrbase->descriptor_size)) {
1678 if (boothowto & RB_VERBOSE) {
1679 if (p->md_type <= EFI_MD_TYPE_PALCODE)
1680 type = types[p->md_type];
1683 kprintf("%23s %012lx %12p %08lx ", type, p->md_phys,
1684 p->md_virt, p->md_pages);
1685 if (p->md_attr & EFI_MD_ATTR_UC)
1687 if (p->md_attr & EFI_MD_ATTR_WC)
1689 if (p->md_attr & EFI_MD_ATTR_WT)
1691 if (p->md_attr & EFI_MD_ATTR_WB)
1693 if (p->md_attr & EFI_MD_ATTR_UCE)
1695 if (p->md_attr & EFI_MD_ATTR_WP)
1697 if (p->md_attr & EFI_MD_ATTR_RP)
1699 if (p->md_attr & EFI_MD_ATTR_XP)
1701 if (p->md_attr & EFI_MD_ATTR_RT)
1706 switch (p->md_type) {
1707 case EFI_MD_TYPE_CODE:
1708 case EFI_MD_TYPE_DATA:
1709 case EFI_MD_TYPE_BS_CODE:
1710 case EFI_MD_TYPE_BS_DATA:
1711 case EFI_MD_TYPE_FREE:
1713 * We're allowed to use any entry with these types.
1720 Realmem += p->md_pages * PAGE_SIZE;
1722 if (p->md_phys == physmap[*physmap_idx + 1]) {
1723 physmap[*physmap_idx + 1] += p->md_pages * PAGE_SIZE;
1728 if (*physmap_idx == PHYSMAP_SIZE) {
1729 kprintf("Too many segments in the physical "
1730 "address map, giving up\n");
1733 physmap[*physmap_idx] = p->md_phys;
1734 physmap[*physmap_idx + 1] = p->md_phys + p->md_pages * PAGE_SIZE;
1738 struct fb_info efi_fb_info;
1739 static int have_efi_framebuffer = 0;
1742 efi_fb_init_vaddr(void)
1746 sz = efi_fb_info.stride * efi_fb_info.height;
1747 efi_fb_info.vaddr = PHYS_TO_DMAP(efi_fb_info.paddr);
1748 pmap_change_attr(efi_fb_info.vaddr, (sz + PAGE_MASK) / PAGE_SIZE,
1749 VM_MEMATTR_WRITE_COMBINING);
1751 if (efi_fb_info.vaddr != 0)
1752 memset((void *)efi_fb_info.vaddr, 0x77, sz);
1756 probe_efi_fb(int early)
1758 struct efi_fb *efifb;
1761 if (have_efi_framebuffer) {
1762 if (!early && efi_fb_info.vaddr == 0)
1763 efi_fb_init_vaddr();
1767 kmdp = preload_search_by_type("elf kernel");
1769 kmdp = preload_search_by_type("elf64 kernel");
1770 efifb = (struct efi_fb *)preload_search_info(kmdp,
1771 MODINFO_METADATA | MODINFOMD_EFI_FB);
1775 have_efi_framebuffer = 1;
1777 efi_fb_info.is_vga_boot_display = 1;
1778 efi_fb_info.width = efifb->fb_width;
1779 efi_fb_info.height = efifb->fb_height;
1780 efi_fb_info.stride = efifb->fb_stride * 4;
1781 efi_fb_info.depth = 32;
1782 efi_fb_info.paddr = efifb->fb_addr;
1784 efi_fb_info.vaddr = 0;
1786 efi_fb_init_vaddr();
1788 efi_fb_info.restore = NULL;
1789 efi_fb_info.device = NULL;
1795 getmemsize(caddr_t kmdp, u_int64_t first)
1797 int off, physmap_idx, pa_indx, da_indx;
1800 vm_paddr_t msgbuf_size;
1801 u_long physmem_tunable;
1803 quad_t dcons_addr, dcons_size;
1805 bzero(physmap, sizeof(physmap));
1809 * get memory map from INT 15:E820, kindly supplied by the loader.
1811 * subr_module.c says:
1812 * "Consumer may safely assume that size value precedes data."
1813 * ie: an int32_t immediately precedes smap.
1815 efihdrbase = (struct efi_map_header *)preload_search_info(kmdp,
1816 MODINFO_METADATA | MODINFOMD_EFI_MAP);
1817 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1818 MODINFO_METADATA | MODINFOMD_SMAP);
1819 if (smapbase == NULL && efihdrbase == NULL)
1820 panic("No BIOS smap or EFI map info from loader!");
1822 if (efihdrbase == NULL)
1823 add_smap_entries(&physmap_idx);
1825 add_efi_map_entries(&physmap_idx);
1827 base_memory = physmap[1] / 1024;
1828 /* make hole for AP bootstrap code */
1829 physmap[1] = mp_bootaddress(base_memory);
1831 /* Save EBDA address, if any */
1832 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1836 * Maxmem isn't the "maximum memory", it's one larger than the
1837 * highest page of the physical address space. It should be
1838 * called something like "Maxphyspage". We may adjust this
1839 * based on ``hw.physmem'' and the results of the memory test.
1841 Maxmem = atop(physmap[physmap_idx + 1]);
1844 Maxmem = MAXMEM / 4;
1847 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
1848 Maxmem = atop(physmem_tunable);
1851 * Don't allow MAXMEM or hw.physmem to extend the amount of memory
1854 if (Maxmem > atop(physmap[physmap_idx + 1]))
1855 Maxmem = atop(physmap[physmap_idx + 1]);
1858 * Blowing out the DMAP will blow up the system.
1860 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) {
1861 kprintf("Limiting Maxmem due to DMAP size\n");
1862 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS);
1865 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1866 (boothowto & RB_VERBOSE)) {
1867 kprintf("Physical memory use set to %ldK\n", Maxmem * 4);
1871 * Call pmap initialization to make new kernel address space
1875 pmap_bootstrap(&first);
1876 physmap[0] = PAGE_SIZE;
1879 * Align the physmap to PHYSMAP_ALIGN and cut out anything
1882 for (i = j = 0; i <= physmap_idx; i += 2) {
1883 if (physmap[i+1] > ptoa(Maxmem))
1884 physmap[i+1] = ptoa(Maxmem);
1885 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) &
1886 ~PHYSMAP_ALIGN_MASK;
1887 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK;
1889 physmap[j] = physmap[i];
1890 physmap[j+1] = physmap[i+1];
1892 if (physmap[i] < physmap[i+1])
1895 physmap_idx = j - 2;
1898 * Align anything else used in the validation loop.
1900 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1903 * Size up each available chunk of physical memory.
1907 phys_avail[pa_indx++] = physmap[0];
1908 phys_avail[pa_indx] = physmap[0];
1909 dump_avail[da_indx] = physmap[0];
1913 * Get dcons buffer address
1915 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1916 kgetenv_quad("dcons.size", &dcons_size) == 0)
1920 * Validate the physical memory. The physical memory segments
1921 * have already been aligned to PHYSMAP_ALIGN which is a multiple
1924 for (i = 0; i <= physmap_idx; i += 2) {
1927 end = physmap[i + 1];
1929 for (pa = physmap[i]; pa < end; pa += PHYSMAP_ALIGN) {
1930 int tmp, page_bad, full;
1931 int *ptr = (int *)CADDR1;
1935 * block out kernel memory as not available.
1937 if (pa >= 0x200000 && pa < first)
1941 * block out dcons buffer
1944 && pa >= trunc_page(dcons_addr)
1945 && pa < dcons_addr + dcons_size) {
1952 * map page into kernel: valid, read/write,non-cacheable
1955 kernel_pmap.pmap_bits[PG_V_IDX] |
1956 kernel_pmap.pmap_bits[PG_RW_IDX] |
1957 kernel_pmap.pmap_bits[PG_N_IDX];
1962 * Test for alternating 1's and 0's
1964 *(volatile int *)ptr = 0xaaaaaaaa;
1966 if (*(volatile int *)ptr != 0xaaaaaaaa)
1969 * Test for alternating 0's and 1's
1971 *(volatile int *)ptr = 0x55555555;
1973 if (*(volatile int *)ptr != 0x55555555)
1978 *(volatile int *)ptr = 0xffffffff;
1980 if (*(volatile int *)ptr != 0xffffffff)
1985 *(volatile int *)ptr = 0x0;
1987 if (*(volatile int *)ptr != 0x0)
1990 * Restore original value.
1995 * Adjust array of valid/good pages.
1997 if (page_bad == TRUE)
2000 * If this good page is a continuation of the
2001 * previous set of good pages, then just increase
2002 * the end pointer. Otherwise start a new chunk.
2003 * Note that "end" points one higher than end,
2004 * making the range >= start and < end.
2005 * If we're also doing a speculative memory
2006 * test and we at or past the end, bump up Maxmem
2007 * so that we keep going. The first bad page
2008 * will terminate the loop.
2010 if (phys_avail[pa_indx] == pa) {
2011 phys_avail[pa_indx] += PHYSMAP_ALIGN;
2014 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
2016 "Too many holes in the physical address space, giving up\n");
2021 phys_avail[pa_indx++] = pa;
2022 phys_avail[pa_indx] = pa + PHYSMAP_ALIGN;
2024 physmem += PHYSMAP_ALIGN / PAGE_SIZE;
2026 if (dump_avail[da_indx] == pa) {
2027 dump_avail[da_indx] += PHYSMAP_ALIGN;
2030 if (da_indx == DUMP_AVAIL_ARRAY_END) {
2034 dump_avail[da_indx++] = pa;
2035 dump_avail[da_indx] = pa + PHYSMAP_ALIGN;
2046 * The last chunk must contain at least one page plus the message
2047 * buffer to avoid complicating other code (message buffer address
2048 * calculation, etc.).
2050 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
2052 while (phys_avail[pa_indx - 1] + PHYSMAP_ALIGN +
2053 msgbuf_size >= phys_avail[pa_indx]) {
2054 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
2055 phys_avail[pa_indx--] = 0;
2056 phys_avail[pa_indx--] = 0;
2059 Maxmem = atop(phys_avail[pa_indx]);
2061 /* Trim off space for the message buffer. */
2062 phys_avail[pa_indx] -= msgbuf_size;
2064 avail_end = phys_avail[pa_indx];
2066 /* Map the message buffer. */
2067 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) {
2068 pmap_kenter((vm_offset_t)msgbufp + off,
2069 phys_avail[pa_indx] + off);
2073 struct machintr_abi MachIntrABI;
2084 * 7 Device Not Available (x87)
2086 * 9 Coprocessor Segment overrun (unsupported, reserved)
2088 * 11 Segment not present
2090 * 13 General Protection
2093 * 16 x87 FP Exception pending
2094 * 17 Alignment Check
2096 * 19 SIMD floating point
2098 * 32-255 INTn/external sources
2101 hammer_time(u_int64_t modulep, u_int64_t physfree)
2104 int gsel_tss, x, cpu;
2106 int metadata_missing, off;
2108 struct mdglobaldata *gd;
2112 * Prevent lowering of the ipl if we call tsleep() early.
2114 gd = &CPU_prvspace[0]->mdglobaldata;
2115 bzero(gd, sizeof(*gd));
2118 * Note: on both UP and SMP curthread must be set non-NULL
2119 * early in the boot sequence because the system assumes
2120 * that 'curthread' is never NULL.
2123 gd->mi.gd_curthread = &thread0;
2124 thread0.td_gd = &gd->mi;
2126 atdevbase = ISA_HOLE_START + PTOV_OFFSET;
2129 metadata_missing = 0;
2130 if (bootinfo.bi_modulep) {
2131 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
2132 preload_bootstrap_relocate(KERNBASE);
2134 metadata_missing = 1;
2136 if (bootinfo.bi_envp)
2137 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
2140 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET);
2141 preload_bootstrap_relocate(PTOV_OFFSET);
2142 kmdp = preload_search_by_type("elf kernel");
2144 kmdp = preload_search_by_type("elf64 kernel");
2145 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
2146 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET;
2148 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
2149 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
2152 if (boothowto & RB_VERBOSE)
2156 * Default MachIntrABI to ICU
2158 MachIntrABI = MachIntrABI_ICU;
2161 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
2162 * and ncpus_fit_mask remain 0.
2167 /* Init basic tunables, hz etc */
2171 * make gdt memory segments
2173 gdt_segs[GPROC0_SEL].ssd_base =
2174 (uintptr_t) &CPU_prvspace[0]->mdglobaldata.gd_common_tss;
2176 gd->mi.gd_prvspace = CPU_prvspace[0];
2178 for (x = 0; x < NGDT; x++) {
2179 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
2180 ssdtosd(&gdt_segs[x], &gdt[x]);
2182 ssdtosyssd(&gdt_segs[GPROC0_SEL],
2183 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
2185 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
2186 r_gdt.rd_base = (long) gdt;
2189 wrmsr(MSR_FSBASE, 0); /* User value */
2190 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi);
2191 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
2193 mi_gdinit(&gd->mi, 0);
2195 proc0paddr = proc0paddr_buff;
2196 mi_proc0init(&gd->mi, proc0paddr);
2197 safepri = TDPRI_MAX;
2199 /* spinlocks and the BGL */
2203 for (x = 0; x < NIDT; x++)
2204 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
2205 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0);
2206 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0);
2207 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1);
2208 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0);
2209 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0);
2210 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0);
2211 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0);
2212 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0);
2213 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1);
2214 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0);
2215 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0);
2216 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0);
2217 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0);
2218 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0);
2219 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0);
2220 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0);
2221 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0);
2222 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0);
2223 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0);
2225 for (cpu = 0; cpu < MAXCPU; ++cpu) {
2226 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1;
2227 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0];
2230 lidt(&r_idt_arr[0]);
2233 * Initialize the console before we print anything out.
2238 if (metadata_missing)
2239 kprintf("WARNING: loader(8) metadata is missing!\n");
2249 * Initialize IRQ mapping
2252 * SHOULD be after elcr_probe()
2254 MachIntrABI_ICU.initmap();
2255 MachIntrABI_IOAPIC.initmap();
2259 if (boothowto & RB_KDB)
2260 Debugger("Boot flags requested debugger");
2264 finishidentcpu(); /* Final stage of CPU initialization */
2265 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2266 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2268 identify_cpu(); /* Final stage of CPU initialization */
2269 initializecpu(0); /* Initialize CPU registers */
2272 * On modern intel cpus, haswell or later, cpu_idle_hlt=1 is better
2273 * becaue the cpu does significant power management in HLT
2274 * (also suggested is to set sysctl machdep.mwait.CX.idle=AUTODEEP).
2276 * On modern amd cpus or on any older amd or intel cpu,
2277 * cpu_idle_hlt=2 is better because ACPI is needed to reduce power
2280 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
2281 CPUID_TO_MODEL(cpu_id) >= 0x3C) { /* Haswell or later */
2285 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */
2286 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable);
2287 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable);
2288 TUNABLE_INT_FETCH("machdep.cpu_idle_hlt", &cpu_idle_hlt);
2291 * Some of the virtual machines do not work w/ I/O APIC
2292 * enabled. If the user does not explicitly enable or
2293 * disable the I/O APIC (ioapic_enable < 0), then we
2294 * disable I/O APIC on all virtual machines.
2297 * This must be done after identify_cpu(), which sets
2300 if (ioapic_enable < 0) {
2301 if (cpu_feature2 & CPUID2_VMM)
2307 /* make an initial tss so cpu can get interrupt stack on syscall! */
2308 gd->gd_common_tss.tss_rsp0 =
2309 (register_t)(thread0.td_kstack +
2310 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb));
2311 /* Ensure the stack is aligned to 16 bytes */
2312 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF;
2314 /* double fault stack */
2315 gd->gd_common_tss.tss_ist1 =
2316 (long)&gd->mi.gd_prvspace->idlestack[
2317 sizeof(gd->mi.gd_prvspace->idlestack)];
2319 /* Set the IO permission bitmap (empty due to tss seg limit) */
2320 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss);
2322 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
2323 gd->gd_tss_gdt = &gdt[GPROC0_SEL];
2324 gd->gd_common_tssd = *gd->gd_tss_gdt;
2327 /* Set up the fast syscall stuff */
2328 msr = rdmsr(MSR_EFER) | EFER_SCE;
2329 wrmsr(MSR_EFER, msr);
2330 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
2331 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
2332 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
2333 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
2334 wrmsr(MSR_STAR, msr);
2335 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL);
2337 getmemsize(kmdp, physfree);
2338 init_param2(physmem);
2340 /* now running on new page tables, configured,and u/iom is accessible */
2342 /* Map the message buffer. */
2344 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
2345 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
2348 msgbufinit(msgbufp, MSGBUF_SIZE);
2351 /* transfer to user mode */
2353 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
2354 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
2355 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL);
2361 /* setup proc 0's pcb */
2362 thread0.td_pcb->pcb_flags = 0;
2363 thread0.td_pcb->pcb_cr3 = KPML4phys;
2364 thread0.td_pcb->pcb_ext = NULL;
2365 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */
2367 /* Location of kernel stack for locore */
2368 return ((u_int64_t)thread0.td_pcb);
2372 * Initialize machine-dependant portions of the global data structure.
2373 * Note that the global data area and cpu0's idlestack in the private
2374 * data space were allocated in locore.
2376 * Note: the idlethread's cpl is 0
2378 * WARNING! Called from early boot, 'mycpu' may not work yet.
2381 cpu_gdinit(struct mdglobaldata *gd, int cpu)
2384 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
2386 lwkt_init_thread(&gd->mi.gd_idlethread,
2387 gd->mi.gd_prvspace->idlestack,
2388 sizeof(gd->mi.gd_prvspace->idlestack),
2390 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
2391 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
2392 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
2393 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
2397 * We only have to check for DMAP bounds, the globaldata space is
2398 * actually part of the kernel_map so we don't have to waste time
2399 * checking CPU_prvspace[*].
2402 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2405 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2406 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2410 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS)
2416 globaldata_find(int cpu)
2418 KKASSERT(cpu >= 0 && cpu < ncpus);
2419 return(&CPU_prvspace[cpu]->mdglobaldata.mi);
2423 * This path should be safe from the SYSRET issue because only stopped threads
2424 * can have their %rip adjusted this way (and all heavy weight thread switches
2425 * clear QUICKREF and thus do not use SYSRET). However, the code path is
2426 * convoluted so add a safety by forcing %rip to be cannonical.
2429 ptrace_set_pc(struct lwp *lp, unsigned long addr)
2431 if (addr & 0x0000800000000000LLU)
2432 lp->lwp_md.md_regs->tf_rip = addr | 0xFFFF000000000000LLU;
2434 lp->lwp_md.md_regs->tf_rip = addr & 0x0000FFFFFFFFFFFFLLU;
2439 ptrace_single_step(struct lwp *lp)
2441 lp->lwp_md.md_regs->tf_rflags |= PSL_T;
2446 fill_regs(struct lwp *lp, struct reg *regs)
2448 struct trapframe *tp;
2450 if ((tp = lp->lwp_md.md_regs) == NULL)
2452 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs));
2457 set_regs(struct lwp *lp, struct reg *regs)
2459 struct trapframe *tp;
2461 tp = lp->lwp_md.md_regs;
2462 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) ||
2463 !CS_SECURE(regs->r_cs))
2465 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs));
2471 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
2473 struct env87 *penv_87 = &sv_87->sv_env;
2474 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2477 /* FPU control/status */
2478 penv_87->en_cw = penv_xmm->en_cw;
2479 penv_87->en_sw = penv_xmm->en_sw;
2480 penv_87->en_tw = penv_xmm->en_tw;
2481 penv_87->en_fip = penv_xmm->en_fip;
2482 penv_87->en_fcs = penv_xmm->en_fcs;
2483 penv_87->en_opcode = penv_xmm->en_opcode;
2484 penv_87->en_foo = penv_xmm->en_foo;
2485 penv_87->en_fos = penv_xmm->en_fos;
2488 for (i = 0; i < 8; ++i)
2489 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
2493 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
2495 struct env87 *penv_87 = &sv_87->sv_env;
2496 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2499 /* FPU control/status */
2500 penv_xmm->en_cw = penv_87->en_cw;
2501 penv_xmm->en_sw = penv_87->en_sw;
2502 penv_xmm->en_tw = penv_87->en_tw;
2503 penv_xmm->en_fip = penv_87->en_fip;
2504 penv_xmm->en_fcs = penv_87->en_fcs;
2505 penv_xmm->en_opcode = penv_87->en_opcode;
2506 penv_xmm->en_foo = penv_87->en_foo;
2507 penv_xmm->en_fos = penv_87->en_fos;
2510 for (i = 0; i < 8; ++i)
2511 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
2515 fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
2517 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL)
2520 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2521 (struct save87 *)fpregs);
2524 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
2529 set_fpregs(struct lwp *lp, struct fpreg *fpregs)
2532 set_fpregs_xmm((struct save87 *)fpregs,
2533 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
2536 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
2541 fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
2546 dbregs->dr[0] = rdr0();
2547 dbregs->dr[1] = rdr1();
2548 dbregs->dr[2] = rdr2();
2549 dbregs->dr[3] = rdr3();
2550 dbregs->dr[4] = rdr4();
2551 dbregs->dr[5] = rdr5();
2552 dbregs->dr[6] = rdr6();
2553 dbregs->dr[7] = rdr7();
2556 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL)
2558 dbregs->dr[0] = pcb->pcb_dr0;
2559 dbregs->dr[1] = pcb->pcb_dr1;
2560 dbregs->dr[2] = pcb->pcb_dr2;
2561 dbregs->dr[3] = pcb->pcb_dr3;
2564 dbregs->dr[6] = pcb->pcb_dr6;
2565 dbregs->dr[7] = pcb->pcb_dr7;
2570 set_dbregs(struct lwp *lp, struct dbreg *dbregs)
2573 load_dr0(dbregs->dr[0]);
2574 load_dr1(dbregs->dr[1]);
2575 load_dr2(dbregs->dr[2]);
2576 load_dr3(dbregs->dr[3]);
2577 load_dr4(dbregs->dr[4]);
2578 load_dr5(dbregs->dr[5]);
2579 load_dr6(dbregs->dr[6]);
2580 load_dr7(dbregs->dr[7]);
2583 struct ucred *ucred;
2585 uint64_t mask1, mask2;
2588 * Don't let an illegal value for dr7 get set. Specifically,
2589 * check for undefined settings. Setting these bit patterns
2590 * result in undefined behaviour and can lead to an unexpected
2593 /* JG this loop looks unreadable */
2594 /* Check 4 2-bit fields for invalid patterns.
2595 * These fields are R/Wi, for i = 0..3
2597 /* Is 10 in LENi allowed when running in compatibility mode? */
2598 /* Pattern 10 in R/Wi might be used to indicate
2599 * breakpoint on I/O. Further analysis should be
2600 * carried to decide if it is safe and useful to
2601 * provide access to that capability
2603 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4;
2604 i++, mask1 <<= 4, mask2 <<= 4)
2605 if ((dbregs->dr[7] & mask1) == mask2)
2608 pcb = lp->lwp_thread->td_pcb;
2609 ucred = lp->lwp_proc->p_ucred;
2612 * Don't let a process set a breakpoint that is not within the
2613 * process's address space. If a process could do this, it
2614 * could halt the system by setting a breakpoint in the kernel
2615 * (if ddb was enabled). Thus, we need to check to make sure
2616 * that no breakpoints are being enabled for addresses outside
2617 * process's address space, unless, perhaps, we were called by
2620 * XXX - what about when the watched area of the user's
2621 * address space is written into from within the kernel
2622 * ... wouldn't that still cause a breakpoint to be generated
2623 * from within kernel mode?
2626 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
2627 if (dbregs->dr[7] & 0x3) {
2628 /* dr0 is enabled */
2629 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS)
2633 if (dbregs->dr[7] & (0x3<<2)) {
2634 /* dr1 is enabled */
2635 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS)
2639 if (dbregs->dr[7] & (0x3<<4)) {
2640 /* dr2 is enabled */
2641 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS)
2645 if (dbregs->dr[7] & (0x3<<6)) {
2646 /* dr3 is enabled */
2647 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS)
2652 pcb->pcb_dr0 = dbregs->dr[0];
2653 pcb->pcb_dr1 = dbregs->dr[1];
2654 pcb->pcb_dr2 = dbregs->dr[2];
2655 pcb->pcb_dr3 = dbregs->dr[3];
2656 pcb->pcb_dr6 = dbregs->dr[6];
2657 pcb->pcb_dr7 = dbregs->dr[7];
2659 pcb->pcb_flags |= PCB_DBREGS;
2666 * Return > 0 if a hardware breakpoint has been hit, and the
2667 * breakpoint was in user space. Return 0, otherwise.
2670 user_dbreg_trap(void)
2672 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */
2673 u_int64_t bp; /* breakpoint bits extracted from dr6 */
2674 int nbp; /* number of breakpoints that triggered */
2675 caddr_t addr[4]; /* breakpoint addresses */
2679 if ((dr7 & 0xff) == 0) {
2681 * all GE and LE bits in the dr7 register are zero,
2682 * thus the trap couldn't have been caused by the
2683 * hardware debug registers
2694 * None of the breakpoint bits are set meaning this
2695 * trap was not caused by any of the debug registers
2701 * at least one of the breakpoints were hit, check to see
2702 * which ones and if any of them are user space addresses
2706 addr[nbp++] = (caddr_t)rdr0();
2709 addr[nbp++] = (caddr_t)rdr1();
2712 addr[nbp++] = (caddr_t)rdr2();
2715 addr[nbp++] = (caddr_t)rdr3();
2718 for (i=0; i<nbp; i++) {
2720 (caddr_t)VM_MAX_USER_ADDRESS) {
2722 * addr[i] is in user space
2729 * None of the breakpoints are in user space.
2737 Debugger(const char *msg)
2739 kprintf("Debugger(\"%s\") called.\n", msg);
2746 * Provide inb() and outb() as functions. They are normally only
2747 * available as macros calling inlined functions, thus cannot be
2748 * called inside DDB.
2750 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2756 /* silence compiler warnings */
2758 void outb(u_int, u_char);
2765 * We use %%dx and not %1 here because i/o is done at %dx and not at
2766 * %edx, while gcc generates inferior code (movw instead of movl)
2767 * if we tell it to load (u_short) port.
2769 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2774 outb(u_int port, u_char data)
2778 * Use an unnecessary assignment to help gcc's register allocator.
2779 * This make a large difference for gcc-1.40 and a tiny difference
2780 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2781 * best results. gcc-2.6.0 can't handle this.
2784 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2792 * initialize all the SMP locks
2795 /* critical region when masking or unmasking interupts */
2796 struct spinlock_deprecated imen_spinlock;
2798 /* lock region used by kernel profiling */
2799 struct spinlock_deprecated mcount_spinlock;
2801 /* locks com (tty) data/hardware accesses: a FASTINTR() */
2802 struct spinlock_deprecated com_spinlock;
2804 /* lock regions around the clock hardware */
2805 struct spinlock_deprecated clock_spinlock;
2811 * Get the initial mplock with a count of 1 for the BSP.
2812 * This uses a LOGICAL cpu ID, ie BSP == 0.
2814 cpu_get_initial_mplock();
2816 spin_init_deprecated(&mcount_spinlock);
2817 spin_init_deprecated(&imen_spinlock);
2818 spin_init_deprecated(&com_spinlock);
2819 spin_init_deprecated(&clock_spinlock);
2821 /* our token pool needs to work early */
2822 lwkt_token_pool_init();
2826 cpu_mwait_hint_valid(uint32_t hint)
2830 cx_idx = MWAIT_EAX_TO_CX(hint);
2831 if (cx_idx >= CPU_MWAIT_CX_MAX)
2834 sub = MWAIT_EAX_TO_CX_SUB(hint);
2835 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt)
2842 cpu_mwait_cx_no_bmsts(void)
2844 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_STS);
2848 cpu_mwait_cx_no_bmarb(void)
2850 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_ARB);
2854 cpu_mwait_cx_hint2name(int hint, char *name, int namelen, boolean_t allow_auto)
2856 int old_cx_idx, sub = 0;
2859 old_cx_idx = MWAIT_EAX_TO_CX(hint);
2860 sub = MWAIT_EAX_TO_CX_SUB(hint);
2861 } else if (hint == CPU_MWAIT_HINT_AUTO) {
2862 old_cx_idx = allow_auto ? CPU_MWAIT_C2 : CPU_MWAIT_CX_MAX;
2863 } else if (hint == CPU_MWAIT_HINT_AUTODEEP) {
2864 old_cx_idx = allow_auto ? CPU_MWAIT_C3 : CPU_MWAIT_CX_MAX;
2866 old_cx_idx = CPU_MWAIT_CX_MAX;
2869 if (!CPU_MWAIT_HAS_CX)
2870 strlcpy(name, "NONE", namelen);
2871 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTO)
2872 strlcpy(name, "AUTO", namelen);
2873 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTODEEP)
2874 strlcpy(name, "AUTODEEP", namelen);
2875 else if (old_cx_idx >= CPU_MWAIT_CX_MAX ||
2876 sub >= cpu_mwait_cx_info[old_cx_idx].subcnt)
2877 strlcpy(name, "INVALID", namelen);
2879 ksnprintf(name, namelen, "C%d/%d", old_cx_idx, sub);
2885 cpu_mwait_cx_name2hint(char *name, int *hint0, boolean_t allow_auto)
2887 int cx_idx, sub, hint;
2890 if (allow_auto && strcmp(name, "AUTO") == 0) {
2891 hint = CPU_MWAIT_HINT_AUTO;
2892 cx_idx = CPU_MWAIT_C2;
2895 if (allow_auto && strcmp(name, "AUTODEEP") == 0) {
2896 hint = CPU_MWAIT_HINT_AUTODEEP;
2897 cx_idx = CPU_MWAIT_C3;
2901 if (strlen(name) < 4 || toupper(name[0]) != 'C')
2906 cx_idx = strtol(start, &ptr, 10);
2907 if (ptr == start || *ptr != '/')
2909 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX)
2915 sub = strtol(start, &ptr, 10);
2918 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt)
2921 hint = MWAIT_EAX_HINT(cx_idx, sub);
2928 cpu_mwait_cx_transit(int old_cx_idx, int cx_idx)
2930 if (cx_idx >= CPU_MWAIT_C3 && cpu_mwait_c3_preamble)
2932 if (old_cx_idx < CPU_MWAIT_C3 && cx_idx >= CPU_MWAIT_C3) {
2935 error = cputimer_intr_powersave_addreq();
2938 } else if (old_cx_idx >= CPU_MWAIT_C3 && cx_idx < CPU_MWAIT_C3) {
2939 cputimer_intr_powersave_remreq();
2945 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0,
2946 boolean_t allow_auto)
2948 int error, cx_idx, old_cx_idx, hint;
2949 char name[CPU_MWAIT_CX_NAMELEN];
2952 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name),
2955 error = sysctl_handle_string(oidp, name, sizeof(name), req);
2956 if (error != 0 || req->newptr == NULL)
2959 if (!CPU_MWAIT_HAS_CX)
2962 cx_idx = cpu_mwait_cx_name2hint(name, &hint, allow_auto);
2966 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx);
2975 cpu_mwait_cx_setname(struct cpu_idle_stat *stat, const char *cx_name)
2977 int error, cx_idx, old_cx_idx, hint;
2978 char name[CPU_MWAIT_CX_NAMELEN];
2980 KASSERT(CPU_MWAIT_HAS_CX, ("cpu does not support mwait CX extension"));
2983 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE);
2985 strlcpy(name, cx_name, sizeof(name));
2986 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE);
2990 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx);
2999 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS)
3001 int hint = cpu_mwait_halt_global;
3002 int error, cx_idx, cpu;
3003 char name[CPU_MWAIT_CX_NAMELEN], cx_name[CPU_MWAIT_CX_NAMELEN];
3005 cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE);
3007 error = sysctl_handle_string(oidp, name, sizeof(name), req);
3008 if (error != 0 || req->newptr == NULL)
3011 if (!CPU_MWAIT_HAS_CX)
3014 /* Save name for later per-cpu CX configuration */
3015 strlcpy(cx_name, name, sizeof(cx_name));
3017 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE);
3021 /* Change per-cpu CX configuration */
3022 for (cpu = 0; cpu < ncpus; ++cpu) {
3023 error = cpu_mwait_cx_setname(&cpu_idle_stats[cpu], cx_name);
3028 cpu_mwait_halt_global = hint;
3033 cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS)
3035 struct cpu_idle_stat *stat = arg1;
3038 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
3044 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS)
3048 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
3049 &cpu_mwait_spin, FALSE);