3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.6 2004/08/02 15:10:08 joerg Exp $
40 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
64 * o TCP/IP checksum offload for both RX and TX
66 * o High and normal priority transmit DMA rings
68 * o VLAN tag insertion and extraction
70 * o TCP large send (segmentation offload)
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
85 * o GMII and TBI ports/registers for interfacing with copper
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
91 * o Slight differences in register layout from the 8139C+
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7.5K, so the max MTU possible with this
111 * driver is 7500 bytes.
114 #include <sys/param.h>
115 #include <sys/endian.h>
116 #include <sys/systm.h>
117 #include <sys/sockio.h>
118 #include <sys/mbuf.h>
119 #include <sys/malloc.h>
120 #include <sys/module.h>
121 #include <sys/kernel.h>
122 #include <sys/socket.h>
125 #include <net/if_arp.h>
126 #include <net/ethernet.h>
127 #include <net/if_dl.h>
128 #include <net/if_media.h>
129 #include <net/if_types.h>
130 #include <net/vlan/if_vlan_var.h>
134 #include <machine/bus_pio.h>
135 #include <machine/bus_memio.h>
136 #include <machine/bus.h>
137 #include <machine/resource.h>
139 #include <sys/rman.h>
141 #include <dev/netif/mii_layer/mii.h>
142 #include <dev/netif/mii_layer/miivar.h>
144 #include <bus/pci/pcireg.h>
145 #include <bus/pci/pcivar.h>
147 /* "controller miibus0" required. See GENERIC if you get errors here. */
148 #include "miibus_if.h"
150 #include <dev/netif/re/if_rereg.h>
152 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
155 * Various supported device vendors/types and their names.
157 static struct re_type re_devs[] = {
158 { RT_VENDORID, RT_DEVICEID_8139, RE_HWREV_8139CPLUS,
159 "RealTek 8139C+ 10/100BaseTX" },
160 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8169,
161 "RealTek 8169 Gigabit Ethernet" },
162 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8169S,
163 "RealTek 8169S Single-chip Gigabit Ethernet" },
164 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8110S,
165 "RealTek 8110S Single-chip Gigabit Ethernet" },
169 static struct re_hwrev re_hwrevs[] = {
170 { RE_HWREV_8139CPLUS, RE_8139CPLUS, "C+"},
171 { RE_HWREV_8169, RE_8169, "8169"},
172 { RE_HWREV_8169S, RE_8169, "8169S"},
173 { RE_HWREV_8110S, RE_8169, "8110S"},
177 static int re_probe(device_t);
178 static int re_attach(device_t);
179 static int re_detach(device_t);
181 static int re_encap(struct re_softc *, struct mbuf *, int *);
183 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int);
184 static void re_dma_map_desc(void *, bus_dma_segment_t *, int,
186 static int re_allocmem(device_t, struct re_softc *);
187 static int re_newbuf(struct re_softc *, int, struct mbuf *);
188 static int re_rx_list_init(struct re_softc *);
189 static int re_tx_list_init(struct re_softc *);
190 static void re_rxeof(struct re_softc *);
191 static void re_txeof(struct re_softc *);
192 static void re_intr(void *);
193 static void re_tick(void *);
194 static void re_start(struct ifnet *);
195 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
196 static void re_init(void *);
197 static void re_stop(struct re_softc *);
198 static void re_watchdog(struct ifnet *);
199 static int re_suspend(device_t);
200 static int re_resume(device_t);
201 static void re_shutdown(device_t);
202 static int re_ifmedia_upd(struct ifnet *);
203 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
205 static void re_eeprom_putbyte(struct re_softc *, int);
206 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *);
207 static void re_read_eeprom(struct re_softc *, caddr_t, int, int, int);
208 static int re_gmii_readreg(device_t, int, int);
209 static int re_gmii_writereg(device_t, int, int, int);
211 static int re_miibus_readreg(device_t, int, int);
212 static int re_miibus_writereg(device_t, int, int, int);
213 static void re_miibus_statchg(device_t);
215 static void re_setmulti(struct re_softc *);
216 static void re_reset(struct re_softc *);
218 static int re_diag(struct re_softc *);
220 static device_method_t re_methods[] = {
221 /* Device interface */
222 DEVMETHOD(device_probe, re_probe),
223 DEVMETHOD(device_attach, re_attach),
224 DEVMETHOD(device_detach, re_detach),
225 DEVMETHOD(device_suspend, re_suspend),
226 DEVMETHOD(device_resume, re_resume),
227 DEVMETHOD(device_shutdown, re_shutdown),
230 DEVMETHOD(bus_print_child, bus_generic_print_child),
231 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
234 DEVMETHOD(miibus_readreg, re_miibus_readreg),
235 DEVMETHOD(miibus_writereg, re_miibus_writereg),
236 DEVMETHOD(miibus_statchg, re_miibus_statchg),
241 static driver_t re_driver = {
244 sizeof(struct re_softc)
247 static devclass_t re_devclass;
249 DECLARE_DUMMY_MODULE(if_re);
250 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0);
251 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0);
252 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
255 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
258 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
261 * Send a read command and address to the EEPROM, check for ACK.
264 re_eeprom_putbyte(struct re_softc *sc, int addr)
268 d = addr | sc->re_eecmd_read;
271 * Feed in each bit and strobe the clock.
273 for (i = 0x400; i != 0; i >>= 1) {
275 EE_SET(RE_EE_DATAIN);
277 EE_CLR(RE_EE_DATAIN);
287 * Read a word of data stored in the EEPROM at address 'addr.'
290 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
295 /* Enter EEPROM access mode. */
296 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL);
299 * Send address of word we want to read.
301 re_eeprom_putbyte(sc, addr);
303 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL);
306 * Start reading bits from EEPROM.
308 for (i = 0x8000; i != 0; i >>= 1) {
311 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
317 /* Turn off EEPROM access mode. */
318 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
324 * Read a sequence of words from the EEPROM.
327 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt, int swap)
330 uint16_t word = 0, *ptr;
332 for (i = 0; i < cnt; i++) {
333 re_eeprom_getword(sc, off + i, &word);
334 ptr = (u_int16_t *)(dest + (i * 2));
336 *ptr = be16toh(word);
343 re_gmii_readreg(device_t dev, int phy, int reg)
345 struct re_softc *sc = device_get_softc(dev);
352 /* Let the rgephy driver read the GMEDIASTAT register */
354 if (reg == RE_GMEDIASTAT)
355 return(CSR_READ_1(sc, RE_GMEDIASTAT));
357 CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
360 for (i = 0; i < RE_TIMEOUT; i++) {
361 rval = CSR_READ_4(sc, RE_PHYAR);
362 if (rval & RE_PHYAR_BUSY)
367 if (i == RE_TIMEOUT) {
368 device_printf(dev, "PHY read failed\n");
372 return(rval & RE_PHYAR_PHYDATA);
376 re_gmii_writereg(device_t dev, int phy, int reg, int data)
378 struct re_softc *sc = device_get_softc(dev);
382 CSR_WRITE_4(sc, RE_PHYAR,
383 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
386 for (i = 0; i < RE_TIMEOUT; i++) {
387 rval = CSR_READ_4(sc, RE_PHYAR);
388 if ((rval & RE_PHYAR_BUSY) == 0)
394 device_printf(dev, "PHY write failed\n");
400 re_miibus_readreg(device_t dev, int phy, int reg)
402 struct re_softc *sc = device_get_softc(dev);
404 uint16_t re8139_reg = 0;
406 if (sc->re_type == RE_8169) {
407 rval = re_gmii_readreg(dev, phy, reg);
411 /* Pretend the internal PHY is only at address 0 */
417 re8139_reg = RE_BMCR;
420 re8139_reg = RE_BMSR;
423 re8139_reg = RE_ANAR;
426 re8139_reg = RE_ANER;
429 re8139_reg = RE_LPAR;
435 * Allow the rlphy driver to read the media status
436 * register. If we have a link partner which does not
437 * support NWAY, this is the register which will tell
438 * us the results of parallel detection.
441 return(CSR_READ_1(sc, RE_MEDIASTAT));
443 device_printf(dev, "bad phy register\n");
446 rval = CSR_READ_2(sc, re8139_reg);
451 re_miibus_writereg(device_t dev, int phy, int reg, int data)
453 struct re_softc *sc= device_get_softc(dev);
454 u_int16_t re8139_reg = 0;
456 if (sc->re_type == RE_8169)
457 return(re_gmii_writereg(dev, phy, reg, data));
459 /* Pretend the internal PHY is only at address 0 */
465 re8139_reg = RE_BMCR;
468 re8139_reg = RE_BMSR;
471 re8139_reg = RE_ANAR;
474 re8139_reg = RE_ANER;
477 re8139_reg = RE_LPAR;
483 device_printf(dev, "bad phy register\n");
486 CSR_WRITE_2(sc, re8139_reg, data);
491 re_miibus_statchg(device_t dev)
496 * Program the 64-bit multicast hash filter.
499 re_setmulti(struct re_softc *sc)
501 struct ifnet *ifp = &sc->arpcom.ac_if;
503 uint32_t hashes[2] = { 0, 0 };
504 struct ifmultiaddr *ifma;
508 rxfilt = CSR_READ_4(sc, RE_RXCFG);
510 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
511 rxfilt |= RE_RXCFG_RX_MULTI;
512 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
513 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
514 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
518 /* first, zot all the existing hash bits */
519 CSR_WRITE_4(sc, RE_MAR0, 0);
520 CSR_WRITE_4(sc, RE_MAR4, 0);
522 /* now program new ones */
523 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
524 if (ifma->ifma_addr->sa_family != AF_LINK)
526 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
527 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
529 hashes[0] |= (1 << h);
531 hashes[1] |= (1 << (h - 32));
536 rxfilt |= RE_RXCFG_RX_MULTI;
538 rxfilt &= ~RE_RXCFG_RX_MULTI;
540 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
541 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
542 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
546 re_reset(struct re_softc *sc)
550 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
552 for (i = 0; i < RE_TIMEOUT; i++) {
554 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
558 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
560 CSR_WRITE_1(sc, 0x82, 1);
564 * The following routine is designed to test for a defect on some
565 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
566 * lines connected to the bus, however for a 32-bit only card, they
567 * should be pulled high. The result of this defect is that the
568 * NIC will not work right if you plug it into a 64-bit slot: DMA
569 * operations will be done with 64-bit transfers, which will fail
570 * because the 64-bit data lines aren't connected.
572 * There's no way to work around this (short of talking a soldering
573 * iron to the board), however we can detect it. The method we use
574 * here is to put the NIC into digital loopback mode, set the receiver
575 * to promiscuous mode, and then try to send a frame. We then compare
576 * the frame data we sent to what was received. If the data matches,
577 * then the NIC is working correctly, otherwise we know the user has
578 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
579 * slot. In the latter case, there's no way the NIC can work correctly,
580 * so we print out a message on the console and abort the device attach.
584 re_diag(struct re_softc *sc)
586 struct ifnet *ifp = &sc->arpcom.ac_if;
588 struct ether_header *eh;
589 struct re_desc *cur_rx;
592 int total_len, i, error = 0;
593 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
594 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
596 /* Allocate a single mbuf */
598 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
603 * Initialize the NIC in test mode. This sets the chip up
604 * so that it can send and receive frames, but performs the
605 * following special functions:
606 * - Puts receiver in promiscuous mode
607 * - Enables digital loopback mode
608 * - Leaves interrupts turned off
611 ifp->if_flags |= IFF_PROMISC;
618 /* Put some data in the mbuf */
620 eh = mtod(m0, struct ether_header *);
621 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
622 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
623 eh->ether_type = htons(ETHERTYPE_IP);
624 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
627 * Queue the packet, start transmission.
628 * Note: IF_HANDOFF() ultimately calls re_start() for us.
631 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
632 IF_HANDOFF(&ifp->if_snd, m0, ifp);
635 /* Wait for it to propagate through the chip */
638 for (i = 0; i < RE_TIMEOUT; i++) {
639 status = CSR_READ_2(sc, RE_ISR);
640 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
641 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
646 if (i == RE_TIMEOUT) {
647 if_printf(ifp, "diagnostic failed to receive packet "
648 "in loopback mode\n");
654 * The packet should have been dumped into the first
655 * entry in the RX DMA ring. Grab it from there.
658 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
659 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
660 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0],
661 BUS_DMASYNC_POSTWRITE);
662 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]);
664 m0 = sc->re_ldata.re_rx_mbuf[0];
665 sc->re_ldata.re_rx_mbuf[0] = NULL;
666 eh = mtod(m0, struct ether_header *);
668 cur_rx = &sc->re_ldata.re_rx_list[0];
669 total_len = RE_RXBYTES(cur_rx);
670 rxstat = le32toh(cur_rx->re_cmdstat);
672 if (total_len != ETHER_MIN_LEN) {
673 if_printf(ifp, "diagnostic failed, received short packet\n");
678 /* Test that the received packet data matches what we sent. */
680 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
681 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
682 be16toh(eh->ether_type) != ETHERTYPE_IP) {
683 if_printf(ifp, "WARNING, DMA FAILURE!\n");
684 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
685 dst, ":", src, ":", ETHERTYPE_IP);
686 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
687 eh->ether_dhost, ":", eh->ether_shost, ":",
688 ntohs(eh->ether_type));
689 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
690 "into a 64-bit PCI slot.\n");
691 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
692 "for proper operation.\n");
693 if_printf(ifp, "Read the re(4) man page for more details.\n");
698 /* Turn interface off, release resources */
701 ifp->if_flags &= ~IFF_PROMISC;
710 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
711 * IDs against our list and return a device name if we find a match.
714 re_probe(device_t dev)
720 uint16_t vendor, product;
724 vendor = pci_get_vendor(dev);
725 product = pci_get_device(dev);
727 for (t = re_devs; t->re_name != NULL; t++) {
728 if (product == t->re_did && vendor == t->re_vid)
733 * Check if we found a RealTek device.
735 if (t->re_name == NULL)
739 * Temporarily map the I/O space so we can read the chip ID register.
741 sc = malloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
743 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
745 if (sc->re_res == NULL) {
746 device_printf(dev, "couldn't map ports/memory\n");
751 sc->re_btag = rman_get_bustag(sc->re_res);
752 sc->re_bhandle = rman_get_bushandle(sc->re_res);
754 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
755 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
759 * and continue matching for the specific chip...
761 for (; t->re_name != NULL; t++) {
762 if (product == t->re_did && vendor == t->re_vid &&
763 t->re_basetype == hwrev) {
764 device_set_desc(dev, t->re_name);
772 * This routine takes the segment list provided as the result of
773 * a bus_dma_map_load() operation and assigns the addresses/lengths
774 * to RealTek DMA descriptors. This can be called either by the RX
775 * code or the TX code. In the RX case, we'll probably wind up mapping
776 * at most one segment. For the TX case, there could be any number of
777 * segments since TX packets may span multiple mbufs. In either case,
778 * if the number of segments is larger than the re_maxsegs limit
779 * specified by the caller, we abort the mapping operation. Sadly,
780 * whoever designed the buffer mapping API did not provide a way to
781 * return an error from here, so we have to fake it a bit.
785 re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg,
786 bus_size_t mapsize, int error)
788 struct re_dmaload_arg *ctx;
789 struct re_desc *d = NULL;
798 /* Signal error to caller if there's too many segments */
799 if (nseg > ctx->re_maxsegs) {
805 * Map the segment array into descriptors. Note that we set the
806 * start-of-frame and end-of-frame markers for either TX or RX, but
807 * they really only have meaning in the TX case. (In the RX case,
808 * it's the chip that tells us where packets begin and end.)
809 * We also keep track of the end of the ring and set the
810 * end-of-ring bits as needed, and we set the ownership bits
811 * in all except the very first descriptor. (The caller will
812 * set this descriptor later when it start transmission or
817 d = &ctx->re_ring[idx];
818 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) {
822 cmdstat = segs[i].ds_len;
823 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
824 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
826 cmdstat |= RE_TDESC_CMD_SOF;
828 cmdstat |= RE_TDESC_CMD_OWN;
829 if (idx == (RE_RX_DESC_CNT - 1))
830 cmdstat |= RE_TDESC_CMD_EOR;
831 d->re_cmdstat = htole32(cmdstat | ctx->re_flags);
838 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
839 ctx->re_maxsegs = nseg;
844 * Map a single buffer address.
848 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
855 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
857 *addr = segs->ds_addr;
861 re_allocmem(device_t dev, struct re_softc *sc)
866 * Allocate map for RX mbufs.
869 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0,
870 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
871 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
872 &sc->re_ldata.re_mtag);
874 device_printf(dev, "could not allocate dma tag\n");
879 * Allocate map for TX descriptor list.
881 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
882 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
883 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
884 &sc->re_ldata.re_tx_list_tag);
886 device_printf(dev, "could not allocate dma tag\n");
890 /* Allocate DMA'able memory for the TX ring */
892 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag,
893 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
894 &sc->re_ldata.re_tx_list_map);
896 device_printf(dev, "could not allocate TX ring\n");
900 /* Load the map for the TX ring. */
902 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag,
903 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list,
904 RE_TX_LIST_SZ, re_dma_map_addr,
905 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT);
907 device_printf(dev, "could not get addres of TX ring\n");
911 /* Create DMA maps for TX buffers */
913 for (i = 0; i < RE_TX_DESC_CNT; i++) {
914 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
915 &sc->re_ldata.re_tx_dmamap[i]);
917 device_printf(dev, "can't create DMA map for TX\n");
923 * Allocate map for RX descriptor list.
925 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
926 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
927 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
928 &sc->re_ldata.re_rx_list_tag);
930 device_printf(dev, "could not allocate dma tag\n");
934 /* Allocate DMA'able memory for the RX ring */
936 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag,
937 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
938 &sc->re_ldata.re_rx_list_map);
940 device_printf(dev, "could not allocate RX ring\n");
944 /* Load the map for the RX ring. */
946 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag,
947 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list,
948 RE_TX_LIST_SZ, re_dma_map_addr,
949 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT);
951 device_printf(dev, "could not get address of RX ring\n");
955 /* Create DMA maps for RX buffers */
957 for (i = 0; i < RE_RX_DESC_CNT; i++) {
958 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
959 &sc->re_ldata.re_rx_dmamap[i]);
961 device_printf(dev, "can't create DMA map for RX\n");
970 * Attach the interface. Allocate softc structures, do ifmedia
971 * setup and ethernet/BPF attach.
974 re_attach(device_t dev)
976 struct re_softc *sc = device_get_softc(dev);
978 struct re_hwrev *hw_rev;
979 uint8_t eaddr[ETHER_ADDR_LEN];
981 u_int16_t re_did = 0;
982 int error = 0, rid, i;
984 callout_init(&sc->re_timer);
988 * Handle power management nonsense.
991 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
992 uint32_t membase, irq;
994 /* Save important PCI config data. */
995 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
996 irq = pci_read_config(dev, PCIR_INTLINE, 4);
998 /* Reset the power state. */
999 device_printf(dev, "chip is is in D%d power mode "
1000 "-- setting to D0\n", pci_get_powerstate(dev));
1002 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1004 /* Restore PCI config data. */
1005 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1006 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1010 * Map control/status registers.
1012 pci_enable_busmaster(dev);
1015 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1018 if (sc->re_res == NULL) {
1019 device_printf(dev, "couldn't map ports/memory\n");
1024 sc->re_btag = rman_get_bustag(sc->re_res);
1025 sc->re_bhandle = rman_get_bushandle(sc->re_res);
1027 /* Allocate interrupt */
1029 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1030 RF_SHAREABLE | RF_ACTIVE);
1032 if (sc->re_irq == NULL) {
1033 device_printf(dev, "couldn't map interrupt\n");
1038 /* Reset the adapter. */
1041 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
1042 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) {
1043 if (hw_rev->re_rev == hwrev) {
1044 sc->re_type = hw_rev->re_type;
1049 if (sc->re_type == RE_8169) {
1050 /* Set RX length mask */
1051 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1053 /* Force station address autoload from the EEPROM */
1054 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_AUTOLOAD);
1055 for (i = 0; i < RE_TIMEOUT; i++) {
1056 if ((CSR_READ_1(sc, RE_EECMD) & RE_EEMODE_AUTOLOAD) == 0)
1060 if (i == RE_TIMEOUT)
1061 device_printf(dev, "eeprom autoload timed out\n");
1063 for (i = 0; i < ETHER_ADDR_LEN; i++)
1064 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i);
1068 /* Set RX length mask */
1069 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1071 sc->re_eecmd_read = RE_EECMD_READ_6BIT;
1072 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0);
1073 if (re_did != 0x8129)
1074 sc->re_eecmd_read = RE_EECMD_READ_8BIT;
1077 * Get station address from the EEPROM.
1079 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3, 0);
1080 for (i = 0; i < 3; i++) {
1081 eaddr[(i * 2) + 0] = as[i] & 0xff;
1082 eaddr[(i * 2) + 1] = as[i] >> 8;
1087 * Allocate the parent bus DMA tag appropriate for PCI.
1089 #define RE_NSEG_NEW 32
1090 error = bus_dma_tag_create(NULL, /* parent */
1091 1, 0, /* alignment, boundary */
1092 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1093 BUS_SPACE_MAXADDR, /* highaddr */
1094 NULL, NULL, /* filter, filterarg */
1095 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */
1096 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1097 BUS_DMA_ALLOCNOW, /* flags */
1098 &sc->re_parent_tag);
1102 error = re_allocmem(dev, sc);
1108 if (mii_phy_probe(dev, &sc->re_miibus,
1109 re_ifmedia_upd, re_ifmedia_sts)) {
1110 device_printf(dev, "MII without any phy!\n");
1115 ifp = &sc->arpcom.ac_if;
1117 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1118 ifp->if_mtu = ETHERMTU;
1119 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1120 ifp->if_ioctl = re_ioctl;
1121 ifp->if_capabilities = IFCAP_VLAN_MTU;
1122 ifp->if_start = re_start;
1123 ifp->if_hwassist = RE_CSUM_FEATURES;
1124 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1125 #ifdef DEVICE_POLLING
1126 ifp->if_capabilities |= IFCAP_POLLING;
1128 ifp->if_watchdog = re_watchdog;
1129 ifp->if_init = re_init;
1130 if (sc->re_type == RE_8169)
1131 ifp->if_baudrate = 1000000000;
1133 ifp->if_baudrate = 100000000;
1134 ifp->if_snd.ifq_maxlen = RE_IFQ_MAXLEN;
1135 ifp->if_capenable = ifp->if_capabilities;
1138 * Call MI attach routine.
1140 ether_ifattach(ifp, eaddr);
1142 /* Perform hardware diagnostic. */
1143 error = re_diag(sc);
1146 device_printf(dev, "hardware diagnostic failure\n");
1147 ether_ifdetach(ifp);
1151 /* Hook interrupt last to avoid having to lock softc */
1152 error = bus_setup_intr(dev, sc->re_irq, INTR_TYPE_NET, re_intr, sc,
1156 device_printf(dev, "couldn't set up irq\n");
1157 ether_ifdetach(ifp);
1169 * Shutdown hardware and free up resources. This can be called any
1170 * time after the mutex has been initialized. It is called in both
1171 * the error case in attach and the normal detach case so it needs
1172 * to be careful about only freeing resources that have actually been
1176 re_detach(device_t dev)
1178 struct re_softc *sc = device_get_softc(dev);
1179 struct ifnet *ifp = &sc->arpcom.ac_if;
1184 /* These should only be active if attach succeeded */
1185 if (device_is_attached(dev)) {
1187 ether_ifdetach(ifp);
1190 device_delete_child(dev, sc->re_miibus);
1191 bus_generic_detach(dev);
1193 if (sc->re_intrhand)
1194 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1196 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
1198 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1201 /* Unload and free the RX DMA ring memory and map */
1203 if (sc->re_ldata.re_rx_list_tag) {
1204 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1205 sc->re_ldata.re_rx_list_map);
1206 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1207 sc->re_ldata.re_rx_list,
1208 sc->re_ldata.re_rx_list_map);
1209 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1212 /* Unload and free the TX DMA ring memory and map */
1214 if (sc->re_ldata.re_tx_list_tag) {
1215 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1216 sc->re_ldata.re_tx_list_map);
1217 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1218 sc->re_ldata.re_tx_list,
1219 sc->re_ldata.re_tx_list_map);
1220 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1223 /* Destroy all the RX and TX buffer maps */
1225 if (sc->re_ldata.re_mtag) {
1226 for (i = 0; i < RE_TX_DESC_CNT; i++)
1227 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1228 sc->re_ldata.re_tx_dmamap[i]);
1229 for (i = 0; i < RE_RX_DESC_CNT; i++)
1230 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1231 sc->re_ldata.re_rx_dmamap[i]);
1232 bus_dma_tag_destroy(sc->re_ldata.re_mtag);
1235 /* Unload and free the stats buffer and map */
1237 if (sc->re_ldata.re_stag) {
1238 bus_dmamap_unload(sc->re_ldata.re_stag,
1239 sc->re_ldata.re_rx_list_map);
1240 bus_dmamem_free(sc->re_ldata.re_stag,
1241 sc->re_ldata.re_stats,
1242 sc->re_ldata.re_smap);
1243 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1246 if (sc->re_parent_tag)
1247 bus_dma_tag_destroy(sc->re_parent_tag);
1255 re_newbuf(struct re_softc *sc, int idx, struct mbuf *m)
1257 struct re_dmaload_arg arg;
1258 struct mbuf *n = NULL;
1262 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1267 m->m_data = m->m_ext.ext_buf;
1270 * Initialize mbuf length fields and fixup
1271 * alignment so that the frame payload is
1274 m->m_len = m->m_pkthdr.len = MCLBYTES;
1275 m_adj(m, ETHER_ALIGN);
1281 arg.re_ring = sc->re_ldata.re_rx_list;
1283 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag,
1284 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc,
1285 &arg, BUS_DMA_NOWAIT);
1286 if (error || arg.re_maxsegs != 1) {
1292 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN);
1293 sc->re_ldata.re_rx_mbuf[idx] = m;
1295 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx],
1296 BUS_DMASYNC_PREREAD);
1302 re_tx_list_init(struct re_softc *sc)
1304 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ);
1305 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *));
1307 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1308 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
1309 sc->re_ldata.re_tx_prodidx = 0;
1310 sc->re_ldata.re_tx_considx = 0;
1311 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT;
1317 re_rx_list_init(struct re_softc *sc)
1321 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ);
1322 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *));
1324 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1325 error = re_newbuf(sc, i, NULL);
1330 /* Flush the RX descriptors */
1332 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1333 sc->re_ldata.re_rx_list_map,
1334 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1336 sc->re_ldata.re_rx_prodidx = 0;
1337 sc->re_head = sc->re_tail = NULL;
1343 * RX handler for C+ and 8169. For the gigE chips, we support
1344 * the reception of jumbo frames that have been fragmented
1345 * across multiple 2K mbuf cluster buffers.
1348 re_rxeof(struct re_softc *sc)
1350 struct ifnet *ifp = &sc->arpcom.ac_if;
1352 struct re_desc *cur_rx;
1353 uint32_t rxstat, rxvlan;
1356 /* Invalidate the descriptor memory */
1358 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1359 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
1361 for (i = sc->re_ldata.re_rx_prodidx;
1362 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) {
1363 cur_rx = &sc->re_ldata.re_rx_list[i];
1364 m = sc->re_ldata.re_rx_mbuf[i];
1365 total_len = RE_RXBYTES(cur_rx);
1366 rxstat = le32toh(cur_rx->re_cmdstat);
1367 rxvlan = le32toh(cur_rx->re_vlanctl);
1369 /* Invalidate the RX mbuf and unload its map */
1371 bus_dmamap_sync(sc->re_ldata.re_mtag,
1372 sc->re_ldata.re_rx_dmamap[i],
1373 BUS_DMASYNC_POSTWRITE);
1374 bus_dmamap_unload(sc->re_ldata.re_mtag,
1375 sc->re_ldata.re_rx_dmamap[i]);
1377 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1378 m->m_len = MCLBYTES - ETHER_ALIGN;
1379 if (sc->re_head == NULL) {
1380 sc->re_head = sc->re_tail = m;
1382 m->m_flags &= ~M_PKTHDR;
1383 sc->re_tail->m_next = m;
1386 re_newbuf(sc, i, NULL);
1391 * NOTE: for the 8139C+, the frame length field
1392 * is always 12 bits in size, but for the gigE chips,
1393 * it is 13 bits (since the max RX frame length is 16K).
1394 * Unfortunately, all 32 bits in the status word
1395 * were already used, so to make room for the extra
1396 * length bit, RealTek took out the 'frame alignment
1397 * error' bit and shifted the other status bits
1398 * over one slot. The OWN, EOR, FS and LS bits are
1399 * still in the same places. We have already extracted
1400 * the frame length and checked the OWN bit, so rather
1401 * than using an alternate bit mapping, we shift the
1402 * status bits one space to the right so we can evaluate
1403 * them using the 8169 status as though it was in the
1404 * same format as that of the 8139C+.
1406 if (sc->re_type == RE_8169)
1409 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1412 * If this is part of a multi-fragment packet,
1413 * discard all the pieces.
1415 if (sc->re_head != NULL) {
1416 m_freem(sc->re_head);
1417 sc->re_head = sc->re_tail = NULL;
1419 re_newbuf(sc, i, m);
1424 * If allocating a replacement mbuf fails,
1425 * reload the current one.
1428 if (re_newbuf(sc, i, NULL)) {
1430 if (sc->re_head != NULL) {
1431 m_freem(sc->re_head);
1432 sc->re_head = sc->re_tail = NULL;
1434 re_newbuf(sc, i, m);
1438 if (sc->re_head != NULL) {
1439 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN);
1441 * Special case: if there's 4 bytes or less
1442 * in this buffer, the mbuf can be discarded:
1443 * the last 4 bytes is the CRC, which we don't
1444 * care about anyway.
1446 if (m->m_len <= ETHER_CRC_LEN) {
1447 sc->re_tail->m_len -=
1448 (ETHER_CRC_LEN - m->m_len);
1451 m->m_len -= ETHER_CRC_LEN;
1452 m->m_flags &= ~M_PKTHDR;
1453 sc->re_tail->m_next = m;
1456 sc->re_head = sc->re_tail = NULL;
1457 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1459 m->m_pkthdr.len = m->m_len =
1460 (total_len - ETHER_CRC_LEN);
1463 m->m_pkthdr.rcvif = ifp;
1465 /* Do RX checksumming if enabled */
1467 if (ifp->if_capenable & IFCAP_RXCSUM) {
1469 /* Check IP header checksum */
1470 if (rxstat & RE_RDESC_STAT_PROTOID)
1471 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1472 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
1473 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1475 /* Check TCP/UDP checksum */
1476 if ((RE_TCPPKT(rxstat) &&
1477 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
1478 (RE_UDPPKT(rxstat) &&
1479 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) {
1480 m->m_pkthdr.csum_flags |=
1481 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1482 m->m_pkthdr.csum_data = 0xffff;
1486 if (rxvlan & RE_RDESC_VLANCTL_TAG)
1488 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA)));
1490 (*ifp->if_input)(ifp, m);
1493 /* Flush the RX DMA ring */
1495 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1496 sc->re_ldata.re_rx_list_map,
1497 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1499 sc->re_ldata.re_rx_prodidx = i;
1503 re_txeof(struct re_softc *sc)
1505 struct ifnet *ifp = &sc->arpcom.ac_if;
1509 /* Invalidate the TX descriptor list */
1511 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1512 sc->re_ldata.re_tx_list_map,
1513 BUS_DMASYNC_POSTREAD);
1515 for (idx = sc->re_ldata.re_tx_considx;
1516 idx != sc->re_ldata.re_tx_prodidx; RE_DESC_INC(idx)) {
1517 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
1518 if (txstat & RE_TDESC_CMD_OWN)
1522 * We only stash mbufs in the last descriptor
1523 * in a fragment chain, which also happens to
1524 * be the only place where the TX status bits
1527 if (txstat & RE_TDESC_CMD_EOF) {
1528 m_freem(sc->re_ldata.re_tx_mbuf[idx]);
1529 sc->re_ldata.re_tx_mbuf[idx] = NULL;
1530 bus_dmamap_unload(sc->re_ldata.re_mtag,
1531 sc->re_ldata.re_tx_dmamap[idx]);
1532 if (txstat & (RE_TDESC_STAT_EXCESSCOL|
1533 RE_TDESC_STAT_COLCNT))
1534 ifp->if_collisions++;
1535 if (txstat & RE_TDESC_STAT_TXERRSUM)
1540 sc->re_ldata.re_tx_free++;
1543 /* No changes made to the TX ring, so no flush needed */
1544 if (idx != sc->re_ldata.re_tx_considx) {
1545 sc->re_ldata.re_tx_considx = idx;
1546 ifp->if_flags &= ~IFF_OACTIVE;
1551 * If not all descriptors have been released reaped yet,
1552 * reload the timer so that we will eventually get another
1553 * interrupt that will cause us to re-enter this routine.
1554 * This is done in case the transmitter has gone idle.
1556 if (sc->re_ldata.re_tx_free != RE_TX_DESC_CNT)
1557 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1563 struct re_softc *sc = xsc;
1564 struct mii_data *mii;
1569 mii = device_get_softc(sc->re_miibus);
1572 callout_reset(&sc->re_timer, hz, re_tick, sc);
1576 #ifdef DEVICE_POLLING
1578 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1580 struct re_softc *sc = ifp->if_softc;
1582 if ((ifp->if_capenable & IFCAP_POLLING) == 0) {
1583 ether_poll_deregister(ifp);
1584 cmd = POLL_DEREGISTER;
1586 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1587 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS);
1591 sc->rxcycles = count;
1595 if (ifp->if_snd.ifq_head != NULL)
1596 (*ifp->if_start)(ifp);
1598 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1601 status = CSR_READ_2(sc, RE_ISR);
1602 if (status == 0xffff)
1605 CSR_WRITE_2(sc, RE_ISR, status);
1608 * XXX check behaviour on receiver stalls.
1611 if (status & RE_ISR_SYSTEM_ERR) {
1617 #endif /* DEVICE_POLLING */
1622 struct re_softc *sc = arg;
1623 struct ifnet *ifp = &sc->arpcom.ac_if;
1627 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0)
1630 #ifdef DEVICE_POLLING
1631 if (ifp->if_flags & IFF_POLLING)
1633 if ((ifp->if_capenable & IFCAP_POLLING) &&
1634 ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */
1635 CSR_WRITE_2(sc, RE_IMR, 0x0000);
1639 #endif /* DEVICE_POLLING */
1644 status = CSR_READ_2(sc, RE_ISR);
1645 /* If the card has gone away the read returns 0xffff. */
1646 if (status == 0xffff)
1649 CSR_WRITE_2(sc, RE_ISR, status);
1651 if ((status & RE_INTRS_CPLUS) == 0)
1654 if (status & RE_ISR_RX_OK)
1657 if (status & RE_ISR_RX_ERR)
1660 if ((status & RE_ISR_TIMEOUT_EXPIRED) ||
1661 (status & RE_ISR_TX_ERR) ||
1662 (status & RE_ISR_TX_DESC_UNAVAIL))
1665 if (status & RE_ISR_SYSTEM_ERR) {
1670 if (status & RE_ISR_LINKCHG)
1674 if (ifp->if_snd.ifq_head != NULL)
1675 (*ifp->if_start)(ifp);
1681 re_encap(sc, m_head, idx)
1682 struct re_softc *sc;
1683 struct mbuf *m_head;
1686 struct ifnet *ifp = &sc->arpcom.ac_if;
1687 struct mbuf *m_new = NULL;
1688 struct re_dmaload_arg arg;
1692 if (sc->re_ldata.re_tx_free <= 4)
1696 * Set up checksum offload. Note: checksum offload bits must
1697 * appear in all descriptors of a multi-descriptor transmit
1698 * attempt. (This is according to testing done with an 8169
1699 * chip. I'm not sure if this is a requirement or a bug.)
1704 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1705 arg.re_flags |= RE_TDESC_CMD_IPCSUM;
1706 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
1707 arg.re_flags |= RE_TDESC_CMD_TCPCSUM;
1708 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
1709 arg.re_flags |= RE_TDESC_CMD_UDPCSUM;
1713 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1714 if (arg.re_maxsegs > 4)
1715 arg.re_maxsegs -= 4;
1716 arg.re_ring = sc->re_ldata.re_tx_list;
1718 map = sc->re_ldata.re_tx_dmamap[*idx];
1719 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1720 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1722 if (error && error != EFBIG) {
1723 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1727 /* Too many segments to map, coalesce into a single mbuf */
1729 if (error || arg.re_maxsegs == 0) {
1730 m_new = m_defrag(m_head, MB_DONTWAIT);
1738 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1739 arg.re_ring = sc->re_ldata.re_tx_list;
1741 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1742 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1744 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1750 * Insure that the map for this transmission
1751 * is placed at the array index of the last descriptor
1754 sc->re_ldata.re_tx_dmamap[*idx] =
1755 sc->re_ldata.re_tx_dmamap[arg.re_idx];
1756 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map;
1758 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m_head;
1759 sc->re_ldata.re_tx_free -= arg.re_maxsegs;
1762 * Set up hardware VLAN tagging. Note: vlan tag info must
1763 * appear in the first descriptor of a multi-descriptor
1764 * transmission attempt.
1767 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1768 m_head->m_pkthdr.rcvif != NULL &&
1769 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) {
1771 ifv = m_head->m_pkthdr.rcvif->if_softc;
1773 sc->re_ldata.re_tx_list[*idx].re_vlanctl =
1774 htole32(htobe16(ifv->ifv_tag) | RE_TDESC_VLANCTL_TAG);
1777 /* Transfer ownership of packet to the chip. */
1779 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |=
1780 htole32(RE_TDESC_CMD_OWN);
1781 if (*idx != arg.re_idx)
1782 sc->re_ldata.re_tx_list[*idx].re_cmdstat |=
1783 htole32(RE_TDESC_CMD_OWN);
1785 RE_DESC_INC(arg.re_idx);
1792 * Main transmit routine for C+ and gigE NICs.
1796 re_start(struct ifnet *ifp)
1798 struct re_softc *sc = ifp->if_softc;
1799 struct mbuf *m_head = NULL;
1804 idx = sc->re_ldata.re_tx_prodidx;
1806 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
1807 IF_DEQUEUE(&ifp->if_snd, m_head);
1811 if (re_encap(sc, m_head, &idx)) {
1812 IF_PREPEND(&ifp->if_snd, m_head);
1813 ifp->if_flags |= IFF_OACTIVE;
1818 * If there's a BPF listener, bounce a copy of this frame
1821 BPF_MTAP(ifp, m_head);
1824 /* Flush the TX descriptors */
1825 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1826 sc->re_ldata.re_tx_list_map,
1827 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1829 sc->re_ldata.re_tx_prodidx = idx;
1832 * RealTek put the TX poll request register in a different
1833 * location on the 8169 gigE chip. I don't know why.
1835 if (sc->re_type == RE_8169)
1836 CSR_WRITE_2(sc, RE_GTXSTART, RE_TXSTART_START);
1838 CSR_WRITE_2(sc, RE_TXSTART, RE_TXSTART_START);
1841 * Use the countdown timer for interrupt moderation.
1842 * 'TX done' interrupts are disabled. Instead, we reset the
1843 * countdown timer, which will begin counting until it hits
1844 * the value in the TIMERINT register, and then trigger an
1845 * interrupt. Each time we write to the TIMERCNT register,
1846 * the timer count is reset to 0.
1848 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1853 * Set a timeout in case the chip goes out to lunch.
1861 struct re_softc *sc = xsc;
1862 struct ifnet *ifp = &sc->arpcom.ac_if;
1863 struct mii_data *mii;
1868 mii = device_get_softc(sc->re_miibus);
1871 * Cancel pending I/O and free all RX/TX buffers.
1876 * Enable C+ RX and TX mode, as well as VLAN stripping and
1877 * RX checksum offload. We must configure the C+ register
1878 * before all others.
1880 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
1881 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP |
1882 (ifp->if_capenable & IFCAP_RXCSUM ?
1883 RE_CPLUSCMD_RXCSUM_ENB : 0));
1886 * Init our MAC address. Even though the chipset
1887 * documentation doesn't mention it, we need to enter "Config
1888 * register write enable" mode to modify the ID registers.
1890 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
1891 CSR_WRITE_STREAM_4(sc, RE_IDR0,
1892 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1893 CSR_WRITE_STREAM_4(sc, RE_IDR4,
1894 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1895 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
1898 * For C+ mode, initialize the RX descriptors and mbufs.
1900 re_rx_list_init(sc);
1901 re_tx_list_init(sc);
1904 * Enable transmit and receive.
1906 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
1909 * Set the initial TX and RX configuration.
1911 if (sc->re_testmode) {
1912 if (sc->re_type == RE_8169)
1913 CSR_WRITE_4(sc, RE_TXCFG,
1914 RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
1916 CSR_WRITE_4(sc, RE_TXCFG,
1917 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
1919 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
1920 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
1922 /* Set the individual bit to receive frames for this host only. */
1923 rxcfg = CSR_READ_4(sc, RE_RXCFG);
1924 rxcfg |= RE_RXCFG_RX_INDIV;
1926 /* If we want promiscuous mode, set the allframes bit. */
1927 if (ifp->if_flags & IFF_PROMISC) {
1928 rxcfg |= RE_RXCFG_RX_ALLPHYS;
1929 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1931 rxcfg &= ~RE_RXCFG_RX_ALLPHYS;
1932 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1936 * Set capture broadcast bit to capture broadcast frames.
1938 if (ifp->if_flags & IFF_BROADCAST) {
1939 rxcfg |= RE_RXCFG_RX_BROAD;
1940 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1942 rxcfg &= ~RE_RXCFG_RX_BROAD;
1943 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1947 * Program the multicast filter, if necessary.
1951 #ifdef DEVICE_POLLING
1953 * Disable interrupts if we are polling.
1955 if (ifp->if_flags & IFF_POLLING)
1956 CSR_WRITE_2(sc, RE_IMR, 0);
1957 else /* otherwise ... */
1958 #endif /* DEVICE_POLLING */
1960 * Enable interrupts.
1962 if (sc->re_testmode)
1963 CSR_WRITE_2(sc, RE_IMR, 0);
1965 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS);
1967 /* Set initial TX threshold */
1968 sc->re_txthresh = RE_TX_THRESH_INIT;
1970 /* Start RX/TX process. */
1971 CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
1973 /* Enable receiver and transmitter. */
1974 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
1977 * Load the addresses of the RX and TX lists into the chip.
1980 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
1981 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
1982 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
1983 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
1985 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
1986 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
1987 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
1988 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
1990 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16);
1993 * Initialize the timer interrupt register so that
1994 * a timer interrupt will be generated once the timer
1995 * reaches a certain number of ticks. The timer is
1996 * reloaded on each transmit. This gives us TX interrupt
1997 * moderation, which dramatically improves TX frame rate.
2000 if (sc->re_type == RE_8169)
2001 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800);
2003 CSR_WRITE_4(sc, RE_TIMERINT, 0x400);
2006 * For 8169 gigE NICs, set the max allowed RX packet
2007 * size so we can receive jumbo frames.
2009 if (sc->re_type == RE_8169)
2010 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2012 if (sc->re_testmode) {
2019 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2021 ifp->if_flags |= IFF_RUNNING;
2022 ifp->if_flags &= ~IFF_OACTIVE;
2024 callout_reset(&sc->re_timer, hz, re_tick, sc);
2029 * Set media options.
2032 re_ifmedia_upd(struct ifnet *ifp)
2034 struct re_softc *sc = ifp->if_softc;
2035 struct mii_data *mii;
2037 mii = device_get_softc(sc->re_miibus);
2044 * Report current media status.
2047 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2049 struct re_softc *sc = ifp->if_softc;
2050 struct mii_data *mii;
2052 mii = device_get_softc(sc->re_miibus);
2055 ifmr->ifm_active = mii->mii_media_active;
2056 ifmr->ifm_status = mii->mii_media_status;
2060 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2062 struct re_softc *sc = ifp->if_softc;
2063 struct ifreq *ifr = (struct ifreq *) data;
2064 struct mii_data *mii;
2071 if (ifr->ifr_mtu > RE_JUMBO_MTU)
2073 ifp->if_mtu = ifr->ifr_mtu;
2076 if (ifp->if_flags & IFF_UP)
2078 else if (ifp->if_flags & IFF_RUNNING)
2089 mii = device_get_softc(sc->re_miibus);
2090 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2093 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING);
2094 ifp->if_capenable |=
2095 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING);
2096 if (ifp->if_capenable & IFCAP_TXCSUM)
2097 ifp->if_hwassist = RE_CSUM_FEATURES;
2099 ifp->if_hwassist = 0;
2100 if (ifp->if_flags & IFF_RUNNING)
2104 error = ether_ioctl(ifp, command, data);
2114 re_watchdog(struct ifnet *ifp)
2116 struct re_softc *sc = ifp->if_softc;
2120 if_printf(ifp, "watchdog timeout\n");
2132 * Stop the adapter and free any mbufs allocated to the
2136 re_stop(struct re_softc *sc)
2138 struct ifnet *ifp = &sc->arpcom.ac_if;
2143 callout_stop(&sc->re_timer);
2145 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2146 #ifdef DEVICE_POLLING
2147 ether_poll_deregister(ifp);
2148 #endif /* DEVICE_POLLING */
2150 CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2151 CSR_WRITE_2(sc, RE_IMR, 0x0000);
2153 if (sc->re_head != NULL) {
2154 m_freem(sc->re_head);
2155 sc->re_head = sc->re_tail = NULL;
2158 /* Free the TX list buffers. */
2159 for (i = 0; i < RE_TX_DESC_CNT; i++) {
2160 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2161 bus_dmamap_unload(sc->re_ldata.re_mtag,
2162 sc->re_ldata.re_tx_dmamap[i]);
2163 m_freem(sc->re_ldata.re_tx_mbuf[i]);
2164 sc->re_ldata.re_tx_mbuf[i] = NULL;
2168 /* Free the RX list buffers. */
2169 for (i = 0; i < RE_RX_DESC_CNT; i++) {
2170 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2171 bus_dmamap_unload(sc->re_ldata.re_mtag,
2172 sc->re_ldata.re_rx_dmamap[i]);
2173 m_freem(sc->re_ldata.re_rx_mbuf[i]);
2174 sc->re_ldata.re_rx_mbuf[i] = NULL;
2182 * Device suspend routine. Stop the interface and save some PCI
2183 * settings in case the BIOS doesn't restore them properly on
2187 re_suspend(device_t dev)
2189 #ifndef BURN_BRIDGES
2192 struct re_softc *sc = device_get_softc(dev);
2196 #ifndef BURN_BRIDGES
2197 for (i = 0; i < 5; i++)
2198 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2199 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2200 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2201 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2202 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2211 * Device resume routine. Restore some PCI settings in case the BIOS
2212 * doesn't, re-enable busmastering, and restart the interface if
2216 re_resume(device_t dev)
2218 struct re_softc *sc = device_get_softc(dev);
2219 struct ifnet *ifp = &sc->arpcom.ac_if;
2220 #ifndef BURN_BRIDGES
2224 #ifndef BURN_BRIDGES
2225 /* better way to do this? */
2226 for (i = 0; i < 5; i++)
2227 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2228 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2229 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2230 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2231 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2233 /* reenable busmastering */
2234 pci_enable_busmaster(dev);
2235 pci_enable_io(dev, SYS_RES_IOPORT);
2238 /* reinitialize interface if necessary */
2239 if (ifp->if_flags & IFF_UP)
2248 * Stop all chip I/O so that the kernel's probe routines don't
2249 * get confused by errant DMAs when rebooting.
2252 re_shutdown(device_t dev)
2254 struct re_softc *sc = device_get_softc(dev);