1 /******************************************************************************
3 * Name: actbl2.h - ACPI Specification Revision 2.0 Tables
6 *****************************************************************************/
8 /******************************************************************************
12 * Some or all of this work - Copyright (c) 1999 - 2003, Intel Corp.
13 * All rights reserved.
17 * 2.1. This is your license from Intel Corp. under its intellectual property
18 * rights. You may have additional license terms from the party that provided
19 * you this software, covering your right to use that party's intellectual
22 * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a
23 * copy of the source code appearing in this file ("Covered Code") an
24 * irrevocable, perpetual, worldwide license under Intel's copyrights in the
25 * base code distributed originally by Intel ("Original Intel Code") to copy,
26 * make derivatives, distribute, use and display any portion of the Covered
27 * Code in any form, with the right to sublicense such rights; and
29 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
30 * license (with the right to sublicense), under only those claims of Intel
31 * patents that are infringed by the Original Intel Code, to make, use, sell,
32 * offer to sell, and import the Covered Code and derivative works thereof
33 * solely to the minimum extent necessary to exercise the above copyright
34 * license, and in no event shall the patent license extend to any additions
35 * to or modifications of the Original Intel Code. No other license or right
36 * is granted directly or by implication, estoppel or otherwise;
38 * The above copyright and patent license is granted only if the following
43 * 3.1. Redistribution of Source with Rights to Further Distribute Source.
44 * Redistribution of source code of any substantial portion of the Covered
45 * Code or modification with rights to further distribute source must include
46 * the above Copyright Notice, the above License, this list of Conditions,
47 * and the following Disclaimer and Export Compliance provision. In addition,
48 * Licensee must cause all Covered Code to which Licensee contributes to
49 * contain a file documenting the changes Licensee made to create that Covered
50 * Code and the date of any change. Licensee must include in that file the
51 * documentation of any changes made by any predecessor Licensee. Licensee
52 * must include a prominent statement that the modification is derived,
53 * directly or indirectly, from Original Intel Code.
55 * 3.2. Redistribution of Source with no Rights to Further Distribute Source.
56 * Redistribution of source code of any substantial portion of the Covered
57 * Code or modification without rights to further distribute source must
58 * include the following Disclaimer and Export Compliance provision in the
59 * documentation and/or other materials provided with distribution. In
60 * addition, Licensee may not authorize further sublicense of source of any
61 * portion of the Covered Code, and must include terms to the effect that the
62 * license from Licensee to its licensee is limited to the intellectual
63 * property embodied in the software Licensee provides to its licensee, and
64 * not to intellectual property embodied in modifications its licensee may
67 * 3.3. Redistribution of Executable. Redistribution in executable form of any
68 * substantial portion of the Covered Code or modification must reproduce the
69 * above Copyright Notice, and the following Disclaimer and Export Compliance
70 * provision in the documentation and/or other materials provided with the
73 * 3.4. Intel retains all right, title, and interest in and to the Original
76 * 3.5. Neither the name Intel nor any other trademark owned or controlled by
77 * Intel shall be used in advertising or otherwise to promote the sale, use or
78 * other dealings in products derived from or relating to the Covered Code
79 * without prior written authorization from Intel.
81 * 4. Disclaimer and Export Compliance
83 * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED
84 * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE
85 * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE,
86 * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY
87 * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY
88 * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A
91 * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES
92 * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR
93 * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT,
94 * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY
95 * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL
96 * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS
97 * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY
100 * 4.3. Licensee shall not export, either directly or indirectly, any of this
101 * software or system incorporating such software without first obtaining any
102 * required license or other approval from the U. S. Department of Commerce or
103 * any other agency or department of the United States Government. In the
104 * event Licensee exports any such software from the United States or
105 * re-exports any such software from a foreign destination, Licensee shall
106 * ensure that the distribution and export/re-export of the software is in
107 * compliance with all laws, regulations, orders, or other restrictions of the
108 * U.S. Export Administration Regulations. Licensee agrees that neither it nor
109 * any of its subsidiaries will export/re-export any technical data, process,
110 * software, or service, directly or indirectly, to any country for which the
111 * United States government or any agency thereof requires an export license,
112 * other governmental approval, or letter of assurance, without first obtaining
113 * such license, approval or letter.
115 *****************************************************************************/
116 /* $DragonFly: src/sys/contrib/dev/acpica/Attic/actbl2.h,v 1.1 2003/09/24 03:32:15 drhodus Exp $ */
122 * Prefered Power Management Profiles
124 #define PM_UNSPECIFIED 0
127 #define PM_WORKSTATION 3
128 #define PM_ENTERPRISE_SERVER 4
129 #define PM_SOHO_SERVER 5
130 #define PM_APPLIANCE_PC 6
133 * ACPI Boot Arch Flags
135 #define BAF_LEGACY_DEVICES 0x0001
136 #define BAF_8042_KEYBOARD_CONTROLLER 0x0002
138 #define FADT2_REVISION_ID 3
144 * ACPI 2.0 Root System Description Table (RSDT)
146 typedef struct rsdt_descriptor_rev2
148 ACPI_TABLE_HEADER Header; /* ACPI table header */
149 UINT32 TableOffsetEntry [1]; /* Array of pointers to */
150 /* ACPI table headers */
151 } RSDT_DESCRIPTOR_REV2;
155 * ACPI 2.0 Extended System Description Table (XSDT)
157 typedef struct xsdt_descriptor_rev2
159 ACPI_TABLE_HEADER Header; /* ACPI table header */
160 UINT64 TableOffsetEntry [1]; /* Array of pointers to */
161 /* ACPI table headers */
162 } XSDT_DESCRIPTOR_REV2;
166 * ACPI 2.0 Firmware ACPI Control Structure (FACS)
168 typedef struct facs_descriptor_rev2
170 char Signature[4]; /* ACPI signature */
171 UINT32 Length; /* Length of structure, in bytes */
172 UINT32 HardwareSignature; /* Hardware configuration signature */
173 UINT32 FirmwareWakingVector; /* 32bit physical address of the Firmware Waking Vector. */
174 UINT32 GlobalLock; /* Global Lock used to synchronize access to shared hardware resources */
175 UINT32 S4Bios_f : 1; /* S4Bios_f - Indicates if S4BIOS support is present */
176 UINT32_BIT Reserved1 : 31; /* Must be 0 */
177 UINT64 XFirmwareWakingVector; /* 64bit physical address of the Firmware Waking Vector. */
178 UINT8 Version; /* Version of this table */
179 UINT8 Reserved3 [31]; /* Reserved - must be zero */
181 } FACS_DESCRIPTOR_REV2;
185 * ACPI 2.0 Generic Address Structure (GAS)
187 typedef struct acpi_generic_address
189 UINT8 AddressSpaceId; /* Address space where struct or register exists. */
190 UINT8 RegisterBitWidth; /* Size in bits of given register */
191 UINT8 RegisterBitOffset; /* Bit offset within the register */
192 UINT8 Reserved; /* Must be 0 */
193 UINT64 Address; /* 64-bit address of struct or register */
195 } ACPI_GENERIC_ADDRESS;
199 * ACPI 2.0 Fixed ACPI Description Table (FADT)
201 typedef struct fadt_descriptor_rev2
203 ACPI_TABLE_HEADER Header; /* ACPI table header */
204 UINT32 V1_FirmwareCtrl; /* 32-bit physical address of FACS */
205 UINT32 V1_Dsdt; /* 32-bit physical address of DSDT */
206 UINT8 Reserved1; /* System Interrupt Model isn't used in ACPI 2.0*/
207 UINT8 Prefer_PM_Profile; /* Conveys preferred power management profile to OSPM. */
208 UINT16 SciInt; /* System vector of SCI interrupt */
209 UINT32 SmiCmd; /* Port address of SMI command port */
210 UINT8 AcpiEnable; /* Value to write to smi_cmd to enable ACPI */
211 UINT8 AcpiDisable; /* Value to write to smi_cmd to disable ACPI */
212 UINT8 S4BiosReq; /* Value to write to SMI CMD to enter S4BIOS state */
213 UINT8 PstateCnt; /* Processor performance state control*/
214 UINT32 V1_Pm1aEvtBlk; /* Port address of Power Mgt 1a AcpiEvent Reg Blk */
215 UINT32 V1_Pm1bEvtBlk; /* Port address of Power Mgt 1b AcpiEvent Reg Blk */
216 UINT32 V1_Pm1aCntBlk; /* Port address of Power Mgt 1a Control Reg Blk */
217 UINT32 V1_Pm1bCntBlk; /* Port address of Power Mgt 1b Control Reg Blk */
218 UINT32 V1_Pm2CntBlk; /* Port address of Power Mgt 2 Control Reg Blk */
219 UINT32 V1_PmTmrBlk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
220 UINT32 V1_Gpe0Blk; /* Port addr of General Purpose AcpiEvent 0 Reg Blk */
221 UINT32 V1_Gpe1Blk; /* Port addr of General Purpose AcpiEvent 1 Reg Blk */
222 UINT8 Pm1EvtLen; /* Byte Length of ports at pm1X_evt_blk */
223 UINT8 Pm1CntLen; /* Byte Length of ports at pm1X_cnt_blk */
224 UINT8 Pm2CntLen; /* Byte Length of ports at pm2_cnt_blk */
225 UINT8 PmTmLen; /* Byte Length of ports at pm_tm_blk */
226 UINT8 Gpe0BlkLen; /* Byte Length of ports at gpe0_blk */
227 UINT8 Gpe1BlkLen; /* Byte Length of ports at gpe1_blk */
228 UINT8 Gpe1Base; /* Offset in gpe model where gpe1 events start */
229 UINT8 CstCnt; /* Support for the _CST object and C States change notification.*/
230 UINT16 Plvl2Lat; /* Worst case HW latency to enter/exit C2 state */
231 UINT16 Plvl3Lat; /* Worst case HW latency to enter/exit C3 state */
232 UINT16 FlushSize; /* Number of flush strides that need to be read */
233 UINT16 FlushStride; /* Processor's memory cache line width, in bytes */
234 UINT8 DutyOffset; /* Processor's duty cycle index in processor's P_CNT reg*/
235 UINT8 DutyWidth; /* Processor's duty cycle value bit width in P_CNT register.*/
236 UINT8 DayAlrm; /* Index to day-of-month alarm in RTC CMOS RAM */
237 UINT8 MonAlrm; /* Index to month-of-year alarm in RTC CMOS RAM */
238 UINT8 Century; /* Index to century in RTC CMOS RAM */
239 UINT16 IapcBootArch; /* IA-PC Boot Architecture Flags. See Table 5-10 for description*/
240 UINT8 Reserved2; /* Reserved */
241 UINT32_BIT WbInvd : 1; /* The wbinvd instruction works properly */
242 UINT32_BIT WbInvdFlush : 1; /* The wbinvd flushes but does not invalidate */
243 UINT32_BIT ProcC1 : 1; /* All processors support C1 state */
244 UINT32_BIT Plvl2Up : 1; /* C2 state works on MP system */
245 UINT32_BIT PwrButton : 1; /* Power button is handled as a generic feature */
246 UINT32_BIT SleepButton : 1; /* Sleep button is handled as a generic feature, or not present */
247 UINT32_BIT FixedRTC : 1; /* RTC wakeup stat not in fixed register space */
248 UINT32_BIT Rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
249 UINT32_BIT TmrValExt : 1; /* Indicates tmr_val is 32 bits 0=24-bits*/
250 UINT32_BIT DockCap : 1; /* Supports Docking */
251 UINT32_BIT ResetRegSup : 1; /* Indicates system supports system reset via the FADT RESET_REG*/
252 UINT32_BIT SealedCase : 1; /* Indicates system has no internal expansion capabilities and case is sealed. */
253 UINT32_BIT Headless : 1; /* Indicates system does not have local video capabilities or local input devices.*/
254 UINT32_BIT CpuSwSleep : 1; /* Indicates to OSPM that a processor native instruction */
255 /* Must be executed after writing the SLP_TYPx register. */
256 UINT32_BIT Reserved6 : 18; /* Reserved - must be zero */
258 ACPI_GENERIC_ADDRESS ResetRegister; /* Reset register address in GAS format */
259 UINT8 ResetValue; /* Value to write to the ResetRegister port to reset the system. */
260 UINT8 Reserved7[3]; /* These three bytes must be zero */
261 UINT64 XFirmwareCtrl; /* 64-bit physical address of FACS */
262 UINT64 XDsdt; /* 64-bit physical address of DSDT */
263 ACPI_GENERIC_ADDRESS XPm1aEvtBlk; /* Extended Power Mgt 1a AcpiEvent Reg Blk address */
264 ACPI_GENERIC_ADDRESS XPm1bEvtBlk; /* Extended Power Mgt 1b AcpiEvent Reg Blk address */
265 ACPI_GENERIC_ADDRESS XPm1aCntBlk; /* Extended Power Mgt 1a Control Reg Blk address */
266 ACPI_GENERIC_ADDRESS XPm1bCntBlk; /* Extended Power Mgt 1b Control Reg Blk address */
267 ACPI_GENERIC_ADDRESS XPm2CntBlk; /* Extended Power Mgt 2 Control Reg Blk address */
268 ACPI_GENERIC_ADDRESS XPmTmrBlk; /* Extended Power Mgt Timer Ctrl Reg Blk address */
269 ACPI_GENERIC_ADDRESS XGpe0Blk; /* Extended General Purpose AcpiEvent 0 Reg Blk address */
270 ACPI_GENERIC_ADDRESS XGpe1Blk; /* Extended General Purpose AcpiEvent 1 Reg Blk address */
272 } FADT_DESCRIPTOR_REV2;
277 #endif /* __ACTBL2_H__ */