2 ********************************************************************************
4 ** FILE NAME : arcmsr.h
5 ** BY : Erich Chen, Ching Huang
6 ** Description: SCSI RAID Device Driver for
7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
8 ** SATA/SAS RAID HOST Adapter
9 ********************************************************************************
10 ********************************************************************************
11 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved.
13 ** Redistribution and use in source and binary forms,with or without
14 ** modification,are permitted provided that the following conditions
16 ** 1. Redistributions of source code must retain the above copyright
17 ** notice,this list of conditions and the following disclaimer.
18 ** 2. Redistributions in binary form must reproduce the above copyright
19 ** notice,this list of conditions and the following disclaimer in the
20 ** documentation and/or other materials provided with the distribution.
21 ** 3. The name of the author may not be used to endorse or promote products
22 ** derived from this software without specific prior written permission.
24 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 ** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES
26 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT,
28 ** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
29 ** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 ** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
31 ** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT
32 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
33 ** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 **************************************************************************
35 * $FreeBSD: head/sys/dev/arcmsr/arcmsr.h 259565 2013-12-18 19:25:40Z delphij $
38 #include <sys/ioccom.h>
40 #define ARCMSR_SCSI_INITIATOR_ID 255
41 #define ARCMSR_DEV_SECTOR_SIZE 512
42 #define ARCMSR_MAX_XFER_SECTORS 4096
43 #define ARCMSR_MAX_TARGETID 17 /*16 max target id + 1*/
44 #define ARCMSR_MAX_TARGETLUN 8 /*8*/
45 #define ARCMSR_MAX_CHIPTYPE_NUM 4
46 #define ARCMSR_MAX_OUTSTANDING_CMD 256
47 #define ARCMSR_MAX_START_JOB 256
48 #define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD
49 #define ARCMSR_MAX_FREESRB_NUM 384
50 #define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */
51 #define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/
52 #define ARCMSR_MAX_ADAPTER 4
53 #define ARCMSR_RELEASE_SIMQ_LEVEL 230
54 #define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */
55 #define ARCMSR_MAX_HBD_POSTQUEUE 256
56 #define ARCMSR_TIMEOUT_DELAY 60 /* in sec */
58 *********************************************************************
67 # define INTR_ENTROPY 0
71 #define offsetof(type, member) ((size_t)(&((type *)0)->member))
74 #define ARCMSR_LOCK_INIT(l, s) lockinit(l, s, 0, LK_CANRECURSE)
75 #define ARCMSR_LOCK_DESTROY(l) lockuninit(l)
76 #define ARCMSR_LOCK_ACQUIRE(l) lockmgr(l, LK_EXCLUSIVE)
77 #define ARCMSR_LOCK_RELEASE(l) lockmgr(l, LK_RELEASE)
78 #define ARCMSR_LOCK_TRY(l) lockmgr(&l, LK_EXCLUSIVE|LK_NOWAIT)
79 #define arcmsr_htole32(x) htole32(x)
80 typedef struct lock arcmsr_lock_t;
83 **********************************************************************************
85 **********************************************************************************
87 #define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */
88 #define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */
89 #define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */
90 #define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */
91 #define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */
92 #define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */
93 #define PCI_DEVICE_ID_ARECA_1200 0x1200 /* Device ID */
94 #define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */
95 #define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */
96 #define PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID */
97 #define PCI_DEVICE_ID_ARECA_1214 0x1214 /* Device ID */
98 #define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */
99 #define PCI_DEVICE_ID_ARECA_1222 0x1222 /* Device ID */
100 #define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */
101 #define PCI_DEVICE_ID_ARECA_1231 0x1231 /* Device ID */
102 #define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */
103 #define PCI_DEVICE_ID_ARECA_1261 0x1261 /* Device ID */
104 #define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */
105 #define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */
106 #define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */
107 #define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */
108 #define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */
109 #define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */
110 #define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */
112 #define ARECA_SUB_DEV_ID_1880 0x1880 /* Subsystem Device ID */
113 #define ARECA_SUB_DEV_ID_1882 0x1882 /* Subsystem Device ID */
114 #define ARECA_SUB_DEV_ID_1883 0x1883 /* Subsystem Device ID */
115 #define ARECA_SUB_DEV_ID_1212 0x1212 /* Subsystem Device ID */
116 #define ARECA_SUB_DEV_ID_1213 0x1213 /* Subsystem Device ID */
117 #define ARECA_SUB_DEV_ID_1222 0x1222 /* Subsystem Device ID */
118 #define ARECA_SUB_DEV_ID_1223 0x1223 /* Subsystem Device ID */
120 #define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */
121 #define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */
122 #define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */
123 #define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */
124 #define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */
125 #define PCIDevVenIDARC1200 0x120017D3 /* Vendor Device ID */
126 #define PCIDevVenIDARC1201 0x120117D3 /* Vendor Device ID */
127 #define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */
128 #define PCIDevVenIDARC1212 0x121217D3 /* Vendor Device ID */
129 #define PCIDevVenIDARC1213 0x121317D3 /* Vendor Device ID */
130 #define PCIDevVenIDARC1214 0x121417D3 /* Vendor Device ID */
131 #define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */
132 #define PCIDevVenIDARC1222 0x122217D3 /* Vendor Device ID */
133 #define PCIDevVenIDARC1223 0x122317D3 /* Vendor Device ID */
134 #define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */
135 #define PCIDevVenIDARC1231 0x123117D3 /* Vendor Device ID */
136 #define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */
137 #define PCIDevVenIDARC1261 0x126117D3 /* Vendor Device ID */
138 #define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */
139 #define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */
140 #define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */
141 #define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */
142 #define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */
143 #define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */
144 #define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */
145 #define PCIDevVenIDARC1882 0x188217D3 /* Vendor Device ID */
148 #define PCIR_BARS 0x10
149 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
152 #define PCI_BASE_ADDR0 0x10
153 #define PCI_BASE_ADDR1 0x14
154 #define PCI_BASE_ADDR2 0x18
155 #define PCI_BASE_ADDR3 0x1C
156 #define PCI_BASE_ADDR4 0x20
157 #define PCI_BASE_ADDR5 0x24
159 **********************************************************************************
161 **********************************************************************************
163 #define ARCMSR_SCSICMD_IOCTL 0x77
164 #define ARCMSR_CDEVSW_IOCTL 0x88
165 #define ARCMSR_MESSAGE_FAIL 0x0001
166 #define ARCMSR_MESSAGE_SUCCESS 0x0000
168 **********************************************************************************
170 **********************************************************************************
172 #define arcmsr_ccbsrb_ptr spriv_ptr0
173 #define arcmsr_ccbacb_ptr spriv_ptr1
174 #define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16)
175 #define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff)
176 #define get_min(x,y) ((x) < (y) ? (x) : (y))
177 #define get_max(x,y) ((x) < (y) ? (y) : (x))
179 **************************************************************************
180 **************************************************************************
182 #define CHIP_REG_READ32(s, b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r))
183 #define CHIP_REG_WRITE32(s, b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r), d)
185 **********************************************************************************
186 ** IOCTL CONTROL Mail Box
187 **********************************************************************************
190 u_int32_t HeaderLength;
191 u_int8_t Signature[8];
193 u_int32_t ControlCode;
194 u_int32_t ReturnCode;
198 struct CMD_MESSAGE_FIELD {
199 struct CMD_MESSAGE cmdmessage; /* ioctl header */
200 u_int8_t messagedatabuffer[1032]; /* areca gui program does not accept more than 1031 byte */
203 /************************************************************************/
204 /************************************************************************/
206 #define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001
207 #define ARCMSR_IOP_ERROR_VENDORID 0x0002
208 #define ARCMSR_IOP_ERROR_DEVICEID 0x0002
209 #define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003
210 #define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004
211 #define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005
212 #define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006
213 #define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007
214 #define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008
215 #define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009
216 #define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A
219 #define ARECA_SATA_RAID 0x90000000
222 #define FUNCTION_READ_RQBUFFER 0x0801
223 #define FUNCTION_WRITE_WQBUFFER 0x0802
224 #define FUNCTION_CLEAR_RQBUFFER 0x0803
225 #define FUNCTION_CLEAR_WQBUFFER 0x0804
226 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805
227 #define FUNCTION_REQUEST_RETURNCODE_3F 0x0806
228 #define FUNCTION_SAY_HELLO 0x0807
229 #define FUNCTION_SAY_GOODBYE 0x0808
230 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809
232 ************************************************************************
233 ** IOCTL CONTROL CODE
234 ************************************************************************
236 /* ARECA IO CONTROL CODE*/
237 #define ARCMSR_MESSAGE_READ_RQBUFFER _IOWR('F', FUNCTION_READ_RQBUFFER, struct CMD_MESSAGE_FIELD)
238 #define ARCMSR_MESSAGE_WRITE_WQBUFFER _IOWR('F', FUNCTION_WRITE_WQBUFFER, struct CMD_MESSAGE_FIELD)
239 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER _IOWR('F', FUNCTION_CLEAR_RQBUFFER, struct CMD_MESSAGE_FIELD)
240 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER _IOWR('F', FUNCTION_CLEAR_WQBUFFER, struct CMD_MESSAGE_FIELD)
241 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER _IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, struct CMD_MESSAGE_FIELD)
242 #define ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F _IOWR('F', FUNCTION_REQUEST_RETURNCODE_3F, struct CMD_MESSAGE_FIELD)
243 #define ARCMSR_MESSAGE_SAY_HELLO _IOWR('F', FUNCTION_SAY_HELLO, struct CMD_MESSAGE_FIELD)
244 #define ARCMSR_MESSAGE_SAY_GOODBYE _IOWR('F', FUNCTION_SAY_GOODBYE, struct CMD_MESSAGE_FIELD)
245 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE _IOWR('F', FUNCTION_FLUSH_ADAPTER_CACHE, struct CMD_MESSAGE_FIELD)
247 /* ARECA IOCTL ReturnCode */
248 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001
249 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006
250 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F
251 #define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON 0x00000088
253 ************************************************************************
254 ** SPEC. for Areca HBA adapter
255 ************************************************************************
257 /* signature of set and get firmware config */
258 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
259 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063
260 /* message code of inbound message register */
261 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000
262 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001
263 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002
264 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003
265 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004
266 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005
267 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006
268 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007
269 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008
270 /* doorbell interrupt generator */
271 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001
272 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002
273 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001
274 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002
275 /* srb areca cdb flag */
276 #define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000
277 #define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000
278 #define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000
279 #define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000
280 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0 0x10000000
281 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1 0x00000001
282 /* outbound firmware ok */
283 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
285 #define ARCMSR_ARC1680_BUS_RESET 0x00000003
287 ************************************************************************
288 ** SPEC. for Areca HBB adapter
289 ************************************************************************
291 /* ARECA HBB COMMAND for its FIRMWARE */
292 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400 /* window of "instruction flags" from driver to iop */
293 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404
294 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408 /* window of "instruction flags" from iop to driver */
295 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C
297 /* ARECA FLAG LANGUAGE */
298 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 /* ioctl transfer */
299 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 /* ioctl transfer */
300 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004
301 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
303 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F
304 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0
305 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7
307 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
308 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
309 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
310 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
311 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
312 #define ARCMSR_MESSAGE_START_BGRB 0x00060008 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
313 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008
314 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008
315 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008
316 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */
318 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 /* ioctl transfer */
319 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 /* ioctl transfer */
320 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004
321 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008
322 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 /* */
324 /* data tunnel buffer between user space program and its firmware */
325 #define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 /* iop msgcode_rwbuffer for message command */
326 #define ARCMSR_IOCTL_WBUFFER 0x0000fe00 /* user space data to iop 128bytes */
327 #define ARCMSR_IOCTL_RBUFFER 0x0000ff00 /* iop data to user space 128bytes */
328 #define ARCMSR_HBB_BASE0_OFFSET 0x00000010
329 #define ARCMSR_HBB_BASE1_OFFSET 0x00000018
330 #define ARCMSR_HBB_BASE0_LEN 0x00021000
331 #define ARCMSR_HBB_BASE1_LEN 0x00010000
333 ************************************************************************
334 ** SPEC. for Areca HBC adapter
335 ************************************************************************
337 #define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12
338 #define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20
339 /* Host Interrupt Mask */
340 #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/
341 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/
342 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/
343 #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */
344 /* Host Interrupt Status */
345 #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001
347 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register.
348 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled).
350 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004
352 ** Set if Outbound Doorbell register bits 30:1 have a non-zero
353 ** value. This bit clears only when Outbound Doorbell bits
354 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell
355 ** Clear register clears bits in the Outbound Doorbell register.
357 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
359 ** Set whenever the Outbound Post List Producer/Consumer
360 ** Register (FIFO) is not empty. It clears when the Outbound
361 ** Post List FIFO is empty.
363 #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010
365 ** This bit indicates a SAS interrupt from a source external to
366 ** the PCIe core. This bit is not maskable.
369 #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002/**/
370 #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004/**/
371 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008/*inbound message 0 ready*/
372 #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010/*more than 12 request completed in a time*/
373 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002/**/
374 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002/*outbound DATA WRITE isr door bell clear*/
375 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004/**/
376 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004/*outbound DATA READ isr door bell clear*/
377 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008/*outbound message 0 ready*/
378 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008/*outbound message cmd isr door bell clear*/
379 #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/
380 #define ARCMSR_HBCMU_RESET_ADAPTER 0x00000024
381 #define ARCMSR_HBCMU_DiagWrite_ENABLE 0x00000080
384 ************************************************************************
385 ** SPEC. for Areca HBD adapter
386 ************************************************************************
388 #define ARCMSR_HBDMU_CHIP_ID 0x00004
389 #define ARCMSR_HBDMU_CPU_MEMORY_CONFIGURATION 0x00008
390 #define ARCMSR_HBDMU_I2_HOST_INTERRUPT_MASK 0x00034
391 #define ARCMSR_HBDMU_MAIN_INTERRUPT_STATUS 0x00200
392 #define ARCMSR_HBDMU_PCIE_F0_INTERRUPT_ENABLE 0x0020C
393 #define ARCMSR_HBDMU_INBOUND_MESSAGE0 0x00400
394 #define ARCMSR_HBDMU_INBOUND_MESSAGE1 0x00404
395 #define ARCMSR_HBDMU_OUTBOUND_MESSAGE0 0x00420
396 #define ARCMSR_HBDMU_OUTBOUND_MESSAGE1 0x00424
397 #define ARCMSR_HBDMU_INBOUND_DOORBELL 0x00460
398 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL 0x00480
399 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL_ENABLE 0x00484
400 #define ARCMSR_HBDMU_INBOUND_LIST_BASE_LOW 0x01000
401 #define ARCMSR_HBDMU_INBOUND_LIST_BASE_HIGH 0x01004
402 #define ARCMSR_HBDMU_INBOUND_LIST_WRITE_POINTER 0x01018
403 #define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_LOW 0x01060
404 #define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_HIGH 0x01064
405 #define ARCMSR_HBDMU_OUTBOUND_LIST_COPY_POINTER 0x0106C
406 #define ARCMSR_HBDMU_OUTBOUND_LIST_READ_POINTER 0x01070
407 #define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_CAUSE 0x01088
408 #define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_ENABLE 0x0108C
410 #define ARCMSR_HBDMU_MESSAGE_WBUFFER 0x02000
411 #define ARCMSR_HBDMU_MESSAGE_RBUFFER 0x02100
412 #define ARCMSR_HBDMU_MESSAGE_RWBUFFER 0x02200
414 #define ARCMSR_HBDMU_ISR_THROTTLING_LEVEL 16
415 #define ARCMSR_HBDMU_ISR_MAX_DONE_QUEUE 20
417 /* Host Interrupt Mask */
418 #define ARCMSR_HBDMU_ALL_INT_ENABLE 0x00001010 /* enable all ISR */
419 #define ARCMSR_HBDMU_ALL_INT_DISABLE 0x00000000 /* disable all ISR */
421 /* Host Interrupt Status */
422 #define ARCMSR_HBDMU_OUTBOUND_INT 0x00001010
423 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT 0x00001000
424 #define ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT 0x00000010
427 #define ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY 0x00000001
428 #define ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ 0x00000002
430 #define ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK 0x00000001
431 #define ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK 0x00000002
433 /*outbound message 0 ready*/
434 #define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE 0x02000000
436 #define ARCMSR_HBDMU_F0_DOORBELL_CAUSE 0x02000003
438 /*outbound message cmd isr door bell clear*/
439 #define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR 0x02000000
442 #define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT 0x00000001
443 #define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001
445 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
446 #define ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK 0x80000000
448 *********************************************************************
449 ** Message Unit structure
450 *********************************************************************
452 struct HBA_MessageUnit
454 u_int32_t resrved0[4]; /*0000 000F*/
455 u_int32_t inbound_msgaddr0; /*0010 0013*/
456 u_int32_t inbound_msgaddr1; /*0014 0017*/
457 u_int32_t outbound_msgaddr0; /*0018 001B*/
458 u_int32_t outbound_msgaddr1; /*001C 001F*/
459 u_int32_t inbound_doorbell; /*0020 0023*/
460 u_int32_t inbound_intstatus; /*0024 0027*/
461 u_int32_t inbound_intmask; /*0028 002B*/
462 u_int32_t outbound_doorbell; /*002C 002F*/
463 u_int32_t outbound_intstatus; /*0030 0033*/
464 u_int32_t outbound_intmask; /*0034 0037*/
465 u_int32_t reserved1[2]; /*0038 003F*/
466 u_int32_t inbound_queueport; /*0040 0043*/
467 u_int32_t outbound_queueport; /*0044 0047*/
468 u_int32_t reserved2[2]; /*0048 004F*/
469 u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/
470 u_int32_t reserved4[128]; /*0800 09FF 128*/
471 u_int32_t msgcode_rwbuffer[256]; /*0a00 0DFF 256*/
472 u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/
473 u_int32_t reserved5[32]; /*0E80 0EFF 32*/
474 u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/
475 u_int32_t reserved6[32]; /*0F80 0FFF 32*/
478 *********************************************************************
480 *********************************************************************
484 u_int8_t doorbell_reserved[ARCMSR_DRV2IOP_DOORBELL]; /*reserved */
485 u_int32_t drv2iop_doorbell; /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */
486 u_int32_t drv2iop_doorbell_mask; /* 04,05,06,07: doorbell mask */
487 u_int32_t iop2drv_doorbell; /* 08,09,10,11: window of "instruction flags" from iop to driver */
488 u_int32_t iop2drv_doorbell_mask; /* 12,13,14,15: doorbell mask */
491 *********************************************************************
493 *********************************************************************
497 u_int8_t message_reserved0[ARCMSR_MSGCODE_RWBUFFER]; /*reserved */
498 u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */
499 u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */
500 u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/
501 u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */
504 *********************************************************************
506 *********************************************************************
508 struct HBB_MessageUnit
510 u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */
511 u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */
512 int32_t postq_index; /* post queue index */
513 int32_t doneq_index; /* done queue index */
514 struct HBB_DOORBELL *hbb_doorbell;
515 struct HBB_RWBUFFER *hbb_rwbuffer;
519 *********************************************************************
521 *********************************************************************
523 struct HBC_MessageUnit {
524 u_int32_t message_unit_status; /*0000 0003*/
525 u_int32_t slave_error_attribute; /*0004 0007*/
526 u_int32_t slave_error_address; /*0008 000B*/
527 u_int32_t posted_outbound_doorbell; /*000C 000F*/
528 u_int32_t master_error_attribute; /*0010 0013*/
529 u_int32_t master_error_address_low; /*0014 0017*/
530 u_int32_t master_error_address_high; /*0018 001B*/
531 u_int32_t hcb_size; /*001C 001F size of the PCIe window used for HCB_Mode accesses*/
532 u_int32_t inbound_doorbell; /*0020 0023*/
533 u_int32_t diagnostic_rw_data; /*0024 0027*/
534 u_int32_t diagnostic_rw_address_low; /*0028 002B*/
535 u_int32_t diagnostic_rw_address_high; /*002C 002F*/
536 u_int32_t host_int_status; /*0030 0033 host interrupt status*/
537 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/
538 u_int32_t dcr_data; /*0038 003B*/
539 u_int32_t dcr_address; /*003C 003F*/
540 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/
541 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/
542 u_int32_t hcb_pci_address_low; /*0048 004B*/
543 u_int32_t hcb_pci_address_high; /*004C 004F*/
544 u_int32_t iop_int_status; /*0050 0053*/
545 u_int32_t iop_int_mask; /*0054 0057*/
546 u_int32_t iop_inbound_queue_port; /*0058 005B*/
547 u_int32_t iop_outbound_queue_port; /*005C 005F*/
548 u_int32_t inbound_free_list_index; /*0060 0063 inbound free list producer consumer index*/
549 u_int32_t inbound_post_list_index; /*0064 0067 inbound post list producer consumer index*/
550 u_int32_t outbound_free_list_index; /*0068 006B outbound free list producer consumer index*/
551 u_int32_t outbound_post_list_index; /*006C 006F outbound post list producer consumer index*/
552 u_int32_t inbound_doorbell_clear; /*0070 0073*/
553 u_int32_t i2o_message_unit_control; /*0074 0077*/
554 u_int32_t last_used_message_source_address_low; /*0078 007B*/
555 u_int32_t last_used_message_source_address_high; /*007C 007F*/
556 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F pull mode data byte count0..count7*/
557 u_int32_t message_dest_address_index; /*0090 0093*/
558 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
559 u_int32_t utility_A_int_counter_timer; /*0098 009B*/
560 u_int32_t outbound_doorbell; /*009C 009F*/
561 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/
562 u_int32_t message_source_address_index; /*00A4 00A7 message accelerator source address consumer producer index*/
563 u_int32_t message_done_queue_index; /*00A8 00AB message accelerator completion queue consumer producer index*/
564 u_int32_t reserved0; /*00AC 00AF*/
565 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/
566 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/
567 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/
568 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/
569 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/
570 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/
571 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/
572 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/
573 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/
574 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/
575 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/
576 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/
577 u_int32_t message_dest_queue_port_low; /*00E0 00E3 message accelerator destination queue port low*/
578 u_int32_t message_dest_queue_port_high; /*00E4 00E7 message accelerator destination queue port high*/
579 u_int32_t last_used_message_dest_address_low; /*00E8 00EB last used message accelerator destination address low*/
580 u_int32_t last_used_message_dest_address_high; /*00EC 00EF last used message accelerator destination address high*/
581 u_int32_t message_done_queue_base_address_low; /*00F0 00F3 message accelerator completion queue base address low*/
582 u_int32_t message_done_queue_base_address_high; /*00F4 00F7 message accelerator completion queue base address high*/
583 u_int32_t host_diagnostic; /*00F8 00FB*/
584 u_int32_t write_sequence; /*00FC 00FF*/
585 u_int32_t reserved1[34]; /*0100 0187*/
586 u_int32_t reserved2[1950]; /*0188 1FFF*/
587 u_int32_t message_wbuffer[32]; /*2000 207F*/
588 u_int32_t reserved3[32]; /*2080 20FF*/
589 u_int32_t message_rbuffer[32]; /*2100 217F*/
590 u_int32_t reserved4[32]; /*2180 21FF*/
591 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/
594 *********************************************************************
596 *********************************************************************
599 uint32_t addressLow; //pointer to SRB block
600 uint32_t addressHigh;
601 uint32_t length; // in DWORDs
605 struct OutBound_SRB {
606 uint32_t addressLow; //pointer to SRB block
607 uint32_t addressHigh;
610 struct HBD_MessageUnit {
612 uint32_t chip_id; //0x0004
613 uint32_t cpu_mem_config; //0x0008
614 uint32_t reserved1[10]; //0x000C
615 uint32_t i2o_host_interrupt_mask; //0x0034
616 uint32_t reserved2[114]; //0x0038
617 uint32_t host_int_status; //0x0200
618 uint32_t host_int_enable; //0x0204
619 uint32_t reserved3[1]; //0x0208
620 uint32_t pcief0_int_enable; //0x020C
621 uint32_t reserved4[124]; //0x0210
622 uint32_t inbound_msgaddr0; //0x0400
623 uint32_t inbound_msgaddr1; //0x0404
624 uint32_t reserved5[6]; //0x0408
625 uint32_t outbound_msgaddr0; //0x0420
626 uint32_t outbound_msgaddr1; //0x0424
627 uint32_t reserved6[14]; //0x0428
628 uint32_t inbound_doorbell; //0x0460
629 uint32_t reserved7[7]; //0x0464
630 uint32_t outbound_doorbell; //0x0480
631 uint32_t outbound_doorbell_enable; //0x0484
632 uint32_t reserved8[734]; //0x0488
633 uint32_t inboundlist_base_low; //0x1000
634 uint32_t inboundlist_base_high; //0x1004
635 uint32_t reserved9[4]; //0x1008
636 uint32_t inboundlist_write_pointer; //0x1018
637 uint32_t inboundlist_read_pointer; //0x101C
638 uint32_t reserved10[16]; //0x1020
639 uint32_t outboundlist_base_low; //0x1060
640 uint32_t outboundlist_base_high; //0x1064
641 uint32_t reserved11; //0x1068
642 uint32_t outboundlist_copy_pointer; //0x106C
643 uint32_t outboundlist_read_pointer; //0x1070 0x1072
644 uint32_t reserved12[5]; //0x1074
645 uint32_t outboundlist_interrupt_cause; //0x1088
646 uint32_t outboundlist_interrupt_enable; //0x108C
647 uint32_t reserved13[988]; //0x1090
648 uint32_t message_wbuffer[32]; //0x2000
649 uint32_t reserved14[32]; //0x2080
650 uint32_t message_rbuffer[32]; //0x2100
651 uint32_t reserved15[32]; //0x2180
652 uint32_t msgcode_rwbuffer[256]; //0x2200
655 struct HBD_MessageUnit0 {
656 struct InBound_SRB post_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE];
657 struct OutBound_SRB done_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE+1];
658 uint16_t postq_index;
659 uint16_t doneq_index;
660 struct HBD_MessageUnit *phbdmu;
664 *********************************************************************
666 *********************************************************************
668 struct MessageUnit_UNION
671 struct HBA_MessageUnit hbamu;
672 struct HBB_MessageUnit hbbmu;
673 struct HBC_MessageUnit hbcmu;
674 struct HBD_MessageUnit0 hbdmu;
678 *************************************************************
679 ** structure for holding DMA address data
680 *************************************************************
682 #define IS_SG64_ADDR 0x01000000 /* bit24 */
684 ************************************************************************************************
685 ** ARECA FIRMWARE SPEC
686 ************************************************************************************************
687 ** Usage of IOP331 adapter
688 ** (All In/Out is in IOP331's view)
689 ** 1. Message 0 --> InitThread message and retrun code
690 ** 2. Doorbell is used for RS-232 emulation
691 ** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK)
692 ** bit1 -- data out has been read (DRIVER DATA READ OK)
693 ** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK)
694 ** bit1 -- data in has been read (IOP331 DATA READ OK)
695 ** 3. Index Memory Usage
696 ** offset 0xf00 : for RS232 out (request buffer)
697 ** offset 0xe00 : for RS232 in (scratch buffer)
698 ** offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331)
699 ** offset 0xa00 : for outbound message code msgcode_rwbuffer (IOP331 send to driver)
700 ** 4. RS-232 emulation
701 ** Currently 128 byte buffer is used
702 ** 1st u_int32_t : Data length (1--124)
703 ** Byte 4--127 : Max 124 bytes of data
705 ** All SCSI Command must be sent through postQ:
706 ** (inbound queue port) Request frame must be 32 bytes aligned
707 ** # bit27--bit31 => flag for post ccb
708 ** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb
709 ** bit31 : 0 : 256 bytes frame
710 ** 1 : 512 bytes frame
711 ** bit30 : 0 : normal request
716 ** -------------------------------------------------------------------------------
717 ** (outbount queue port) Request reply
718 ** # bit27--bit31 => flag for reply
719 ** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb
720 ** bit31 : must be 0 (for this type of reply)
721 ** bit30 : reserved for BIOS handshake
723 ** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData
724 ** 1 : Error, error code in AdapStatus/DevStatus/SenseData
727 ** All BIOS request is the same with request from PostQ
729 ** Request frame is sent from configuration space
730 ** offset: 0x78 : Request Frame (bit30 == 1)
731 ** offset: 0x18 : writeonly to generate IRQ to IOP331
732 ** Completion of request:
733 ** (bit30 == 0, bit28==err flag)
734 ** 7. Definition of SGL entry (structure)
735 ** 8. Message1 Out - Diag Status Code (????)
736 ** 9. Message0 message code :
738 ** 0x01 : Get Config ->offset 0xa00 :for outbound message code msgcode_rwbuffer (IOP331 send to driver)
739 ** Signature 0x87974060(4)
740 ** Request len 0x00000200(4)
741 ** numbers of queue 0x00000100(4)
742 ** SDRAM Size 0x00000100(4)-->256 MB
743 ** IDE Channels 0x00000008(4)
744 ** vendor 40 bytes char
745 ** model 8 bytes char
746 ** FirmVer 16 bytes char
747 ** Device Map 16 bytes char
749 ** FirmwareVersion DWORD <== Added for checking of new firmware capability
750 ** 0x02 : Set Config ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331)
751 ** Signature 0x87974063(4)
752 ** UPPER32 of Request Frame (4)-->Driver Only
753 ** 0x03 : Reset (Abort all queued Command)
754 ** 0x04 : Stop Background Activity
755 ** 0x05 : Flush Cache
756 ** 0x06 : Start Background Activity (re-start if background is halted)
757 ** 0x07 : Check If Host Command Pending (Novell May Need This Function)
758 ** 0x08 : Set controller time ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver to IOP331)
759 ** byte 0 : 0xaa <-- signature
760 ** byte 1 : 0x55 <-- signature
761 ** byte 2 : year (04)
762 ** byte 3 : month (1..12)
763 ** byte 4 : date (1..31)
764 ** byte 5 : hour (0..23)
765 ** byte 6 : minute (0..59)
766 ** byte 7 : second (0..59)
767 ** *********************************************************************************
768 ** Porting Of LSI2108/2116 Based PCIE SAS/6G host raid adapter
769 ** ==> Difference from IOP348
770 ** <1> Message Register 0,1 (the same usage) Init Thread message and retrun code
771 ** Inbound Message 0 (inbound_msgaddr0) : at offset 0xB0 (Scratchpad0) for inbound message code msgcode_rwbuffer (driver send to IOP)
772 ** Inbound Message 1 (inbound_msgaddr1) : at offset 0xB4 (Scratchpad1) Out.... Diag Status Code
773 ** Outbound Message 0 (outbound_msgaddr0): at offset 0xB8 (Scratchpad3) Out.... Diag Status Code
774 ** Outbound Message 1 (outbound_msgaddr1): at offset 0xBC (Scratchpad2) for outbound message code msgcode_rwbuffer (IOP send to driver)
775 ** <A> use doorbell to generate interrupt
777 ** inbound doorbell: bit3 -- inbound message 0 ready (driver to iop)
778 ** outbound doorbell: bit3 -- outbound message 0 ready (iop to driver)
780 ** a. Message1: Out - Diag Status Code (????)
782 ** b. Message0: message code
784 ** 0x01 : Get Config ->offset 0xB8 :for outbound message code msgcode_rwbuffer (IOP send to driver)
785 ** Signature 0x87974060(4)
786 ** Request len 0x00000200(4)
787 ** numbers of queue 0x00000100(4)
788 ** SDRAM Size 0x00000100(4)-->256 MB
789 ** IDE Channels 0x00000008(4)
790 ** vendor 40 bytes char
791 ** model 8 bytes char
792 ** FirmVer 16 bytes char
793 ** Device Map 16 bytes char
794 ** cfgVersion ULONG <== Added for checking of new firmware capability
795 ** 0x02 : Set Config ->offset 0xB0 :for inbound message code msgcode_rwbuffer (driver send to IOP)
796 ** Signature 0x87974063(4)
797 ** UPPER32 of Request Frame (4)-->Driver Only
798 ** 0x03 : Reset (Abort all queued Command)
799 ** 0x04 : Stop Background Activity
800 ** 0x05 : Flush Cache
801 ** 0x06 : Start Background Activity (re-start if background is halted)
802 ** 0x07 : Check If Host Command Pending (Novell May Need This Function)
803 ** 0x08 : Set controller time ->offset 0xB0 : for inbound message code msgcode_rwbuffer (driver to IOP)
804 ** byte 0 : 0xaa <-- signature
805 ** byte 1 : 0x55 <-- signature
806 ** byte 2 : year (04)
807 ** byte 3 : month (1..12)
808 ** byte 4 : date (1..31)
809 ** byte 5 : hour (0..23)
810 ** byte 6 : minute (0..59)
811 ** byte 7 : second (0..59)
813 ** <2> Doorbell Register is used for RS-232 emulation
814 ** <A> different clear register
815 ** <B> different bit0 definition (bit0 is reserved)
817 ** inbound doorbell : at offset 0x20
818 ** inbound doorbell clear : at offset 0x70
820 ** inbound doorbell : bit0 -- reserved
821 ** bit1 -- data in ready (DRIVER DATA WRITE OK)
822 ** bit2 -- data out has been read (DRIVER DATA READ OK)
823 ** bit3 -- inbound message 0 ready
824 ** bit4 -- more than 12 request completed in a time
826 ** outbound doorbell : at offset 0x9C
827 ** outbound doorbell clear : at offset 0xA0
829 ** outbound doorbell : bit0 -- reserved
830 ** bit1 -- data out ready (IOP DATA WRITE OK)
831 ** bit2 -- data in has been read (IOP DATA READ OK)
832 ** bit3 -- outbound message 0 ready
834 ** <3> Index Memory Usage (Buffer Area)
835 ** COMPORT_IN at 0x2000: message_wbuffer -- 128 bytes (to be sent to ROC) : for RS232 in (scratch buffer)
836 ** COMPORT_OUT at 0x2100: message_rbuffer -- 128 bytes (to be sent to host): for RS232 out (request buffer)
837 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for outbound message code msgcode_rwbuffer (IOP send to driver)
838 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for inbound message code msgcode_rwbuffer (driver send to IOP)
840 ** <4> PostQ (Command Post Address)
841 ** All SCSI Command must be sent through postQ:
842 ** inbound queue port32 at offset 0x40 , 0x41, 0x42, 0x43
843 ** inbound queue port64 at offset 0xC0 (lower)/0xC4 (upper)
844 ** outbound queue port32 at offset 0x44
845 ** outbound queue port64 at offset 0xC8 (lower)/0xCC (upper)
846 ** <A> For 32bit queue, access low part is enough to send/receive request
847 ** i.e. write 0x40/0xC0, ROC will get the request with high part == 0, the
848 ** same for outbound queue port
849 ** <B> For 64bit queue, if 64bit instruction is supported, use 64bit instruction
850 ** to post inbound request in a single instruction, and use 64bit instruction
851 ** to retrieve outbound request in a single instruction.
852 ** If in 32bit environment, when sending inbound queue, write high part first
853 ** then write low part. For receiving outbound request, read high part first
854 ** then low part, to check queue empty, ONLY check high part to be 0xFFFFFFFF.
855 ** If high part is 0xFFFFFFFF, DO NOT read low part, this may corrupt the
856 ** consistency of the FIFO. Another way to check empty is to check status flag
858 ** <C> Post Address IS NOT shifted (must be 16 bytes aligned)
859 ** For BIOS, 16bytes aligned is OK
860 ** For Driver, 32bytes alignment is recommended.
861 ** POST Command bit0 to bit3 is defined differently
862 ** ----------------------------
863 ** bit0:1 for PULL mode (must be 1)
864 ** ----------------------------
865 ** bit3/2/1: for arcmsr cdb size (arccdbsize)
866 ** 000: <= 0x0080 (128)
867 ** 001: <= 0x0100 (256)
868 ** 010: <= 0x0180 (384)
869 ** 011: <= 0x0200 (512)
870 ** 100: <= 0x0280 (640)
871 ** 101: <= 0x0300 (768)
872 ** 110: <= 0x0300 (reserved)
873 ** 111: <= 0x0300 (reserved)
874 ** -----------------------------
875 ** if len > 0x300 the len always set as 0x300
876 ** -----------------------------
877 ** post addr = addr | ((len-1) >> 6) | 1
878 ** -----------------------------
879 ** page length in command buffer still required,
881 ** if page length > 3,
882 ** firmware will assume more request data need to be retrieved
884 ** <D> Outbound Posting
885 ** bit0:0 , no error, 1 with error, refer to status buffer
886 ** bit1:0 , reserved (will be 0)
887 ** bit2:0 , reserved (will be 0)
888 ** bit3:0 , reserved (will be 0)
889 ** bit63-4: Completed command address
891 ** <E> BIOS support, no special support is required.
892 ** LSI2108 support I/O register
893 ** All driver functionality is supported through I/O address
895 ************************************************************************************************
898 **********************************
900 **********************************
903 /* 32bit Scatter-Gather list */
904 struct SG32ENTRY { /* length bit 24 == 0 */
905 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */
909 /* 64bit Scatter-Gather list */
910 struct SG64ENTRY { /* length bit 24 == 1 */
911 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */
913 u_int32_t addresshigh;
915 struct SGENTRY_UNION {
917 struct SG32ENTRY sg32entry; /* 30h Scatter gather address */
918 struct SG64ENTRY sg64entry; /* 30h */
922 **********************************
924 **********************************
931 **********************************
933 typedef struct PHYS_ADDR64 {
934 u_int32_t phyadd_low;
935 u_int32_t phyadd_high;
938 ************************************************************************************************
940 ************************************************************************************************
942 #define ARCMSR_FW_MODEL_OFFSET 15
943 #define ARCMSR_FW_VERS_OFFSET 17
944 #define ARCMSR_FW_DEVMAP_OFFSET 21
945 #define ARCMSR_FW_CFGVER_OFFSET 25
947 struct FIRMWARE_INFO {
948 u_int32_t signature; /*0,00-03*/
949 u_int32_t request_len; /*1,04-07*/
950 u_int32_t numbers_queue; /*2,08-11*/
951 u_int32_t sdram_size; /*3,12-15*/
952 u_int32_t ide_channels; /*4,16-19*/
953 char vendor[40]; /*5,20-59*/
954 char model[8]; /*15,60-67*/
955 char firmware_ver[16]; /*17,68-83*/
956 char device_map[16]; /*21,84-99*/
957 u_int32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/
958 char cfgSerial[16]; /*26,104-119*/
959 u_int32_t cfgPicStatus; /*30,120-123*/
961 /* (A) For cfgVersion in FIRMWARE_INFO
962 ** if low BYTE (byte#0) >= 3 (version 3)
963 ** then byte#1 report the capability of the firmware can xfer in a single request
973 ** (B) Byte offset 7 (Reserved1) of CDB is changed to msgPages
974 ** Driver support new xfer method need to set this field to indicate
975 ** large CDB block in 0x100 unit (we use 0x100 byte as one page)
976 ** e.g. If the length of CDB including MSG header and SGL is 0x1508
977 ** driver need to set the msgPages to 0x16
978 ** (C) REQ_LEN_512BYTE must be used also to indicate SRB length
979 ** e.g. CDB len msgPages REQ_LEN_512BYTE flag
989 ************************************************************************************************
991 ************************************************************************************************
994 u_int8_t Bus; /* 00h should be 0 */
995 u_int8_t TargetID; /* 01h should be 0--15 */
996 u_int8_t LUN; /* 02h should be 0--7 */
997 u_int8_t Function; /* 03h should be 1 */
999 u_int8_t CdbLength; /* 04h not used now */
1000 u_int8_t sgcount; /* 05h */
1001 u_int8_t Flags; /* 06h */
1002 u_int8_t msgPages; /* 07h */
1004 u_int32_t Context; /* 08h Address of this request */
1005 u_int32_t DataLength; /* 0ch not used now */
1007 u_int8_t Cdb[16]; /* 10h SCSI CDB */
1009 ********************************************************
1010 ** Device Status : the same from SCSI bus if error occur
1011 ** SCSI bus status codes.
1012 ********************************************************
1014 u_int8_t DeviceStatus; /* 20h if error */
1016 u_int8_t SenseData[15]; /* 21h output */
1019 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */
1020 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */
1024 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */
1025 #define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */
1026 #define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */
1027 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */
1028 #define ARCMSR_CDB_FLAG_HEADQ 0x08
1029 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10
1031 #define SCSISTAT_GOOD 0x00
1032 #define SCSISTAT_CHECK_CONDITION 0x02
1033 #define SCSISTAT_CONDITION_MET 0x04
1034 #define SCSISTAT_BUSY 0x08
1035 #define SCSISTAT_INTERMEDIATE 0x10
1036 #define SCSISTAT_INTERMEDIATE_COND_MET 0x14
1037 #define SCSISTAT_RESERVATION_CONFLICT 0x18
1038 #define SCSISTAT_COMMAND_TERMINATED 0x22
1039 #define SCSISTAT_QUEUE_FULL 0x28
1041 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0
1042 #define ARCMSR_DEV_ABORTED 0xF1
1043 #define ARCMSR_DEV_INIT_FAIL 0xF2
1045 *********************************************************************
1046 ** Command Control Block (SrbExtension)
1047 ** SRB must be not cross page boundary,and the order from offset 0
1048 ** structure describing an ATA disk request
1049 ** this SRB length must be 32 bytes boundary
1050 *********************************************************************
1052 struct CommandControlBlock {
1053 struct ARCMSR_CDB arcmsr_cdb; /* 0 -503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */
1054 u_int32_t cdb_phyaddr_low; /* 504-507 */
1055 u_int32_t arc_cdb_size; /* 508-511 */
1056 /* ======================512+32 bytes============================ */
1057 union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */
1058 struct AdapterControlBlock *acb; /* 520-523 524-527 */
1059 bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */
1060 u_int16_t srb_flags; /* 536-537 */
1061 u_int16_t srb_state; /* 538-539 */
1062 u_int32_t cdb_phyaddr_high; /* 540-543 */
1063 struct callout ccb_callout;
1064 /* ========================================================== */
1067 #define SRB_FLAG_READ 0x0000
1068 #define SRB_FLAG_WRITE 0x0001
1069 #define SRB_FLAG_ERROR 0x0002
1070 #define SRB_FLAG_FLUSHCACHE 0x0004
1071 #define SRB_FLAG_MASTER_ABORTED 0x0008
1072 #define SRB_FLAG_DMAVALID 0x0010
1073 #define SRB_FLAG_DMACONSISTENT 0x0020
1074 #define SRB_FLAG_DMAWRITE 0x0040
1075 #define SRB_FLAG_PKTBIND 0x0080
1076 #define SRB_FLAG_TIMER_START 0x0080
1078 #define ARCMSR_SRB_DONE 0x0000
1079 #define ARCMSR_SRB_UNBUILD 0x0000
1080 #define ARCMSR_SRB_TIMEOUT 0x1111
1081 #define ARCMSR_SRB_RETRY 0x2222
1082 #define ARCMSR_SRB_START 0x55AA
1083 #define ARCMSR_SRB_PENDING 0xAA55
1084 #define ARCMSR_SRB_RESET 0xA5A5
1085 #define ARCMSR_SRB_ABORTED 0x5A5A
1086 #define ARCMSR_SRB_ILLEGAL 0xFFFF
1088 #define SRB_SIZE ((sizeof(struct CommandControlBlock)+0x1f) & 0xffe0)
1089 #define ARCMSR_SRBS_POOL_SIZE (SRB_SIZE * ARCMSR_MAX_FREESRB_NUM)
1092 *********************************************************************
1093 ** Adapter Control Block
1094 *********************************************************************
1096 #define ACB_ADAPTER_TYPE_A 0x00000001 /* hba I IOP */
1097 #define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb M IOP */
1098 #define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc L IOP */
1099 #define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd M IOP */
1101 struct AdapterControlBlock {
1102 u_int32_t adapter_type; /* adapter A,B..... */
1104 bus_space_tag_t btag[2];
1105 bus_space_handle_t bhandle[2];
1106 bus_dma_tag_t parent_dmat;
1107 bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */
1108 bus_dma_tag_t srb_dmat; /* dmat for freesrb */
1109 bus_dmamap_t srb_dmamap;
1111 struct cdev *ioctl_dev;
1114 struct resource *sys_res_arcmsr[2];
1115 struct resource *irqres;
1116 void *ih; /* interrupt handle */
1119 /* Hooks into the CAM XPT */
1120 struct cam_sim *psim;
1121 struct cam_path *ppath;
1122 u_int8_t *uncacheptr;
1123 unsigned long vir2phy_offset;
1125 unsigned long phyaddr;
1127 u_int32_t phyadd_low;
1128 u_int32_t phyadd_high;
1131 // unsigned long srb_phyaddr;
1132 /* Offset is used in making arc cdb physical to virtual calculations */
1133 u_int32_t outbound_int_enable;
1135 struct MessageUnit_UNION *pmu; /* message unit ATU inbound base address0 */
1137 u_int8_t adapter_index;
1139 u_int16_t acb_flags;
1141 struct CommandControlBlock *psrb_pool[ARCMSR_MAX_FREESRB_NUM]; /* serial srb pointer array */
1142 struct CommandControlBlock *srbworkingQ[ARCMSR_MAX_FREESRB_NUM]; /* working srb pointer array */
1143 int32_t workingsrb_doneindex; /* done srb array index */
1144 int32_t workingsrb_startindex; /* start srb array index */
1145 int32_t srboutstandingcount;
1147 u_int8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */
1148 u_int32_t rqbuf_firstindex; /* first of read buffer */
1149 u_int32_t rqbuf_lastindex; /* last of read buffer */
1151 u_int8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */
1152 u_int32_t wqbuf_firstindex; /* first of write buffer */
1153 u_int32_t wqbuf_lastindex; /* last of write buffer */
1155 arcmsr_lock_t isr_lock;
1156 arcmsr_lock_t srb_lock;
1157 arcmsr_lock_t postDone_lock;
1158 arcmsr_lock_t qbuffer_lock;
1160 u_int8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */
1161 u_int32_t num_resets;
1162 u_int32_t num_aborts;
1163 u_int32_t firm_request_len; /*1,04-07*/
1164 u_int32_t firm_numbers_queue; /*2,08-11*/
1165 u_int32_t firm_sdram_size; /*3,12-15*/
1166 u_int32_t firm_ide_channels; /*4,16-19*/
1167 u_int32_t firm_cfg_version;
1168 char firm_model[12]; /*15,60-67*/
1169 char firm_version[20]; /*17,68-83*/
1170 char device_map[20]; /*21,84-99 */
1171 struct callout devmap_callout;
1172 u_int32_t pktRequestCount;
1173 u_int32_t pktReturnCount;
1174 u_int32_t vendor_device_id;
1175 u_int32_t adapter_bus_speed;
1176 u_int32_t maxOutstanding;
1177 u_int16_t sub_device_id;
1178 };/* HW_DEVICE_EXTENSION */
1180 #define ACB_F_SCSISTOPADAPTER 0x0001
1181 #define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */
1182 #define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */
1183 #define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */
1184 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */
1185 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */
1186 #define ACB_F_MESSAGE_WQBUFFER_READ 0x0040
1187 #define ACB_F_BUS_RESET 0x0080
1188 #define ACB_F_IOP_INITED 0x0100 /* iop init */
1189 #define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb faild */
1190 #define ACB_F_CAM_DEV_QFRZN 0x0400
1191 #define ACB_F_BUS_HANG_ON 0x0800 /* need hardware reset bus */
1192 #define ACB_F_SRB_FUNCTION_POWER 0x1000
1194 #define ARECA_RAID_GONE 0x55
1195 #define ARECA_RAID_GOOD 0xaa
1196 /* adapter_bus_speed */
1197 #define ACB_BUS_SPEED_3G 0
1198 #define ACB_BUS_SPEED_6G 1
1199 #define ACB_BUS_SPEED_12G 2
1201 *************************************************************
1202 *************************************************************
1205 u_int8_t ErrorCode:7;
1207 u_int8_t SegmentNumber;
1208 u_int8_t SenseKey:4;
1209 u_int8_t Reserved:1;
1210 u_int8_t IncorrectLength:1;
1211 u_int8_t EndOfMedia:1;
1212 u_int8_t FileMark:1;
1213 u_int8_t Information[4];
1214 u_int8_t AdditionalSenseLength;
1215 u_int8_t CommandSpecificInformation[4];
1216 u_int8_t AdditionalSenseCode;
1217 u_int8_t AdditionalSenseCodeQualifier;
1218 u_int8_t FieldReplaceableUnitCode;
1219 u_int8_t SenseKeySpecific[3];
1222 **********************************
1223 ** Peripheral Device Type definitions
1224 **********************************
1226 #define SCSI_DASD 0x00 /* Direct-access Device */
1227 #define SCSI_SEQACESS 0x01 /* Sequential-access device */
1228 #define SCSI_PRINTER 0x02 /* Printer device */
1229 #define SCSI_PROCESSOR 0x03 /* Processor device */
1230 #define SCSI_WRITEONCE 0x04 /* Write-once device */
1231 #define SCSI_CDROM 0x05 /* CD-ROM device */
1232 #define SCSI_SCANNER 0x06 /* Scanner device */
1233 #define SCSI_OPTICAL 0x07 /* Optical memory device */
1234 #define SCSI_MEDCHGR 0x08 /* Medium changer device */
1235 #define SCSI_COMM 0x09 /* Communications device */
1236 #define SCSI_NODEV 0x1F /* Unknown or no device type */
1238 ************************************************************************************************************
1239 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1240 ** 80331 PCI-to-PCI Bridge
1241 ** PCI Configuration Space
1243 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1244 ** Programming Interface
1245 ** ========================
1246 ** Configuration Register Address Space Groupings and Ranges
1247 ** =============================================================
1248 ** Register Group Configuration Offset
1249 ** -------------------------------------------------------------
1250 ** Standard PCI Configuration 00-3Fh
1251 ** -------------------------------------------------------------
1252 ** Device Specific Registers 40-A7h
1253 ** -------------------------------------------------------------
1255 ** -------------------------------------------------------------
1256 ** Enhanced Capability List CC-FFh
1257 ** ==========================================================================================================
1258 ** Standard PCI [Type 1] Configuration Space Address Map
1259 ** **********************************************************************************************************
1260 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset
1261 ** ----------------------------------------------------------------------------------------------------------
1262 ** | Device ID | Vendor ID | 00h
1263 ** ----------------------------------------------------------------------------------------------------------
1264 ** | Primary Status | Primary Command | 04h
1265 ** ----------------------------------------------------------------------------------------------------------
1266 ** | Class Code | RevID | 08h
1267 ** ----------------------------------------------------------------------------------------------------------
1268 ** | reserved | Header Type | Primary MLT | Primary CLS | 0Ch
1269 ** ----------------------------------------------------------------------------------------------------------
1271 ** ----------------------------------------------------------------------------------------------------------
1273 ** ----------------------------------------------------------------------------------------------------------
1274 ** | Secondary MLT | Subordinate Bus Number | Secondary Bus Number | Primary Bus Number | 18h
1275 ** ----------------------------------------------------------------------------------------------------------
1276 ** | Secondary Status | I/O Limit | I/O Base | 1Ch
1277 ** ----------------------------------------------------------------------------------------------------------
1278 ** | Non-prefetchable Memory Limit Address | Non-prefetchable Memory Base Address | 20h
1279 ** ----------------------------------------------------------------------------------------------------------
1280 ** | Prefetchable Memory Limit Address | Prefetchable Memory Base Address | 24h
1281 ** ----------------------------------------------------------------------------------------------------------
1282 ** | Prefetchable Memory Base Address Upper 32 Bits | 28h
1283 ** ----------------------------------------------------------------------------------------------------------
1284 ** | Prefetchable Memory Limit Address Upper 32 Bits | 2Ch
1285 ** ----------------------------------------------------------------------------------------------------------
1286 ** | I/O Limit Upper 16 Bits | I/O Base Upper 16 | 30h
1287 ** ----------------------------------------------------------------------------------------------------------
1288 ** | Reserved | Capabilities Pointer | 34h
1289 ** ----------------------------------------------------------------------------------------------------------
1291 ** ----------------------------------------------------------------------------------------------------------
1292 ** | Bridge Control | Primary Interrupt Pin | Primary Interrupt Line | 3Ch
1293 **=============================================================================================================
1296 **=============================================================================================================
1298 ** Bit Default Description
1299 **31:16 0335h Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG.
1300 ** ID is unique per product speed as indicated.
1301 **15:00 8086h Vendor ID (VID): 16-bit field which indicates that Intel is the vendor.
1302 **=============================================================================================================
1304 #define ARCMSR_PCI2PCI_VENDORID_REG 0x00 /*word*/
1305 #define ARCMSR_PCI2PCI_DEVICEID_REG 0x02 /*word*/
1307 **==============================================================================
1308 ** 0x05-0x04 : command register
1309 ** Bit Default Description
1310 **15:11 00h Reserved
1311 ** 10 0 Interrupt Disable: Disables/Enables the generation of Interrupts on the primary bus.
1312 ** The bridge does not support interrupts.
1313 ** 09 0 FB2B Enable: Enables/Disables the generation of fast back to back
1314 ** transactions on the primary bus.
1315 ** The bridge does not generate fast back to back
1316 ** transactions on the primary bus.
1317 ** 08 0 SERR# Enable (SEE): Enables primary bus SERR# assertions.
1318 ** 0=The bridge does not assert P_SERR#.
1319 ** 1=The bridge may assert P_SERR#, subject to other programmable criteria.
1320 ** 07 0 Wait Cycle Control (WCC): Always returns 0bzero indicating
1321 ** that bridge does not perform address or data stepping,
1322 ** 06 0 Parity Error Response (PER): Controls bridge response to a detected primary bus parity error.
1323 ** 0=When a data parity error is detected bridge does not assert S_PERR#.
1324 ** Also bridge does not assert P_SERR# in response to
1325 ** a detected address or attribute parity error.
1326 ** 1=When a data parity error is detected bridge asserts S_PERR#.
1327 ** The bridge also asserts P_SERR#
1328 ** (when enabled globally via bit(8) of this register)
1329 ** in response to a detected address or attribute parity error.
1330 ** 05 0 VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible palette write transactions.
1331 ** VGA palette write transactions are I/O transactions
1332 ** whose address bits are: P_AD[9:0] equal to 3C6h, 3C8h or 3C9h
1333 ** P_AD[15:10] are not decoded (i.e. aliases are claimed),
1334 ** or are fully decoding
1335 ** (i.e., must be all 0's depending upon the VGA
1336 ** aliasing bit in the Bridge Control Register, offset 3Eh.
1337 ** P_AD[31:16] equal to 0000h
1338 ** 0=The bridge ignores VGA palette write transactions,
1339 ** unless decoded by the standard I/O address range window.
1340 ** 1=The bridge responds to VGA palette write transactions
1341 ** with medium DEVSEL# timing and forwards them to the secondary bus.
1342 ** 04 0 Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transactions to MWI transactions.
1343 ** MWI transactions targeting resources on the opposite side of the bridge,
1344 ** however, are forwarded as MWI transactions.
1345 ** 03 0 Special Cycle Enable (SCE): The bridge ignores special cycle transactions.
1346 ** This bit is read only and always returns 0 when read
1347 ** 02 0 Bus Master Enable (BME): Enables bridge to initiate memory and I/O transactions on the primary interface.
1348 ** Initiation of configuration transactions is not affected by the state of this bit.
1349 ** 0=The bridge does not initiate memory or I/O transactions on the primary interface.
1350 ** 1=The bridge is enabled to function as an initiator on the primary interface.
1351 ** 01 0 Memory Space Enable (MSE): Controls target response to memory transactions on the primary interface.
1352 ** 0=The bridge target response to memory transactions on the primary interface is disabled.
1353 ** 1=The bridge target response to memory transactions on the primary interface is enabled.
1354 ** 00 0 I/O Space Enable (IOSE): Controls target response to I/O transactions on the primary interface.
1355 ** 0=The bridge target response to I/O transactions on the primary interface is disabled.
1356 ** 1=The bridge target response to I/O transactions on the primary interface is enabled.
1357 **==============================================================================
1359 #define ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG 0x04 /*word*/
1360 #define PCI_DISABLE_INTERRUPT 0x0400
1362 **==============================================================================
1363 ** 0x07-0x06 : status register
1364 ** Bit Default Description
1365 ** 15 0 Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address,
1366 ** attribute or data parity error.
1367 ** This bit is set regardless of the state of the PER bit in the command register.
1368 ** 14 0 Signaled System Error: The bridge sets this bit to a 1b whenever it asserts SERR# on the primary bus.
1369 ** 13 0 Received Master Abort: The bridge sets this bit to a 1b when,
1370 ** acting as the initiator on the primary bus,
1371 ** its transaction (with the exception of special cycles)
1372 ** has been terminated with a Master Abort.
1373 ** 12 0 Received Target Abort: The bridge sets this bit to a 1b when,
1374 ** acting as the initiator on the primary bus,
1375 ** its transaction has been terminated with a Target Abort.
1376 ** 11 0 Signaled Target Abort: The bridge sets this bit to a 1b when it,
1377 ** as the target of a transaction, terminates it with a Target Abort.
1378 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code.
1379 ** 10:09 01 DEVSEL# Timing: Indicates slowest response to a non-configuration command on the primary interface.
1380 ** Returns ¡§01b¡¨ when read, indicating that bridge responds no slower than with medium timing.
1381 ** 08 0 Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true:
1382 ** The bridge is the current master on the primary bus
1383 ** S_PERR# is detected asserted or is asserted by bridge
1384 ** The Parity Error Response bit is set in the Command register
1385 ** 07 1 Fast Back to Back Capable: Returns a 1b when read indicating that bridge
1386 ** is able to respond to fast back to back transactions on its primary interface.
1388 ** 05 1 66 MHz Capable Indication: Returns a 1b when read indicating that bridge primary interface is 66 MHz capable.
1390 ** 04 1 Capabilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced capabilities.
1391 ** Offset 34h (Capability Pointer register)
1392 ** provides the offset for the first entry
1393 ** in the linked list of enhanced capabilities.
1394 ** 03 0 Interrupt Status: Reflects the state of the interrupt in the device/function.
1395 ** The bridge does not support interrupts.
1396 ** 02:00 000 Reserved
1397 **==============================================================================
1399 #define ARCMSR_PCI2PCI_PRIMARY_STATUS_REG 0x06 /*word: 06,07 */
1400 #define ARCMSR_ADAP_66MHZ 0x20
1402 **==============================================================================
1403 ** 0x08 : revision ID
1404 ** Bit Default Description
1405 ** 07:00 00000000 Revision ID (RID): '00h' indicating bridge A-0 stepping.
1406 **==============================================================================
1408 #define ARCMSR_PCI2PCI_REVISIONID_REG 0x08 /*byte*/
1410 **==============================================================================
1411 ** 0x0b-0x09 : 0180_00 (class code 1,native pci mode )
1412 ** Bit Default Description
1413 ** 23:16 06h Base Class Code (BCC): Indicates that this is a bridge device.
1414 ** 15:08 04h Sub Class Code (SCC): Indicates this is of type PCI-to-PCI bridge.
1415 ** 07:00 00h Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge.
1416 **==============================================================================
1418 #define ARCMSR_PCI2PCI_CLASSCODE_REG 0x09 /*3bytes*/
1420 **==============================================================================
1421 ** 0x0c : cache line size
1422 ** Bit Default Description
1423 ** 07:00 00h Cache Line Size (CLS): Designates the cache line size in 32-bit dword units.
1424 ** The contents of this register are factored into
1425 ** internal policy decisions associated with memory read prefetching,
1426 ** and the promotion of Memory Write transactions to MWI transactions.
1427 ** Valid cache line sizes are 8 and 16 dwords.
1428 ** When the cache line size is set to an invalid value,
1429 ** bridge behaves as though the cache line size was set to 00h.
1430 **==============================================================================
1432 #define ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C /*byte*/
1434 **==============================================================================
1435 ** 0x0d : latency timer (number of pci clock 00-ff )
1436 ** Bit Default Description
1437 ** Primary Latency Timer (PTV):
1438 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Primary bus Master latency timer. Indicates the number of PCI clock cycles,
1439 ** referenced from the assertion of FRAME# to the expiration of the timer,
1440 ** when bridge may continue as master of the current transaction. All bits are writable,
1441 ** resulting in a granularity of 1 PCI clock cycle.
1442 ** When the timer expires (i.e., equals 00h)
1443 ** bridge relinquishes the bus after the first data transfer
1444 ** when its PCI bus grant has been deasserted.
1445 ** or 40h (PCI-X) PCI-X Mode: Primary bus Master latency timer.
1446 ** Indicates the number of PCI clock cycles,
1447 ** referenced from the assertion of FRAME# to the expiration of the timer,
1448 ** when bridge may continue as master of the current transaction.
1449 ** All bits are writable, resulting in a granularity of 1 PCI clock cycle.
1450 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB.
1451 ** (Except in the case where MLT expires within 3 data phases
1452 ** of an ADB.In this case bridge continues on
1453 ** until it reaches the next ADB before relinquishing the bus.)
1454 **==============================================================================
1456 #define ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG 0x0D /*byte*/
1458 **==============================================================================
1459 ** 0x0e : (header type,single function )
1460 ** Bit Default Description
1461 ** 07 0 Multi-function device (MVD): 80331 is a single-function device.
1462 ** 06:00 01h Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space.
1463 ** Returns ¡§01h¡¨ when read indicating
1464 ** that the register layout conforms to the standard PCI-to-PCI bridge layout.
1465 **==============================================================================
1467 #define ARCMSR_PCI2PCI_HEADERTYPE_REG 0x0E /*byte*/
1469 **==============================================================================
1471 **==============================================================================
1474 **==============================================================================
1476 ** PCI CFG Base Address #0 (0x10)
1477 **==============================================================================
1480 **==============================================================================
1482 ** PCI CFG Base Address #1 (0x14)
1483 **==============================================================================
1486 **==============================================================================
1488 ** PCI CFG Base Address #2 (0x18)
1489 **-----------------0x1A,0x19,0x18--Bus Number Register - BNR
1490 ** Bit Default Description
1491 ** 23:16 00h Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below this bridge.
1492 ** Any Type 1 configuration cycle
1493 ** on the primary bus whose bus number is greater than the secondary bus number,
1494 ** and less than or equal to the subordinate bus number
1495 ** is forwarded unaltered as a Type 1 configuration cycle on the secondary PCI bus.
1496 ** 15:08 00h Secondary Bus Number (SCBN): Indicates the bus number of PCI to which the secondary interface is connected.
1497 ** Any Type 1 configuration cycle matching this bus number
1498 ** is translated to a Type 0 configuration cycle (or a Special Cycle)
1499 ** before being executed on bridge's secondary PCI bus.
1500 ** 07:00 00h Primary Bus Number (PBN): Indicates bridge primary bus number.
1501 ** Any Type 1 configuration cycle on the primary interface
1502 ** with a bus number that is less than the contents
1503 ** of this register field does not be claimed by bridge.
1504 **-----------------0x1B--Secondary Latency Timer Register - SLTR
1505 ** Bit Default Description
1506 ** Secondary Latency Timer (STV):
1507 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Secondary bus Master latency timer.
1508 ** Indicates the number of PCI clock cycles,
1509 ** referenced from the assertion of FRAME# to the expiration of the timer,
1510 ** when bridge may continue as master of the current transaction. All bits are writable,
1511 ** resulting in a granularity of 1 PCI clock cycle.
1512 ** When the timer expires (i.e., equals 00h)
1513 ** bridge relinquishes the bus after the first data transfer
1514 ** when its PCI bus grant has been deasserted.
1515 ** or 40h (PCI-X) PCI-X Mode: Secondary bus Master latency timer.
1516 ** Indicates the number of PCI clock cycles,referenced from the assertion of FRAME#
1517 ** to the expiration of the timer,
1518 ** when bridge may continue as master of the current transaction. All bits are writable,
1519 ** resulting in a granularity of 1 PCI clock cycle.
1520 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB.
1521 ** (Except in the case where MLT expires within 3 data phases of an ADB.
1522 ** In this case bridge continues on until it reaches the next ADB
1523 ** before relinquishing the bus)
1524 **==============================================================================
1526 #define ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG 0x18 /*3byte 0x1A,0x19,0x18*/
1527 #define ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG 0x19 /*byte*/
1528 #define ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG 0x1A /*byte*/
1529 #define ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG 0x1B /*byte*/
1531 **==============================================================================
1533 ** PCI CFG Base Address #3 (0x1C)
1534 **-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL
1535 ** Bit Default Description
1536 ** 15:12 0h I/O Limit Address Bits [15:12]: Defines the top address of an address range to
1537 ** determine when to forward I/O transactions from one interface to the other.
1538 ** These bits correspond to address lines 15:12 for 4KB alignment.
1539 ** Bits 11:0 are assumed to be FFFh.
1540 ** 11:08 1h I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit I/O addressing.
1541 ** 07:04 0h I/O Base Address Bits [15:12]: Defines the bottom address of
1542 ** an address range to determine when to forward I/O transactions
1543 ** from one interface to the other.
1544 ** These bits correspond to address lines 15:12 for 4KB alignment.
1545 ** Bits 11:0 are assumed to be 000h.
1546 ** 03:00 1h I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bit I/O addressing.
1547 **-----------------0x1F,0x1E--Secondary Status Register - SSR
1548 ** Bit Default Description
1549 ** 15 0b Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address,
1550 ** attribute or data parity error on its secondary interface.
1551 ** 14 0b Received System Error: The bridge sets this bit when it samples SERR# asserted on its secondary bus interface.
1552 ** 13 0b Received Master Abort: The bridge sets this bit to a 1b when,
1553 ** acting as the initiator on the secondary bus,
1554 ** it's transaction (with the exception of special cycles)
1555 ** has been terminated with a Master Abort.
1556 ** 12 0b Received Target Abort: The bridge sets this bit to a 1b when,
1557 ** acting as the initiator on the secondary bus,
1558 ** it's transaction has been terminated with a Target Abort.
1559 ** 11 0b Signaled Target Abort: The bridge sets this bit to a 1b when it,
1560 ** as the target of a transaction, terminates it with a Target Abort.
1561 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code.
1562 ** 10:09 01b DEVSEL# Timing: Indicates slowest response to a non-configuration command on the secondary interface.
1563 ** Returns ¡§01b¡¨ when read, indicating that bridge responds no slower than with medium timing.
1564 ** 08 0b Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true:
1565 ** The bridge is the current master on the secondary bus
1566 ** S_PERR# is detected asserted or is asserted by bridge
1567 ** The Parity Error Response bit is set in the Command register
1568 ** 07 1b Fast Back-to-Back Capable (FBC): Indicates that the secondary interface of bridge can receive fast back-to-back cycles.
1570 ** 05 1b 66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66 MHz capable.
1572 ** 04:00 00h Reserved
1573 **==============================================================================
1575 #define ARCMSR_PCI2PCI_IO_BASE_REG 0x1C /*byte*/
1576 #define ARCMSR_PCI2PCI_IO_LIMIT_REG 0x1D /*byte*/
1577 #define ARCMSR_PCI2PCI_SECONDARY_STATUS_REG 0x1E /*word: 0x1F,0x1E */
1579 **==============================================================================
1581 ** PCI CFG Base Address #4 (0x20)
1582 **-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL
1583 ** Bit Default Description
1584 ** 31:20 000h Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine
1585 ** the upper 1MB aligned value (exclusive) of the range.
1586 ** The incoming address must be less than or equal to this value.
1587 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]
1588 ** are assumed to be F FFFFh.
1589 ** 19:16 0h Reserved.
1590 ** 15:04 000h Memory Base: These 12 bits are compared with bits P_AD[31:20]
1591 ** of the incoming address to determine the lower 1MB
1592 ** aligned value (inclusive) of the range.
1593 ** The incoming address must be greater than or equal to this value.
1594 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0])
1595 ** are assumed to be 0 0000h.
1596 ** 03:00 0h Reserved.
1597 **==============================================================================
1599 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG 0x20 /*word: 0x21,0x20 */
1600 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG 0x22 /*word: 0x23,0x22 */
1602 **==============================================================================
1604 ** PCI CFG Base Address #5 (0x24)
1605 **-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL
1606 ** Bit Default Description
1607 ** 31:20 000h Prefetchable Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine
1608 ** the upper 1MB aligned value (exclusive) of the range.
1609 ** The incoming address must be less than or equal to this value.
1610 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]
1611 ** are assumed to be F FFFFh.
1612 ** 19:16 1h 64-bit Indicator: Indicates that 64-bit addressing is supported.
1613 ** 15:04 000h Prefetchable Memory Base: These 12 bits are compared with bits P_AD[31:20]
1614 ** of the incoming address to determine the lower 1MB aligned value (inclusive)
1616 ** The incoming address must be greater than or equal to this value.
1617 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0])
1618 ** are assumed to be 0 0000h.
1619 ** 03:00 1h 64-bit Indicator: Indicates that 64-bit addressing is supported.
1620 **==============================================================================
1622 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG 0x24 /*word: 0x25,0x24 */
1623 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG 0x26 /*word: 0x27,0x26 */
1625 **==============================================================================
1627 ** Bit Default Description
1628 ** 31:00 00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable
1629 ** bridge supports full 64-bit addressing.
1630 **==============================================================================
1632 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG 0x28 /*dword: 0x2b,0x2a,0x29,0x28 */
1634 **==============================================================================
1636 ** Bit Default Description
1637 ** 31:00 00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable
1638 ** bridge supports full 64-bit addressing.
1639 **==============================================================================
1641 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG 0x2C /*dword: 0x2f,0x2e,0x2d,0x2c */
1643 **==============================================================================
1645 ** Bit Default Description
1646 ** 07:00 DCh Capabilities Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration
1647 ** space. (Power Management Capability Registers)
1648 **==============================================================================
1650 #define ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG 0x34 /*byte*/
1652 **==============================================================================
1653 ** 0x3b-0x35 : reserved
1654 **==============================================================================
1657 **==============================================================================
1660 ** Bit Default Description
1661 ** 15:08 00h Interrupt Pin (PIN): Bridges do not support the generation of interrupts.
1662 ** 07:00 00h Interrupt Line (LINE): The bridge does not generate interrupts, so this is reserved as '00h'.
1663 **==============================================================================
1665 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG 0x3C /*byte*/
1666 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG 0x3D /*byte*/
1668 **==============================================================================
1670 ** Bit Default Description
1671 ** 15:12 0h Reserved
1672 ** 11 0b Discard Timer SERR# Enable: Controls the generation of SERR# on the primary interface (P_SERR#) in response
1673 ** to a timer discard on either the primary or secondary interface.
1674 ** 0b=SERR# is not asserted.
1675 ** 1b=SERR# is asserted.
1676 ** 10 0b Discard Timer Status (DTS): This bit is set to a '1b' when either the primary or secondary discard timer expires.
1677 ** The delayed completion is then discarded.
1678 ** 09 0b Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles
1679 ** that bridge waits for an initiator on the secondary bus
1680 ** to repeat a delayed transaction request.
1681 ** The counter starts when the delayed transaction completion is ready
1682 ** to be returned to the initiator.
1683 ** When the initiator has not repeated the transaction
1684 ** at least once before the counter expires,bridge
1685 ** discards the delayed transaction from its queues.
1686 ** 0b=The secondary master time-out counter is 2 15 PCI clock cycles.
1687 ** 1b=The secondary master time-out counter is 2 10 PCI clock cycles.
1688 ** 08 0b Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles
1689 ** that bridge waits for an initiator on the primary bus
1690 ** to repeat a delayed transaction request.
1691 ** The counter starts when the delayed transaction completion
1692 ** is ready to be returned to the initiator.
1693 ** When the initiator has not repeated the transaction
1694 ** at least once before the counter expires,
1695 ** bridge discards the delayed transaction from its queues.
1696 ** 0b=The primary master time-out counter is 2 15 PCI clock cycles.
1697 ** 1b=The primary master time-out counter is 2 10 PCI clock cycles.
1698 ** 07 0b Fast Back-to-Back Enable (FBE): The bridge does not initiate back to back transactions.
1699 ** 06 0b Secondary Bus Reset (SBR):
1700 ** When cleared to 0b: The bridge deasserts S_RST#,
1701 ** when it had been asserted by writing this bit to a 1b.
1702 ** When set to 1b: The bridge asserts S_RST#.
1703 ** 05 0b Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus
1704 ** when a master abort termination occurs in response to
1705 ** a delayed transaction initiated by bridge on the target bus.
1706 ** 0b=The bridge asserts TRDY# in response to a non-locked delayed transaction,
1707 ** and returns FFFF FFFFh when a read.
1708 ** 1b=When the transaction had not yet been completed on the initiator bus
1709 ** (e.g.,delayed reads, or non-posted writes),
1710 ** then bridge returns a Target Abort in response to the original requester
1711 ** when it returns looking for its delayed completion on the initiator bus.
1712 ** When the transaction had completed on the initiator bus (e.g., a PMW),
1713 ** then bridge asserts P_SERR# (when enabled).
1714 ** For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort
1715 ** while attempting to deliver a posted memory write on the destination bus.
1716 ** 04 0b VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit
1717 ** (also of this register),
1718 ** and the VGA Palette Snoop Enable bit (Command Register).
1719 ** When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b)
1720 ** the VGA Aliasing bit for the corresponding enabled functionality,:
1721 ** 0b=Ignores address bits AD[15:10] when decoding VGA I/O addresses.
1722 ** 1b=Ensures that address bits AD[15:10] equal 000000b when decoding VGA I/O addresses.
1723 ** When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b),
1724 ** then this bit has no impact on bridge behavior.
1725 ** 03 0b VGA Enable: Setting this bit enables address decoding
1726 ** and transaction forwarding of the following VGA transactions from the primary bus
1727 ** to the secondary bus:
1728 ** frame buffer memory addresses 000A0000h:000BFFFFh,
1729 ** VGA I/O addresses 3B0:3BBh and 3C0h:3DFh, where AD[31:16]=¡§0000h?** ?and AD[15:10] are either not decoded (i.e., don't cares),
1730 ** or must be ¡§000000b¡¨
1731 ** depending upon the state of the VGA Alias Filter Enable bit. (bit(4) of this register)
1732 ** I/O and Memory Enable bits must be set in the Command register
1733 ** to enable forwarding of VGA cycles.
1734 ** 02 0b ISA Enable: Setting this bit enables special handling
1735 ** for the forwarding of ISA I/O transactions that fall within the address range
1736 ** specified by the I/O Base and Limit registers,
1737 ** and are within the lowest 64Kbyte of the I/O address map
1738 ** (i.e., 0000 0000h - 0000 FFFFh).
1739 ** 0b=All I/O transactions that fall within the I/O Base
1740 ** and Limit registers' specified range are forwarded
1741 ** from primary to secondary unfiltered.
1742 ** 1b=Blocks the forwarding from primary to secondary
1743 ** of the top 768 bytes of each 1Kbyte alias.
1744 ** On the secondary the top 768 bytes of each 1K alias
1745 ** are inversely decoded and forwarded
1746 ** from secondary to primary.
1747 ** 01 0b SERR# Forward Enable: 0b=The bridge does not assert P_SERR# as a result of an S_SERR# assertion.
1748 ** 1b=The bridge asserts P_SERR# whenever S_SERR# is detected
1749 ** asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b).
1750 ** 00 0b Parity Error Response: This bit controls bridge response to a parity error
1751 ** that is detected on its secondary interface.
1752 ** 0b=When a data parity error is detected bridge does not assert S_PERR#.
1753 ** Also bridge does not assert P_SERR# in response to a detected address
1754 ** or attribute parity error.
1755 ** 1b=When a data parity error is detected bridge asserts S_PERR#.
1756 ** The bridge also asserts P_SERR# (when enabled globally via bit(8)
1757 ** of the Command register)
1758 ** in response to a detected address or attribute parity error.
1759 **==============================================================================
1761 #define ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG 0x3E /*word*/
1763 **************************************************************************
1764 ** Device Specific Registers 40-A7h
1765 **************************************************************************
1766 ** ----------------------------------------------------------------------------------------------------------
1767 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset
1768 ** ----------------------------------------------------------------------------------------------------------
1769 ** | Bridge Control 0 | Arbiter Control/Status | Reserved | 40h
1770 ** ----------------------------------------------------------------------------------------------------------
1771 ** | Bridge Control 2 | Bridge Control 1 | 44h
1772 ** ----------------------------------------------------------------------------------------------------------
1773 ** | Reserved | Bridge Status | 48h
1774 ** ----------------------------------------------------------------------------------------------------------
1776 ** ----------------------------------------------------------------------------------------------------------
1777 ** | Prefetch Policy | Multi-Transaction Timer | 50h
1778 ** ----------------------------------------------------------------------------------------------------------
1779 ** | Reserved | Pre-boot Status | P_SERR# Assertion Control | 54h
1780 ** ----------------------------------------------------------------------------------------------------------
1781 ** | Reserved | Reserved | Secondary Decode Enable | 58h
1782 ** ----------------------------------------------------------------------------------------------------------
1783 ** | Reserved | Secondary IDSEL | 5Ch
1784 ** ----------------------------------------------------------------------------------------------------------
1786 ** ----------------------------------------------------------------------------------------------------------
1787 ** | Reserved | 68h:CBh
1788 ** ----------------------------------------------------------------------------------------------------------
1789 **************************************************************************
1790 **==============================================================================
1791 ** 0x42-0x41: Secondary Arbiter Control/Status Register - SACSR
1792 ** Bit Default Description
1793 ** 15:12 1111b Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule
1794 ** (PCI=16 clocks,PCI-X=6 clocks).
1795 ** Note that this field is only meaningful when:
1796 ** # Bit[11] of this register is set to 1b,
1797 ** indicating that a Grant Time-out violation had occurred.
1798 ** # bridge internal arbiter is enabled.
1799 ** Bits[15:12] Violating Agent (REQ#/GNT# pair number)
1800 ** 0000b REQ#/GNT#[0]
1801 ** 0001b REQ#/GNT#[1]
1802 ** 0010b REQ#/GNT#[2]
1803 ** 0011b REQ#/GNT#[3]
1804 ** 1111b Default Value (no violation detected)
1805 ** When bit[11] is cleared by software, this field reverts back to its default value.
1806 ** All other values are Reserved
1807 ** 11 0b Grant Time-out Occurred: When set to 1b,
1808 ** this indicates that a Grant Time-out error had occurred involving one of the secondary bus agents.
1809 ** Software clears this bit by writing a 1b to it.
1810 ** 10 0b Bus Parking Control: 0=During bus idle, bridge parks the bus on the last master to use the bus.
1811 ** 1=During bus idle, bridge parks the bus on itself.
1812 ** The bus grant is removed from the last master and internally asserted to bridge.
1813 ** 09:08 00b Reserved
1814 ** 07:00 0000 0000b Secondary Bus Arbiter Priority Configuration: The bridge secondary arbiter provides two rings of arbitration priority.
1815 ** Each bit of this field assigns its corresponding secondary
1816 ** bus master to either the high priority arbiter ring (1b)
1817 ** or to the low priority arbiter ring (0b).
1818 ** Bits [3:0] correspond to request inputs S_REQ#[3:0], respectively.
1819 ** Bit [6] corresponds to the bridge internal secondary bus request
1820 ** while Bit [7] corresponds to the SATU secondary bus request.
1821 ** Bits [5:4] are unused.
1822 ** 0b=Indicates that the master belongs to the low priority group.
1823 ** 1b=Indicates that the master belongs to the high priority group
1824 **=================================================================================
1825 ** 0x43: Bridge Control Register 0 - BCR0
1826 ** Bit Default Description
1827 ** 07 0b Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight
1828 ** and the Posted Write data is limited to 4KB.
1829 ** 1=Operation in fully dynamic queue mode. The bridge enqueues up to
1830 ** 14 Posted Memory Write transactions and 8KB of posted write data.
1831 ** 06:03 0H Reserved.
1832 ** 02 0b Upstream Prefetch Disable: This bit disables bridge ability
1833 ** to perform upstream prefetch operations for Memory
1834 ** Read requests received on its secondary interface.
1835 ** This bit also controls the bridge's ability to generate advanced read commands
1836 ** when forwarding a Memory Read Block transaction request upstream from a PCI-X bus
1837 ** to a Conventional PCI bus.
1838 ** 0b=bridge treats all upstream Memory Read requests as though they target prefetchable memory.
1839 ** The use of Memory Read Line and Memory Read
1840 ** Multiple is enabled when forwarding a PCI-X Memory Read Block request
1841 ** to an upstream bus operating in Conventional PCI mode.
1842 ** 1b=bridge treats upstream PCI Memory Read requests as though
1843 ** they target non-prefetchable memory and forwards upstream PCI-X Memory
1844 ** Read Block commands as Memory Read
1845 ** when the primary bus is operating
1846 ** in Conventional PCI mode.
1847 ** NOTE: This bit does not affect bridge ability to perform read prefetching
1848 ** when the received command is Memory Read Line or Memory Read Multiple.
1849 **=================================================================================
1850 ** 0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2)
1851 ** Bit Default Description
1852 ** 15:08 0000000b Reserved
1853 ** 07:06 00b Alias Command Mapping: This two bit field determines how bridge handles PCI-X ¡§Alias¡¨ commands,
1854 ** specifically the Alias to Memory Read Block and Alias to Memory Write Block commands.
1855 ** The three options for handling these alias commands are to either pass it as is,
1856 ** re-map to the actual block memory read/write command encoding, or ignore
1857 ** the transaction forcing a Master Abort to occur on the Origination Bus.
1858 ** Bit (7:6) Handling of command
1859 ** 0 0 Re-map to Memory Read/Write Block before forwarding
1860 ** 0 1 Enqueue and forward the alias command code unaltered
1861 ** 1 0 Ignore the transaction, forcing Master Abort
1863 ** 05 1b Watchdog Timers Disable: Disables or enables all 2 24 Watchdog Timers in both directions.
1864 ** The watchdog timers are used to detect prohibitively long latencies in the system.
1865 ** The watchdog timer expires when any Posted Memory Write (PMW), Delayed Request,
1866 ** or Split Requests (PCI-X mode) is not completed within 2 24 events
1867 ** (¡§events¡¨ are defined as PCI Clocks when operating in PCI-X mode,
1868 ** and as the number of times being retried when operating in Conventional PCI mode)
1869 ** 0b=All 2 24 watchdog timers are enabled.
1870 ** 1b=All 2 24 watchdog timers are disabled and there is no limits to
1871 ** the number of attempts bridge makes when initiating a PMW,
1872 ** transacting a Delayed Transaction, or how long it waits for
1873 ** a split completion corresponding to one of its requests.
1874 ** 04 0b GRANT# time-out disable: This bit enables/disables the GNT# time-out mechanism.
1875 ** Grant time-out is 16 clocks for conventional PCI, and 6 clocks for PCI-X.
1876 ** 0b=The Secondary bus arbiter times out an agent
1877 ** that does not assert FRAME# within 16/6 clocks of receiving its grant,
1878 ** once the bus has gone idle.
1879 ** The time-out counter begins as soon as the bus goes idle with the new GNT# asserted.
1880 ** An infringing agent does not receive a subsequent GNT#
1881 ** until it de-asserts its REQ# for at least one clock cycle.
1882 ** 1b=GNT# time-out mechanism is disabled.
1884 ** 02 0b Secondary Discard Timer Disable: This bit enables/disables bridge secondary delayed transaction discard mechanism.
1885 ** The time out mechanism is used to ensure that initiators
1886 ** of delayed transactions return for their delayed completion data/status
1887 ** within a reasonable amount of time after it is available from bridge.
1888 ** 0b=The secondary master time-out counter is enabled
1889 ** and uses the value specified by the Secondary Discard Timer bit
1890 ** (see Bridge Control Register).
1891 ** 1b=The secondary master time-out counter is disabled.
1892 ** The bridge waits indefinitely for a secondary bus master
1893 ** to repeat a delayed transaction.
1894 ** 01 0b Primary Discard Timer Disable: This bit enables/disables bridge primary delayed transaction discard mechanism.
1895 ** The time out mechanism is used to ensure that initiators
1896 ** of delayed transactions return for their delayed completion data/status
1897 ** within a reasonable amount of time after it is available from bridge.
1898 ** 0b=The primary master time-out counter is enabled and uses the value specified
1899 ** by the Primary Discard Timer bit (see Bridge Control Register).
1900 ** 1b=The secondary master time-out counter is disabled.
1901 ** The bridge waits indefinitely for a secondary bus master
1902 ** to repeat a delayed transaction.
1904 **=================================================================================
1905 ** 0x47-0x46: Bridge Control Register 2 - BCR2
1906 ** Bit Default Description
1907 ** 15:07 0000b Reserved.
1908 ** 06 0b Global Clock Out Disable (External Secondary Bus Clock Source Enable):
1909 ** This bit disables all of the secondary PCI clock outputs including
1910 ** the feedback clock S_CLKOUT.
1911 ** This means that the user is required to provide an S_CLKIN input source.
1912 ** 05:04 11 (66 MHz) Preserved.
1915 ** 03:00 Fh (100 MHz & 66 MHz)
1917 ** This 4 bit field provides individual enable/disable mask bits for each of bridge
1918 ** secondary PCI clock outputs. Some, or all secondary clock outputs (S_CLKO[3:0])
1919 ** default to being enabled following the rising edge of P_RST#, depending on the
1920 ** frequency of the secondary bus clock:
1921 ** ¡E Designs with 100 MHz (or lower) Secondary PCI clock power up with
1922 ** all four S_CLKOs enabled by default. (SCLKO[3:0])¡P
1923 ** ¡E Designs with 133 MHz Secondary PCI clock power up
1924 ** with the lower order 3 S_CLKOs enabled by default.
1925 ** (S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected
1926 ** to downstream device clock inputs.
1927 **=================================================================================
1928 ** 0x49-0x48: Bridge Status Register - BSR
1929 ** Bit Default Description
1930 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR#
1931 ** is conditionally asserted when the secondary discard timer expires.
1932 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired:
1933 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR#
1934 ** is conditionally asserted when bridge discards an upstream delayed read ** ** transaction request after 2 24 retries following the initial retry.
1935 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted
1936 ** when bridge discards an upstream split read request
1937 ** after waiting in excess of 2 24 clocks for the corresponding
1938 ** Split Completion to arrive.
1939 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired:
1940 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR#
1941 ** is conditionally asserted when bridge discards an upstream delayed write ** ** transaction request after 2 24 retries following the initial retry.
1942 ** PCI-X Mode: This bit is set to a 1b and P_SERR#
1943 ** is conditionally asserted when bridge discards an upstream split write request ** after waiting in excess of 2 24 clocks for the corresponding
1944 ** Split Completion to arrive.
1945 ** 12 0b Master Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR#
1946 ** is conditionally asserted when a Master Abort occurs as a result of an attempt,
1947 ** by bridge, to retire a PMW upstream.
1948 ** 11 0b Target Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR#
1949 ** is conditionally asserted when a Target Abort occurs as a result of an attempt,
1950 ** by bridge, to retire a PMW upstream.
1951 ** 10 0b Upstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR#
1952 ** is conditionally asserted when bridge discards an upstream PMW transaction
1953 ** after receiving 2 24 target retries from the primary bus target
1954 ** 09 0b Upstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR#
1955 ** is conditionally asserted when a data parity error is detected by bridge
1956 ** while attempting to retire a PMW upstream
1957 ** 08 0b Secondary Bus Address Parity Error: This bit is set to a 1b and P_SERR#
1958 ** is conditionally asserted when bridge detects an address parity error on
1959 ** the secondary bus.
1960 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR#
1961 ** is conditionally asserted when the primary bus discard timer expires.
1962 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired:
1963 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR#
1964 ** is conditionally asserted when bridge discards a downstream delayed read ** ** transaction request after receiving 2 24 target retries
1965 ** from the secondary bus target.
1966 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted
1967 ** when bridge discards a downstream split read request
1968 ** after waiting in excess of 2 24 clocks for the corresponding
1969 ** Split Completion to arrive.
1970 ** 05 0b Downstream Delayed Write/Split Watchdog Timer Expired:
1971 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted
1972 ** when bridge discards a downstream delayed write transaction request
1973 ** after receiving 2 24 target retries from the secondary bus target.
1974 ** PCI-X Mode: This bit is set to a 1b and P_SERR#
1975 ** is conditionally asserted when bridge discards a downstream
1976 ** split write request after waiting in excess of 2 24 clocks
1977 ** for the corresponding Split Completion to arrive.
1978 ** 04 0b Master Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR#
1979 ** is conditionally asserted when a Master Abort occurs as a result of an attempt,
1980 ** by bridge, to retire a PMW downstream.
1981 ** 03 0b Target Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted
1982 ** when a Target Abort occurs as a result of an attempt, by bridge,
1983 ** to retire a PMW downstream.
1984 ** 02 0b Downstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR#
1985 ** is conditionally asserted when bridge discards a downstream PMW transaction
1986 ** after receiving 2 24 target retries from the secondary bus target
1987 ** 01 0b Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR#
1988 ** is conditionally asserted when a data parity error is detected by bridge
1989 ** while attempting to retire a PMW downstream.
1990 ** 00 0b Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted
1991 ** when bridge detects an address parity error on the primary bus.
1992 **==================================================================================
1993 ** 0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR
1994 ** Bit Default Description
1995 ** 15:13 000b Reserved
1996 ** 12:10 000b GRANT# Duration: This field specifies the count (PCI clocks)
1997 ** that a secondary bus master has its grant maintained in order to enable
1998 ** multiple transactions to execute within the same arbitration cycle.
1999 ** Bit[02:00] GNT# Extended Duration
2000 ** 000 MTT Disabled (Default=no GNT# extension)
2006 ** 110 Invalid (treated as 000)
2007 ** 111 Invalid (treated as 000)
2008 ** 09:08 00b Reserved
2009 ** 07:00 FFh MTT Mask: This field enables/disables MTT usage for each REQ#/GNT#
2010 ** pair supported by bridge secondary arbiter.
2011 ** Bit(7) corresponds to SATU internal REQ#/GNT# pair,
2012 ** bit(6) corresponds to bridge internal REQ#/GNT# pair,
2013 ** bit(5) corresponds to REQ#/GNT#(5) pair, etc.
2014 ** When a given bit is set to 1b, its corresponding REQ#/GNT#
2015 ** pair is enabled for MTT functionality as determined by bits(12:10) of this register.
2016 ** When a given bit is cleared to 0b, its corresponding REQ#/GNT# pair is disabled from using the MTT.
2017 **==================================================================================
2018 ** 0x53-0x52: Read Prefetch Policy Register - RPPR
2019 ** Bit Default Description
2020 ** 15:13 000b ReRead_Primary Bus: 3-bit field indicating the multiplication factor
2021 ** to be used in calculating the number of bytes to prefetch from the secondary bus interface on ** subsequent PreFetch operations given that the read demands were not satisfied
2022 ** using the FirstRead parameter.
2023 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs
2024 ** Memory Read Line 1 cache lines Memory Read Multiple 2 cache lines
2025 ** 12:10 000b FirstRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating
2026 ** the number of bytes to prefetch from the secondary bus interface
2027 ** on the initial PreFetch operation.
2028 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs
2029 ** Memory Read Line 1 cache line Memory Read Multiple 2 cache lines
2030 ** 09:07 010b ReRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used
2031 ** in calculating the number of bytes to prefetch from the primary
2032 ** bus interface on subsequent PreFetch operations given
2033 ** that the read demands were not satisfied using
2034 ** the FirstRead parameter.
2035 ** The default value of 010b correlates to: Command Type Hardwired pre-fetch a
2036 ** mount Memory Read 3 cache lines Memory Read Line 3 cache lines
2037 ** Memory Read Multiple 6 cache lines
2038 ** 06:04 000b FirstRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used
2039 ** in calculating the number of bytes to prefetch from
2040 ** the primary bus interface on the initial PreFetch operation.
2041 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount
2042 ** Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines
2043 ** 03:00 1111b Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch
2044 ** algorithm for the secondary and the primary bus interfaces.
2045 ** Bit(3) is a ganged enable bit for REQ#/GNT#[7:3], and bits(2:0) provide individual
2046 ** enable bits for REQ#/GNT#[2:0].
2047 ** (bit(2) is the enable bit for REQ#/GNT#[2], etc...)
2048 ** 1b: enables the staged pre-fetch feature
2049 ** 0b: disables staged pre-fetch,
2050 ** and hardwires read pre-fetch policy to the following for
2052 ** Memory Read Line,
2053 ** and Memory Read Multiple commands:
2054 ** Command Type Hardwired Pre-Fetch Amount...
2055 ** Memory Read 4 DWORDs
2056 ** Memory Read Line 1 cache line
2057 ** Memory Read Multiple 2 cache lines
2058 ** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands
2059 ** only to the next higher cache line boundary.For non-cache line aligned Memory Read
2060 ** Multiple commands bridge pre-fetches only to the second cache line boundary encountered.
2061 **==================================================================================
2062 ** 0x55-0x54: P_SERR# Assertion Control - SERR_CTL
2063 ** Bit Default Description
2064 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior
2065 ** in response to its discarding of a delayed transaction that was initiated from the primary bus.
2066 ** 0b=bridge asserts P_SERR#.
2067 ** 1b=bridge does not assert P_SERR#
2068 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
2069 ** 0b=bridge asserts P_SERR#.
2070 ** 1b=bridge does not assert P_SERR#
2071 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
2072 ** 0b=bridge asserts P_SERR#.
2073 ** 1b=bridge does not assert P_SERR#
2074 ** 12 0b Master Abort during Upstream Posted Write: Dictates bridge behavior following
2075 ** its having detected a Master Abort while attempting to retire one of its PMWs upstream.
2076 ** 0b=bridge asserts P_SERR#.
2077 ** 1b=bridge does not assert P_SERR#
2078 ** 11 0b Target Abort during Upstream Posted Write: Dictates bridge behavior following
2079 ** its having been terminated with Target Abort while attempting to retire one of its PMWs upstream.
2080 ** 0b=bridge asserts P_SERR#.
2081 ** 1b=bridge does not assert P_SERR#
2082 ** 10 0b Upstream Posted Write Data Discarded: Dictates bridge behavior in the event that
2083 ** it discards an upstream posted write transaction.
2084 ** 0b=bridge asserts P_SERR#.
2085 ** 1b=bridge does not assert P_SERR#
2086 ** 09 0b Upstream Posted Write Data Parity Error: Dictates bridge behavior
2087 ** when a data parity error is detected while attempting to retire on of its PMWs upstream.
2088 ** 0b=bridge asserts P_SERR#.
2089 ** 1b=bridge does not assert P_SERR#
2090 ** 08 0b Secondary Bus Address Parity Error: This bit dictates bridge behavior
2091 ** when it detects an address parity error on the secondary bus.
2092 ** 0b=bridge asserts P_SERR#.
2093 ** 1b=bridge does not assert P_SERR#
2094 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior in response to
2095 ** its discarding of a delayed transaction that was initiated on the secondary bus.
2096 ** 0b=bridge asserts P_SERR#.
2097 ** 1b=bridge does not assert P_SERR#
2098 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
2099 ** 0b=bridge asserts P_SERR#.
2100 ** 1b=bridge does not assert P_SERR#
2101 ** 05 0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
2102 ** 0b=bridge asserts P_SERR#.
2103 ** 1b=bridge does not assert P_SERR#
2104 ** 04 0b Master Abort during Downstream Posted Write: Dictates bridge behavior following
2105 ** its having detected a Master Abort while attempting to retire one of its PMWs downstream.
2106 ** 0b=bridge asserts P_SERR#.
2107 ** 1b=bridge does not assert P_SERR#
2108 ** 03 0b Target Abort during Downstream Posted Write: Dictates bridge behavior following
2109 ** its having been terminated with Target Abort while attempting to retire one of its PMWs downstream.
2110 ** 0b=bridge asserts P_SERR#.
2111 ** 1b=bridge does not assert P_SERR#
2112 ** 02 0b Downstream Posted Write Data Discarded: Dictates bridge behavior in the event
2113 ** that it discards a downstream posted write transaction.
2114 ** 0b=bridge asserts P_SERR#.
2115 ** 1b=bridge does not assert P_SERR#
2116 ** 01 0b Downstream Posted Write Data Parity Error: Dictates bridge behavior
2117 ** when a data parity error is detected while attempting to retire on of its PMWs downstream.
2118 ** 0b=bridge asserts P_SERR#.
2119 ** 1b=bridge does not assert P_SERR#
2120 ** 00 0b Primary Bus Address Parity Error: This bit dictates bridge behavior
2121 ** when it detects an address parity error on the primary bus.
2122 ** 0b=bridge asserts P_SERR#.
2123 ** 1b=bridge does not assert P_SERR#
2124 **===============================================================================
2125 ** 0x56: Pre-Boot Status Register - PBSR
2126 ** Bit Default Description
2128 ** 06 - Reserved - value indeterminate
2130 ** 01 Varies with External State of S_133EN at PCI Bus Reset Secondary Bus Max Frequency Setting:
2131 ** This bit reflect captured S_133EN strap,
2132 ** indicating the maximum secondary bus clock frequency when in PCI-X mode.
2133 ** Max Allowable Secondary Bus Frequency
2134 ** ** S_133EN PCI-X Mode
2138 **===============================================================================
2139 ** 0x59-0x58: Secondary Decode Enable Register - SDER
2140 ** Bit Default Description
2141 ** 15:03 FFF1h Preserved.
2142 ** 02 Varies with External State of PRIVMEM at PCI Bus Reset Private Memory Space Enable - when set,
2143 ** bridge overrides its secondary inverse decode logic and not
2144 ** forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b.
2145 ** This creates a private memory space on the Secondary PCI bus
2146 ** that allows peer-to-peer transactions.
2147 ** 01:00 10 2 Preserved.
2148 **===============================================================================
2149 ** 0x5D-0x5C: Secondary IDSEL Select Register - SISR
2150 ** Bit Default Description
2151 ** 15:10 000000 2 Reserved.
2152 ** 09 Varies with External State of PRIVDEV at PCI Bus Reset AD25- IDSEL Disable - When this bit is set,
2153 ** AD25 is deasserted for any possible Type 1 to Type 0 conversion.
2154 ** When this bit is clear,
2155 ** AD25 is asserted when Primary addresses AD[15:11]=01001 2 during a Type 1 to Type 0 conversion.
2156 ** 08 Varies with External State of PRIVDEV at PCI Bus Reset AD24- IDSEL Disable - When this bit is set,
2157 ** AD24 is deasserted for any possible Type 1 to Type 0 conversion.
2158 ** When this bit is clear,
2159 ** AD24 is asserted when Primary addresses AD[15:11]=01000 2 during a Type 1 to Type 0 conversion.
2160 ** 07 Varies with External State of PRIVDEV at PCI Bus Reset AD23- IDSEL Disable - When this bit is set,
2161 ** AD23 is deasserted for any possible Type 1 to Type 0 conversion.
2162 ** When this bit is clear,
2163 ** AD23 is asserted when Primary addresses AD[15:11]=00111 2 during a Type 1 to Type 0 conversion.
2164 ** 06 Varies with External State of PRIVDEV at PCI Bus Reset AD22- IDSEL Disable - When this bit is set,
2165 ** AD22 is deasserted for any possible Type 1 to Type 0 conversion.
2166 ** When this bit is clear,
2167 ** AD22 is asserted when Primary addresses AD[15:11]=00110 2 during a Type 1 to Type 0 conversion.
2168 ** 05 Varies with External State of PRIVDEV at PCI Bus Reset AD21- IDSEL Disable - When this bit is set,
2169 ** AD21 is deasserted for any possible Type 1 to Type 0 conversion.
2170 ** When this bit is clear,
2171 ** AD21 is asserted when Primary addresses AD[15:11]=00101 2 during a Type 1 to Type 0 conversion.
2172 ** 04 Varies with External State of PRIVDEV at PCI Bus Reset AD20- IDSEL Disable - When this bit is set,
2173 ** AD20 is deasserted for any possible Type 1 to Type 0 conversion.
2174 ** When this bit is clear,
2175 ** AD20 is asserted when Primary addresses AD[15:11]=00100 2 during a Type 1 to Type 0 conversion.
2176 ** 03 Varies with External State of PRIVDEV at PCI Bus Reset AD19- IDSEL Disable - When this bit is set,
2177 ** AD19 is deasserted for any possible Type 1 to Type 0 conversion.
2178 ** When this bit is clear,
2179 ** AD19 is asserted when Primary addresses AD[15:11]=00011 2 during a Type 1 to Type 0 conversion.
2180 ** 02 Varies with External State of PRIVDEV at PCI Bus Reset AD18- IDSEL Disable - When this bit is set,
2181 ** AD18 is deasserted for any possible Type 1 to Type 0 conversion.
2182 ** When this bit is clear,
2183 ** AD18 is asserted when Primary addresses AD[15:11]=00010 2 during a Type 1 to Type 0 conversion.
2184 ** 01 Varies with External State of PRIVDEV at PCI Bus Reset AD17- IDSEL Disable - When this bit is set,
2185 ** AD17 is deasserted for any possible Type 1 to Type 0 conversion.
2186 ** When this bit is clear,
2187 ** AD17 is asserted when Primary addresses AD[15:11]=00001 2 during a Type 1 to Type 0 conversion.
2188 ** 00 Varies with External State of PRIVDEV at PCI Bus Reset AD16- IDSEL Disable - When this bit is set,
2189 ** AD16 is deasserted for any possible Type 1 to Type 0 conversion.
2190 ** When this bit is clear,
2191 ** AD16 is asserted when Primary addresses AD[15:11]=00000 2 during a Type 1 to Type 0 conversion.
2192 **************************************************************************
2195 **************************************************************************
2197 **************************************************************************
2200 **************************************************************************
2201 ** PCI Extended Enhanced Capabilities List CC-FFh
2202 **************************************************************************
2203 ** ----------------------------------------------------------------------------------------------------------
2204 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset
2205 ** ----------------------------------------------------------------------------------------------------------
2206 ** | Power Management Capabilities | Next Item Ptr | Capability ID | DCh
2207 ** ----------------------------------------------------------------------------------------------------------
2208 ** | PM Data | PPB Support | Extensions Power Management CSR | E0h
2209 ** ----------------------------------------------------------------------------------------------------------
2210 ** | Reserved | Reserved | Reserved | E4h
2211 ** ----------------------------------------------------------------------------------------------------------
2213 ** ----------------------------------------------------------------------------------------------------------
2214 ** | Reserved | Reserved | Reserved | Reserved | ECh
2215 ** ----------------------------------------------------------------------------------------------------------
2216 ** | PCI-X Secondary Status | Next Item Ptr | Capability ID | F0h
2217 ** ----------------------------------------------------------------------------------------------------------
2218 ** | PCI-X Bridge Status | F4h
2219 ** ----------------------------------------------------------------------------------------------------------
2220 ** | PCI-X Upstream Split Transaction Control | F8h
2221 ** ----------------------------------------------------------------------------------------------------------
2222 ** | PCI-X Downstream Split Transaction Control | FCh
2223 ** ----------------------------------------------------------------------------------------------------------
2224 **===============================================================================
2225 ** 0xDC: Power Management Capabilities Identifier - PM_CAPID
2226 ** Bit Default Description
2227 ** 07:00 01h Identifier (ID): PCI SIG assigned ID for PCI-PM register block
2228 **===============================================================================
2229 ** 0xDD: Next Item Pointer - PM_NXTP
2230 ** Bit Default Description
2231 ** 07:00 F0H Next Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capability Header.
2232 **===============================================================================
2233 ** 0xDF-0xDE: Power Management Capabilities Register - PMCR
2234 ** Bit Default Description
2235 ** 15:11 00h PME Supported (PME): PME# cannot be asserted by bridge.
2236 ** 10 0h State D2 Supported (D2): Indicates no support for state D2. No power management action in this state.
2237 ** 09 1h State D1 Supported (D1): Indicates support for state D1. No power management action in this state.
2238 ** 08:06 0h Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function.
2239 ** This returns 000b as PME# wake-up for bridge is not implemented.
2240 ** 05 0 Special Initialization Required (SINT): Special initialization is not required for bridge.
2241 ** 04:03 00 Reserved
2242 ** 02:00 010 Version (VS): Indicates that this supports PCI Bus Power Management Interface Specification, Revision 1.1.
2243 **===============================================================================
2244 ** 0xE1-0xE0: Power Management Control / Status - Register - PMCSR
2245 ** Bit Default Description
2246 ** 15:09 00h Reserved
2247 ** 08 0b PME_Enable: This bit, when set to 1b enables bridge to assert PME#.
2248 ** Note that bridge never has occasion to assert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug.
2249 ** 07:02 00h Reserved
2250 ** 01:00 00 Power State (PSTATE): This 2-bit field is used both to determine the current power state of
2251 ** a function and to set the Function into a new power state.
2255 ** 11 - D3 hot state
2256 **===============================================================================
2257 ** 0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE
2258 ** Bit Default Description
2259 ** 07 0 Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clock control policies have been disabled.
2260 ** 06 0 B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that
2261 ** is to occur as a direct result of programming the function to D3 hot.
2262 ** This bit is only meaningful when bit 7 (BPCC_En) is a ¡§1¡¨.
2263 ** 05:00 00h Reserved
2264 **===============================================================================
2265 ** 0xE3: Power Management Data Register - PMDR
2266 ** Bit Default Description
2267 ** 07:00 00h Reserved
2268 **===============================================================================
2269 ** 0xF0: PCI-X Capabilities Identifier - PX_CAPID
2270 ** Bit Default Description
2271 ** 07:00 07h Identifier (ID): Indicates this is a PCI-X capabilities list.
2272 **===============================================================================
2273 ** 0xF1: Next Item Pointer - PX_NXTP
2274 ** Bit Default Description
2275 ** 07:00 00h Next Item Pointer: Points to the next capability in the linked list The power on default value of this
2276 ** register is 00h indicating that this is the last entry in the linked list of capabilities.
2277 **===============================================================================
2278 ** 0xF3-0xF2: PCI-X Secondary Status - PX_SSTS
2279 ** Bit Default Description
2280 ** 15:09 00h Reserved
2281 ** 08:06 Xxx Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus.
2283 ** ** BitsMax FrequencyClock Period
2284 ** ** 000PCI ModeN/A
2288 ** ** 1xxreservedreserved
2289 ** ** The default value for this register is the operating frequency of the secondary bus
2290 ** 05 0b Split Request Delayed. (SRD): This bit is supposed to be set by a bridge when it cannot forward a transaction on the
2291 ** secondary bus to the primary bus because there is not enough room within the limit
2292 ** specified in the Split Transaction Commitment Limit field in the Downstream Split
2293 ** Transaction Control register. The bridge does not set this bit.
2294 ** 04 0b Split Completion Overrun (SCO): This bit is supposed to be set when a bridge terminates a Split Completion on the ** ** secondary bus with retry or Disconnect at next ADB because its buffers are full.
2295 ** The bridge does not set this bit.
2296 ** 03 0b Unexpected Split Completion (USC): This bit is set when an unexpected split completion with a requester ID
2297 ** equal to bridge secondary bus number, device number 00h,
2298 ** and function number 0 is received on the secondary interface.
2299 ** This bit is cleared by software writing a '1'.
2300 ** 02 0b Split Completion Discarded (SCD): This bit is set
2301 ** when bridge discards a split completion moving toward the secondary bus
2302 ** because the requester would not accept it. This bit cleared by software writing a '1'.
2303 ** 01 1b 133 MHz Capable: Indicates that bridge is capable of running its secondary bus at 133 MHz
2304 ** 00 1b 64-bit Device (D64): Indicates the width of the secondary bus as 64-bits.
2305 **===============================================================================
2306 ** 0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS
2307 ** Bit Default Description
2309 ** 21 0 Split Request Delayed (SRD): This bit does not be set by bridge.
2310 ** 20 0 Split Completion Overrun (SCO): This bit does not be set by bridge
2311 ** because bridge throttles traffic on the completion side.
2312 ** 19 0 Unexpected Split Completion (USC): The bridge sets this bit to 1b
2313 ** when it encounters a corrupted Split Completion, possibly with an ** ** inconsistent remaining byte count.Software clears
2314 ** this bit by writing a 1b to it.
2315 ** 18 0 Split Completion Discarded (SCD): The bridge sets this bit to 1b
2316 ** when it has discarded a Split Completion.Software clears this bit by ** ** writing a 1b to it.
2317 ** 17 1 133 MHz Capable: This bit indicates that the bridge primary interface is ** capable of 133 MHz operation in PCI-X mode.
2318 ** 0=The maximum operating frequency is 66 MHz.
2319 ** 1=The maximum operating frequency is 133 MHz.
2320 ** 16 Varies with the external state of P_32BITPCI# at PCI Bus Reset 64-bit Device (D64): Indicates bus width of the Primary PCI bus interface.
2321 ** 0=Primary Interface is connected as a 32-bit PCI bus.
2322 ** 1=Primary Interface is connected as a 64-bit PCI bus.
2323 ** 15:08 00h Bus Number (BNUM): This field is simply an alias to the PBN field
2324 ** of the BNUM register at offset 18h.
2325 ** Apparently it was deemed necessary reflect it here for diagnostic purposes.
2326 ** 07:03 1fh Device Number (DNUM): Indicates which IDSEL bridge consumes.
2327 ** May be updated whenever a PCI-X
2328 ** configuration write cycle that targets bridge scores a hit.
2329 ** 02:00 0h Function Number (FNUM): The bridge Function #
2330 **===============================================================================
2331 ** 0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC
2332 ** Bit Default Description
2333 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs.
2334 ** Software is permitted to program this register to any value greater than or equal to
2335 ** the contents of the Split Transaction Capacity register. A value less than the contents
2336 ** of the Split Transaction Capacity register causes unspecified results.
2337 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any
2338 ** size regardless of the amount of buffer space available.
2339 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing
2340 ** split completions. This register controls behavior of the bridge buffers for forwarding
2341 ** Split Transactions from a primary bus requester to a secondary bus completer.
2342 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes).
2343 **===============================================================================
2344 ** 0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC
2345 ** Bit Default Description
2346 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs.
2347 ** Software is permitted to program this register to any value greater than or equal to
2348 ** the contents of the Split Transaction Capacity register. A value less than the contents
2349 ** of the Split Transaction Capacity register causes unspecified results.
2350 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any
2351 ** size regardless of the amount of buffer space available.
2352 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing
2353 ** split completions. This register controls behavior of the bridge buffers for forwarding
2354 ** Split Transactions from a primary bus requester to a secondary bus completer.
2355 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs
2357 **************************************************************************
2364 *************************************************************************************************************************************
2365 ** 80331 Address Translation Unit Register Definitions
2366 ** ATU Interface Configuration Header Format
2367 ** The ATU is programmed via a [Type 0] configuration command on the PCI interface.
2368 *************************************************************************************************************************************
2369 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configuration Byte Offset
2370 **===================================================================================================================================
2371 ** | ATU Device ID | Vendor ID | 00h
2372 ** ----------------------------------------------------------------------------------------------------------
2373 ** | Status | Command | 04H
2374 ** ----------------------------------------------------------------------------------------------------------
2375 ** | ATU Class Code | Revision ID | 08H
2376 ** ----------------------------------------------------------------------------------------------------------
2377 ** | ATUBISTR | Header Type | Latency Timer | Cacheline Size | 0CH
2378 ** ----------------------------------------------------------------------------------------------------------
2379 ** | Inbound ATU Base Address 0 | 10H
2380 ** ----------------------------------------------------------------------------------------------------------
2381 ** | Inbound ATU Upper Base Address 0 | 14H
2382 ** ----------------------------------------------------------------------------------------------------------
2383 ** | Inbound ATU Base Address 1 | 18H
2384 ** ----------------------------------------------------------------------------------------------------------
2385 ** | Inbound ATU Upper Base Address 1 | 1CH
2386 ** ----------------------------------------------------------------------------------------------------------
2387 ** | Inbound ATU Base Address 2 | 20H
2388 ** ----------------------------------------------------------------------------------------------------------
2389 ** | Inbound ATU Upper Base Address 2 | 24H
2390 ** ----------------------------------------------------------------------------------------------------------
2392 ** ----------------------------------------------------------------------------------------------------------
2393 ** | ATU Subsystem ID | ATU Subsystem Vendor ID | 2CH
2394 ** ----------------------------------------------------------------------------------------------------------
2395 ** | Expansion ROM Base Address | 30H
2396 ** ----------------------------------------------------------------------------------------------------------
2397 ** | Reserved Capabilities Pointer | 34H
2398 ** ----------------------------------------------------------------------------------------------------------
2400 ** ----------------------------------------------------------------------------------------------------------
2401 ** | Maximum Latency | Minimum Grant | Interrupt Pin | Interrupt Line | 3CH
2402 ** ----------------------------------------------------------------------------------------------------------
2403 *********************************************************************************************************************
2406 ***********************************************************************************
2407 ** ATU Vendor ID Register - ATUVID
2408 ** -----------------------------------------------------------------
2409 ** Bit Default Description
2410 ** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Intel.
2411 ** This register, combined with the DID, uniquely identify the PCI device.
2412 ** Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID
2413 ** to simulate the interface of a standard mechanism currently used by existing application software.
2414 ***********************************************************************************
2416 #define ARCMSR_ATU_VENDOR_ID_REG 0x00 /*word*/
2418 ***********************************************************************************
2419 ** ATU Device ID Register - ATUDID
2420 ** -----------------------------------------------------------------
2421 ** Bit Default Description
2422 ** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the ATU.
2423 ** This ID, combined with the VID, uniquely identify any PCI device.
2424 ***********************************************************************************
2426 #define ARCMSR_ATU_DEVICE_ID_REG 0x02 /*word*/
2428 ***********************************************************************************
2429 ** ATU Command Register - ATUCMD
2430 ** -----------------------------------------------------------------
2431 ** Bit Default Description
2432 ** 15:11 000000 2 Reserved
2433 ** 10 0 Interrupt Disable - This bit disables 80331 from asserting the ATU interrupt signal.
2434 ** 0=enables the assertion of interrupt signal.
2435 ** 1=disables the assertion of its interrupt signal.
2436 ** 09 0 2 Fast Back to Back Enable - When cleared,
2437 ** the ATU interface is not allowed to generate fast back-to-back cycles on its bus.
2438 ** Ignored when operating in the PCI-X mode.
2439 ** 08 0 2 SERR# Enable - When cleared, the ATU interface is not allowed to assert SERR# on the PCI interface.
2440 ** 07 1 2 Address/Data Stepping Control - Address stepping is implemented for configuration transactions. The
2441 ** ATU inserts 2 clock cycles of address stepping for Conventional Mode and 4 clock cycles
2442 ** of address stepping for PCI-X mode.
2443 ** 06 0 2 Parity Error Response - When set, the ATU takes normal action when a parity error
2444 ** is detected. When cleared, parity checking is disabled.
2445 ** 05 0 2 VGA Palette Snoop Enable - The ATU interface does not support I/O writes and therefore,
2446 ** does not perform VGA palette snooping.
2447 ** 04 0 2 Memory Write and Invalidate Enable - When set, ATU may generate MWI commands.
2448 ** When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode.
2449 ** 03 0 2 Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way.
2450 ** Not implemented and a reserved bit field.
2451 ** 02 0 2 Bus Master Enable - The ATU interface can act as a master on the PCI bus.
2452 ** When cleared, disables the device from generating PCI accesses.
2453 ** When set, allows the device to behave as a PCI bus master.
2454 ** When operating in the PCI-X mode, ATU initiates a split completion transaction regardless
2455 ** of the state of this bit.
2456 ** 01 0 2 Memory Enable - Controls the ATU interface¡¦s response to PCI memory addresses.
2457 ** When cleared, the ATU interface does not respond to any memory access on the PCI bus.
2458 ** 00 0 2 I/O Space Enable - Controls the ATU interface response to I/O transactions.
2459 ** Not implemented and a reserved bit field.
2460 ***********************************************************************************
2462 #define ARCMSR_ATU_COMMAND_REG 0x04 /*word*/
2464 ***********************************************************************************
2465 ** ATU Status Register - ATUSR (Sheet 1 of 2)
2466 ** -----------------------------------------------------------------
2467 ** Bit Default Description
2468 ** 15 0 2 Detected Parity Error - set when a parity error is detected in data received by the ATU on the PCI bus even
2469 ** when the ATUCMD register¡¦s Parity Error Response bit is cleared. Set under the following conditions:
2470 ** ¡E Write Data Parity Error when the ATU is a target (inbound write).
2471 ** ¡E Read Data Parity Error when the ATU is a requester (outbound read).
2472 ** ¡E Any Address or Attribute (PCI-X Only) Parity Error on the Bus ** ** ** (including one generated by the ATU).
2473 ** 14 0 2 SERR# Asserted - set when SERR# is asserted on the PCI bus by the ATU.
2474 ** 13 0 2 Master Abort - set when a transaction initiated by the ATU PCI master interface, ends in a Master-Abort
2475 ** or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode.
2476 ** 12 0 2 Target Abort (master) - set when a transaction initiated by the ATU PCI master interface, ends in a target
2477 ** abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode.
2478 ** 11 0 2 Target Abort (target) - set when the ATU interface, acting as a target,
2479 ** terminates the transaction on the PCI bus with a target abort.
2480 ** 10:09 01 2 DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL#
2481 ** timing for a target device in Conventional PCI Mode regardless of the operating mode
2482 ** (except configuration accesses).
2487 ** The ATU interface uses Medium timing.
2488 ** 08 0 2 Master Parity Error - The ATU interface sets this bit under the following conditions:
2489 ** ¡E The ATU asserted PERR# itself or the ATU observed PERR# asserted.
2490 ** ¡E And the ATU acted as the requester
2491 ** for the operation in which the error occurred.
2492 ** ¡E And the ATUCMD register¡¦s Parity Error Response bit is set
2493 ** ¡E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message
2494 ** ¡E And the ATUCMD register¡¦s Parity Error Response bit is set
2495 ** 07 1 2 (Conventional mode)
2497 ** Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-to-back
2498 ** transactions in Conventional PCI mode when the transactions are not to the same target. Since fast
2499 ** back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI-X mode.
projects / dragonfly.git / blob