1 /******************************************************************************
3 Copyright (c) 2001-2009, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
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21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ******************************************************************************/
35 #ifndef _E1000_ICH8LAN_H_
36 #define _E1000_ICH8LAN_H_
38 #define ICH_FLASH_GFPREG 0x0000
39 #define ICH_FLASH_HSFSTS 0x0004
40 #define ICH_FLASH_HSFCTL 0x0006
41 #define ICH_FLASH_FADDR 0x0008
42 #define ICH_FLASH_FDATA0 0x0010
44 /* Requires up to 10 seconds when MNG might be accessing part. */
45 #define ICH_FLASH_READ_COMMAND_TIMEOUT 10000000
46 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000
47 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000
48 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
49 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
51 #define ICH_CYCLE_READ 0
52 #define ICH_CYCLE_WRITE 2
53 #define ICH_CYCLE_ERASE 3
55 #define FLASH_GFPREG_BASE_MASK 0x1FFF
56 #define FLASH_SECTOR_ADDR_SHIFT 12
58 #define ICH_FLASH_SEG_SIZE_256 256
59 #define ICH_FLASH_SEG_SIZE_4K 4096
60 #define ICH_FLASH_SEG_SIZE_8K 8192
61 #define ICH_FLASH_SEG_SIZE_64K 65536
62 #define ICH_FLASH_SECTOR_SIZE 4096
64 #define ICH_FLASH_REG_MAPSIZE 0x00A0
66 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
67 #define E1000_ICH_FWSM_DISSW 0x10000000 /* FW Disables SW Writes */
68 /* FW established a valid mode */
69 #define E1000_ICH_FWSM_FW_VALID 0x00008000
71 #define E1000_ICH_MNG_IAMT_MODE 0x2
73 #define E1000_FWSM_PROXY_MODE 0x00000008 /* FW is in proxy mode */
75 /* Shared Receive Address Registers */
76 #define E1000_SHRAL(_i) (0x05438 + ((_i) * 8))
77 #define E1000_SHRAH(_i) (0x0543C + ((_i) * 8))
78 #define E1000_SHRAH_AV 0x80000000 /* Addr Valid bit */
79 #define E1000_SHRAH_MAV 0x40000000 /* Multicast Addr Valid bit */
81 #define E1000_H2ME 0x05B50 /* Host to ME */
82 #define E1000_H2ME_LSECREQ 0x00000001 /* Linksec Request */
83 #define E1000_H2ME_LSECA 0x00000002 /* Linksec Active */
84 #define E1000_H2ME_LSECSF 0x00000004 /* Linksec Failed */
85 #define E1000_H2ME_LSECD 0x00000008 /* Linksec Disabled */
86 #define E1000_H2ME_SLCAPD 0x00000010 /* Start LCAPD */
87 #define E1000_H2ME_IPV4_ARP_EN 0x00000020 /* Arp Offload enable bit */
88 #define E1000_H2ME_IPV6_NS_EN 0x00000040 /* NS Offload enable bit */
90 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
91 (ID_LED_OFF1_OFF2 << 8) | \
92 (ID_LED_OFF1_ON2 << 4) | \
95 #define E1000_ICH_NVM_SIG_WORD 0x13
96 #define E1000_ICH_NVM_SIG_MASK 0xC000
97 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
98 #define E1000_ICH_NVM_SIG_VALUE 0x80
100 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
102 #define E1000_FEXTNVM_SW_CONFIG 1
103 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */
105 #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
106 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
107 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
109 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
111 #define E1000_ICH_RAR_ENTRIES 7
112 #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
114 #define PHY_PAGE_SHIFT 5
115 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
116 ((reg) & MAX_PHY_REG_ADDRESS))
117 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
118 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
119 #define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */
120 #define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */
122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
124 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
125 #define IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020
127 /* PHY Wakeup Registers and defines */
128 #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
129 #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
130 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
131 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
132 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
133 #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
134 #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
135 #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
136 #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
137 #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
138 #define BM_IPAV (BM_PHY_REG(BM_WUC_PAGE, 64))
139 #define BM_IP4AT_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 82 + ((_i) * 2)))
140 #define BM_IP4AT_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 83 + ((_i) * 2)))
142 #define BM_SHRAL_LOWER(_i) (BM_PHY_REG(BM_WUC_PAGE, 44 + ((_i) * 4)))
143 #define BM_SHRAL_UPPER(_i) (BM_PHY_REG(BM_WUC_PAGE, 45 + ((_i) * 4)))
144 #define BM_SHRAH_LOWER(_i) (BM_PHY_REG(BM_WUC_PAGE, 46 + ((_i) * 4)))
145 #define BM_SHRAH_UPPER(_i) (BM_PHY_REG(BM_WUC_PAGE, 47 + ((_i) * 4)))
147 #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
148 #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
149 #define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
150 #define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
151 #define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
152 #define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
153 #define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
155 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
156 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
157 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
158 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
159 #define HV_STATS_PAGE 778
160 #define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */
161 #define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17)
162 #define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */
163 #define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19)
164 #define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */
165 #define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21)
166 #define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */
167 #define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
168 #define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */
169 #define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26)
170 #define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
171 #define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28)
172 #define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */
173 #define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30)
175 #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
177 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
178 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
180 /* SMBus Address Phy Register */
181 #define HV_SMB_ADDR PHY_REG(768, 26)
182 #define HV_SMB_ADDR_MASK 0x007F
183 #define HV_SMB_ADDR_PEC_EN 0x0200
184 #define HV_SMB_ADDR_VALID 0x0080
186 /* Strapping Option Register - RO */
187 #define E1000_STRAP 0x0000C
188 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
189 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
191 /* OEM Bits Phy Register */
192 #define HV_OEM_BITS PHY_REG(768, 25)
193 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
194 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
195 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
197 #define LCD_CFG_PHY_ADDR_BIT 0x0020 /* Phy address bit from LCD Config word */
199 /* KMRN Mode Control */
200 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
201 #define HV_KMRN_MDIO_SLOW 0x0400
203 /* KMRN FIFO Control and Status */
204 #define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16)
205 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000
206 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12
208 /* PHY Power Management Control */
209 #define HV_PM_CTRL PHY_REG(770, 17)
211 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
213 /* PHY Low Power Idle Control */
214 #define I82579_LPI_CTRL PHY_REG(772, 20)
215 #define I82579_LPI_CTRL_ENABLE_MASK 0x6000
218 #define I82579_EMI_ADDR 0x10
219 #define I82579_EMI_DATA 0x11
220 #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
223 * Additional interrupts need to be handled for ICH family:
224 * DSW = The FW changed the status of the DISSW bit in FWSM
225 * PHYINT = The LAN connected device generates an interrupt
226 * EPRST = Manageability reset event
228 #define IMS_ICH_ENABLE_MASK (\
233 /* Additional interrupt register bit definitions */
234 #define E1000_ICR_LSECPNC 0x00004000 /* PN threshold - client */
235 #define E1000_IMS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */
236 #define E1000_ICS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */
238 /* Security Processing bit Indication */
239 #define E1000_RXDEXT_LINKSEC_STATUS_LSECH 0x01000000
240 #define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK 0x60000000
241 #define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH 0x20000000
242 #define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000
243 #define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG 0x60000000
245 /* Receive Address Initial CRC Calculation */
246 #define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4))
248 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
250 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
251 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
252 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
253 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
254 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
255 s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_config);
256 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
257 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);