sys/dev/crypto/hifn/hifn7751.c

   1 /* $FreeBSD: src/sys/dev/hifn/hifn7751.c,v 1.5.2.5 2003/06/04 17:56:59 sam Exp $ */
   2 /* $DragonFly: src/sys/dev/crypto/hifn/hifn7751.c,v 1.13 2006/12/22 23:26:15 swildner Exp $ */
   3 /*      $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $  */
   4
   5 /*
   6  * Invertex AEON / Hifn 7751 driver
   7  * Copyright (c) 1999 Invertex Inc. All rights reserved.
   8  * Copyright (c) 1999 Theo de Raadt
   9  * Copyright (c) 2000-2001 Network Security Technologies, Inc.
  10  *                      http://www.netsec.net
  11  *
  12  * This driver is based on a previous driver by Invertex, for which they
  13  * requested:  Please send any comments, feedback, bug-fixes, or feature
  14  * requests to software@invertex.com.
  15  *
  16  * Redistribution and use in source and binary forms, with or without
  17  * modification, are permitted provided that the following conditions
  18  * are met:
  19  *
  20  * 1. Redistributions of source code must retain the above copyright
  21  *   notice, this list of conditions and the following disclaimer.
  22  * 2. Redistributions in binary form must reproduce the above copyright
  23  *   notice, this list of conditions and the following disclaimer in the
  24  *   documentation and/or other materials provided with the distribution.
  25  * 3. The name of the author may not be used to endorse or promote products
  26  *   derived from this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  29  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  30  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  31  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  32  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  33  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  34  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  35  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  36  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  37  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38  *
  39  * Effort sponsored in part by the Defense Advanced Research Projects
  40  * Agency (DARPA) and Air Force Research Laboratory, Air Force
  41  * Materiel Command, USAF, under agreement number F30602-01-2-0537.
  42  *
  43  */
  44
  45 /*
  46  * Driver for the Hifn 7751 encryption processor.
  47  */
  48 #include "opt_hifn.h"
  49
  50 #include <sys/param.h>
  51 #include <sys/systm.h>
  52 #include <sys/proc.h>
  53 #include <sys/errno.h>
  54 #include <sys/malloc.h>
  55 #include <sys/kernel.h>
  56 #include <sys/mbuf.h>
  57 #include <sys/sysctl.h>
  58 #include <sys/bus.h>
  59 #include <sys/rman.h>
  60 #include <sys/random.h>
  61 #include <sys/thread2.h>
  62
  63 #include <vm/vm.h>
  64 #include <vm/pmap.h>
  65
  66 #include <machine/clock.h>
  67 #include <opencrypto/cryptodev.h>
  68
  69 #include <bus/pci/pcivar.h>
  70 #include <bus/pci/pcireg.h>
  71
  72 #ifdef HIFN_RNDTEST
  73 #include "../rndtest/rndtest.h"
  74 #endif
  75 #include "hifn7751reg.h"
  76 #include "hifn7751var.h"
  77
  78 /*
  79  * Prototypes and count for the pci_device structure
  80  */
  81 static  int hifn_probe(device_t);
  82 static  int hifn_attach(device_t);
  83 static  int hifn_detach(device_t);
  84 static  int hifn_suspend(device_t);
  85 static  int hifn_resume(device_t);
  86 static  void hifn_shutdown(device_t);
  87
  88 static device_method_t hifn_methods[] = {
  89         /* Device interface */
  90         DEVMETHOD(device_probe,         hifn_probe),
  91         DEVMETHOD(device_attach,        hifn_attach),
  92         DEVMETHOD(device_detach,        hifn_detach),
  93         DEVMETHOD(device_suspend,       hifn_suspend),
  94         DEVMETHOD(device_resume,        hifn_resume),
  95         DEVMETHOD(device_shutdown,      hifn_shutdown),
  96
  97         /* bus interface */
  98         DEVMETHOD(bus_print_child,      bus_generic_print_child),
  99         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 100
 101         { 0, 0 }
 102 };
 103 static driver_t hifn_driver = {
 104         "hifn",
 105         hifn_methods,
 106         sizeof (struct hifn_softc)
 107 };
 108 static devclass_t hifn_devclass;
 109
 110 DECLARE_DUMMY_MODULE(hifn);
 111 DRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, 0, 0);
 112 MODULE_DEPEND(hifn, crypto, 1, 1, 1);
 113 #ifdef HIFN_RNDTEST
 114 MODULE_DEPEND(hifn, rndtest, 1, 1, 1);
 115 #endif
 116
 117 static  void hifn_reset_board(struct hifn_softc *, int);
 118 static  void hifn_reset_puc(struct hifn_softc *);
 119 static  void hifn_puc_wait(struct hifn_softc *);
 120 static  int hifn_enable_crypto(struct hifn_softc *);
 121 static  void hifn_set_retry(struct hifn_softc *sc);
 122 static  void hifn_init_dma(struct hifn_softc *);
 123 static  void hifn_init_pci_registers(struct hifn_softc *);
 124 static  int hifn_sramsize(struct hifn_softc *);
 125 static  int hifn_dramsize(struct hifn_softc *);
 126 static  int hifn_ramtype(struct hifn_softc *);
 127 static  void hifn_sessions(struct hifn_softc *);
 128 static  void hifn_intr(void *);
 129 static  u_int hifn_write_command(struct hifn_command *, u_int8_t *);
 130 static  u_int32_t hifn_next_signature(u_int32_t a, u_int cnt);
 131 static  int hifn_newsession(void *, u_int32_t *, struct cryptoini *);
 132 static  int hifn_freesession(void *, u_int64_t);
 133 static  int hifn_process(void *, struct cryptop *, int);
 134 static  void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *);
 135 static  int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int);
 136 static  int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *);
 137 static  int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *);
 138 static  int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *);
 139 static  int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *);
 140 static  int hifn_init_pubrng(struct hifn_softc *);
 141 #ifndef HIFN_NO_RNG
 142 static  void hifn_rng(void *);
 143 #endif
 144 static  void hifn_tick(void *);
 145 static  void hifn_abort(struct hifn_softc *);
 146 static  void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *);
 147
 148 static  void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t);
 149 static  void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t);
 150
 151 static __inline__ u_int32_t
 152 READ_REG_0(struct hifn_softc *sc, bus_size_t reg)
 153 {
 154     u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg);
 155     sc->sc_bar0_lastreg = (bus_size_t) -1;
 156     return (v);
 157 }
 158 #define WRITE_REG_0(sc, reg, val)       hifn_write_reg_0(sc, reg, val)
 159
 160 static __inline__ u_int32_t
 161 READ_REG_1(struct hifn_softc *sc, bus_size_t reg)
 162 {
 163     u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg);
 164     sc->sc_bar1_lastreg = (bus_size_t) -1;
 165     return (v);
 166 }
 167 #define WRITE_REG_1(sc, reg, val)       hifn_write_reg_1(sc, reg, val)
 168
 169 SYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD, 0, "Hifn driver parameters");
 170
 171 #ifdef HIFN_DEBUG
 172 static  int hifn_debug = 0;
 173 SYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug,
 174             0, "control debugging msgs");
 175 #endif
 176
 177 static  struct hifn_stats hifnstats;
 178 SYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats,
 179             hifn_stats, "driver statistics");
 180 static  int hifn_maxbatch = 1;
 181 SYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch,
 182             0, "max ops to batch w/o interrupt");
 183
 184 /*
 185  * Probe for a supported device.  The PCI vendor and device
 186  * IDs are used to detect devices we know how to handle.
 187  */
 188 static int
 189 hifn_probe(device_t dev)
 190 {
 191         if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX &&
 192             pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON)
 193                 return (0);
 194         if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
 195             (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 ||
 196              pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 ||
 197              pci_get_device(dev) == PCI_PRODUCT_HIFN_7811))
 198                 return (0);
 199         if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC &&
 200             pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751)
 201                 return (0);
 202         return (ENXIO);
 203 }
 204
 205 static void
 206 hifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 207 {
 208         bus_addr_t *paddr = (bus_addr_t*) arg;
 209         *paddr = segs->ds_addr;
 210 }
 211
 212 static const char*
 213 hifn_partname(struct hifn_softc *sc)
 214 {
 215         /* XXX sprintf numbers when not decoded */
 216         switch (pci_get_vendor(sc->sc_dev)) {
 217         case PCI_VENDOR_HIFN:
 218                 switch (pci_get_device(sc->sc_dev)) {
 219                 case PCI_PRODUCT_HIFN_6500:     return "Hifn 6500";
 220                 case PCI_PRODUCT_HIFN_7751:     return "Hifn 7751";
 221                 case PCI_PRODUCT_HIFN_7811:     return "Hifn 7811";
 222                 case PCI_PRODUCT_HIFN_7951:     return "Hifn 7951";
 223                 }
 224                 return "Hifn unknown-part";
 225         case PCI_VENDOR_INVERTEX:
 226                 switch (pci_get_device(sc->sc_dev)) {
 227                 case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON";
 228                 }
 229                 return "Invertex unknown-part";
 230         case PCI_VENDOR_NETSEC:
 231                 switch (pci_get_device(sc->sc_dev)) {
 232                 case PCI_PRODUCT_NETSEC_7751:   return "NetSec 7751";
 233                 }
 234                 return "NetSec unknown-part";
 235         }
 236         return "Unknown-vendor unknown-part";
 237 }
 238
 239 static void
 240 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
 241 {
 242         u_int32_t *p = (u_int32_t *)buf;
 243         for (count /= sizeof (u_int32_t); count; count--)
 244                 add_true_randomness(*p++);
 245 }
 246
 247 /*
 248  * Attach an interface that successfully probed.
 249  */
 250 static int
 251 hifn_attach(device_t dev)
 252 {
 253         struct hifn_softc *sc = device_get_softc(dev);
 254         u_int32_t cmd;
 255         caddr_t kva;
 256         int rseg, rid;
 257         char rbase;
 258         u_int16_t ena, rev;
 259
 260         KASSERT(sc != NULL, ("hifn_attach: null software carrier!"));
 261         bzero(sc, sizeof (*sc));
 262         sc->sc_dev = dev;
 263
 264         /* XXX handle power management */
 265
 266         /*
 267          * The 7951 has a random number generator and
 268          * public key support; note this.
 269          */
 270         if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
 271             pci_get_device(dev) == PCI_PRODUCT_HIFN_7951)
 272                 sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC;
 273         /*
 274          * The 7811 has a random number generator and
 275          * we also note it's identity 'cuz of some quirks.
 276          */
 277         if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
 278             pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)
 279                 sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG;
 280
 281         /*
 282          * Configure support for memory-mapped access to
 283          * registers and for DMA operations.
 284          */
 285 #define PCIM_ENA        (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN)
 286         cmd = pci_read_config(dev, PCIR_COMMAND, 4);
 287         cmd |= PCIM_ENA;
 288         pci_write_config(dev, PCIR_COMMAND, cmd, 4);
 289         cmd = pci_read_config(dev, PCIR_COMMAND, 4);
 290         if ((cmd & PCIM_ENA) != PCIM_ENA) {
 291                 device_printf(dev, "failed to enable %s\n",
 292                         (cmd & PCIM_ENA) == 0 ?
 293                                 "memory mapping & bus mastering" :
 294                         (cmd & PCIM_CMD_MEMEN) == 0 ?
 295                                 "memory mapping" : "bus mastering");
 296                 goto fail_pci;
 297         }
 298 #undef PCIM_ENA
 299
 300         /*
 301          * Setup PCI resources. Note that we record the bus
 302          * tag and handle for each register mapping, this is
 303          * used by the READ_REG_0, WRITE_REG_0, READ_REG_1,
 304          * and WRITE_REG_1 macros throughout the driver.
 305          */
 306         rid = HIFN_BAR0;
 307         sc->sc_bar0res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
 308                                             0, ~0, 1, RF_ACTIVE);
 309         if (sc->sc_bar0res == NULL) {
 310                 device_printf(dev, "cannot map bar%d register space\n", 0);
 311                 goto fail_pci;
 312         }
 313         sc->sc_st0 = rman_get_bustag(sc->sc_bar0res);
 314         sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res);
 315         sc->sc_bar0_lastreg = (bus_size_t) -1;
 316
 317         rid = HIFN_BAR1;
 318         sc->sc_bar1res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
 319                                             0, ~0, 1, RF_ACTIVE);
 320         if (sc->sc_bar1res == NULL) {
 321                 device_printf(dev, "cannot map bar%d register space\n", 1);
 322                 goto fail_io0;
 323         }
 324         sc->sc_st1 = rman_get_bustag(sc->sc_bar1res);
 325         sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res);
 326         sc->sc_bar1_lastreg = (bus_size_t) -1;
 327
 328         hifn_set_retry(sc);
 329
 330         /*
 331          * Setup the area where the Hifn DMA's descriptors
 332          * and associated data structures.
 333          */
 334         if (bus_dma_tag_create(NULL,                    /* parent */
 335                                1, 0,                    /* alignment,boundary */
 336                                BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
 337                                BUS_SPACE_MAXADDR,       /* highaddr */
 338                                NULL, NULL,              /* filter, filterarg */
 339                                HIFN_MAX_DMALEN,         /* maxsize */
 340                                MAX_SCATTER,             /* nsegments */
 341                                HIFN_MAX_SEGLEN,         /* maxsegsize */
 342                                BUS_DMA_ALLOCNOW,        /* flags */
 343                                &sc->sc_dmat)) {
 344                 device_printf(dev, "cannot allocate DMA tag\n");
 345                 goto fail_io1;
 346         }
 347         if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) {
 348                 device_printf(dev, "cannot create dma map\n");
 349                 bus_dma_tag_destroy(sc->sc_dmat);
 350                 goto fail_io1;
 351         }
 352         if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) {
 353                 device_printf(dev, "cannot alloc dma buffer\n");
 354                 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
 355                 bus_dma_tag_destroy(sc->sc_dmat);
 356                 goto fail_io1;
 357         }
 358         if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva,
 359                              sizeof (*sc->sc_dma),
 360                              hifn_dmamap_cb, &sc->sc_dma_physaddr,
 361                              BUS_DMA_NOWAIT)) {
 362                 device_printf(dev, "cannot load dma map\n");
 363                 bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap);
 364                 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
 365                 bus_dma_tag_destroy(sc->sc_dmat);
 366                 goto fail_io1;
 367         }
 368         sc->sc_dma = (struct hifn_dma *)kva;
 369         bzero(sc->sc_dma, sizeof(*sc->sc_dma));
 370
 371         KASSERT(sc->sc_st0 != NULL, ("hifn_attach: null bar0 tag!"));
 372         KASSERT(sc->sc_sh0 != NULL, ("hifn_attach: null bar0 handle!"));
 373         KASSERT(sc->sc_st1 != NULL, ("hifn_attach: null bar1 tag!"));
 374         KASSERT(sc->sc_sh1 != NULL, ("hifn_attach: null bar1 handle!"));
 375
 376         /*
 377          * Reset the board and do the ``secret handshake''
 378          * to enable the crypto support.  Then complete the
 379          * initialization procedure by setting up the interrupt
 380          * and hooking in to the system crypto support so we'll
 381          * get used for system services like the crypto device,
 382          * IPsec, RNG device, etc.
 383          */
 384         hifn_reset_board(sc, 0);
 385
 386         if (hifn_enable_crypto(sc) != 0) {
 387                 device_printf(dev, "crypto enabling failed\n");
 388                 goto fail_mem;
 389         }
 390         hifn_reset_puc(sc);
 391
 392         hifn_init_dma(sc);
 393         hifn_init_pci_registers(sc);
 394
 395         if (hifn_ramtype(sc))
 396                 goto fail_mem;
 397
 398         if (sc->sc_drammodel == 0)
 399                 hifn_sramsize(sc);
 400         else
 401                 hifn_dramsize(sc);
 402
 403         /*
 404          * Workaround for NetSec 7751 rev A: half ram size because two
 405          * of the address lines were left floating
 406          */
 407         if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC &&
 408             pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 &&
 409             pci_get_revid(dev) == 0x61) /*XXX???*/
 410                 sc->sc_ramsize >>= 1;
 411
 412         /*
 413          * Arrange the interrupt line.
 414          */
 415         rid = 0;
 416         sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
 417                                         0, ~0, 1, RF_SHAREABLE|RF_ACTIVE);
 418         if (sc->sc_irq == NULL) {
 419                 device_printf(dev, "could not map interrupt\n");
 420                 goto fail_mem;
 421         }
 422         /*
 423          * NB: Network code assumes we are blocked with splimp()
 424          *     so make sure the IRQ is marked appropriately.
 425          */
 426         if (bus_setup_intr(dev, sc->sc_irq, 0,
 427                            hifn_intr, sc,
 428                            &sc->sc_intrhand, NULL)) {
 429                 device_printf(dev, "could not setup interrupt\n");
 430                 goto fail_intr2;
 431         }
 432
 433         hifn_sessions(sc);
 434
 435         /*
 436          * NB: Keep only the low 16 bits; this masks the chip id
 437          *     from the 7951.
 438          */
 439         rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff;
 440
 441         rseg = sc->sc_ramsize / 1024;
 442         rbase = 'K';
 443         if (sc->sc_ramsize >= (1024 * 1024)) {
 444                 rbase = 'M';
 445                 rseg /= 1024;
 446         }
 447         device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram, %u sessions\n",
 448                 hifn_partname(sc), rev,
 449                 rseg, rbase, sc->sc_drammodel ? 'd' : 's',
 450                 sc->sc_maxses);
 451
 452         sc->sc_cid = crypto_get_driverid(0);
 453         if (sc->sc_cid < 0) {
 454                 device_printf(dev, "could not get crypto driver id\n");
 455                 goto fail_intr;
 456         }
 457
 458         WRITE_REG_0(sc, HIFN_0_PUCNFG,
 459             READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID);
 460         ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
 461
 462         switch (ena) {
 463         case HIFN_PUSTAT_ENA_2:
 464                 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0,
 465                     hifn_newsession, hifn_freesession, hifn_process, sc);
 466                 crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0,
 467                     hifn_newsession, hifn_freesession, hifn_process, sc);
 468                 /*FALLTHROUGH*/
 469         case HIFN_PUSTAT_ENA_1:
 470                 crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0,
 471                     hifn_newsession, hifn_freesession, hifn_process, sc);
 472                 crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0,
 473                     hifn_newsession, hifn_freesession, hifn_process, sc);
 474                 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0,
 475                     hifn_newsession, hifn_freesession, hifn_process, sc);
 476                 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0,
 477                     hifn_newsession, hifn_freesession, hifn_process, sc);
 478                 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0,
 479                     hifn_newsession, hifn_freesession, hifn_process, sc);
 480                 break;
 481         }
 482
 483         bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
 484             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 485
 486         if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG))
 487                 hifn_init_pubrng(sc);
 488
 489         /* NB: 1 means the callout runs w/o Giant locked */
 490         callout_init(&sc->sc_tickto);
 491         callout_reset(&sc->sc_tickto, hz, hifn_tick, sc);
 492
 493         return (0);
 494
 495 fail_intr:
 496         bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
 497 fail_intr2:
 498         /* XXX don't store rid */
 499         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
 500 fail_mem:
 501         bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap);
 502         bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap);
 503         bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
 504         bus_dma_tag_destroy(sc->sc_dmat);
 505
 506         /* Turn off DMA polling */
 507         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 508             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 509 fail_io1:
 510         bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res);
 511 fail_io0:
 512         bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res);
 513 fail_pci:
 514         return (ENXIO);
 515 }
 516
 517 /*
 518  * Detach an interface that successfully probed.
 519  */
 520 static int
 521 hifn_detach(device_t dev)
 522 {
 523         struct hifn_softc *sc = device_get_softc(dev);
 524
 525         KASSERT(sc != NULL, ("hifn_detach: null software carrier!"));
 526
 527         crit_enter();
 528         /*XXX other resources */
 529         callout_stop(&sc->sc_tickto);
 530         callout_stop(&sc->sc_rngto);
 531 #ifdef HIFN_RNDTEST
 532         if (sc->sc_rndtest)
 533                 rndtest_detach(sc->sc_rndtest);
 534 #endif
 535
 536         /* Turn off DMA polling */
 537         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 538             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 539
 540         crypto_unregister_all(sc->sc_cid);
 541
 542         bus_generic_detach(dev);        /*XXX should be no children, right? */
 543
 544         bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
 545         /* XXX don't store rid */
 546         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
 547
 548         bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap);
 549         bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap);
 550         bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
 551         bus_dma_tag_destroy(sc->sc_dmat);
 552
 553         bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res);
 554         bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res);
 555         crit_exit();
 556
 557         return (0);
 558 }
 559
 560 /*
 561  * Stop all chip I/O so that the kernel's probe routines don't
 562  * get confused by errant DMAs when rebooting.
 563  */
 564 static void
 565 hifn_shutdown(device_t dev)
 566 {
 567 #ifdef notyet
 568         hifn_stop(device_get_softc(dev));
 569 #endif
 570 }
 571
 572 /*
 573  * Device suspend routine.  Stop the interface and save some PCI
 574  * settings in case the BIOS doesn't restore them properly on
 575  * resume.
 576  */
 577 static int
 578 hifn_suspend(device_t dev)
 579 {
 580         struct hifn_softc *sc = device_get_softc(dev);
 581 #ifdef notyet
 582         int i;
 583
 584         hifn_stop(sc);
 585         for (i = 0; i < 5; i++)
 586                 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
 587         sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
 588         sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
 589         sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
 590         sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
 591 #endif
 592         sc->sc_suspended = 1;
 593
 594         return (0);
 595 }
 596
 597 /*
 598  * Device resume routine.  Restore some PCI settings in case the BIOS
 599  * doesn't, re-enable busmastering, and restart the interface if
 600  * appropriate.
 601  */
 602 static int
 603 hifn_resume(device_t dev)
 604 {
 605         struct hifn_softc *sc = device_get_softc(dev);
 606 #ifdef notyet
 607         int i;
 608
 609         /* better way to do this? */
 610         for (i = 0; i < 5; i++)
 611                 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
 612         pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
 613         pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
 614         pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
 615         pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
 616
 617         /* reenable busmastering */
 618         pci_enable_busmaster(dev);
 619         pci_enable_io(dev, HIFN_RES);
 620
 621         /* reinitialize interface if necessary */
 622         if (ifp->if_flags & IFF_UP)
 623                 rl_init(sc);
 624 #endif
 625         sc->sc_suspended = 0;
 626
 627         return (0);
 628 }
 629
 630 static int
 631 hifn_init_pubrng(struct hifn_softc *sc)
 632 {
 633         u_int32_t r;
 634         int i;
 635
 636 #ifdef HIFN_RNDTEST
 637         sc->sc_rndtest = rndtest_attach(sc->sc_dev);
 638         if (sc->sc_rndtest)
 639                 sc->sc_harvest = rndtest_harvest;
 640         else
 641                 sc->sc_harvest = default_harvest;
 642 #else
 643         sc->sc_harvest = default_harvest;
 644 #endif
 645         if ((sc->sc_flags & HIFN_IS_7811) == 0) {
 646                 /* Reset 7951 public key/rng engine */
 647                 WRITE_REG_1(sc, HIFN_1_PUB_RESET,
 648                     READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET);
 649
 650                 for (i = 0; i < 100; i++) {
 651                         DELAY(1000);
 652                         if ((READ_REG_1(sc, HIFN_1_PUB_RESET) &
 653                             HIFN_PUBRST_RESET) == 0)
 654                                 break;
 655                 }
 656
 657                 if (i == 100) {
 658                         device_printf(sc->sc_dev, "public key init failed\n");
 659                         return (1);
 660                 }
 661         }
 662
 663 #ifndef HIFN_NO_RNG
 664         /* Enable the rng, if available */
 665         if (sc->sc_flags & HIFN_HAS_RNG) {
 666                 if (sc->sc_flags & HIFN_IS_7811) {
 667                         r = READ_REG_1(sc, HIFN_1_7811_RNGENA);
 668                         if (r & HIFN_7811_RNGENA_ENA) {
 669                                 r &= ~HIFN_7811_RNGENA_ENA;
 670                                 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r);
 671                         }
 672                         WRITE_REG_1(sc, HIFN_1_7811_RNGCFG,
 673                             HIFN_7811_RNGCFG_DEFL);
 674                         r |= HIFN_7811_RNGENA_ENA;
 675                         WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r);
 676                 } else
 677                         WRITE_REG_1(sc, HIFN_1_RNG_CONFIG,
 678                             READ_REG_1(sc, HIFN_1_RNG_CONFIG) |
 679                             HIFN_RNGCFG_ENA);
 680
 681                 sc->sc_rngfirst = 1;
 682                 if (hz >= 100)
 683                         sc->sc_rnghz = hz / 100;
 684                 else
 685                         sc->sc_rnghz = 1;
 686                 /* NB: 1 means the callout runs w/o Giant locked */
 687                 callout_init(&sc->sc_rngto);
 688                 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc);
 689         }
 690 #endif
 691
 692         /* Enable public key engine, if available */
 693         if (sc->sc_flags & HIFN_HAS_PUBLIC) {
 694                 WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
 695                 sc->sc_dmaier |= HIFN_DMAIER_PUBDONE;
 696                 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
 697         }
 698
 699         return (0);
 700 }
 701
 702 #ifndef HIFN_NO_RNG
 703 static void
 704 hifn_rng(void *vsc)
 705 {
 706 #define RANDOM_BITS(n)  (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0
 707         struct hifn_softc *sc = vsc;
 708         u_int32_t sts, num[2];
 709         int i;
 710
 711         if (sc->sc_flags & HIFN_IS_7811) {
 712                 for (i = 0; i < 5; i++) {
 713                         sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS);
 714                         if (sts & HIFN_7811_RNGSTS_UFL) {
 715                                 device_printf(sc->sc_dev,
 716                                               "RNG underflow: disabling\n");
 717                                 return;
 718                         }
 719                         if ((sts & HIFN_7811_RNGSTS_RDY) == 0)
 720                                 break;
 721
 722                         /*
 723                          * There are at least two words in the RNG FIFO
 724                          * at this point.
 725                          */
 726                         num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT);
 727                         num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT);
 728                         /* NB: discard first data read */
 729                         if (sc->sc_rngfirst)
 730                                 sc->sc_rngfirst = 0;
 731                         else
 732                                 (*sc->sc_harvest)(sc->sc_rndtest,
 733                                         num, sizeof (num));
 734                 }
 735         } else {
 736                 num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA);
 737
 738                 /* NB: discard first data read */
 739                 if (sc->sc_rngfirst)
 740                         sc->sc_rngfirst = 0;
 741                 else
 742                         (*sc->sc_harvest)(sc->sc_rndtest,
 743                                 num, sizeof (num[0]));
 744         }
 745
 746         callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc);
 747 #undef RANDOM_BITS
 748 }
 749 #endif
 750
 751 static void
 752 hifn_puc_wait(struct hifn_softc *sc)
 753 {
 754         int i;
 755
 756         for (i = 5000; i > 0; i--) {
 757                 DELAY(1);
 758                 if (!(READ_REG_0(sc, HIFN_0_PUCTRL) & HIFN_PUCTRL_RESET))
 759                         break;
 760         }
 761         if (!i)
 762                 device_printf(sc->sc_dev, "proc unit did not reset\n");
 763 }
 764
 765 /*
 766  * Reset the processing unit.
 767  */
 768 static void
 769 hifn_reset_puc(struct hifn_softc *sc)
 770 {
 771         /* Reset processing unit */
 772         WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
 773         hifn_puc_wait(sc);
 774 }
 775
 776 /*
 777  * Set the Retry and TRDY registers; note that we set them to
 778  * zero because the 7811 locks up when forced to retry (section
 779  * 3.6 of "Specification Update SU-0014-04".  Not clear if we
 780  * should do this for all Hifn parts, but it doesn't seem to hurt.
 781  */
 782 static void
 783 hifn_set_retry(struct hifn_softc *sc)
 784 {
 785         /* NB: RETRY only responds to 8-bit reads/writes */
 786         pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1);
 787         pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 4);
 788 }
 789
 790 /*
 791  * Resets the board.  Values in the regesters are left as is
 792  * from the reset (i.e. initial values are assigned elsewhere).
 793  */
 794 static void
 795 hifn_reset_board(struct hifn_softc *sc, int full)
 796 {
 797         u_int32_t reg;
 798
 799         /*
 800          * Set polling in the DMA configuration register to zero.  0x7 avoids
 801          * resetting the board and zeros out the other fields.
 802          */
 803         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 804             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 805
 806         /*
 807          * Now that polling has been disabled, we have to wait 1 ms
 808          * before resetting the board.
 809          */
 810         DELAY(1000);
 811
 812         /* Reset the DMA unit */
 813         if (full) {
 814                 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
 815                 DELAY(1000);
 816         } else {
 817                 WRITE_REG_1(sc, HIFN_1_DMA_CNFG,
 818                     HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET);
 819                 hifn_reset_puc(sc);
 820         }
 821
 822         KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!"));
 823         bzero(sc->sc_dma, sizeof(*sc->sc_dma));
 824
 825         /* Bring dma unit out of reset */
 826         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 827             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 828
 829         hifn_puc_wait(sc);
 830         hifn_set_retry(sc);
 831
 832         if (sc->sc_flags & HIFN_IS_7811) {
 833                 for (reg = 0; reg < 1000; reg++) {
 834                         if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) &
 835                             HIFN_MIPSRST_CRAMINIT)
 836                                 break;
 837                         DELAY(1000);
 838                 }
 839                 if (reg == 1000)
 840                         kprintf(": cram init timeout\n");
 841         }
 842 }
 843
 844 static u_int32_t
 845 hifn_next_signature(u_int32_t a, u_int cnt)
 846 {
 847         int i;
 848         u_int32_t v;
 849
 850         for (i = 0; i < cnt; i++) {
 851
 852                 /* get the parity */
 853                 v = a & 0x80080125;
 854                 v ^= v >> 16;
 855                 v ^= v >> 8;
 856                 v ^= v >> 4;
 857                 v ^= v >> 2;
 858                 v ^= v >> 1;
 859
 860                 a = (v & 1) ^ (a << 1);
 861         }
 862
 863         return a;
 864 }
 865
 866 struct pci2id {
 867         u_short         pci_vendor;
 868         u_short         pci_prod;
 869         char            card_id[13];
 870 };
 871 static struct pci2id pci2id[] = {
 872         {
 873                 PCI_VENDOR_HIFN,
 874                 PCI_PRODUCT_HIFN_7951,
 875                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 876                   0x00, 0x00, 0x00, 0x00, 0x00 }
 877         }, {
 878                 PCI_VENDOR_NETSEC,
 879                 PCI_PRODUCT_NETSEC_7751,
 880                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 881                   0x00, 0x00, 0x00, 0x00, 0x00 }
 882         }, {
 883                 PCI_VENDOR_INVERTEX,
 884                 PCI_PRODUCT_INVERTEX_AEON,
 885                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 886                   0x00, 0x00, 0x00, 0x00, 0x00 }
 887         }, {
 888                 PCI_VENDOR_HIFN,
 889                 PCI_PRODUCT_HIFN_7811,
 890                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 891                   0x00, 0x00, 0x00, 0x00, 0x00 }
 892         }, {
 893                 /*
 894                  * Other vendors share this PCI ID as well, such as
 895                  * http://www.powercrypt.com, and obviously they also
 896                  * use the same key.
 897                  */
 898                 PCI_VENDOR_HIFN,
 899                 PCI_PRODUCT_HIFN_7751,
 900                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 901                   0x00, 0x00, 0x00, 0x00, 0x00 }
 902         },
 903 };
 904
 905 /*
 906  * Checks to see if crypto is already enabled.  If crypto isn't enable,
 907  * "hifn_enable_crypto" is called to enable it.  The check is important,
 908  * as enabling crypto twice will lock the board.
 909  */
 910 static int
 911 hifn_enable_crypto(struct hifn_softc *sc)
 912 {
 913         u_int32_t dmacfg, ramcfg, encl, addr, i;
 914         char *offtbl = NULL;
 915
 916         for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) {
 917                 if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) &&
 918                     pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) {
 919                         offtbl = pci2id[i].card_id;
 920                         break;
 921                 }
 922         }
 923         if (offtbl == NULL) {
 924                 device_printf(sc->sc_dev, "Unknown card!\n");
 925                 return (1);
 926         }
 927
 928         ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG);
 929         dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG);
 930
 931         /*
 932          * The RAM config register's encrypt level bit needs to be set before
 933          * every read performed on the encryption level register.
 934          */
 935         WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID);
 936
 937         encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
 938
 939         /*
 940          * Make sure we don't re-unlock.  Two unlocks kills chip until the
 941          * next reboot.
 942          */
 943         if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) {
 944 #ifdef HIFN_DEBUG
 945                 if (hifn_debug)
 946                         device_printf(sc->sc_dev,
 947                             "Strong crypto already enabled!\n");
 948 #endif
 949                 goto report;
 950         }
 951
 952         if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) {
 953 #ifdef HIFN_DEBUG
 954                 if (hifn_debug)
 955                         device_printf(sc->sc_dev,
 956                               "Unknown encryption level 0x%x\n", encl);
 957 #endif
 958                 return 1;
 959         }
 960
 961         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK |
 962             HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 963         DELAY(1000);
 964         addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1);
 965         DELAY(1000);
 966         WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0);
 967         DELAY(1000);
 968
 969         for (i = 0; i <= 12; i++) {
 970                 addr = hifn_next_signature(addr, offtbl[i] + 0x101);
 971                 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr);
 972
 973                 DELAY(1000);
 974         }
 975
 976         WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID);
 977         encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
 978
 979 #ifdef HIFN_DEBUG
 980         if (hifn_debug) {
 981                 if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2)
 982                         device_printf(sc->sc_dev, "Engine is permanently "
 983                                 "locked until next system reset!\n");
 984                 else
 985                         device_printf(sc->sc_dev, "Engine enabled "
 986                                 "successfully!\n");
 987         }
 988 #endif
 989
 990 report:
 991         WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg);
 992         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg);
 993
 994         switch (encl) {
 995         case HIFN_PUSTAT_ENA_1:
 996         case HIFN_PUSTAT_ENA_2:
 997                 break;
 998         case HIFN_PUSTAT_ENA_0:
 999         default:
1000                 device_printf(sc->sc_dev, "disabled");
1001                 break;
1002         }
1003
1004         return 0;
1005 }
1006
1007 /*
1008  * Give initial values to the registers listed in the "Register Space"
1009  * section of the HIFN Software Development reference manual.
1010  */
1011 static void
1012 hifn_init_pci_registers(struct hifn_softc *sc)
1013 {
1014         /* write fixed values needed by the Initialization registers */
1015         WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
1016         WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD);
1017         WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER);
1018
1019         /* write all 4 ring address registers */
1020         WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr +
1021             offsetof(struct hifn_dma, cmdr[0]));
1022         WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr +
1023             offsetof(struct hifn_dma, srcr[0]));
1024         WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr +
1025             offsetof(struct hifn_dma, dstr[0]));
1026         WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr +
1027             offsetof(struct hifn_dma, resr[0]));
1028
1029         DELAY(2000);
1030
1031         /* write status register */
1032         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1033             HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
1034             HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS |
1035             HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
1036             HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
1037             HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
1038             HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
1039             HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
1040             HIFN_DMACSR_S_WAIT |
1041             HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
1042             HIFN_DMACSR_C_WAIT |
1043             HIFN_DMACSR_ENGINE |
1044             ((sc->sc_flags & HIFN_HAS_PUBLIC) ?
1045                 HIFN_DMACSR_PUBDONE : 0) |
1046             ((sc->sc_flags & HIFN_IS_7811) ?
1047                 HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0));
1048
1049         sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0;
1050         sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT |
1051             HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
1052             HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT |
1053             ((sc->sc_flags & HIFN_IS_7811) ?
1054                 HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0);
1055         sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
1056         WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
1057
1058         WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
1059             HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
1060             HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
1061             (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM));
1062
1063         WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1064         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
1065             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST |
1066             ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) |
1067             ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL));
1068 }
1069
1070 /*
1071  * The maximum number of sessions supported by the card
1072  * is dependent on the amount of context ram, which
1073  * encryption algorithms are enabled, and how compression
1074  * is configured.  This should be configured before this
1075  * routine is called.
1076  */
1077 static void
1078 hifn_sessions(struct hifn_softc *sc)
1079 {
1080         u_int32_t pucnfg;
1081         int ctxsize;
1082
1083         pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG);
1084
1085         if (pucnfg & HIFN_PUCNFG_COMPSING) {
1086                 if (pucnfg & HIFN_PUCNFG_ENCCNFG)
1087                         ctxsize = 128;
1088                 else
1089                         ctxsize = 512;
1090                 sc->sc_maxses = 1 +
1091                     ((sc->sc_ramsize - 32768) / ctxsize);
1092         } else
1093                 sc->sc_maxses = sc->sc_ramsize / 16384;
1094
1095         if (sc->sc_maxses > 2048)
1096                 sc->sc_maxses = 2048;
1097 }
1098
1099 /*
1100  * Determine ram type (sram or dram).  Board should be just out of a reset
1101  * state when this is called.
1102  */
1103 static int
1104 hifn_ramtype(struct hifn_softc *sc)
1105 {
1106         u_int8_t data[8], dataexpect[8];
1107         int i;
1108
1109         for (i = 0; i < sizeof(data); i++)
1110                 data[i] = dataexpect[i] = 0x55;
1111         if (hifn_writeramaddr(sc, 0, data))
1112                 return (-1);
1113         if (hifn_readramaddr(sc, 0, data))
1114                 return (-1);
1115         if (bcmp(data, dataexpect, sizeof(data)) != 0) {
1116                 sc->sc_drammodel = 1;
1117                 return (0);
1118         }
1119
1120         for (i = 0; i < sizeof(data); i++)
1121                 data[i] = dataexpect[i] = 0xaa;
1122         if (hifn_writeramaddr(sc, 0, data))
1123                 return (-1);
1124         if (hifn_readramaddr(sc, 0, data))
1125                 return (-1);
1126         if (bcmp(data, dataexpect, sizeof(data)) != 0) {
1127                 sc->sc_drammodel = 1;
1128                 return (0);
1129         }
1130
1131         return (0);
1132 }
1133
1134 #define HIFN_SRAM_MAX           (32 << 20)
1135 #define HIFN_SRAM_STEP_SIZE     16384
1136 #define HIFN_SRAM_GRANULARITY   (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE)
1137
1138 static int
1139 hifn_sramsize(struct hifn_softc *sc)
1140 {
1141         u_int32_t a;
1142         u_int8_t data[8];
1143         u_int8_t dataexpect[sizeof(data)];
1144         int32_t i;
1145
1146         for (i = 0; i < sizeof(data); i++)
1147                 data[i] = dataexpect[i] = i ^ 0x5a;
1148
1149         for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) {
1150                 a = i * HIFN_SRAM_STEP_SIZE;
1151                 bcopy(&i, data, sizeof(i));
1152                 hifn_writeramaddr(sc, a, data);
1153         }
1154
1155         for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) {
1156                 a = i * HIFN_SRAM_STEP_SIZE;
1157                 bcopy(&i, dataexpect, sizeof(i));
1158                 if (hifn_readramaddr(sc, a, data) < 0)
1159                         return (0);
1160                 if (bcmp(data, dataexpect, sizeof(data)) != 0)
1161                         return (0);
1162                 sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE;
1163         }
1164
1165         return (0);
1166 }
1167
1168 /*
1169  * XXX For dram boards, one should really try all of the
1170  * HIFN_PUCNFG_DSZ_*'s.  This just assumes that PUCNFG
1171  * is already set up correctly.
1172  */
1173 static int
1174 hifn_dramsize(struct hifn_softc *sc)
1175 {
1176         u_int32_t cnfg;
1177
1178         cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) &
1179             HIFN_PUCNFG_DRAMMASK;
1180         sc->sc_ramsize = 1 << ((cnfg >> 13) + 18);
1181         return (0);
1182 }
1183
1184 static void
1185 hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp)
1186 {
1187         struct hifn_dma *dma = sc->sc_dma;
1188
1189         if (dma->cmdi == HIFN_D_CMD_RSIZE) {
1190                 dma->cmdi = 0;
1191                 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
1192                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1193                 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE,
1194                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1195         }
1196         *cmdp = dma->cmdi++;
1197         dma->cmdk = dma->cmdi;
1198
1199         if (dma->srci == HIFN_D_SRC_RSIZE) {
1200                 dma->srci = 0;
1201                 dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID |
1202                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1203                 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE,
1204                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1205         }
1206         *srcp = dma->srci++;
1207         dma->srck = dma->srci;
1208
1209         if (dma->dsti == HIFN_D_DST_RSIZE) {
1210                 dma->dsti = 0;
1211                 dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID |
1212                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1213                 HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE,
1214                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1215         }
1216         *dstp = dma->dsti++;
1217         dma->dstk = dma->dsti;
1218
1219         if (dma->resi == HIFN_D_RES_RSIZE) {
1220                 dma->resi = 0;
1221                 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID |
1222                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1223                 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE,
1224                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1225         }
1226         *resp = dma->resi++;
1227         dma->resk = dma->resi;
1228 }
1229
1230 static int
1231 hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data)
1232 {
1233         struct hifn_dma *dma = sc->sc_dma;
1234         hifn_base_command_t wc;
1235         const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ;
1236         int r, cmdi, resi, srci, dsti;
1237
1238         wc.masks = htole16(3 << 13);
1239         wc.session_num = htole16(addr >> 14);
1240         wc.total_source_count = htole16(8);
1241         wc.total_dest_count = htole16(addr & 0x3fff);
1242
1243         hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi);
1244
1245         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1246             HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1247             HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA);
1248
1249         /* build write command */
1250         bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND);
1251         *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc;
1252         bcopy(data, &dma->test_src, sizeof(dma->test_src));
1253
1254         dma->srcr[srci].p = htole32(sc->sc_dma_physaddr
1255             + offsetof(struct hifn_dma, test_src));
1256         dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr
1257             + offsetof(struct hifn_dma, test_dst));
1258
1259         dma->cmdr[cmdi].l = htole32(16 | masks);
1260         dma->srcr[srci].l = htole32(8 | masks);
1261         dma->dstr[dsti].l = htole32(4 | masks);
1262         dma->resr[resi].l = htole32(4 | masks);
1263
1264         bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1265             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1266
1267         for (r = 10000; r >= 0; r--) {
1268                 DELAY(10);
1269                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1270                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1271                 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0)
1272                         break;
1273                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1274                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1275         }
1276         if (r == 0) {
1277                 device_printf(sc->sc_dev, "writeramaddr -- "
1278                     "result[%d](addr %d) still valid\n", resi, addr);
1279                 r = -1;
1280                 return (-1);
1281         } else
1282                 r = 0;
1283
1284         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1285             HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS |
1286             HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS);
1287
1288         return (r);
1289 }
1290
1291 static int
1292 hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data)
1293 {
1294         struct hifn_dma *dma = sc->sc_dma;
1295         hifn_base_command_t rc;
1296         const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ;
1297         int r, cmdi, srci, dsti, resi;
1298
1299         rc.masks = htole16(2 << 13);
1300         rc.session_num = htole16(addr >> 14);
1301         rc.total_source_count = htole16(addr & 0x3fff);
1302         rc.total_dest_count = htole16(8);
1303
1304         hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi);
1305
1306         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1307             HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1308             HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA);
1309
1310         bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND);
1311         *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc;
1312
1313         dma->srcr[srci].p = htole32(sc->sc_dma_physaddr +
1314             offsetof(struct hifn_dma, test_src));
1315         dma->test_src = 0;
1316         dma->dstr[dsti].p =  htole32(sc->sc_dma_physaddr +
1317             offsetof(struct hifn_dma, test_dst));
1318         dma->test_dst = 0;
1319         dma->cmdr[cmdi].l = htole32(8 | masks);
1320         dma->srcr[srci].l = htole32(8 | masks);
1321         dma->dstr[dsti].l = htole32(8 | masks);
1322         dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks);
1323
1324         bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1325             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1326
1327         for (r = 10000; r >= 0; r--) {
1328                 DELAY(10);
1329                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1330                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1331                 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0)
1332                         break;
1333                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1334                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1335         }
1336         if (r == 0) {
1337                 device_printf(sc->sc_dev, "readramaddr -- "
1338                     "result[%d](addr %d) still valid\n", resi, addr);
1339                 r = -1;
1340         } else {
1341                 r = 0;
1342                 bcopy(&dma->test_dst, data, sizeof(dma->test_dst));
1343         }
1344
1345         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1346             HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS |
1347             HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS);
1348
1349         return (r);
1350 }
1351
1352 /*
1353  * Initialize the descriptor rings.
1354  */
1355 static void
1356 hifn_init_dma(struct hifn_softc *sc)
1357 {
1358         struct hifn_dma *dma = sc->sc_dma;
1359         int i;
1360
1361         hifn_set_retry(sc);
1362
1363         /* initialize static pointer values */
1364         for (i = 0; i < HIFN_D_CMD_RSIZE; i++)
1365                 dma->cmdr[i].p = htole32(sc->sc_dma_physaddr +
1366                     offsetof(struct hifn_dma, command_bufs[i][0]));
1367         for (i = 0; i < HIFN_D_RES_RSIZE; i++)
1368                 dma->resr[i].p = htole32(sc->sc_dma_physaddr +
1369                     offsetof(struct hifn_dma, result_bufs[i][0]));
1370
1371         dma->cmdr[HIFN_D_CMD_RSIZE].p =
1372             htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0]));
1373         dma->srcr[HIFN_D_SRC_RSIZE].p =
1374             htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0]));
1375         dma->dstr[HIFN_D_DST_RSIZE].p =
1376             htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0]));
1377         dma->resr[HIFN_D_RES_RSIZE].p =
1378             htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0]));
1379
1380         dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0;
1381         dma->cmdi = dma->srci = dma->dsti = dma->resi = 0;
1382         dma->cmdk = dma->srck = dma->dstk = dma->resk = 0;
1383 }
1384
1385 /*
1386  * Writes out the raw command buffer space.  Returns the
1387  * command buffer size.
1388  */
1389 static u_int
1390 hifn_write_command(struct hifn_command *cmd, u_int8_t *buf)
1391 {
1392         u_int8_t *buf_pos;
1393         hifn_base_command_t *base_cmd;
1394         hifn_mac_command_t *mac_cmd;
1395         hifn_crypt_command_t *cry_cmd;
1396         int using_mac, using_crypt, len;
1397         u_int32_t dlen, slen;
1398
1399         buf_pos = buf;
1400         using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC;
1401         using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT;
1402
1403         base_cmd = (hifn_base_command_t *)buf_pos;
1404         base_cmd->masks = htole16(cmd->base_masks);
1405         slen = cmd->src_mapsize;
1406         if (cmd->sloplen)
1407                 dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t);
1408         else
1409                 dlen = cmd->dst_mapsize;
1410         base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO);
1411         base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO);
1412         dlen >>= 16;
1413         slen >>= 16;
1414         base_cmd->session_num = htole16(cmd->session_num |
1415             ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) |
1416             ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));
1417         buf_pos += sizeof(hifn_base_command_t);
1418
1419         if (using_mac) {
1420                 mac_cmd = (hifn_mac_command_t *)buf_pos;
1421                 dlen = cmd->maccrd->crd_len;
1422                 mac_cmd->source_count = htole16(dlen & 0xffff);
1423                 dlen >>= 16;
1424                 mac_cmd->masks = htole16(cmd->mac_masks |
1425                     ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M));
1426                 mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip);
1427                 mac_cmd->reserved = 0;
1428                 buf_pos += sizeof(hifn_mac_command_t);
1429         }
1430
1431         if (using_crypt) {
1432                 cry_cmd = (hifn_crypt_command_t *)buf_pos;
1433                 dlen = cmd->enccrd->crd_len;
1434                 cry_cmd->source_count = htole16(dlen & 0xffff);
1435                 dlen >>= 16;
1436                 cry_cmd->masks = htole16(cmd->cry_masks |
1437                     ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M));
1438                 cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip);
1439                 cry_cmd->reserved = 0;
1440                 buf_pos += sizeof(hifn_crypt_command_t);
1441         }
1442
1443         if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) {
1444                 bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH);
1445                 buf_pos += HIFN_MAC_KEY_LENGTH;
1446         }
1447
1448         if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) {
1449                 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) {
1450                 case HIFN_CRYPT_CMD_ALG_3DES:
1451                         bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH);
1452                         buf_pos += HIFN_3DES_KEY_LENGTH;
1453                         break;
1454                 case HIFN_CRYPT_CMD_ALG_DES:
1455                         bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH);
1456                         buf_pos += cmd->cklen;
1457                         break;
1458                 case HIFN_CRYPT_CMD_ALG_RC4:
1459                         len = 256;
1460                         do {
1461                                 int clen;
1462
1463                                 clen = MIN(cmd->cklen, len);
1464                                 bcopy(cmd->ck, buf_pos, clen);
1465                                 len -= clen;
1466                                 buf_pos += clen;
1467                         } while (len > 0);
1468                         bzero(buf_pos, 4);
1469                         buf_pos += 4;
1470                         break;
1471                 }
1472         }
1473
1474         if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) {
1475                 bcopy(cmd->iv, buf_pos, HIFN_IV_LENGTH);
1476                 buf_pos += HIFN_IV_LENGTH;
1477         }
1478
1479         if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) {
1480                 bzero(buf_pos, 8);
1481                 buf_pos += 8;
1482         }
1483
1484         return (buf_pos - buf);
1485 #undef  MIN
1486 }
1487
1488 static int
1489 hifn_dmamap_aligned(struct hifn_operand *op)
1490 {
1491         int i;
1492
1493         for (i = 0; i < op->nsegs; i++) {
1494                 if (op->segs[i].ds_addr & 3)
1495                         return (0);
1496                 if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3))
1497                         return (0);
1498         }
1499         return (1);
1500 }
1501
1502 static int
1503 hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd)
1504 {
1505         struct hifn_dma *dma = sc->sc_dma;
1506         struct hifn_operand *dst = &cmd->dst;
1507         u_int32_t p, l;
1508         int idx, used = 0, i;
1509
1510         idx = dma->dsti;
1511         for (i = 0; i < dst->nsegs - 1; i++) {
1512                 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr);
1513                 dma->dstr[idx].l = htole32(HIFN_D_VALID |
1514                     HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len);
1515                 HIFN_DSTR_SYNC(sc, idx,
1516                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1517                 used++;
1518
1519                 if (++idx == HIFN_D_DST_RSIZE) {
1520                         dma->dstr[idx].l = htole32(HIFN_D_VALID |
1521                             HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1522                         HIFN_DSTR_SYNC(sc, idx,
1523                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1524                         idx = 0;
1525                 }
1526         }
1527
1528         if (cmd->sloplen == 0) {
1529                 p = dst->segs[i].ds_addr;
1530                 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST |
1531                     dst->segs[i].ds_len;
1532         } else {
1533                 p = sc->sc_dma_physaddr +
1534                     offsetof(struct hifn_dma, slop[cmd->slopidx]);
1535                 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST |
1536                     sizeof(u_int32_t);
1537
1538                 if ((dst->segs[i].ds_len - cmd->sloplen) != 0) {
1539                         dma->dstr[idx].p = htole32(dst->segs[i].ds_addr);
1540                         dma->dstr[idx].l = htole32(HIFN_D_VALID |
1541                             HIFN_D_MASKDONEIRQ |
1542                             (dst->segs[i].ds_len - cmd->sloplen));
1543                         HIFN_DSTR_SYNC(sc, idx,
1544                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1545                         used++;
1546
1547                         if (++idx == HIFN_D_DST_RSIZE) {
1548                                 dma->dstr[idx].l = htole32(HIFN_D_VALID |
1549                                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1550                                 HIFN_DSTR_SYNC(sc, idx,
1551                                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1552                                 idx = 0;
1553                         }
1554                 }
1555         }
1556         dma->dstr[idx].p = htole32(p);
1557         dma->dstr[idx].l = htole32(l);
1558         HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1559         used++;
1560
1561         if (++idx == HIFN_D_DST_RSIZE) {
1562                 dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP |
1563                     HIFN_D_MASKDONEIRQ);
1564                 HIFN_DSTR_SYNC(sc, idx,
1565                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1566                 idx = 0;
1567         }
1568
1569         dma->dsti = idx;
1570         dma->dstu += used;
1571         return (idx);
1572 }
1573
1574 static int
1575 hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd)
1576 {
1577         struct hifn_dma *dma = sc->sc_dma;
1578         struct hifn_operand *src = &cmd->src;
1579         int idx, i;
1580         u_int32_t last = 0;
1581
1582         idx = dma->srci;
1583         for (i = 0; i < src->nsegs; i++) {
1584                 if (i == src->nsegs - 1)
1585                         last = HIFN_D_LAST;
1586
1587                 dma->srcr[idx].p = htole32(src->segs[i].ds_addr);
1588                 dma->srcr[idx].l = htole32(src->segs[i].ds_len |
1589                     HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last);
1590                 HIFN_SRCR_SYNC(sc, idx,
1591                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1592
1593                 if (++idx == HIFN_D_SRC_RSIZE) {
1594                         dma->srcr[idx].l = htole32(HIFN_D_VALID |
1595                             HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1596                         HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE,
1597                             BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1598                         idx = 0;
1599                 }
1600         }
1601         dma->srci = idx;
1602         dma->srcu += src->nsegs;
1603         return (idx);
1604 }
1605
1606 static void
1607 hifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
1608 {
1609         struct hifn_operand *op = arg;
1610
1611         KASSERT(nsegs <= MAX_SCATTER,
1612                 ("hifn_op_cb: too many DMA segments (%u > %u) "
1613                  "returned when mapping operand", nsegs, MAX_SCATTER));
1614         op->mapsize = mapsize;
1615         op->nsegs = nsegs;
1616         bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
1617 }
1618
1619 static int
1620 hifn_crypto(
1621         struct hifn_softc *sc,
1622         struct hifn_command *cmd,
1623         struct cryptop *crp,
1624         int hint)
1625 {
1626         struct  hifn_dma *dma = sc->sc_dma;
1627         u_int32_t cmdlen;
1628         int cmdi, resi, err = 0;
1629
1630         /*
1631          * need 1 cmd, and 1 res
1632          *
1633          * NB: check this first since it's easy.
1634          */
1635         if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE ||
1636             (dma->resu + 1) > HIFN_D_RES_RSIZE) {
1637 #ifdef HIFN_DEBUG
1638                 if (hifn_debug) {
1639                         device_printf(sc->sc_dev,
1640                                 "cmd/result exhaustion, cmdu %u resu %u\n",
1641                                 dma->cmdu, dma->resu);
1642                 }
1643 #endif
1644                 hifnstats.hst_nomem_cr++;
1645                 return (ERESTART);
1646         }
1647
1648         if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) {
1649                 hifnstats.hst_nomem_map++;
1650                 return (ENOMEM);
1651         }
1652
1653         if (crp->crp_flags & CRYPTO_F_IMBUF) {
1654                 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map,
1655                     cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) {
1656                         hifnstats.hst_nomem_load++;
1657                         err = ENOMEM;
1658                         goto err_srcmap1;
1659                 }
1660         } else if (crp->crp_flags & CRYPTO_F_IOV) {
1661                 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map,
1662                     cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) {
1663                         hifnstats.hst_nomem_load++;
1664                         err = ENOMEM;
1665                         goto err_srcmap1;
1666                 }
1667         } else {
1668                 err = EINVAL;
1669                 goto err_srcmap1;
1670         }
1671
1672         if (hifn_dmamap_aligned(&cmd->src)) {
1673                 cmd->sloplen = cmd->src_mapsize & 3;
1674                 cmd->dst = cmd->src;
1675         } else {
1676                 if (crp->crp_flags & CRYPTO_F_IOV) {
1677                         err = EINVAL;
1678                         goto err_srcmap;
1679                 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1680                         int totlen, len;
1681                         struct mbuf *m, *m0, *mlast;
1682
1683                         KASSERT(cmd->dst_m == cmd->src_m,
1684                                 ("hifn_crypto: dst_m initialized improperly"));
1685                         hifnstats.hst_unaligned++;
1686                         /*
1687                          * Source is not aligned on a longword boundary.
1688                          * Copy the data to insure alignment.  If we fail
1689                          * to allocate mbufs or clusters while doing this
1690                          * we return ERESTART so the operation is requeued
1691                          * at the crypto later, but only if there are
1692                          * ops already posted to the hardware; otherwise we
1693                          * have no guarantee that we'll be re-entered.
1694                          */
1695                         totlen = cmd->src_mapsize;
1696                         if (cmd->src_m->m_flags & M_PKTHDR) {
1697                                 len = MHLEN;
1698                                 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
1699                                 if (m0 && !m_dup_pkthdr(m0, cmd->src_m, MB_DONTWAIT)) {
1700                                         m_free(m0);
1701                                         m0 = NULL;
1702                                 }
1703                         } else {
1704                                 len = MLEN;
1705                                 MGET(m0, MB_DONTWAIT, MT_DATA);
1706                         }
1707                         if (m0 == NULL) {
1708                                 hifnstats.hst_nomem_mbuf++;
1709                                 err = dma->cmdu ? ERESTART : ENOMEM;
1710                                 goto err_srcmap;
1711                         }
1712                         if (totlen >= MINCLSIZE) {
1713                                 MCLGET(m0, MB_DONTWAIT);
1714                                 if ((m0->m_flags & M_EXT) == 0) {
1715                                         hifnstats.hst_nomem_mcl++;
1716                                         err = dma->cmdu ? ERESTART : ENOMEM;
1717                                         m_freem(m0);
1718                                         goto err_srcmap;
1719                                 }
1720                                 len = MCLBYTES;
1721                         }
1722                         totlen -= len;
1723                         m0->m_pkthdr.len = m0->m_len = len;
1724                         mlast = m0;
1725
1726                         while (totlen > 0) {
1727                                 MGET(m, MB_DONTWAIT, MT_DATA);
1728                                 if (m == NULL) {
1729                                         hifnstats.hst_nomem_mbuf++;
1730                                         err = dma->cmdu ? ERESTART : ENOMEM;
1731                                         m_freem(m0);
1732                                         goto err_srcmap;
1733                                 }
1734                                 len = MLEN;
1735                                 if (totlen >= MINCLSIZE) {
1736                                         MCLGET(m, MB_DONTWAIT);
1737                                         if ((m->m_flags & M_EXT) == 0) {
1738                                                 hifnstats.hst_nomem_mcl++;
1739                                                 err = dma->cmdu ? ERESTART : ENOMEM;
1740                                                 mlast->m_next = m;
1741                                                 m_freem(m0);
1742                                                 goto err_srcmap;
1743                                         }
1744                                         len = MCLBYTES;
1745                                 }
1746
1747                                 m->m_len = len;
1748                                 m0->m_pkthdr.len += len;
1749                                 totlen -= len;
1750
1751                                 mlast->m_next = m;
1752                                 mlast = m;
1753                         }
1754                         cmd->dst_m = m0;
1755                 }
1756         }
1757
1758         if (cmd->dst_map == NULL) {
1759                 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) {
1760                         hifnstats.hst_nomem_map++;
1761                         err = ENOMEM;
1762                         goto err_srcmap;
1763                 }
1764                 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1765                         if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map,
1766                             cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) {
1767                                 hifnstats.hst_nomem_map++;
1768                                 err = ENOMEM;
1769                                 goto err_dstmap1;
1770                         }
1771                 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1772                         if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map,
1773                             cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) {
1774                                 hifnstats.hst_nomem_load++;
1775                                 err = ENOMEM;
1776                                 goto err_dstmap1;
1777                         }
1778                 }
1779         }
1780
1781 #ifdef HIFN_DEBUG
1782         if (hifn_debug) {
1783                 device_printf(sc->sc_dev,
1784                     "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n",
1785                     READ_REG_1(sc, HIFN_1_DMA_CSR),
1786                     READ_REG_1(sc, HIFN_1_DMA_IER),
1787                     dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1788                     cmd->src_nsegs, cmd->dst_nsegs);
1789         }
1790 #endif
1791
1792         if (cmd->src_map == cmd->dst_map) {
1793                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
1794                     BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1795         } else {
1796                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
1797                     BUS_DMASYNC_PREWRITE);
1798                 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
1799                     BUS_DMASYNC_PREREAD);
1800         }
1801
1802         /*
1803          * need N src, and N dst
1804          */
1805         if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE ||
1806             (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) {
1807 #ifdef HIFN_DEBUG
1808                 if (hifn_debug) {
1809                         device_printf(sc->sc_dev,
1810                                 "src/dst exhaustion, srcu %u+%u dstu %u+%u\n",
1811                                 dma->srcu, cmd->src_nsegs,
1812                                 dma->dstu, cmd->dst_nsegs);
1813                 }
1814 #endif
1815                 hifnstats.hst_nomem_sd++;
1816                 err = ERESTART;
1817                 goto err_dstmap;
1818         }
1819
1820         if (dma->cmdi == HIFN_D_CMD_RSIZE) {
1821                 dma->cmdi = 0;
1822                 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
1823                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1824                 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE,
1825                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1826         }
1827         cmdi = dma->cmdi++;
1828         cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]);
1829         HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE);
1830
1831         /* .p for command/result already set */
1832         dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST |
1833             HIFN_D_MASKDONEIRQ);
1834         HIFN_CMDR_SYNC(sc, cmdi,
1835             BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1836         dma->cmdu++;
1837         if (sc->sc_c_busy == 0) {
1838                 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA);
1839                 sc->sc_c_busy = 1;
1840         }
1841
1842         /*
1843          * We don't worry about missing an interrupt (which a "command wait"
1844          * interrupt salvages us from), unless there is more than one command
1845          * in the queue.
1846          */
1847         if (dma->cmdu > 1) {
1848                 sc->sc_dmaier |= HIFN_DMAIER_C_WAIT;
1849                 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
1850         }
1851
1852         hifnstats.hst_ipackets++;
1853         hifnstats.hst_ibytes += cmd->src_mapsize;
1854
1855         hifn_dmamap_load_src(sc, cmd);
1856         if (sc->sc_s_busy == 0) {
1857                 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA);
1858                 sc->sc_s_busy = 1;
1859         }
1860
1861         /*
1862          * Unlike other descriptors, we don't mask done interrupt from
1863          * result descriptor.
1864          */
1865 #ifdef HIFN_DEBUG
1866         if (hifn_debug)
1867                 kprintf("load res\n");
1868 #endif
1869         if (dma->resi == HIFN_D_RES_RSIZE) {
1870                 dma->resi = 0;
1871                 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID |
1872                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1873                 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE,
1874                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1875         }
1876         resi = dma->resi++;
1877         KASSERT(dma->hifn_commands[resi] == NULL,
1878                 ("hifn_crypto: command slot %u busy", resi));
1879         dma->hifn_commands[resi] = cmd;
1880         HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD);
1881         if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) {
1882                 dma->resr[resi].l = htole32(HIFN_MAX_RESULT |
1883                     HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ);
1884                 sc->sc_curbatch++;
1885                 if (sc->sc_curbatch > hifnstats.hst_maxbatch)
1886                         hifnstats.hst_maxbatch = sc->sc_curbatch;
1887                 hifnstats.hst_totbatch++;
1888         } else {
1889                 dma->resr[resi].l = htole32(HIFN_MAX_RESULT |
1890                     HIFN_D_VALID | HIFN_D_LAST);
1891                 sc->sc_curbatch = 0;
1892         }
1893         HIFN_RESR_SYNC(sc, resi,
1894             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1895         dma->resu++;
1896         if (sc->sc_r_busy == 0) {
1897                 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA);
1898                 sc->sc_r_busy = 1;
1899         }
1900
1901         if (cmd->sloplen)
1902                 cmd->slopidx = resi;
1903
1904         hifn_dmamap_load_dst(sc, cmd);
1905
1906         if (sc->sc_d_busy == 0) {
1907                 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA);
1908                 sc->sc_d_busy = 1;
1909         }
1910
1911 #ifdef HIFN_DEBUG
1912         if (hifn_debug) {
1913                 device_printf(sc->sc_dev, "command: stat %8x ier %8x\n",
1914                     READ_REG_1(sc, HIFN_1_DMA_CSR),
1915                     READ_REG_1(sc, HIFN_1_DMA_IER));
1916         }
1917 #endif
1918
1919         sc->sc_active = 5;
1920         KASSERT(err == 0, ("hifn_crypto: success with error %u", err));
1921         return (err);           /* success */
1922
1923 err_dstmap:
1924         if (cmd->src_map != cmd->dst_map)
1925                 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
1926 err_dstmap1:
1927         if (cmd->src_map != cmd->dst_map)
1928                 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
1929 err_srcmap:
1930         if (crp->crp_flags & CRYPTO_F_IMBUF) {
1931                 if (cmd->src_m != cmd->dst_m)
1932                         m_freem(cmd->dst_m);
1933         }
1934         bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
1935 err_srcmap1:
1936         bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
1937         return (err);
1938 }
1939
1940 static void
1941 hifn_tick(void* vsc)
1942 {
1943         struct hifn_softc *sc = vsc;
1944
1945         crit_enter();
1946         if (sc->sc_active == 0) {
1947                 struct hifn_dma *dma = sc->sc_dma;
1948                 u_int32_t r = 0;
1949
1950                 if (dma->cmdu == 0 && sc->sc_c_busy) {
1951                         sc->sc_c_busy = 0;
1952                         r |= HIFN_DMACSR_C_CTRL_DIS;
1953                 }
1954                 if (dma->srcu == 0 && sc->sc_s_busy) {
1955                         sc->sc_s_busy = 0;
1956                         r |= HIFN_DMACSR_S_CTRL_DIS;
1957                 }
1958                 if (dma->dstu == 0 && sc->sc_d_busy) {
1959                         sc->sc_d_busy = 0;
1960                         r |= HIFN_DMACSR_D_CTRL_DIS;
1961                 }
1962                 if (dma->resu == 0 && sc->sc_r_busy) {
1963                         sc->sc_r_busy = 0;
1964                         r |= HIFN_DMACSR_R_CTRL_DIS;
1965                 }
1966                 if (r)
1967                         WRITE_REG_1(sc, HIFN_1_DMA_CSR, r);
1968         } else
1969                 sc->sc_active--;
1970         crit_exit();
1971         callout_reset(&sc->sc_tickto, hz, hifn_tick, sc);
1972 }
1973
1974 static void
1975 hifn_intr(void *arg)
1976 {
1977         struct hifn_softc *sc = arg;
1978         struct hifn_dma *dma;
1979         u_int32_t dmacsr, restart;
1980         int i, u;
1981
1982         dma = sc->sc_dma;
1983
1984         dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR);
1985
1986 #ifdef HIFN_DEBUG
1987         if (hifn_debug) {
1988                 device_printf(sc->sc_dev,
1989                     "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n",
1990                     dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier,
1991                     dma->cmdi, dma->srci, dma->dsti, dma->resi,
1992                     dma->cmdk, dma->srck, dma->dstk, dma->resk,
1993                     dma->cmdu, dma->srcu, dma->dstu, dma->resu);
1994         }
1995 #endif
1996
1997         /* Nothing in the DMA unit interrupted */
1998         if ((dmacsr & sc->sc_dmaier) == 0) {
1999                 hifnstats.hst_noirq++;
2000                 return;
2001         }
2002
2003         WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier);
2004
2005         if ((sc->sc_flags & HIFN_HAS_PUBLIC) &&
2006             (dmacsr & HIFN_DMACSR_PUBDONE))
2007                 WRITE_REG_1(sc, HIFN_1_PUB_STATUS,
2008                     READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE);
2009
2010         restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER);
2011         if (restart)
2012                 device_printf(sc->sc_dev, "overrun %x\n", dmacsr);
2013
2014         if (sc->sc_flags & HIFN_IS_7811) {
2015                 if (dmacsr & HIFN_DMACSR_ILLR)
2016                         device_printf(sc->sc_dev, "illegal read\n");
2017                 if (dmacsr & HIFN_DMACSR_ILLW)
2018                         device_printf(sc->sc_dev, "illegal write\n");
2019         }
2020
2021         restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT |
2022             HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT);
2023         if (restart) {
2024                 device_printf(sc->sc_dev, "abort, resetting.\n");
2025                 hifnstats.hst_abort++;
2026                 hifn_abort(sc);
2027                 return;
2028         }
2029
2030         if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) {
2031                 /*
2032                  * If no slots to process and we receive a "waiting on
2033                  * command" interrupt, we disable the "waiting on command"
2034                  * (by clearing it).
2035                  */
2036                 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
2037                 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
2038         }
2039
2040         /* clear the rings */
2041         i = dma->resk; u = dma->resu;
2042         while (u != 0) {
2043                 HIFN_RESR_SYNC(sc, i,
2044                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2045                 if (dma->resr[i].l & htole32(HIFN_D_VALID)) {
2046                         HIFN_RESR_SYNC(sc, i,
2047                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2048                         break;
2049                 }
2050
2051                 if (i != HIFN_D_RES_RSIZE) {
2052                         struct hifn_command *cmd;
2053                         u_int8_t *macbuf = NULL;
2054
2055                         HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD);
2056                         cmd = dma->hifn_commands[i];
2057                         KASSERT(cmd != NULL,
2058                                 ("hifn_intr: null command slot %u", i));
2059                         dma->hifn_commands[i] = NULL;
2060
2061                         if (cmd->base_masks & HIFN_BASE_CMD_MAC) {
2062                                 macbuf = dma->result_bufs[i];
2063                                 macbuf += 12;
2064                         }
2065
2066                         hifn_callback(sc, cmd, macbuf);
2067                         hifnstats.hst_opackets++;
2068                         u--;
2069                 }
2070
2071                 if (++i == (HIFN_D_RES_RSIZE + 1))
2072                         i = 0;
2073         }
2074         dma->resk = i; dma->resu = u;
2075
2076         i = dma->srck; u = dma->srcu;
2077         while (u != 0) {
2078                 if (i == HIFN_D_SRC_RSIZE)
2079                         i = 0;
2080                 HIFN_SRCR_SYNC(sc, i,
2081                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2082                 if (dma->srcr[i].l & htole32(HIFN_D_VALID)) {
2083                         HIFN_SRCR_SYNC(sc, i,
2084                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2085                         break;
2086                 }
2087                 i++, u--;
2088         }
2089         dma->srck = i; dma->srcu = u;
2090
2091         i = dma->cmdk; u = dma->cmdu;
2092         while (u != 0) {
2093                 HIFN_CMDR_SYNC(sc, i,
2094                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2095                 if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) {
2096                         HIFN_CMDR_SYNC(sc, i,
2097                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2098                         break;
2099                 }
2100                 if (i != HIFN_D_CMD_RSIZE) {
2101                         u--;
2102                         HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE);
2103                 }
2104                 if (++i == (HIFN_D_CMD_RSIZE + 1))
2105                         i = 0;
2106         }
2107         dma->cmdk = i; dma->cmdu = u;
2108
2109         if (sc->sc_needwakeup) {                /* XXX check high watermark */
2110                 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
2111 #ifdef HIFN_DEBUG
2112                 if (hifn_debug)
2113                         device_printf(sc->sc_dev,
2114                                 "wakeup crypto (%x) u %d/%d/%d/%d\n",
2115                                 sc->sc_needwakeup,
2116                                 dma->cmdu, dma->srcu, dma->dstu, dma->resu);
2117 #endif
2118                 sc->sc_needwakeup &= ~wakeup;
2119                 crypto_unblock(sc->sc_cid, wakeup);
2120         }
2121 }
2122
2123 /*
2124  * Allocate a new 'session' and return an encoded session id.  'sidp'
2125  * contains our registration id, and should contain an encoded session
2126  * id on successful allocation.
2127  */
2128 static int
2129 hifn_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri)
2130 {
2131         struct cryptoini *c;
2132         struct hifn_softc *sc = arg;
2133         int i, mac = 0, cry = 0;
2134
2135         KASSERT(sc != NULL, ("hifn_newsession: null softc"));
2136         if (sidp == NULL || cri == NULL || sc == NULL)
2137                 return (EINVAL);
2138
2139         for (i = 0; i < sc->sc_maxses; i++)
2140                 if (sc->sc_sessions[i].hs_state == HS_STATE_FREE)
2141                         break;
2142         if (i == sc->sc_maxses)
2143                 return (ENOMEM);
2144
2145         for (c = cri; c != NULL; c = c->cri_next) {
2146                 switch (c->cri_alg) {
2147                 case CRYPTO_MD5:
2148                 case CRYPTO_SHA1:
2149                 case CRYPTO_MD5_HMAC:
2150                 case CRYPTO_SHA1_HMAC:
2151                         if (mac)
2152                                 return (EINVAL);
2153                         mac = 1;
2154                         break;
2155                 case CRYPTO_DES_CBC:
2156                 case CRYPTO_3DES_CBC:
2157                         /* XXX this may read fewer, does it matter? */
2158                         read_random(sc->sc_sessions[i].hs_iv, HIFN_IV_LENGTH);
2159                         /*FALLTHROUGH*/
2160                 case CRYPTO_ARC4:
2161                         if (cry)
2162                                 return (EINVAL);
2163                         cry = 1;
2164                         break;
2165                 default:
2166                         return (EINVAL);
2167                 }
2168         }
2169         if (mac == 0 && cry == 0)
2170                 return (EINVAL);
2171
2172         *sidp = HIFN_SID(device_get_unit(sc->sc_dev), i);
2173         sc->sc_sessions[i].hs_state = HS_STATE_USED;
2174
2175         return (0);
2176 }
2177
2178 /*
2179  * Deallocate a session.
2180  * XXX this routine should run a zero'd mac/encrypt key into context ram.
2181  * XXX to blow away any keys already stored there.
2182  */
2183 static int
2184 hifn_freesession(void *arg, u_int64_t tid)
2185 {
2186         struct hifn_softc *sc = arg;
2187         int session;
2188         u_int32_t sid = ((u_int32_t) tid) & 0xffffffff;
2189
2190         KASSERT(sc != NULL, ("hifn_freesession: null softc"));
2191         if (sc == NULL)
2192                 return (EINVAL);
2193
2194         session = HIFN_SESSION(sid);
2195         if (session >= sc->sc_maxses)
2196                 return (EINVAL);
2197
2198         bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session]));
2199         return (0);
2200 }
2201
2202 static int
2203 hifn_process(void *arg, struct cryptop *crp, int hint)
2204 {
2205         struct hifn_softc *sc = arg;
2206         struct hifn_command *cmd = NULL;
2207         int session, err;
2208         struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
2209
2210         if (crp == NULL || crp->crp_callback == NULL) {
2211                 hifnstats.hst_invalid++;
2212                 return (EINVAL);
2213         }
2214         session = HIFN_SESSION(crp->crp_sid);
2215
2216         if (sc == NULL || session >= sc->sc_maxses) {
2217                 err = EINVAL;
2218                 goto errout;
2219         }
2220
2221         cmd = kmalloc(sizeof(struct hifn_command), M_DEVBUF, M_INTWAIT | M_ZERO);
2222
2223         if (crp->crp_flags & CRYPTO_F_IMBUF) {
2224                 cmd->src_m = (struct mbuf *)crp->crp_buf;
2225                 cmd->dst_m = (struct mbuf *)crp->crp_buf;
2226         } else if (crp->crp_flags & CRYPTO_F_IOV) {
2227                 cmd->src_io = (struct uio *)crp->crp_buf;
2228                 cmd->dst_io = (struct uio *)crp->crp_buf;
2229         } else {
2230                 err = EINVAL;
2231                 goto errout;    /* XXX we don't handle contiguous buffers! */
2232         }
2233
2234         crd1 = crp->crp_desc;
2235         if (crd1 == NULL) {
2236                 err = EINVAL;
2237                 goto errout;
2238         }
2239         crd2 = crd1->crd_next;
2240
2241         if (crd2 == NULL) {
2242                 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
2243                     crd1->crd_alg == CRYPTO_SHA1_HMAC ||
2244                     crd1->crd_alg == CRYPTO_SHA1 ||
2245                     crd1->crd_alg == CRYPTO_MD5) {
2246                         maccrd = crd1;
2247                         enccrd = NULL;
2248                 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
2249                     crd1->crd_alg == CRYPTO_3DES_CBC ||
2250                     crd1->crd_alg == CRYPTO_ARC4) {
2251                         if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0)
2252                                 cmd->base_masks |= HIFN_BASE_CMD_DECODE;
2253                         maccrd = NULL;
2254                         enccrd = crd1;
2255                 } else {
2256                         err = EINVAL;
2257                         goto errout;
2258                 }
2259         } else {
2260                 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
2261                      crd1->crd_alg == CRYPTO_SHA1_HMAC ||
2262                      crd1->crd_alg == CRYPTO_MD5 ||
2263                      crd1->crd_alg == CRYPTO_SHA1) &&
2264                     (crd2->crd_alg == CRYPTO_DES_CBC ||
2265                      crd2->crd_alg == CRYPTO_3DES_CBC ||
2266                      crd2->crd_alg == CRYPTO_ARC4) &&
2267                     ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
2268                         cmd->base_masks = HIFN_BASE_CMD_DECODE;
2269                         maccrd = crd1;
2270                         enccrd = crd2;
2271                 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
2272                      crd1->crd_alg == CRYPTO_ARC4 ||
2273                      crd1->crd_alg == CRYPTO_3DES_CBC) &&
2274                     (crd2->crd_alg == CRYPTO_MD5_HMAC ||
2275                      crd2->crd_alg == CRYPTO_SHA1_HMAC ||
2276                      crd2->crd_alg == CRYPTO_MD5 ||
2277                      crd2->crd_alg == CRYPTO_SHA1) &&
2278                     (crd1->crd_flags & CRD_F_ENCRYPT)) {
2279                         enccrd = crd1;
2280                         maccrd = crd2;
2281                 } else {
2282                         /*
2283                          * We cannot order the 7751 as requested
2284                          */
2285                         err = EINVAL;
2286                         goto errout;
2287                 }
2288         }
2289
2290         if (enccrd) {
2291                 cmd->enccrd = enccrd;
2292                 cmd->base_masks |= HIFN_BASE_CMD_CRYPT;
2293                 switch (enccrd->crd_alg) {
2294                 case CRYPTO_ARC4:
2295                         cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4;
2296                         if ((enccrd->crd_flags & CRD_F_ENCRYPT)
2297                             != sc->sc_sessions[session].hs_prev_op)
2298                                 sc->sc_sessions[session].hs_state =
2299                                     HS_STATE_USED;
2300                         break;
2301                 case CRYPTO_DES_CBC:
2302                         cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES |
2303                             HIFN_CRYPT_CMD_MODE_CBC |
2304                             HIFN_CRYPT_CMD_NEW_IV;
2305                         break;
2306                 case CRYPTO_3DES_CBC:
2307                         cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES |
2308                             HIFN_CRYPT_CMD_MODE_CBC |
2309                             HIFN_CRYPT_CMD_NEW_IV;
2310                         break;
2311                 default:
2312                         err = EINVAL;
2313                         goto errout;
2314                 }
2315                 if (enccrd->crd_alg != CRYPTO_ARC4) {
2316                         if (enccrd->crd_flags & CRD_F_ENCRYPT) {
2317                                 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
2318                                         bcopy(enccrd->crd_iv, cmd->iv,
2319                                             HIFN_IV_LENGTH);
2320                                 else
2321                                         bcopy(sc->sc_sessions[session].hs_iv,
2322                                             cmd->iv, HIFN_IV_LENGTH);
2323
2324                                 if ((enccrd->crd_flags & CRD_F_IV_PRESENT)
2325                                     == 0) {
2326                                         if (crp->crp_flags & CRYPTO_F_IMBUF)
2327                                                 m_copyback(cmd->src_m,
2328                                                     enccrd->crd_inject,
2329                                                     HIFN_IV_LENGTH, cmd->iv);
2330                                         else if (crp->crp_flags & CRYPTO_F_IOV)
2331                                                 cuio_copyback(cmd->src_io,
2332                                                     enccrd->crd_inject,
2333                                                     HIFN_IV_LENGTH, cmd->iv);
2334                                 }
2335                         } else {
2336                                 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
2337                                         bcopy(enccrd->crd_iv, cmd->iv,
2338                                             HIFN_IV_LENGTH);
2339                                 else if (crp->crp_flags & CRYPTO_F_IMBUF)
2340                                         m_copydata(cmd->src_m,
2341                                             enccrd->crd_inject,
2342                                             HIFN_IV_LENGTH, cmd->iv);
2343                                 else if (crp->crp_flags & CRYPTO_F_IOV)
2344                                         cuio_copydata(cmd->src_io,
2345                                             enccrd->crd_inject,
2346                                             HIFN_IV_LENGTH, cmd->iv);
2347                         }
2348                 }
2349
2350                 cmd->ck = enccrd->crd_key;
2351                 cmd->cklen = enccrd->crd_klen >> 3;
2352
2353                 if (sc->sc_sessions[session].hs_state == HS_STATE_USED)
2354                         cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY;
2355         }
2356
2357         if (maccrd) {
2358                 cmd->maccrd = maccrd;
2359                 cmd->base_masks |= HIFN_BASE_CMD_MAC;
2360
2361                 switch (maccrd->crd_alg) {
2362                 case CRYPTO_MD5:
2363                         cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 |
2364                             HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH |
2365                             HIFN_MAC_CMD_POS_IPSEC;
2366                        break;
2367                 case CRYPTO_MD5_HMAC:
2368                         cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 |
2369                             HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC |
2370                             HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC;
2371                         break;
2372                 case CRYPTO_SHA1:
2373                         cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 |
2374                             HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH |
2375                             HIFN_MAC_CMD_POS_IPSEC;
2376                         break;
2377                 case CRYPTO_SHA1_HMAC:
2378                         cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 |
2379                             HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC |
2380                             HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC;
2381                         break;
2382                 }
2383
2384                 if ((maccrd->crd_alg == CRYPTO_SHA1_HMAC ||
2385                      maccrd->crd_alg == CRYPTO_MD5_HMAC) &&
2386                     sc->sc_sessions[session].hs_state == HS_STATE_USED) {
2387                         cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY;
2388                         bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3);
2389                         bzero(cmd->mac + (maccrd->crd_klen >> 3),
2390                             HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3));
2391                 }
2392         }
2393
2394         cmd->crp = crp;
2395         cmd->session_num = session;
2396         cmd->softc = sc;
2397
2398         err = hifn_crypto(sc, cmd, crp, hint);
2399         if (!err) {
2400                 if (enccrd)
2401                         sc->sc_sessions[session].hs_prev_op =
2402                                 enccrd->crd_flags & CRD_F_ENCRYPT;
2403                 if (sc->sc_sessions[session].hs_state == HS_STATE_USED)
2404                         sc->sc_sessions[session].hs_state = HS_STATE_KEY;
2405                 return 0;
2406         } else if (err == ERESTART) {
2407                 /*
2408                  * There weren't enough resources to dispatch the request
2409                  * to the part.  Notify the caller so they'll requeue this
2410                  * request and resubmit it again soon.
2411                  */
2412 #ifdef HIFN_DEBUG
2413                 if (hifn_debug)
2414                         device_printf(sc->sc_dev, "requeue request\n");
2415 #endif
2416                 kfree(cmd, M_DEVBUF);
2417                 sc->sc_needwakeup |= CRYPTO_SYMQ;
2418                 return (err);
2419         }
2420
2421 errout:
2422         if (cmd != NULL)
2423                 kfree(cmd, M_DEVBUF);
2424         if (err == EINVAL)
2425                 hifnstats.hst_invalid++;
2426         else
2427                 hifnstats.hst_nomem++;
2428         crp->crp_etype = err;
2429         crypto_done(crp);
2430         return (err);
2431 }
2432
2433 static void
2434 hifn_abort(struct hifn_softc *sc)
2435 {
2436         struct hifn_dma *dma = sc->sc_dma;
2437         struct hifn_command *cmd;
2438         struct cryptop *crp;
2439         int i, u;
2440
2441         i = dma->resk; u = dma->resu;
2442         while (u != 0) {
2443                 cmd = dma->hifn_commands[i];
2444                 KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i));
2445                 dma->hifn_commands[i] = NULL;
2446                 crp = cmd->crp;
2447
2448                 if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) {
2449                         /* Salvage what we can. */
2450                         u_int8_t *macbuf;
2451
2452                         if (cmd->base_masks & HIFN_BASE_CMD_MAC) {
2453                                 macbuf = dma->result_bufs[i];
2454                                 macbuf += 12;
2455                         } else
2456                                 macbuf = NULL;
2457                         hifnstats.hst_opackets++;
2458                         hifn_callback(sc, cmd, macbuf);
2459                 } else {
2460                         if (cmd->src_map == cmd->dst_map) {
2461                                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2462                                     BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2463                         } else {
2464                                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2465                                     BUS_DMASYNC_POSTWRITE);
2466                                 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2467                                     BUS_DMASYNC_POSTREAD);
2468                         }
2469
2470                         if (cmd->src_m != cmd->dst_m) {
2471                                 m_freem(cmd->src_m);
2472                                 crp->crp_buf = (caddr_t)cmd->dst_m;
2473                         }
2474
2475                         /* non-shared buffers cannot be restarted */
2476                         if (cmd->src_map != cmd->dst_map) {
2477                                 /*
2478                                  * XXX should be EAGAIN, delayed until
2479                                  * after the reset.
2480                                  */
2481                                 crp->crp_etype = ENOMEM;
2482                                 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2483                                 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2484                         } else
2485                                 crp->crp_etype = ENOMEM;
2486
2487                         bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2488                         bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2489
2490                         kfree(cmd, M_DEVBUF);
2491                         if (crp->crp_etype != EAGAIN)
2492                                 crypto_done(crp);
2493                 }
2494
2495                 if (++i == HIFN_D_RES_RSIZE)
2496                         i = 0;
2497                 u--;
2498         }
2499         dma->resk = i; dma->resu = u;
2500
2501         /* Force upload of key next time */
2502         for (i = 0; i < sc->sc_maxses; i++)
2503                 if (sc->sc_sessions[i].hs_state == HS_STATE_KEY)
2504                         sc->sc_sessions[i].hs_state = HS_STATE_USED;
2505
2506         hifn_reset_board(sc, 1);
2507         hifn_init_dma(sc);
2508         hifn_init_pci_registers(sc);
2509 }
2510
2511 static void
2512 hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf)
2513 {
2514         struct hifn_dma *dma = sc->sc_dma;
2515         struct cryptop *crp = cmd->crp;
2516         struct cryptodesc *crd;
2517         struct mbuf *m;
2518         int totlen, i, u;
2519
2520         if (cmd->src_map == cmd->dst_map) {
2521                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2522                     BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2523         } else {
2524                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2525                     BUS_DMASYNC_POSTWRITE);
2526                 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2527                     BUS_DMASYNC_POSTREAD);
2528         }
2529
2530         if (crp->crp_flags & CRYPTO_F_IMBUF) {
2531                 if (cmd->src_m != cmd->dst_m) {
2532                         crp->crp_buf = (caddr_t)cmd->dst_m;
2533                         totlen = cmd->src_mapsize;
2534                         for (m = cmd->dst_m; m != NULL; m = m->m_next) {
2535                                 if (totlen < m->m_len) {
2536                                         m->m_len = totlen;
2537                                         totlen = 0;
2538                                 } else
2539                                         totlen -= m->m_len;
2540                         }
2541                         cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len;
2542                         m_freem(cmd->src_m);
2543                 }
2544         }
2545
2546         if (cmd->sloplen != 0) {
2547                 if (crp->crp_flags & CRYPTO_F_IMBUF)
2548                         m_copyback((struct mbuf *)crp->crp_buf,
2549                             cmd->src_mapsize - cmd->sloplen,
2550                             cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]);
2551                 else if (crp->crp_flags & CRYPTO_F_IOV)
2552                         cuio_copyback((struct uio *)crp->crp_buf,
2553                             cmd->src_mapsize - cmd->sloplen,
2554                             cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]);
2555         }
2556
2557         i = dma->dstk; u = dma->dstu;
2558         while (u != 0) {
2559                 if (i == HIFN_D_DST_RSIZE)
2560                         i = 0;
2561                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
2562                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2563                 if (dma->dstr[i].l & htole32(HIFN_D_VALID)) {
2564                         bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
2565                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2566                         break;
2567                 }
2568                 i++, u--;
2569         }
2570         dma->dstk = i; dma->dstu = u;
2571
2572         hifnstats.hst_obytes += cmd->dst_mapsize;
2573
2574         if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) ==
2575             HIFN_BASE_CMD_CRYPT) {
2576                 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
2577                         if (crd->crd_alg != CRYPTO_DES_CBC &&
2578                             crd->crd_alg != CRYPTO_3DES_CBC)
2579                                 continue;
2580                         if (crp->crp_flags & CRYPTO_F_IMBUF)
2581                                 m_copydata((struct mbuf *)crp->crp_buf,
2582                                     crd->crd_skip + crd->crd_len - HIFN_IV_LENGTH,
2583                                     HIFN_IV_LENGTH,
2584                                     cmd->softc->sc_sessions[cmd->session_num].hs_iv);
2585                         else if (crp->crp_flags & CRYPTO_F_IOV) {
2586                                 cuio_copydata((struct uio *)crp->crp_buf,
2587                                     crd->crd_skip + crd->crd_len - HIFN_IV_LENGTH,
2588                                     HIFN_IV_LENGTH,
2589                                     cmd->softc->sc_sessions[cmd->session_num].hs_iv);
2590                         }
2591                         break;
2592                 }
2593         }
2594
2595         if (macbuf != NULL) {
2596                 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
2597                         int len;
2598
2599                         if (crd->crd_alg == CRYPTO_MD5)
2600                                 len = 16;
2601                         else if (crd->crd_alg == CRYPTO_SHA1)
2602                                 len = 20;
2603                         else if (crd->crd_alg == CRYPTO_MD5_HMAC ||
2604                             crd->crd_alg == CRYPTO_SHA1_HMAC)
2605                                 len = 12;
2606                         else
2607                                 continue;
2608
2609                         if (crp->crp_flags & CRYPTO_F_IMBUF)
2610                                 m_copyback((struct mbuf *)crp->crp_buf,
2611                                    crd->crd_inject, len, macbuf);
2612                         else if ((crp->crp_flags & CRYPTO_F_IOV) && crp->crp_mac)
2613                                 bcopy((caddr_t)macbuf, crp->crp_mac, len);
2614                         break;
2615                 }
2616         }
2617
2618         if (cmd->src_map != cmd->dst_map) {
2619                 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2620                 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2621         }
2622         bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2623         bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2624         kfree(cmd, M_DEVBUF);
2625         crypto_done(crp);
2626 }
2627
2628 /*
2629  * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0
2630  * and Group 1 registers; avoid conditions that could create
2631  * burst writes by doing a read in between the writes.
2632  *
2633  * NB: The read we interpose is always to the same register;
2634  *     we do this because reading from an arbitrary (e.g. last)
2635  *     register may not always work.
2636  */
2637 static void
2638 hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val)
2639 {
2640         if (sc->sc_flags & HIFN_IS_7811) {
2641                 if (sc->sc_bar0_lastreg == reg - 4)
2642                         bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG);
2643                 sc->sc_bar0_lastreg = reg;
2644         }
2645         bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val);
2646 }
2647
2648 static void
2649 hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val)
2650 {
2651         if (sc->sc_flags & HIFN_IS_7811) {
2652                 if (sc->sc_bar1_lastreg == reg - 4)
2653                         bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID);
2654                 sc->sc_bar1_lastreg = reg;
2655         }
2656         bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val);
2657 }