sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.102 2008/07/13 11:02:50 sephe Exp $
  35  *
  36  */
  37
  38 /*
  39  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  40  *
  41  * Written by Bill Paul <wpaul@windriver.com>
  42  * Senior Engineer, Wind River Systems
  43  */
  44
  45 /*
  46  * The Broadcom BCM5700 is based on technology originally developed by
  47  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  48  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  49  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  50  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  51  * frames, highly configurable RX filtering, and 16 RX and TX queues
  52  * (which, along with RX filter rules, can be used for QOS applications).
  53  * Other features, such as TCP segmentation, may be available as part
  54  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  55  * firmware images can be stored in hardware and need not be compiled
  56  * into the driver.
  57  *
  58  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  59  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  60  *
  61  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  62  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  63  * does not support external SSRAM.
  64  *
  65  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  66  * brand name, which is functionally similar but lacks PCI-X support.
  67  *
  68  * Without external SSRAM, you can only have at most 4 TX rings,
  69  * and the use of the mini RX ring is disabled. This seems to imply
  70  * that these features are simply not available on the BCM5701. As a
  71  * result, this driver does not implement any support for the mini RX
  72  * ring.
  73  */
  74
  75 #include "opt_polling.h"
  76 #include "opt_ethernet.h"
  77
  78 #include <sys/param.h>
  79 #include <sys/bus.h>
  80 #include <sys/endian.h>
  81 #include <sys/kernel.h>
  82 #include <sys/ktr.h>
  83 #include <sys/interrupt.h>
  84 #include <sys/mbuf.h>
  85 #include <sys/malloc.h>
  86 #include <sys/queue.h>
  87 #include <sys/rman.h>
  88 #include <sys/serialize.h>
  89 #include <sys/socket.h>
  90 #include <sys/sockio.h>
  91 #include <sys/sysctl.h>
  92
  93 #include <net/bpf.h>
  94 #include <net/ethernet.h>
  95 #include <net/if.h>
  96 #include <net/if_arp.h>
  97 #include <net/if_dl.h>
  98 #include <net/if_media.h>
  99 #include <net/if_types.h>
 100 #include <net/ifq_var.h>
 101 #include <net/vlan/if_vlan_var.h>
 102 #include <net/vlan/if_vlan_ether.h>
 103
 104 #include <dev/netif/mii_layer/mii.h>
 105 #include <dev/netif/mii_layer/miivar.h>
 106 #include <dev/netif/mii_layer/brgphyreg.h>
 107
 108 #include <bus/pci/pcidevs.h>
 109 #include <bus/pci/pcireg.h>
 110 #include <bus/pci/pcivar.h>
 111
 112 #include <dev/netif/bge/if_bgereg.h>
 113
 114 /* "device miibus" required.  See GENERIC if you get errors here. */
 115 #include "miibus_if.h"
 116
 117 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 118 #define BGE_MIN_FRAME           60
 119
 120 static const struct bge_type bge_devs[] = {
 121         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
 122                 "3COM 3C996 Gigabit Ethernet" },
 123
 124         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 125                 "Alteon BCM5700 Gigabit Ethernet" },
 126         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
 127                 "Alteon BCM5701 Gigabit Ethernet" },
 128
 129         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 130                 "Altima AC1000 Gigabit Ethernet" },
 131         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 132                 "Altima AC1002 Gigabit Ethernet" },
 133         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 134                 "Altima AC9100 Gigabit Ethernet" },
 135
 136         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
 137                 "Apple BCM5701 Gigabit Ethernet" },
 138
 139         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 140                 "Broadcom BCM5700 Gigabit Ethernet" },
 141         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 142                 "Broadcom BCM5701 Gigabit Ethernet" },
 143         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
 144                 "Broadcom BCM5702 Gigabit Ethernet" },
 145         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 146                 "Broadcom BCM5702X Gigabit Ethernet" },
 147         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
 148                 "Broadcom BCM5702 Gigabit Ethernet" },
 149         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
 150                 "Broadcom BCM5703 Gigabit Ethernet" },
 151         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 152                 "Broadcom BCM5703X Gigabit Ethernet" },
 153         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
 154                 "Broadcom BCM5703 Gigabit Ethernet" },
 155         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 156                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 157         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 158                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 159         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
 160                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 161         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 162                 "Broadcom BCM5705 Gigabit Ethernet" },
 163         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
 164                 "Broadcom BCM5705F Gigabit Ethernet" },
 165         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
 166                 "Broadcom BCM5705K Gigabit Ethernet" },
 167         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 168                 "Broadcom BCM5705M Gigabit Ethernet" },
 169         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
 170                 "Broadcom BCM5705M Gigabit Ethernet" },
 171         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
 172                 "Broadcom BCM5714C Gigabit Ethernet" },
 173         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
 174                 "Broadcom BCM5714S Gigabit Ethernet" },
 175         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
 176                 "Broadcom BCM5715 Gigabit Ethernet" },
 177         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
 178                 "Broadcom BCM5715S Gigabit Ethernet" },
 179         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
 180                 "Broadcom BCM5720 Gigabit Ethernet" },
 181         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
 182                 "Broadcom BCM5721 Gigabit Ethernet" },
 183         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
 184                 "Broadcom BCM5722 Gigabit Ethernet" },
 185         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
 186                 "Broadcom BCM5750 Gigabit Ethernet" },
 187         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
 188                 "Broadcom BCM5750M Gigabit Ethernet" },
 189         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
 190                 "Broadcom BCM5751 Gigabit Ethernet" },
 191         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
 192                 "Broadcom BCM5751F Gigabit Ethernet" },
 193         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
 194                 "Broadcom BCM5751M Gigabit Ethernet" },
 195         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
 196                 "Broadcom BCM5752 Gigabit Ethernet" },
 197         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
 198                 "Broadcom BCM5752M Gigabit Ethernet" },
 199         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
 200                 "Broadcom BCM5753 Gigabit Ethernet" },
 201         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
 202                 "Broadcom BCM5753F Gigabit Ethernet" },
 203         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
 204                 "Broadcom BCM5753M Gigabit Ethernet" },
 205         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
 206                 "Broadcom BCM5754 Gigabit Ethernet" },
 207         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
 208                 "Broadcom BCM5754M Gigabit Ethernet" },
 209         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
 210                 "Broadcom BCM5755 Gigabit Ethernet" },
 211         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
 212                 "Broadcom BCM5755M Gigabit Ethernet" },
 213         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
 214                 "Broadcom BCM5756 Gigabit Ethernet" },
 215         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
 216                 "Broadcom BCM5780 Gigabit Ethernet" },
 217         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
 218                 "Broadcom BCM5780S Gigabit Ethernet" },
 219         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
 220                 "Broadcom BCM5781 Gigabit Ethernet" },
 221         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 222                 "Broadcom BCM5782 Gigabit Ethernet" },
 223         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
 224                 "Broadcom BCM5786 Gigabit Ethernet" },
 225         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
 226                 "Broadcom BCM5787 Gigabit Ethernet" },
 227         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
 228                 "Broadcom BCM5787F Gigabit Ethernet" },
 229         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
 230                 "Broadcom BCM5787M Gigabit Ethernet" },
 231         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
 232                 "Broadcom BCM5788 Gigabit Ethernet" },
 233         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
 234                 "Broadcom BCM5789 Gigabit Ethernet" },
 235         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 236                 "Broadcom BCM5901 Fast Ethernet" },
 237         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 238                 "Broadcom BCM5901A2 Fast Ethernet" },
 239         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
 240                 "Broadcom BCM5903M Fast Ethernet" },
 241
 242         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 243                 "SysKonnect Gigabit Ethernet" },
 244
 245         { 0, 0, NULL }
 246 };
 247
 248 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 249 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 250 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 251 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 252 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 253
 254 static int      bge_probe(device_t);
 255 static int      bge_attach(device_t);
 256 static int      bge_detach(device_t);
 257 static void     bge_txeof(struct bge_softc *);
 258 static void     bge_rxeof(struct bge_softc *);
 259
 260 static void     bge_tick(void *);
 261 static void     bge_stats_update(struct bge_softc *);
 262 static void     bge_stats_update_regs(struct bge_softc *);
 263 static int      bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 264
 265 #ifdef DEVICE_POLLING
 266 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 267 #endif
 268 static void     bge_intr(void *);
 269 static void     bge_enable_intr(struct bge_softc *);
 270 static void     bge_disable_intr(struct bge_softc *);
 271 static void     bge_start(struct ifnet *);
 272 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 273 static void     bge_init(void *);
 274 static void     bge_stop(struct bge_softc *);
 275 static void     bge_watchdog(struct ifnet *);
 276 static void     bge_shutdown(device_t);
 277 static int      bge_suspend(device_t);
 278 static int      bge_resume(device_t);
 279 static int      bge_ifmedia_upd(struct ifnet *);
 280 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 281
 282 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 283 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 284
 285 static void     bge_setmulti(struct bge_softc *);
 286 static void     bge_setpromisc(struct bge_softc *);
 287
 288 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 289 static void     bge_free_jumbo_mem(struct bge_softc *);
 290 static struct bge_jslot
 291                 *bge_jalloc(struct bge_softc *);
 292 static void     bge_jfree(void *);
 293 static void     bge_jref(void *);
 294 static int      bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
 295 static int      bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
 296 static int      bge_init_rx_ring_std(struct bge_softc *);
 297 static void     bge_free_rx_ring_std(struct bge_softc *);
 298 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 299 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 300 static void     bge_free_tx_ring(struct bge_softc *);
 301 static int      bge_init_tx_ring(struct bge_softc *);
 302
 303 static int      bge_chipinit(struct bge_softc *);
 304 static int      bge_blockinit(struct bge_softc *);
 305
 306 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 307 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 308 #ifdef notdef
 309 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 310 #endif
 311 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 312 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
 313 static void     bge_set_max_readrq(struct bge_softc *);
 314
 315 static int      bge_miibus_readreg(device_t, int, int);
 316 static int      bge_miibus_writereg(device_t, int, int, int);
 317 static void     bge_miibus_statchg(device_t);
 318 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
 319 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
 320 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
 321
 322 static void     bge_reset(struct bge_softc *);
 323
 324 static void     bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 325 static void     bge_dma_map_mbuf(void *, bus_dma_segment_t *, int,
 326                                  bus_size_t, int);
 327 static int      bge_dma_alloc(struct bge_softc *);
 328 static void     bge_dma_free(struct bge_softc *);
 329 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
 330                                     bus_dma_tag_t *, bus_dmamap_t *,
 331                                     void **, bus_addr_t *);
 332 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 333
 334 static void     bge_coal_change(struct bge_softc *);
 335 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 336 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 337 static int      bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 338 static int      bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 339 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
 340
 341 /*
 342  * Set following tunable to 1 for some IBM blade servers with the DNLK
 343  * switch module. Auto negotiation is broken for those configurations.
 344  */
 345 static int      bge_fake_autoneg = 0;
 346 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
 347
 348 /* Interrupt moderation control variables. */
 349 static int      bge_rx_coal_ticks = 150;        /* usec */
 350 static int      bge_tx_coal_ticks = 1023;       /* usec */
 351 static int      bge_rx_max_coal_bds = 80;
 352 static int      bge_tx_max_coal_bds = 128;
 353
 354 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
 355 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
 356 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
 357 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
 358
 359 #if !defined(KTR_IF_BGE)
 360 #define KTR_IF_BGE      KTR_ALL
 361 #endif
 362 KTR_INFO_MASTER(if_bge);
 363 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr", 0);
 364 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt", 0);
 365 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt", 0);
 366 #define logif(name)     KTR_LOG(if_bge_ ## name)
 367
 368 static device_method_t bge_methods[] = {
 369         /* Device interface */
 370         DEVMETHOD(device_probe,         bge_probe),
 371         DEVMETHOD(device_attach,        bge_attach),
 372         DEVMETHOD(device_detach,        bge_detach),
 373         DEVMETHOD(device_shutdown,      bge_shutdown),
 374         DEVMETHOD(device_suspend,       bge_suspend),
 375         DEVMETHOD(device_resume,        bge_resume),
 376
 377         /* bus interface */
 378         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 379         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 380
 381         /* MII interface */
 382         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 383         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 384         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 385
 386         { 0, 0 }
 387 };
 388
 389 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 390 static devclass_t bge_devclass;
 391
 392 DECLARE_DUMMY_MODULE(if_bge);
 393 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
 394 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 395
 396 static uint32_t
 397 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 398 {
 399         device_t dev = sc->bge_dev;
 400         uint32_t val;
 401
 402         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 403         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 404         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 405         return (val);
 406 }
 407
 408 static void
 409 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 410 {
 411         device_t dev = sc->bge_dev;
 412
 413         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 414         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 415         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 416 }
 417
 418 /*
 419  * PCI Express only
 420  */
 421 static void
 422 bge_set_max_readrq(struct bge_softc *sc)
 423 {
 424         device_t dev = sc->bge_dev;
 425         uint16_t val;
 426         uint8_t expr_ptr;
 427
 428         KKASSERT((sc->bge_flags & BGE_FLAG_PCIE) && sc->bge_expr_ptr != 0);
 429         expr_ptr = sc->bge_expr_ptr;
 430
 431         val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
 432         if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) !=
 433             PCIEM_DEVCTL_MAX_READRQ_4096) {
 434                 device_printf(dev, "adjust device control 0x%04x ", val);
 435
 436                 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
 437                 val |= PCIEM_DEVCTL_MAX_READRQ_4096;
 438                 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
 439
 440                 kprintf("-> 0x%04x\n", val);
 441         }
 442 }
 443
 444 #ifdef notdef
 445 static uint32_t
 446 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 447 {
 448         device_t dev = sc->bge_dev;
 449
 450         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 451         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 452 }
 453 #endif
 454
 455 static void
 456 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 457 {
 458         device_t dev = sc->bge_dev;
 459
 460         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 461         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 462 }
 463
 464 static void
 465 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
 466 {
 467         CSR_WRITE_4(sc, off, val);
 468 }
 469
 470 /*
 471  * Read a byte of data stored in the EEPROM at address 'addr.' The
 472  * BCM570x supports both the traditional bitbang interface and an
 473  * auto access interface for reading the EEPROM. We use the auto
 474  * access method.
 475  */
 476 static uint8_t
 477 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 478 {
 479         int i;
 480         uint32_t byte = 0;
 481
 482         /*
 483          * Enable use of auto EEPROM access so we can avoid
 484          * having to use the bitbang method.
 485          */
 486         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 487
 488         /* Reset the EEPROM, load the clock period. */
 489         CSR_WRITE_4(sc, BGE_EE_ADDR,
 490             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 491         DELAY(20);
 492
 493         /* Issue the read EEPROM command. */
 494         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 495
 496         /* Wait for completion */
 497         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 498                 DELAY(10);
 499                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 500                         break;
 501         }
 502
 503         if (i == BGE_TIMEOUT) {
 504                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 505                 return(1);
 506         }
 507
 508         /* Get result. */
 509         byte = CSR_READ_4(sc, BGE_EE_DATA);
 510
 511         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 512
 513         return(0);
 514 }
 515
 516 /*
 517  * Read a sequence of bytes from the EEPROM.
 518  */
 519 static int
 520 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 521 {
 522         size_t i;
 523         int err;
 524         uint8_t byte;
 525
 526         for (byte = 0, err = 0, i = 0; i < len; i++) {
 527                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 528                 if (err)
 529                         break;
 530                 *(dest + i) = byte;
 531         }
 532
 533         return(err ? 1 : 0);
 534 }
 535
 536 static int
 537 bge_miibus_readreg(device_t dev, int phy, int reg)
 538 {
 539         struct bge_softc *sc = device_get_softc(dev);
 540         struct ifnet *ifp = &sc->arpcom.ac_if;
 541         uint32_t val, autopoll;
 542         int i;
 543
 544         /*
 545          * Broadcom's own driver always assumes the internal
 546          * PHY is at GMII address 1. On some chips, the PHY responds
 547          * to accesses at all addresses, which could cause us to
 548          * bogusly attach the PHY 32 times at probe type. Always
 549          * restricting the lookup to address 1 is simpler than
 550          * trying to figure out which chips revisions should be
 551          * special-cased.
 552          */
 553         if (phy != 1)
 554                 return(0);
 555
 556         /* Reading with autopolling on may trigger PCI errors */
 557         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 558         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 559                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 560                 DELAY(40);
 561         }
 562
 563         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
 564             BGE_MIPHY(phy)|BGE_MIREG(reg));
 565
 566         for (i = 0; i < BGE_TIMEOUT; i++) {
 567                 DELAY(10);
 568                 val = CSR_READ_4(sc, BGE_MI_COMM);
 569                 if (!(val & BGE_MICOMM_BUSY))
 570                         break;
 571         }
 572
 573         if (i == BGE_TIMEOUT) {
 574                 if_printf(ifp, "PHY read timed out "
 575                           "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 576                 val = 0;
 577                 goto done;
 578         }
 579
 580         DELAY(5);
 581         val = CSR_READ_4(sc, BGE_MI_COMM);
 582
 583 done:
 584         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 585                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 586                 DELAY(40);
 587         }
 588
 589         if (val & BGE_MICOMM_READFAIL)
 590                 return(0);
 591
 592         return(val & 0xFFFF);
 593 }
 594
 595 static int
 596 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 597 {
 598         struct bge_softc *sc = device_get_softc(dev);
 599         uint32_t autopoll;
 600         int i;
 601
 602         /*
 603          * See the related comment in bge_miibus_readreg()
 604          */
 605         if (phy != 1)
 606                 return(0);
 607
 608         /* Reading with autopolling on may trigger PCI errors */
 609         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 610         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 611                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 612                 DELAY(40);
 613         }
 614
 615         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
 616             BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
 617
 618         for (i = 0; i < BGE_TIMEOUT; i++) {
 619                 DELAY(10);
 620                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 621                         DELAY(5);
 622                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 623                         break;
 624                 }
 625         }
 626
 627         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 628                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 629                 DELAY(40);
 630         }
 631
 632         if (i == BGE_TIMEOUT) {
 633                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 634                           "(phy %d, reg %d, val %d)\n", phy, reg, val);
 635                 return(0);
 636         }
 637
 638         return(0);
 639 }
 640
 641 static void
 642 bge_miibus_statchg(device_t dev)
 643 {
 644         struct bge_softc *sc;
 645         struct mii_data *mii;
 646
 647         sc = device_get_softc(dev);
 648         mii = device_get_softc(sc->bge_miibus);
 649
 650         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 651         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
 652                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 653         } else {
 654                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 655         }
 656
 657         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 658                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 659         } else {
 660                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 661         }
 662 }
 663
 664 /*
 665  * Memory management for jumbo frames.
 666  */
 667 static int
 668 bge_alloc_jumbo_mem(struct bge_softc *sc)
 669 {
 670         struct ifnet *ifp = &sc->arpcom.ac_if;
 671         struct bge_jslot *entry;
 672         uint8_t *ptr;
 673         bus_addr_t paddr;
 674         int i, error;
 675
 676         /*
 677          * Create tag for jumbo mbufs.
 678          * This is really a bit of a kludge. We allocate a special
 679          * jumbo buffer pool which (thanks to the way our DMA
 680          * memory allocation works) will consist of contiguous
 681          * pages. This means that even though a jumbo buffer might
 682          * be larger than a page size, we don't really need to
 683          * map it into more than one DMA segment. However, the
 684          * default mbuf tag will result in multi-segment mappings,
 685          * so we have to create a special jumbo mbuf tag that
 686          * lets us get away with mapping the jumbo buffers as
 687          * a single segment. I think eventually the driver should
 688          * be changed so that it uses ordinary mbufs and cluster
 689          * buffers, i.e. jumbo frames can span multiple DMA
 690          * descriptors. But that's a project for another day.
 691          */
 692
 693         /*
 694          * Create DMA stuffs for jumbo RX ring.
 695          */
 696         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 697                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
 698                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
 699                                     (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
 700                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
 701         if (error) {
 702                 if_printf(ifp, "could not create jumbo RX ring\n");
 703                 return error;
 704         }
 705
 706         /*
 707          * Create DMA stuffs for jumbo buffer block.
 708          */
 709         error = bge_dma_block_alloc(sc, BGE_JMEM,
 710                                     &sc->bge_cdata.bge_jumbo_tag,
 711                                     &sc->bge_cdata.bge_jumbo_map,
 712                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
 713                                     &paddr);
 714         if (error) {
 715                 if_printf(ifp, "could not create jumbo buffer\n");
 716                 return error;
 717         }
 718
 719         SLIST_INIT(&sc->bge_jfree_listhead);
 720
 721         /*
 722          * Now divide it up into 9K pieces and save the addresses
 723          * in an array. Note that we play an evil trick here by using
 724          * the first few bytes in the buffer to hold the the address
 725          * of the softc structure for this interface. This is because
 726          * bge_jfree() needs it, but it is called by the mbuf management
 727          * code which will not pass it to us explicitly.
 728          */
 729         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
 730                 entry = &sc->bge_cdata.bge_jslots[i];
 731                 entry->bge_sc = sc;
 732                 entry->bge_buf = ptr;
 733                 entry->bge_paddr = paddr;
 734                 entry->bge_inuse = 0;
 735                 entry->bge_slot = i;
 736                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 737
 738                 ptr += BGE_JLEN;
 739                 paddr += BGE_JLEN;
 740         }
 741         return 0;
 742 }
 743
 744 static void
 745 bge_free_jumbo_mem(struct bge_softc *sc)
 746 {
 747         /* Destroy jumbo RX ring. */
 748         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 749                            sc->bge_cdata.bge_rx_jumbo_ring_map,
 750                            sc->bge_ldata.bge_rx_jumbo_ring);
 751
 752         /* Destroy jumbo buffer block. */
 753         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
 754                            sc->bge_cdata.bge_jumbo_map,
 755                            sc->bge_ldata.bge_jumbo_buf);
 756 }
 757
 758 /*
 759  * Allocate a jumbo buffer.
 760  */
 761 static struct bge_jslot *
 762 bge_jalloc(struct bge_softc *sc)
 763 {
 764         struct bge_jslot *entry;
 765
 766         lwkt_serialize_enter(&sc->bge_jslot_serializer);
 767         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 768         if (entry) {
 769                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 770                 entry->bge_inuse = 1;
 771         } else {
 772                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 773         }
 774         lwkt_serialize_exit(&sc->bge_jslot_serializer);
 775         return(entry);
 776 }
 777
 778 /*
 779  * Adjust usage count on a jumbo buffer.
 780  */
 781 static void
 782 bge_jref(void *arg)
 783 {
 784         struct bge_jslot *entry = (struct bge_jslot *)arg;
 785         struct bge_softc *sc = entry->bge_sc;
 786
 787         if (sc == NULL)
 788                 panic("bge_jref: can't find softc pointer!");
 789
 790         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 791                 panic("bge_jref: asked to reference buffer "
 792                     "that we don't manage!");
 793         } else if (entry->bge_inuse == 0) {
 794                 panic("bge_jref: buffer already free!");
 795         } else {
 796                 atomic_add_int(&entry->bge_inuse, 1);
 797         }
 798 }
 799
 800 /*
 801  * Release a jumbo buffer.
 802  */
 803 static void
 804 bge_jfree(void *arg)
 805 {
 806         struct bge_jslot *entry = (struct bge_jslot *)arg;
 807         struct bge_softc *sc = entry->bge_sc;
 808
 809         if (sc == NULL)
 810                 panic("bge_jfree: can't find softc pointer!");
 811
 812         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 813                 panic("bge_jfree: asked to free buffer that we don't manage!");
 814         } else if (entry->bge_inuse == 0) {
 815                 panic("bge_jfree: buffer already free!");
 816         } else {
 817                 /*
 818                  * Possible MP race to 0, use the serializer.  The atomic insn
 819                  * is still needed for races against bge_jref().
 820                  */
 821                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
 822                 atomic_subtract_int(&entry->bge_inuse, 1);
 823                 if (entry->bge_inuse == 0) {
 824                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
 825                                           entry, jslot_link);
 826                 }
 827                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
 828         }
 829 }
 830
 831
 832 /*
 833  * Intialize a standard receive ring descriptor.
 834  */
 835 static int
 836 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
 837 {
 838         struct mbuf *m_new = NULL;
 839         struct bge_dmamap_arg ctx;
 840         bus_dma_segment_t seg;
 841         struct bge_rx_bd *r;
 842         int error;
 843
 844         if (m == NULL) {
 845                 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
 846                 if (m_new == NULL)
 847                         return ENOBUFS;
 848         } else {
 849                 m_new = m;
 850                 m_new->m_data = m_new->m_ext.ext_buf;
 851         }
 852         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 853
 854         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 855                 m_adj(m_new, ETHER_ALIGN);
 856
 857         ctx.bge_maxsegs = 1;
 858         ctx.bge_segs = &seg;
 859         error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag,
 860                                      sc->bge_cdata.bge_rx_std_dmamap[i],
 861                                      m_new, bge_dma_map_mbuf, &ctx,
 862                                      BUS_DMA_NOWAIT);
 863         if (error || ctx.bge_maxsegs == 0) {
 864                 if (!error) {
 865                         if_printf(&sc->arpcom.ac_if, "too many segments?!\n");
 866                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
 867                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
 868                 }
 869                 if (m == NULL)
 870                         m_freem(m_new);
 871                 return ENOMEM;
 872         }
 873
 874         sc->bge_cdata.bge_rx_std_chain[i] = m_new;
 875
 876         r = &sc->bge_ldata.bge_rx_std_ring[i];
 877         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[0].ds_addr);
 878         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[0].ds_addr);
 879         r->bge_flags = BGE_RXBDFLAG_END;
 880         r->bge_len = m_new->m_len;
 881         r->bge_idx = i;
 882
 883         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
 884                         sc->bge_cdata.bge_rx_std_dmamap[i],
 885                         BUS_DMASYNC_PREREAD);
 886         return 0;
 887 }
 888
 889 /*
 890  * Initialize a jumbo receive ring descriptor. This allocates
 891  * a jumbo buffer from the pool managed internally by the driver.
 892  */
 893 static int
 894 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
 895 {
 896         struct mbuf *m_new = NULL;
 897         struct bge_jslot *buf;
 898         struct bge_rx_bd *r;
 899         bus_addr_t paddr;
 900
 901         if (m == NULL) {
 902                 /* Allocate the mbuf. */
 903                 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
 904                 if (m_new == NULL)
 905                         return(ENOBUFS);
 906
 907                 /* Allocate the jumbo buffer */
 908                 buf = bge_jalloc(sc);
 909                 if (buf == NULL) {
 910                         m_freem(m_new);
 911                         if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
 912                             "-- packet dropped!\n");
 913                         return ENOBUFS;
 914                 }
 915
 916                 /* Attach the buffer to the mbuf. */
 917                 m_new->m_ext.ext_arg = buf;
 918                 m_new->m_ext.ext_buf = buf->bge_buf;
 919                 m_new->m_ext.ext_free = bge_jfree;
 920                 m_new->m_ext.ext_ref = bge_jref;
 921                 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 922
 923                 m_new->m_flags |= M_EXT;
 924         } else {
 925                 KKASSERT(m->m_flags & M_EXT);
 926                 m_new = m;
 927                 buf = m_new->m_ext.ext_arg;
 928         }
 929         m_new->m_data = m_new->m_ext.ext_buf;
 930         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 931
 932         paddr = buf->bge_paddr;
 933         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
 934                 m_adj(m_new, ETHER_ALIGN);
 935                 paddr += ETHER_ALIGN;
 936         }
 937
 938         /* Set up the descriptor. */
 939         sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
 940
 941         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
 942         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(paddr);
 943         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(paddr);
 944         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 945         r->bge_len = m_new->m_len;
 946         r->bge_idx = i;
 947
 948         return 0;
 949 }
 950
 951 /*
 952  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
 953  * that's 1MB or memory, which is a lot. For now, we fill only the first
 954  * 256 ring entries and hope that our CPU is fast enough to keep up with
 955  * the NIC.
 956  */
 957 static int
 958 bge_init_rx_ring_std(struct bge_softc *sc)
 959 {
 960         int i;
 961
 962         for (i = 0; i < BGE_SSLOTS; i++) {
 963                 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
 964                         return(ENOBUFS);
 965         };
 966
 967         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
 968                         sc->bge_cdata.bge_rx_std_ring_map,
 969                         BUS_DMASYNC_PREWRITE);
 970
 971         sc->bge_std = i - 1;
 972         CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
 973
 974         return(0);
 975 }
 976
 977 static void
 978 bge_free_rx_ring_std(struct bge_softc *sc)
 979 {
 980         int i;
 981
 982         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 983                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 984                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
 985                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
 986                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
 987                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
 988                 }
 989                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
 990                     sizeof(struct bge_rx_bd));
 991         }
 992 }
 993
 994 static int
 995 bge_init_rx_ring_jumbo(struct bge_softc *sc)
 996 {
 997         int i;
 998         struct bge_rcb *rcb;
 999
1000         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1001                 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1002                         return(ENOBUFS);
1003         };
1004
1005         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1006                         sc->bge_cdata.bge_rx_jumbo_ring_map,
1007                         BUS_DMASYNC_PREWRITE);
1008
1009         sc->bge_jumbo = i - 1;
1010
1011         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1012         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1013         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1014
1015         CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1016
1017         return(0);
1018 }
1019
1020 static void
1021 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1022 {
1023         int i;
1024
1025         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1026                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1027                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1028                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1029                 }
1030                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1031                     sizeof(struct bge_rx_bd));
1032         }
1033 }
1034
1035 static void
1036 bge_free_tx_ring(struct bge_softc *sc)
1037 {
1038         int i;
1039
1040         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1041                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1042                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
1043                                           sc->bge_cdata.bge_tx_dmamap[i]);
1044                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1045                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1046                 }
1047                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1048                     sizeof(struct bge_tx_bd));
1049         }
1050 }
1051
1052 static int
1053 bge_init_tx_ring(struct bge_softc *sc)
1054 {
1055         sc->bge_txcnt = 0;
1056         sc->bge_tx_saved_considx = 0;
1057         sc->bge_tx_prodidx = 0;
1058
1059         /* Initialize transmit producer index for host-memory send ring. */
1060         CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1061
1062         /* 5700 b2 errata */
1063         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1064                 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
1065
1066         CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1067         /* 5700 b2 errata */
1068         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1069                 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1070
1071         return(0);
1072 }
1073
1074 static void
1075 bge_setmulti(struct bge_softc *sc)
1076 {
1077         struct ifnet *ifp;
1078         struct ifmultiaddr *ifma;
1079         uint32_t hashes[4] = { 0, 0, 0, 0 };
1080         int h, i;
1081
1082         ifp = &sc->arpcom.ac_if;
1083
1084         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1085                 for (i = 0; i < 4; i++)
1086                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1087                 return;
1088         }
1089
1090         /* First, zot all the existing filters. */
1091         for (i = 0; i < 4; i++)
1092                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1093
1094         /* Now program new ones. */
1095         LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1096                 if (ifma->ifma_addr->sa_family != AF_LINK)
1097                         continue;
1098                 h = ether_crc32_le(
1099                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1100                     ETHER_ADDR_LEN) & 0x7f;
1101                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1102         }
1103
1104         for (i = 0; i < 4; i++)
1105                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1106 }
1107
1108 /*
1109  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1110  * self-test results.
1111  */
1112 static int
1113 bge_chipinit(struct bge_softc *sc)
1114 {
1115         int i;
1116         uint32_t dma_rw_ctl;
1117
1118         /* Set endian type before we access any non-PCI registers. */
1119         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1120
1121         /*
1122          * Check the 'ROM failed' bit on the RX CPU to see if
1123          * self-tests passed.
1124          */
1125         if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1126                 if_printf(&sc->arpcom.ac_if,
1127                           "RX CPU self-diagnostics failed!\n");
1128                 return(ENODEV);
1129         }
1130
1131         /* Clear the MAC control register */
1132         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1133
1134         /*
1135          * Clear the MAC statistics block in the NIC's
1136          * internal memory.
1137          */
1138         for (i = BGE_STATS_BLOCK;
1139             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1140                 BGE_MEMWIN_WRITE(sc, i, 0);
1141
1142         for (i = BGE_STATUS_BLOCK;
1143             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1144                 BGE_MEMWIN_WRITE(sc, i, 0);
1145
1146         /* Set up the PCI DMA control register. */
1147         if (sc->bge_flags & BGE_FLAG_PCIE) {
1148                 /* PCI Express */
1149                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1150                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1151                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1152         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1153                 /* PCI-X bus */
1154                 if (BGE_IS_5714_FAMILY(sc)) {
1155                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1156                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1157                         /* XXX magic values, Broadcom-supplied Linux driver */
1158                         if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1159                                 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1160                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1161                         } else {
1162                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1163                         }
1164                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1165                         /*
1166                          * The 5704 uses a different encoding of read/write
1167                          * watermarks.
1168                          */
1169                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1170                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1171                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1172                 } else {
1173                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1174                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1175                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1176                             (0x0F);
1177                 }
1178
1179                 /*
1180                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1181                  * for hardware bugs.
1182                  */
1183                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1184                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1185                         uint32_t tmp;
1186
1187                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1188                         if (tmp == 0x6 || tmp == 0x7)
1189                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1190                 }
1191         } else {
1192                 /* Conventional PCI bus */
1193                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1194                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1195                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1196                     (0x0F);
1197         }
1198
1199         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1200             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1201             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1202                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1203         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1204
1205         /*
1206          * Set up general mode register.
1207          */
1208         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1209             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1210             BGE_MODECTL_TX_NO_PHDR_CSUM);
1211
1212         /*
1213          * Disable memory write invalidate.  Apparently it is not supported
1214          * properly by these devices.
1215          */
1216         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1217
1218         /* Set the timer prescaler (always 66Mhz) */
1219         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1220
1221         return(0);
1222 }
1223
1224 static int
1225 bge_blockinit(struct bge_softc *sc)
1226 {
1227         struct bge_rcb *rcb;
1228         bus_size_t vrcb;
1229         bge_hostaddr taddr;
1230         uint32_t val;
1231         int i;
1232
1233         /*
1234          * Initialize the memory window pointer register so that
1235          * we can access the first 32K of internal NIC RAM. This will
1236          * allow us to set up the TX send ring RCBs and the RX return
1237          * ring RCBs, plus other things which live in NIC memory.
1238          */
1239         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1240
1241         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1242
1243         if (!BGE_IS_5705_PLUS(sc)) {
1244                 /* Configure mbuf memory pool */
1245                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1246                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1247                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1248                 else
1249                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1250
1251                 /* Configure DMA resource pool */
1252                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1253                     BGE_DMA_DESCRIPTORS);
1254                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1255         }
1256
1257         /* Configure mbuf pool watermarks */
1258         if (BGE_IS_5705_PLUS(sc)) {
1259                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1260                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1261         } else {
1262                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1263                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1264         }
1265         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1266
1267         /* Configure DMA resource watermarks */
1268         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1269         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1270
1271         /* Enable buffer manager */
1272         if (!BGE_IS_5705_PLUS(sc)) {
1273                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1274                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1275
1276                 /* Poll for buffer manager start indication */
1277                 for (i = 0; i < BGE_TIMEOUT; i++) {
1278                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1279                                 break;
1280                         DELAY(10);
1281                 }
1282
1283                 if (i == BGE_TIMEOUT) {
1284                         if_printf(&sc->arpcom.ac_if,
1285                                   "buffer manager failed to start\n");
1286                         return(ENXIO);
1287                 }
1288         }
1289
1290         /* Enable flow-through queues */
1291         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1292         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1293
1294         /* Wait until queue initialization is complete */
1295         for (i = 0; i < BGE_TIMEOUT; i++) {
1296                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1297                         break;
1298                 DELAY(10);
1299         }
1300
1301         if (i == BGE_TIMEOUT) {
1302                 if_printf(&sc->arpcom.ac_if,
1303                           "flow-through queue init failed\n");
1304                 return(ENXIO);
1305         }
1306
1307         /* Initialize the standard RX ring control block */
1308         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1309         rcb->bge_hostaddr.bge_addr_lo =
1310             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1311         rcb->bge_hostaddr.bge_addr_hi =
1312             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1313         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1314             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1315         if (BGE_IS_5705_PLUS(sc))
1316                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1317         else
1318                 rcb->bge_maxlen_flags =
1319                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1320         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1321         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1322         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1323         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1324         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1325
1326         /*
1327          * Initialize the jumbo RX ring control block
1328          * We set the 'ring disabled' bit in the flags
1329          * field until we're actually ready to start
1330          * using this ring (i.e. once we set the MTU
1331          * high enough to require it).
1332          */
1333         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1334                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1335
1336                 rcb->bge_hostaddr.bge_addr_lo =
1337                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1338                 rcb->bge_hostaddr.bge_addr_hi =
1339                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1340                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1341                     sc->bge_cdata.bge_rx_jumbo_ring_map,
1342                     BUS_DMASYNC_PREREAD);
1343                 rcb->bge_maxlen_flags =
1344                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1345                     BGE_RCB_FLAG_RING_DISABLED);
1346                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1347                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1348                     rcb->bge_hostaddr.bge_addr_hi);
1349                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1350                     rcb->bge_hostaddr.bge_addr_lo);
1351                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1352                     rcb->bge_maxlen_flags);
1353                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1354
1355                 /* Set up dummy disabled mini ring RCB */
1356                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1357                 rcb->bge_maxlen_flags =
1358                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1359                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1360                     rcb->bge_maxlen_flags);
1361         }
1362
1363         /*
1364          * Set the BD ring replentish thresholds. The recommended
1365          * values are 1/8th the number of descriptors allocated to
1366          * each ring.
1367          */
1368         if (BGE_IS_5705_PLUS(sc))
1369                 val = 8;
1370         else
1371                 val = BGE_STD_RX_RING_CNT / 8;
1372         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1373         CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1374
1375         /*
1376          * Disable all unused send rings by setting the 'ring disabled'
1377          * bit in the flags field of all the TX send ring control blocks.
1378          * These are located in NIC memory.
1379          */
1380         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1381         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1382                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1383                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1384                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1385                 vrcb += sizeof(struct bge_rcb);
1386         }
1387
1388         /* Configure TX RCB 0 (we use only the first ring) */
1389         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1390         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1391         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1392         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1393         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1394             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1395         if (!BGE_IS_5705_PLUS(sc)) {
1396                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1397                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1398         }
1399
1400         /* Disable all unused RX return rings */
1401         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1402         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1403                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1404                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1405                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1406                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1407                     BGE_RCB_FLAG_RING_DISABLED));
1408                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1409                 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1410                     (i * (sizeof(uint64_t))), 0);
1411                 vrcb += sizeof(struct bge_rcb);
1412         }
1413
1414         /* Initialize RX ring indexes */
1415         CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1416         CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1417         CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1418
1419         /*
1420          * Set up RX return ring 0
1421          * Note that the NIC address for RX return rings is 0x00000000.
1422          * The return rings live entirely within the host, so the
1423          * nicaddr field in the RCB isn't used.
1424          */
1425         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1426         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1427         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1428         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1429         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1430         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1431             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1432
1433         /* Set random backoff seed for TX */
1434         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1435             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1436             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1437             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1438             BGE_TX_BACKOFF_SEED_MASK);
1439
1440         /* Set inter-packet gap */
1441         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1442
1443         /*
1444          * Specify which ring to use for packets that don't match
1445          * any RX rules.
1446          */
1447         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1448
1449         /*
1450          * Configure number of RX lists. One interrupt distribution
1451          * list, sixteen active lists, one bad frames class.
1452          */
1453         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1454
1455         /* Inialize RX list placement stats mask. */
1456         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1457         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1458
1459         /* Disable host coalescing until we get it set up */
1460         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1461
1462         /* Poll to make sure it's shut down. */
1463         for (i = 0; i < BGE_TIMEOUT; i++) {
1464                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1465                         break;
1466                 DELAY(10);
1467         }
1468
1469         if (i == BGE_TIMEOUT) {
1470                 if_printf(&sc->arpcom.ac_if,
1471                           "host coalescing engine failed to idle\n");
1472                 return(ENXIO);
1473         }
1474
1475         /* Set up host coalescing defaults */
1476         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1477         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1478         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1479         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1480         if (!BGE_IS_5705_PLUS(sc)) {
1481                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1482                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1483         }
1484         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1485         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1486
1487         /* Set up address of statistics block */
1488         if (!BGE_IS_5705_PLUS(sc)) {
1489                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1490                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1491                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1492                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1493
1494                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1495                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1496                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1497         }
1498
1499         /* Set up address of status block */
1500         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1501             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1502         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1503             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1504         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1505         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1506
1507         /* Turn on host coalescing state machine */
1508         CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1509
1510         /* Turn on RX BD completion state machine and enable attentions */
1511         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1512             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1513
1514         /* Turn on RX list placement state machine */
1515         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1516
1517         /* Turn on RX list selector state machine. */
1518         if (!BGE_IS_5705_PLUS(sc))
1519                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1520
1521         /* Turn on DMA, clear stats */
1522         CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1523             BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1524             BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1525             BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1526             ((sc->bge_flags & BGE_FLAG_TBI) ?
1527              BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1528
1529         /* Set misc. local control, enable interrupts on attentions */
1530         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1531
1532 #ifdef notdef
1533         /* Assert GPIO pins for PHY reset */
1534         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1535             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1536         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1537             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1538 #endif
1539
1540         /* Turn on DMA completion state machine */
1541         if (!BGE_IS_5705_PLUS(sc))
1542                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1543
1544         /* Turn on write DMA state machine */
1545         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1546         if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1547             sc->bge_asicrev == BGE_ASICREV_BCM5787)
1548                 val |= (1 << 29);       /* Enable host coalescing bug fix. */
1549         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1550         DELAY(40);
1551
1552         /* Turn on read DMA state machine */
1553         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1554         if (sc->bge_flags & BGE_FLAG_PCIE)
1555                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1556         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1557         DELAY(40);
1558
1559         /* Turn on RX data completion state machine */
1560         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1561
1562         /* Turn on RX BD initiator state machine */
1563         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1564
1565         /* Turn on RX data and RX BD initiator state machine */
1566         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1567
1568         /* Turn on Mbuf cluster free state machine */
1569         if (!BGE_IS_5705_PLUS(sc))
1570                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1571
1572         /* Turn on send BD completion state machine */
1573         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1574
1575         /* Turn on send data completion state machine */
1576         CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1577
1578         /* Turn on send data initiator state machine */
1579         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1580
1581         /* Turn on send BD initiator state machine */
1582         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1583
1584         /* Turn on send BD selector state machine */
1585         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1586
1587         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1588         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1589             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1590
1591         /* ack/clear link change events */
1592         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1593             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1594             BGE_MACSTAT_LINK_CHANGED);
1595         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1596
1597         /* Enable PHY auto polling (for MII/GMII only) */
1598         if (sc->bge_flags & BGE_FLAG_TBI) {
1599                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1600         } else {
1601                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1602                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1603                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1604                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1605                             BGE_EVTENB_MI_INTERRUPT);
1606                 }
1607         }
1608
1609         /*
1610          * Clear any pending link state attention.
1611          * Otherwise some link state change events may be lost until attention
1612          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1613          * It's not necessary on newer BCM chips - perhaps enabling link
1614          * state change attentions implies clearing pending attention.
1615          */
1616         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1617             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1618             BGE_MACSTAT_LINK_CHANGED);
1619
1620         /* Enable link state change attentions. */
1621         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1622
1623         return(0);
1624 }
1625
1626 /*
1627  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1628  * against our list and return its name if we find a match. Note
1629  * that since the Broadcom controller contains VPD support, we
1630  * can get the device name string from the controller itself instead
1631  * of the compiled-in string. This is a little slow, but it guarantees
1632  * we'll always announce the right product name.
1633  */
1634 static int
1635 bge_probe(device_t dev)
1636 {
1637         const struct bge_type *t;
1638         uint16_t product, vendor;
1639
1640         product = pci_get_device(dev);
1641         vendor = pci_get_vendor(dev);
1642
1643         for (t = bge_devs; t->bge_name != NULL; t++) {
1644                 if (vendor == t->bge_vid && product == t->bge_did)
1645                         break;
1646         }
1647         if (t->bge_name == NULL)
1648                 return(ENXIO);
1649
1650         device_set_desc(dev, t->bge_name);
1651         if (pci_get_subvendor(dev) == PCI_VENDOR_DELL) {
1652                 struct bge_softc *sc = device_get_softc(dev);
1653                 sc->bge_flags |= BGE_FLAG_NO_3LED;
1654         }
1655         return(0);
1656 }
1657
1658 static int
1659 bge_attach(device_t dev)
1660 {
1661         struct ifnet *ifp;
1662         struct bge_softc *sc;
1663         uint32_t hwcfg = 0;
1664         uint32_t mac_addr = 0;
1665         int error = 0, rid;
1666         uint8_t ether_addr[ETHER_ADDR_LEN];
1667
1668         sc = device_get_softc(dev);
1669         sc->bge_dev = dev;
1670         callout_init(&sc->bge_stat_timer);
1671         lwkt_serialize_init(&sc->bge_jslot_serializer);
1672
1673         /*
1674          * Map control/status registers.
1675          */
1676         pci_enable_busmaster(dev);
1677
1678         rid = BGE_PCI_BAR0;
1679         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1680             RF_ACTIVE);
1681
1682         if (sc->bge_res == NULL) {
1683                 device_printf(dev, "couldn't map memory\n");
1684                 return ENXIO;
1685         }
1686
1687         sc->bge_btag = rman_get_bustag(sc->bge_res);
1688         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1689
1690         /* Save various chip information */
1691         sc->bge_chipid =
1692             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1693             BGE_PCIMISCCTL_ASICREV;
1694         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1695         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1696
1697         /* Save chipset family. */
1698         switch (sc->bge_asicrev) {
1699         case BGE_ASICREV_BCM5700:
1700         case BGE_ASICREV_BCM5701:
1701         case BGE_ASICREV_BCM5703:
1702         case BGE_ASICREV_BCM5704:
1703                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1704                 break;
1705
1706         case BGE_ASICREV_BCM5714_A0:
1707         case BGE_ASICREV_BCM5780:
1708         case BGE_ASICREV_BCM5714:
1709                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1710                 /* Fall through */
1711
1712         case BGE_ASICREV_BCM5750:
1713         case BGE_ASICREV_BCM5752:
1714         case BGE_ASICREV_BCM5755:
1715         case BGE_ASICREV_BCM5787:
1716                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1717                 /* Fall through */
1718
1719         case BGE_ASICREV_BCM5705:
1720                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1721                 break;
1722         }
1723
1724         /*
1725          * Set various quirk flags.
1726          */
1727
1728         sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1729         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1730             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1731              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1732               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1733             sc->bge_asicrev == BGE_ASICREV_BCM5906)
1734                 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1735
1736         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1737             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1738                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1739
1740         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1741             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1742                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1743
1744         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1745                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1746
1747         if (BGE_IS_5705_PLUS(sc)) {
1748                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1749                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1750                         uint32_t product = pci_get_device(dev);
1751
1752                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
1753                             product != PCI_PRODUCT_BROADCOM_BCM5756)
1754                                 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
1755                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
1756                                 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1757                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1758                         sc->bge_flags |= BGE_FLAG_BER_BUG;
1759                 }
1760         }
1761
1762         /* Allocate interrupt */
1763         rid = 0;
1764
1765         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1766             RF_SHAREABLE | RF_ACTIVE);
1767
1768         if (sc->bge_irq == NULL) {
1769                 device_printf(dev, "couldn't map interrupt\n");
1770                 error = ENXIO;
1771                 goto fail;
1772         }
1773
1774         /*
1775          * Check if this is a PCI-X or PCI Express device.
1776          */
1777         if (BGE_IS_5705_PLUS(sc)) {
1778                 sc->bge_expr_ptr = pci_get_pciecap_ptr(dev);
1779
1780                 if (sc->bge_expr_ptr != 0) {
1781                         sc->bge_flags |= BGE_FLAG_PCIE;
1782                         bge_set_max_readrq(sc);
1783                 }
1784         } else {
1785                 /*
1786                  * Check if the device is in PCI-X Mode.
1787                  * (This bit is not valid on PCI Express controllers.)
1788                  */
1789                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1790                     BGE_PCISTATE_PCI_BUSMODE) == 0)
1791                         sc->bge_flags |= BGE_FLAG_PCIX;
1792         }
1793
1794         device_printf(dev, "CHIP ID 0x%08x; "
1795                       "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
1796                       sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
1797                       (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
1798                       : ((sc->bge_flags & BGE_FLAG_PCIE) ?
1799                         "PCI-E" : "PCI"));
1800
1801         ifp = &sc->arpcom.ac_if;
1802         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1803
1804         /* Try to reset the chip. */
1805         bge_reset(sc);
1806
1807         if (bge_chipinit(sc)) {
1808                 device_printf(dev, "chip initialization failed\n");
1809                 error = ENXIO;
1810                 goto fail;
1811         }
1812
1813         /*
1814          * Get station address from the EEPROM.
1815          */
1816         mac_addr = bge_readmem_ind(sc, 0x0c14);
1817         if ((mac_addr >> 16) == 0x484b) {
1818                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
1819                 ether_addr[1] = (uint8_t)mac_addr;
1820                 mac_addr = bge_readmem_ind(sc, 0x0c18);
1821                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
1822                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
1823                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
1824                 ether_addr[5] = (uint8_t)mac_addr;
1825         } else if (bge_read_eeprom(sc, ether_addr,
1826             BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1827                 device_printf(dev, "failed to read station address\n");
1828                 error = ENXIO;
1829                 goto fail;
1830         }
1831
1832         /* 5705/5750 limits RX return ring to 512 entries. */
1833         if (BGE_IS_5705_PLUS(sc))
1834                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1835         else
1836                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1837
1838         error = bge_dma_alloc(sc);
1839         if (error)
1840                 goto fail;
1841
1842         /* Set default tuneable values. */
1843         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1844         sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
1845         sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
1846         sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
1847         sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
1848
1849         /* Set up ifnet structure */
1850         ifp->if_softc = sc;
1851         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1852         ifp->if_ioctl = bge_ioctl;
1853         ifp->if_start = bge_start;
1854 #ifdef DEVICE_POLLING
1855         ifp->if_poll = bge_poll;
1856 #endif
1857         ifp->if_watchdog = bge_watchdog;
1858         ifp->if_init = bge_init;
1859         ifp->if_mtu = ETHERMTU;
1860         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1861         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1862         ifq_set_ready(&ifp->if_snd);
1863
1864         /*
1865          * 5700 B0 chips do not support checksumming correctly due
1866          * to hardware bugs.
1867          */
1868         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
1869                 ifp->if_capabilities |= IFCAP_HWCSUM;
1870                 ifp->if_hwassist = BGE_CSUM_FEATURES;
1871         }
1872         ifp->if_capenable = ifp->if_capabilities;
1873
1874         /*
1875          * Figure out what sort of media we have by checking the
1876          * hardware config word in the first 32k of NIC internal memory,
1877          * or fall back to examining the EEPROM if necessary.
1878          * Note: on some BCM5700 cards, this value appears to be unset.
1879          * If that's the case, we have to rely on identifying the NIC
1880          * by its PCI subsystem ID, as we do below for the SysKonnect
1881          * SK-9D41.
1882          */
1883         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1884                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1885         else {
1886                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1887                                     sizeof(hwcfg))) {
1888                         device_printf(dev, "failed to read EEPROM\n");
1889                         error = ENXIO;
1890                         goto fail;
1891                 }
1892                 hwcfg = ntohl(hwcfg);
1893         }
1894
1895         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1896                 sc->bge_flags |= BGE_FLAG_TBI;
1897
1898         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1899         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1900                 sc->bge_flags |= BGE_FLAG_TBI;
1901
1902         if (sc->bge_flags & BGE_FLAG_TBI) {
1903                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1904                     bge_ifmedia_upd, bge_ifmedia_sts);
1905                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1906                 ifmedia_add(&sc->bge_ifmedia,
1907                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1908                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1909                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1910                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
1911         } else {
1912                 /*
1913                  * Do transceiver setup.
1914                  */
1915                 if (mii_phy_probe(dev, &sc->bge_miibus,
1916                     bge_ifmedia_upd, bge_ifmedia_sts)) {
1917                         device_printf(dev, "MII without any PHY!\n");
1918                         error = ENXIO;
1919                         goto fail;
1920                 }
1921         }
1922
1923         /*
1924          * When using the BCM5701 in PCI-X mode, data corruption has
1925          * been observed in the first few bytes of some received packets.
1926          * Aligning the packet buffer in memory eliminates the corruption.
1927          * Unfortunately, this misaligns the packet payloads.  On platforms
1928          * which do not support unaligned accesses, we will realign the
1929          * payloads by copying the received packets.
1930          */
1931         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1932             (sc->bge_flags & BGE_FLAG_PCIX))
1933                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
1934
1935         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1936             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1937                 sc->bge_link_upd = bge_bcm5700_link_upd;
1938                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
1939         } else if (sc->bge_flags & BGE_FLAG_TBI) {
1940                 sc->bge_link_upd = bge_tbi_link_upd;
1941                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
1942         } else {
1943                 sc->bge_link_upd = bge_copper_link_upd;
1944                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
1945         }
1946
1947         /*
1948          * Create sysctl nodes.
1949          */
1950         sysctl_ctx_init(&sc->bge_sysctl_ctx);
1951         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
1952                                               SYSCTL_STATIC_CHILDREN(_hw),
1953                                               OID_AUTO,
1954                                               device_get_nameunit(dev),
1955                                               CTLFLAG_RD, 0, "");
1956         if (sc->bge_sysctl_tree == NULL) {
1957                 device_printf(dev, "can't add sysctl node\n");
1958                 error = ENXIO;
1959                 goto fail;
1960         }
1961
1962         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1963                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1964                         OID_AUTO, "rx_coal_ticks",
1965                         CTLTYPE_INT | CTLFLAG_RW,
1966                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
1967                         "Receive coalescing ticks (usec).");
1968         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1969                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1970                         OID_AUTO, "tx_coal_ticks",
1971                         CTLTYPE_INT | CTLFLAG_RW,
1972                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
1973                         "Transmit coalescing ticks (usec).");
1974         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1975                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1976                         OID_AUTO, "rx_max_coal_bds",
1977                         CTLTYPE_INT | CTLFLAG_RW,
1978                         sc, 0, bge_sysctl_rx_max_coal_bds, "I",
1979                         "Receive max coalesced BD count.");
1980         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1981                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1982                         OID_AUTO, "tx_max_coal_bds",
1983                         CTLTYPE_INT | CTLFLAG_RW,
1984                         sc, 0, bge_sysctl_tx_max_coal_bds, "I",
1985                         "Transmit max coalesced BD count.");
1986
1987         /*
1988          * Call MI attach routine.
1989          */
1990         ether_ifattach(ifp, ether_addr, NULL);
1991
1992         error = bus_setup_intr(dev, sc->bge_irq, INTR_NETSAFE,
1993                                bge_intr, sc, &sc->bge_intrhand,
1994                                ifp->if_serializer);
1995         if (error) {
1996                 ether_ifdetach(ifp);
1997                 device_printf(dev, "couldn't set up irq\n");
1998                 goto fail;
1999         }
2000
2001         ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bge_irq));
2002         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2003
2004         return(0);
2005 fail:
2006         bge_detach(dev);
2007         return(error);
2008 }
2009
2010 static int
2011 bge_detach(device_t dev)
2012 {
2013         struct bge_softc *sc = device_get_softc(dev);
2014
2015         if (device_is_attached(dev)) {
2016                 struct ifnet *ifp = &sc->arpcom.ac_if;
2017
2018                 lwkt_serialize_enter(ifp->if_serializer);
2019                 bge_stop(sc);
2020                 bge_reset(sc);
2021                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2022                 lwkt_serialize_exit(ifp->if_serializer);
2023
2024                 ether_ifdetach(ifp);
2025         }
2026
2027         if (sc->bge_flags & BGE_FLAG_TBI)
2028                 ifmedia_removeall(&sc->bge_ifmedia);
2029         if (sc->bge_miibus)
2030                 device_delete_child(dev, sc->bge_miibus);
2031         bus_generic_detach(dev);
2032
2033         if (sc->bge_irq != NULL)
2034                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2035
2036         if (sc->bge_res != NULL)
2037                 bus_release_resource(dev, SYS_RES_MEMORY,
2038                     BGE_PCI_BAR0, sc->bge_res);
2039
2040         if (sc->bge_sysctl_tree != NULL)
2041                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2042
2043         bge_dma_free(sc);
2044
2045         return 0;
2046 }
2047
2048 static void
2049 bge_reset(struct bge_softc *sc)
2050 {
2051         device_t dev;
2052         uint32_t cachesize, command, pcistate, reset;
2053         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2054         int i, val = 0;
2055
2056         dev = sc->bge_dev;
2057
2058         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc)) {
2059                 if (sc->bge_flags & BGE_FLAG_PCIE)
2060                         write_op = bge_writemem_direct;
2061                 else
2062                         write_op = bge_writemem_ind;
2063         } else {
2064                 write_op = bge_writereg_ind;
2065         }
2066
2067         /* Save some important PCI state. */
2068         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2069         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2070         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2071
2072         pci_write_config(dev, BGE_PCI_MISC_CTL,
2073             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2074             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2075
2076         /* Disable fastboot on controllers that support it. */
2077         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2078             sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2079             sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2080                 if (bootverbose)
2081                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2082                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2083         }
2084
2085         /*
2086          * Write the magic number to SRAM at offset 0xB50.
2087          * When firmware finishes its initialization it will
2088          * write ~BGE_MAGIC_NUMBER to the same location.
2089          */
2090         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2091
2092         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2093
2094         /* XXX: Broadcom Linux driver. */
2095         if (sc->bge_flags & BGE_FLAG_PCIE) {
2096                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
2097                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
2098                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2099                         /* Prevent PCIE link training during global reset */
2100                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2101                         reset |= (1<<29);
2102                 }
2103         }
2104
2105         /*
2106          * Set GPHY Power Down Override to leave GPHY
2107          * powered up in D0 uninitialized.
2108          */
2109         if (BGE_IS_5705_PLUS(sc))
2110                 reset |= 0x04000000;
2111
2112         /* Issue global reset */
2113         write_op(sc, BGE_MISC_CFG, reset);
2114
2115         DELAY(1000);
2116
2117         /* XXX: Broadcom Linux driver. */
2118         if (sc->bge_flags & BGE_FLAG_PCIE) {
2119                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2120                         uint32_t v;
2121
2122                         DELAY(500000); /* wait for link training to complete */
2123                         v = pci_read_config(dev, 0xc4, 4);
2124                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2125                 }
2126                 /*
2127                  * Set PCIE max payload size to 128 bytes and
2128                  * clear error status.
2129                  */
2130                 pci_write_config(dev, 0xd8, 0xf5000, 4);
2131         }
2132
2133         /* Reset some of the PCI state that got zapped by reset */
2134         pci_write_config(dev, BGE_PCI_MISC_CTL,
2135             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2136             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2137         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2138         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2139         write_op(sc, BGE_MISC_CFG, (65 << 1));
2140
2141         /* Enable memory arbiter. */
2142         if (BGE_IS_5714_FAMILY(sc)) {
2143                 uint32_t val;
2144
2145                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2146                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2147         } else {
2148                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2149         }
2150
2151         /*
2152          * Poll until we see the 1's complement of the magic number.
2153          * This indicates that the firmware initialization
2154          * is complete.
2155          */
2156         for (i = 0; i < BGE_TIMEOUT; i++) {
2157                 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2158                 if (val == ~BGE_MAGIC_NUMBER)
2159                         break;
2160                 DELAY(10);
2161         }
2162
2163         if (i == BGE_TIMEOUT) {
2164                 if_printf(&sc->arpcom.ac_if, "firmware handshake timed out,"
2165                           "found 0x%08x\n", val);
2166                 return;
2167         }
2168
2169         /*
2170          * XXX Wait for the value of the PCISTATE register to
2171          * return to its original pre-reset state. This is a
2172          * fairly good indicator of reset completion. If we don't
2173          * wait for the reset to fully complete, trying to read
2174          * from the device's non-PCI registers may yield garbage
2175          * results.
2176          */
2177         for (i = 0; i < BGE_TIMEOUT; i++) {
2178                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2179                         break;
2180                 DELAY(10);
2181         }
2182
2183         if (sc->bge_flags & BGE_FLAG_PCIE) {
2184                 reset = bge_readmem_ind(sc, 0x7c00);
2185                 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2186         }
2187
2188         /* Fix up byte swapping */
2189         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2190             BGE_MODECTL_BYTESWAP_DATA);
2191
2192         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2193
2194         /*
2195          * The 5704 in TBI mode apparently needs some special
2196          * adjustment to insure the SERDES drive level is set
2197          * to 1.2V.
2198          */
2199         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2200             (sc->bge_flags & BGE_FLAG_TBI)) {
2201                 uint32_t serdescfg;
2202
2203                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2204                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2205                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2206         }
2207
2208         /* XXX: Broadcom Linux driver. */
2209         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2210             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2211                 uint32_t v;
2212
2213                 v = CSR_READ_4(sc, 0x7c00);
2214                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2215         }
2216
2217         DELAY(10000);
2218 }
2219
2220 /*
2221  * Frame reception handling. This is called if there's a frame
2222  * on the receive return list.
2223  *
2224  * Note: we have to be able to handle two possibilities here:
2225  * 1) the frame is from the jumbo recieve ring
2226  * 2) the frame is from the standard receive ring
2227  */
2228
2229 static void
2230 bge_rxeof(struct bge_softc *sc)
2231 {
2232         struct ifnet *ifp;
2233         int stdcnt = 0, jumbocnt = 0;
2234 #ifdef ETHER_INPUT_CHAIN
2235         struct mbuf_chain chain[MAXCPU];
2236 #endif
2237
2238         if (sc->bge_rx_saved_considx ==
2239             sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2240                 return;
2241
2242 #ifdef ETHER_INPUT_CHAIN
2243         ether_input_chain_init(chain);
2244 #endif
2245
2246         ifp = &sc->arpcom.ac_if;
2247
2248         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
2249                         sc->bge_cdata.bge_rx_return_ring_map,
2250                         BUS_DMASYNC_POSTREAD);
2251         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2252                         sc->bge_cdata.bge_rx_std_ring_map,
2253                         BUS_DMASYNC_POSTREAD);
2254         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2255                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2256                                 sc->bge_cdata.bge_rx_jumbo_ring_map,
2257                                 BUS_DMASYNC_POSTREAD);
2258         }
2259
2260         while (sc->bge_rx_saved_considx !=
2261                sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2262                 struct bge_rx_bd        *cur_rx;
2263                 uint32_t                rxidx;
2264                 struct mbuf             *m = NULL;
2265                 uint16_t                vlan_tag = 0;
2266                 int                     have_tag = 0;
2267
2268                 cur_rx =
2269             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2270
2271                 rxidx = cur_rx->bge_idx;
2272                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2273                 logif(rx_pkt);
2274
2275                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2276                         have_tag = 1;
2277                         vlan_tag = cur_rx->bge_vlan_tag;
2278                 }
2279
2280                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2281                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2282                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
2283                         sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
2284                         jumbocnt++;
2285                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2286                                 ifp->if_ierrors++;
2287                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2288                                 continue;
2289                         }
2290                         if (bge_newbuf_jumbo(sc,
2291                             sc->bge_jumbo, NULL) == ENOBUFS) {
2292                                 ifp->if_ierrors++;
2293                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2294                                 continue;
2295                         }
2296                 } else {
2297                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2298                         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2299                                         sc->bge_cdata.bge_rx_std_dmamap[rxidx],
2300                                         BUS_DMASYNC_POSTREAD);
2301                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2302                                 sc->bge_cdata.bge_rx_std_dmamap[rxidx]);
2303                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2304                         sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2305                         stdcnt++;
2306                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2307                                 ifp->if_ierrors++;
2308                                 bge_newbuf_std(sc, sc->bge_std, m);
2309                                 continue;
2310                         }
2311                         if (bge_newbuf_std(sc, sc->bge_std,
2312                             NULL) == ENOBUFS) {
2313                                 ifp->if_ierrors++;
2314                                 bge_newbuf_std(sc, sc->bge_std, m);
2315                                 continue;
2316                         }
2317                 }
2318
2319                 ifp->if_ipackets++;
2320 #ifndef __i386__
2321                 /*
2322                  * The i386 allows unaligned accesses, but for other
2323                  * platforms we must make sure the payload is aligned.
2324                  */
2325                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2326                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2327                             cur_rx->bge_len);
2328                         m->m_data += ETHER_ALIGN;
2329                 }
2330 #endif
2331                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2332                 m->m_pkthdr.rcvif = ifp;
2333
2334                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2335                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2336                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2337                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2338                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2339                         }
2340                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2341                             m->m_pkthdr.len >= BGE_MIN_FRAME) {
2342                                 m->m_pkthdr.csum_data =
2343                                         cur_rx->bge_tcp_udp_csum;
2344                                 m->m_pkthdr.csum_flags |=
2345                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2346                         }
2347                 }
2348
2349                 /*
2350                  * If we received a packet with a vlan tag, pass it
2351                  * to vlan_input() instead of ether_input().
2352                  */
2353                 if (have_tag) {
2354                         m->m_flags |= M_VLANTAG;
2355                         m->m_pkthdr.ether_vlantag = vlan_tag;
2356                         have_tag = vlan_tag = 0;
2357                 }
2358 #ifdef ETHER_INPUT_CHAIN
2359 #ifdef ETHER_INPUT2
2360                 ether_input_chain2(ifp, m, chain);
2361 #else
2362                 ether_input_chain(ifp, m, chain);
2363 #endif
2364 #else
2365                 ifp->if_input(ifp, m);
2366 #endif
2367         }
2368
2369 #ifdef ETHER_INPUT_CHAIN
2370         ether_input_dispatch(chain);
2371 #endif
2372
2373         if (stdcnt > 0) {
2374                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2375                                 sc->bge_cdata.bge_rx_std_ring_map,
2376                                 BUS_DMASYNC_PREWRITE);
2377         }
2378
2379         if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) {
2380                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2381                                 sc->bge_cdata.bge_rx_jumbo_ring_map,
2382                                 BUS_DMASYNC_PREWRITE);
2383         }
2384
2385         CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2386         if (stdcnt)
2387                 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2388         if (jumbocnt)
2389                 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2390 }
2391
2392 static void
2393 bge_txeof(struct bge_softc *sc)
2394 {
2395         struct bge_tx_bd *cur_tx = NULL;
2396         struct ifnet *ifp;
2397
2398         if (sc->bge_tx_saved_considx ==
2399             sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2400                 return;
2401
2402         ifp = &sc->arpcom.ac_if;
2403
2404         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
2405                         sc->bge_cdata.bge_tx_ring_map,
2406                         BUS_DMASYNC_POSTREAD);
2407
2408         /*
2409          * Go through our tx ring and free mbufs for those
2410          * frames that have been sent.
2411          */
2412         while (sc->bge_tx_saved_considx !=
2413                sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2414                 uint32_t idx = 0;
2415
2416                 idx = sc->bge_tx_saved_considx;
2417                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2418                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2419                         ifp->if_opackets++;
2420                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2421                         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2422                                         sc->bge_cdata.bge_tx_dmamap[idx],
2423                                         BUS_DMASYNC_POSTWRITE);
2424                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2425                             sc->bge_cdata.bge_tx_dmamap[idx]);
2426                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2427                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2428                 }
2429                 sc->bge_txcnt--;
2430                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2431                 logif(tx_pkt);
2432         }
2433
2434         if (cur_tx != NULL &&
2435             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2436             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2437                 ifp->if_flags &= ~IFF_OACTIVE;
2438
2439         if (sc->bge_txcnt == 0)
2440                 ifp->if_timer = 0;
2441
2442         if (!ifq_is_empty(&ifp->if_snd))
2443                 if_devstart(ifp);
2444 }
2445
2446 #ifdef DEVICE_POLLING
2447
2448 static void
2449 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2450 {
2451         struct bge_softc *sc = ifp->if_softc;
2452         uint32_t status;
2453
2454         switch(cmd) {
2455         case POLL_REGISTER:
2456                 bge_disable_intr(sc);
2457                 break;
2458         case POLL_DEREGISTER:
2459                 bge_enable_intr(sc);
2460                 break;
2461         case POLL_AND_CHECK_STATUS:
2462                 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2463                                 sc->bge_cdata.bge_status_map,
2464                                 BUS_DMASYNC_POSTREAD);
2465
2466                 /*
2467                  * Process link state changes.
2468                  */
2469                 status = CSR_READ_4(sc, BGE_MAC_STS);
2470                 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2471                         sc->bge_link_evt = 0;
2472                         sc->bge_link_upd(sc, status);
2473                 }
2474                 /* fall through */
2475         case POLL_ONLY:
2476                 if (ifp->if_flags & IFF_RUNNING) {
2477                         bge_rxeof(sc);
2478                         bge_txeof(sc);
2479                 }
2480                 break;
2481         }
2482 }
2483
2484 #endif
2485
2486 static void
2487 bge_intr(void *xsc)
2488 {
2489         struct bge_softc *sc = xsc;
2490         struct ifnet *ifp = &sc->arpcom.ac_if;
2491         uint32_t status;
2492
2493         logif(intr);
2494
2495         /*
2496          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
2497          * disable interrupts by writing nonzero like we used to, since with
2498          * our current organization this just gives complications and
2499          * pessimizations for re-enabling interrupts.  We used to have races
2500          * instead of the necessary complications.  Disabling interrupts
2501          * would just reduce the chance of a status update while we are
2502          * running (by switching to the interrupt-mode coalescence
2503          * parameters), but this chance is already very low so it is more
2504          * efficient to get another interrupt than prevent it.
2505          *
2506          * We do the ack first to ensure another interrupt if there is a
2507          * status update after the ack.  We don't check for the status
2508          * changing later because it is more efficient to get another
2509          * interrupt than prevent it, not quite as above (not checking is
2510          * a smaller optimization than not toggling the interrupt enable,
2511          * since checking doesn't involve PCI accesses and toggling require
2512          * the status check).  So toggling would probably be a pessimization
2513          * even with MSI.  It would only be needed for using a task queue.
2514          */
2515         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2516
2517         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2518                         sc->bge_cdata.bge_status_map,
2519                         BUS_DMASYNC_POSTREAD);
2520
2521         /*
2522          * Process link state changes.
2523          */
2524         status = CSR_READ_4(sc, BGE_MAC_STS);
2525         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2526                 sc->bge_link_evt = 0;
2527                 sc->bge_link_upd(sc, status);
2528         }
2529
2530         if (ifp->if_flags & IFF_RUNNING) {
2531                 /* Check RX return ring producer/consumer */
2532                 bge_rxeof(sc);
2533
2534                 /* Check TX ring producer/consumer */
2535                 bge_txeof(sc);
2536         }
2537
2538         if (sc->bge_coal_chg)
2539                 bge_coal_change(sc);
2540 }
2541
2542 static void
2543 bge_tick(void *xsc)
2544 {
2545         struct bge_softc *sc = xsc;
2546         struct ifnet *ifp = &sc->arpcom.ac_if;
2547
2548         lwkt_serialize_enter(ifp->if_serializer);
2549
2550         if (BGE_IS_5705_PLUS(sc))
2551                 bge_stats_update_regs(sc);
2552         else
2553                 bge_stats_update(sc);
2554
2555         if (sc->bge_flags & BGE_FLAG_TBI) {
2556                 /*
2557                  * Since in TBI mode auto-polling can't be used we should poll
2558                  * link status manually. Here we register pending link event
2559                  * and trigger interrupt.
2560                  */
2561                 sc->bge_link_evt++;
2562                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2563         } else if (!sc->bge_link) {
2564                 mii_tick(device_get_softc(sc->bge_miibus));
2565         }
2566
2567         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2568
2569         lwkt_serialize_exit(ifp->if_serializer);
2570 }
2571
2572 static void
2573 bge_stats_update_regs(struct bge_softc *sc)
2574 {
2575         struct ifnet *ifp = &sc->arpcom.ac_if;
2576         struct bge_mac_stats_regs stats;
2577         uint32_t *s;
2578         int i;
2579
2580         s = (uint32_t *)&stats;
2581         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2582                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2583                 s++;
2584         }
2585
2586         ifp->if_collisions +=
2587            (stats.dot3StatsSingleCollisionFrames +
2588            stats.dot3StatsMultipleCollisionFrames +
2589            stats.dot3StatsExcessiveCollisions +
2590            stats.dot3StatsLateCollisions) -
2591            ifp->if_collisions;
2592 }
2593
2594 static void
2595 bge_stats_update(struct bge_softc *sc)
2596 {
2597         struct ifnet *ifp = &sc->arpcom.ac_if;
2598         bus_size_t stats;
2599
2600         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2601
2602 #define READ_STAT(sc, stats, stat)      \
2603         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2604
2605         ifp->if_collisions +=
2606            (READ_STAT(sc, stats,
2607                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2608             READ_STAT(sc, stats,
2609                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2610             READ_STAT(sc, stats,
2611                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2612             READ_STAT(sc, stats,
2613                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
2614            ifp->if_collisions;
2615
2616 #undef READ_STAT
2617
2618 #ifdef notdef
2619         ifp->if_collisions +=
2620            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2621            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2622            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2623            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2624            ifp->if_collisions;
2625 #endif
2626 }
2627
2628 /*
2629  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2630  * pointers to descriptors.
2631  */
2632 static int
2633 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
2634 {
2635         struct bge_tx_bd *d = NULL;
2636         uint16_t csum_flags = 0;
2637         struct bge_dmamap_arg ctx;
2638         bus_dma_segment_t segs[BGE_NSEG_NEW];
2639         bus_dmamap_t map;
2640         int error, maxsegs, idx, i;
2641         struct mbuf *m_head = *m_head0;
2642
2643         if (m_head->m_pkthdr.csum_flags) {
2644                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2645                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2646                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2647                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2648                 if (m_head->m_flags & M_LASTFRAG)
2649                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2650                 else if (m_head->m_flags & M_FRAG)
2651                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2652         }
2653
2654         idx = *txidx;
2655         map = sc->bge_cdata.bge_tx_dmamap[idx];
2656
2657         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2658         KASSERT(maxsegs >= BGE_NSEG_SPARE,
2659                 ("not enough segments %d\n", maxsegs));
2660
2661         if (maxsegs > BGE_NSEG_NEW)
2662                 maxsegs = BGE_NSEG_NEW;
2663
2664         /*
2665          * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2666          * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2667          * but when such padded frames employ the bge IP/TCP checksum
2668          * offload, the hardware checksum assist gives incorrect results
2669          * (possibly from incorporating its own padding into the UDP/TCP
2670          * checksum; who knows).  If we pad such runts with zeros, the
2671          * onboard checksum comes out correct.  We do this by pretending
2672          * the mbuf chain has too many fragments so the coalescing code
2673          * below can assemble the packet into a single buffer that's
2674          * padded out to the mininum frame size.
2675          */
2676         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2677             m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2678                 error = EFBIG;
2679         } else {
2680                 ctx.bge_segs = segs;
2681                 ctx.bge_maxsegs = maxsegs;
2682                 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2683                                              m_head, bge_dma_map_mbuf, &ctx,
2684                                              BUS_DMA_NOWAIT);
2685         }
2686         if (error == EFBIG || ctx.bge_maxsegs == 0) {
2687                 struct mbuf *m_new;
2688
2689                 if (!error)
2690                         bus_dmamap_unload(sc->bge_cdata.bge_mtag, map);
2691
2692                 m_new = m_defrag(m_head, MB_DONTWAIT);
2693                 if (m_new == NULL) {
2694                         if_printf(&sc->arpcom.ac_if,
2695                                   "could not defrag TX mbuf\n");
2696                         error = ENOBUFS;
2697                         goto back;
2698                 } else {
2699                         m_head = m_new;
2700                         *m_head0 = m_head;
2701                 }
2702
2703                 /*
2704                  * Manually pad short frames, and zero the pad space
2705                  * to avoid leaking data.
2706                  */
2707                 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2708                     m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2709                         int pad_len = BGE_MIN_FRAME - m_head->m_pkthdr.len;
2710
2711                         bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
2712                               pad_len);
2713                         m_head->m_pkthdr.len += pad_len;
2714                         m_head->m_len = m_head->m_pkthdr.len;
2715                 }
2716
2717                 ctx.bge_segs = segs;
2718                 ctx.bge_maxsegs = maxsegs;
2719                 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2720                                              m_head, bge_dma_map_mbuf, &ctx,
2721                                              BUS_DMA_NOWAIT);
2722                 if (error || ctx.bge_maxsegs == 0) {
2723                         if_printf(&sc->arpcom.ac_if,
2724                                   "could not defrag TX mbuf\n");
2725                         if (!error) {
2726                                 bus_dmamap_unload(sc->bge_cdata.bge_mtag, map);
2727                                 error = EFBIG;
2728                         }
2729                         goto back;
2730                 }
2731         } else if (error) {
2732                 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
2733                 goto back;
2734         }
2735
2736         bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE);
2737
2738         for (i = 0; ; i++) {
2739                 d = &sc->bge_ldata.bge_tx_ring[idx];
2740
2741                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[i].ds_addr);
2742                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[i].ds_addr);
2743                 d->bge_len = segs[i].ds_len;
2744                 d->bge_flags = csum_flags;
2745
2746                 if (i == ctx.bge_maxsegs - 1)
2747                         break;
2748                 BGE_INC(idx, BGE_TX_RING_CNT);
2749         }
2750         /* Mark the last segment as end of packet... */
2751         d->bge_flags |= BGE_TXBDFLAG_END;
2752
2753         /* Set vlan tag to the first segment of the packet. */
2754         d = &sc->bge_ldata.bge_tx_ring[*txidx];
2755         if (m_head->m_flags & M_VLANTAG) {
2756                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2757                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
2758         } else {
2759                 d->bge_vlan_tag = 0;
2760         }
2761
2762         /*
2763          * Insure that the map for this transmission is placed at
2764          * the array index of the last descriptor in this chain.
2765          */
2766         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2767         sc->bge_cdata.bge_tx_dmamap[idx] = map;
2768         sc->bge_cdata.bge_tx_chain[idx] = m_head;
2769         sc->bge_txcnt += ctx.bge_maxsegs;
2770
2771         BGE_INC(idx, BGE_TX_RING_CNT);
2772         *txidx = idx;
2773 back:
2774         if (error) {
2775                 m_freem(m_head);
2776                 *m_head0 = NULL;
2777         }
2778         return error;
2779 }
2780
2781 /*
2782  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2783  * to the mbuf data regions directly in the transmit descriptors.
2784  */
2785 static void
2786 bge_start(struct ifnet *ifp)
2787 {
2788         struct bge_softc *sc = ifp->if_softc;
2789         struct mbuf *m_head = NULL;
2790         uint32_t prodidx;
2791         int need_trans;
2792
2793         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2794                 return;
2795
2796         prodidx = sc->bge_tx_prodidx;
2797
2798         need_trans = 0;
2799         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2800                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2801                 if (m_head == NULL)
2802                         break;
2803
2804                 /*
2805                  * XXX
2806                  * The code inside the if() block is never reached since we
2807                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2808                  * requests to checksum TCP/UDP in a fragmented packet.
2809                  *
2810                  * XXX
2811                  * safety overkill.  If this is a fragmented packet chain
2812                  * with delayed TCP/UDP checksums, then only encapsulate
2813                  * it if we have enough descriptors to handle the entire
2814                  * chain at once.
2815                  * (paranoia -- may not actually be needed)
2816                  */
2817                 if ((m_head->m_flags & M_FIRSTFRAG) &&
2818                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
2819                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2820                             m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
2821                                 ifp->if_flags |= IFF_OACTIVE;
2822                                 ifq_prepend(&ifp->if_snd, m_head);
2823                                 break;
2824                         }
2825                 }
2826
2827                 /*
2828                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2829                  * descriptors of the end of the ring.  Also make
2830                  * sure there are BGE_NSEG_SPARE descriptors for
2831                  * jumbo buffers' defragmentation.
2832                  */
2833                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2834                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
2835                         ifp->if_flags |= IFF_OACTIVE;
2836                         ifq_prepend(&ifp->if_snd, m_head);
2837                         break;
2838                 }
2839
2840                 /*
2841                  * Pack the data into the transmit ring. If we
2842                  * don't have room, set the OACTIVE flag and wait
2843                  * for the NIC to drain the ring.
2844                  */
2845                 if (bge_encap(sc, &m_head, &prodidx)) {
2846                         ifp->if_flags |= IFF_OACTIVE;
2847                         break;
2848                 }
2849                 need_trans = 1;
2850
2851                 ETHER_BPF_MTAP(ifp, m_head);
2852         }
2853
2854         if (!need_trans)
2855                 return;
2856
2857         /* Transmit */
2858         CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2859         /* 5700 b2 errata */
2860         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2861                 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2862
2863         sc->bge_tx_prodidx = prodidx;
2864
2865         /*
2866          * Set a timeout in case the chip goes out to lunch.
2867          */
2868         ifp->if_timer = 5;
2869 }
2870
2871 static void
2872 bge_init(void *xsc)
2873 {
2874         struct bge_softc *sc = xsc;
2875         struct ifnet *ifp = &sc->arpcom.ac_if;
2876         uint16_t *m;
2877
2878         ASSERT_SERIALIZED(ifp->if_serializer);
2879
2880         if (ifp->if_flags & IFF_RUNNING)
2881                 return;
2882
2883         /* Cancel pending I/O and flush buffers. */
2884         bge_stop(sc);
2885         bge_reset(sc);
2886         bge_chipinit(sc);
2887
2888         /*
2889          * Init the various state machines, ring
2890          * control blocks and firmware.
2891          */
2892         if (bge_blockinit(sc)) {
2893                 if_printf(ifp, "initialization failure\n");
2894                 return;
2895         }
2896
2897         /* Specify MTU. */
2898         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2899             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2900
2901         /* Load our MAC address. */
2902         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2903         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2904         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2905
2906         /* Enable or disable promiscuous mode as needed. */
2907         bge_setpromisc(sc);
2908
2909         /* Program multicast filter. */
2910         bge_setmulti(sc);
2911
2912         /* Init RX ring. */
2913         bge_init_rx_ring_std(sc);
2914
2915         /*
2916          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2917          * memory to insure that the chip has in fact read the first
2918          * entry of the ring.
2919          */
2920         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2921                 uint32_t                v, i;
2922                 for (i = 0; i < 10; i++) {
2923                         DELAY(20);
2924                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2925                         if (v == (MCLBYTES - ETHER_ALIGN))
2926                                 break;
2927                 }
2928                 if (i == 10)
2929                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
2930         }
2931
2932         /* Init jumbo RX ring. */
2933         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2934                 bge_init_rx_ring_jumbo(sc);
2935
2936         /* Init our RX return ring index */
2937         sc->bge_rx_saved_considx = 0;
2938
2939         /* Init TX ring. */
2940         bge_init_tx_ring(sc);
2941
2942         /* Turn on transmitter */
2943         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2944
2945         /* Turn on receiver */
2946         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2947
2948         /* Tell firmware we're alive. */
2949         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2950
2951         /* Enable host interrupts if polling(4) is not enabled. */
2952         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2953 #ifdef DEVICE_POLLING
2954         if (ifp->if_flags & IFF_POLLING)
2955                 bge_disable_intr(sc);
2956         else
2957 #endif
2958         bge_enable_intr(sc);
2959
2960         bge_ifmedia_upd(ifp);
2961
2962         ifp->if_flags |= IFF_RUNNING;
2963         ifp->if_flags &= ~IFF_OACTIVE;
2964
2965         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2966 }
2967
2968 /*
2969  * Set media options.
2970  */
2971 static int
2972 bge_ifmedia_upd(struct ifnet *ifp)
2973 {
2974         struct bge_softc *sc = ifp->if_softc;
2975
2976         /* If this is a 1000baseX NIC, enable the TBI port. */
2977         if (sc->bge_flags & BGE_FLAG_TBI) {
2978                 struct ifmedia *ifm = &sc->bge_ifmedia;
2979
2980                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2981                         return(EINVAL);
2982
2983                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2984                 case IFM_AUTO:
2985                         /*
2986                          * The BCM5704 ASIC appears to have a special
2987                          * mechanism for programming the autoneg
2988                          * advertisement registers in TBI mode.
2989                          */
2990                         if (!bge_fake_autoneg &&
2991                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2992                                 uint32_t sgdig;
2993
2994                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
2995                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
2996                                 sgdig |= BGE_SGDIGCFG_AUTO |
2997                                          BGE_SGDIGCFG_PAUSE_CAP |
2998                                          BGE_SGDIGCFG_ASYM_PAUSE;
2999                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3000                                             sgdig | BGE_SGDIGCFG_SEND);
3001                                 DELAY(5);
3002                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3003                         }
3004                         break;
3005                 case IFM_1000_SX:
3006                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3007                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3008                                     BGE_MACMODE_HALF_DUPLEX);
3009                         } else {
3010                                 BGE_SETBIT(sc, BGE_MAC_MODE,
3011                                     BGE_MACMODE_HALF_DUPLEX);
3012                         }
3013                         break;
3014                 default:
3015                         return(EINVAL);
3016                 }
3017         } else {
3018                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3019
3020                 sc->bge_link_evt++;
3021                 sc->bge_link = 0;
3022                 if (mii->mii_instance) {
3023                         struct mii_softc *miisc;
3024
3025                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3026                                 mii_phy_reset(miisc);
3027                 }
3028                 mii_mediachg(mii);
3029         }
3030         return(0);
3031 }
3032
3033 /*
3034  * Report current media status.
3035  */
3036 static void
3037 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3038 {
3039         struct bge_softc *sc = ifp->if_softc;
3040
3041         if (sc->bge_flags & BGE_FLAG_TBI) {
3042                 ifmr->ifm_status = IFM_AVALID;
3043                 ifmr->ifm_active = IFM_ETHER;
3044                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3045                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3046                         ifmr->ifm_status |= IFM_ACTIVE;
3047                 } else {
3048                         ifmr->ifm_active |= IFM_NONE;
3049                         return;
3050                 }
3051
3052                 ifmr->ifm_active |= IFM_1000_SX;
3053                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3054                         ifmr->ifm_active |= IFM_HDX;
3055                 else
3056                         ifmr->ifm_active |= IFM_FDX;
3057         } else {
3058                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3059
3060                 mii_pollstat(mii);
3061                 ifmr->ifm_active = mii->mii_media_active;
3062                 ifmr->ifm_status = mii->mii_media_status;
3063         }
3064 }
3065
3066 static int
3067 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3068 {
3069         struct bge_softc *sc = ifp->if_softc;
3070         struct ifreq *ifr = (struct ifreq *)data;
3071         int mask, error = 0;
3072
3073         ASSERT_SERIALIZED(ifp->if_serializer);
3074
3075         switch (command) {
3076         case SIOCSIFMTU:
3077                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3078                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3079                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3080                         error = EINVAL;
3081                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3082                         ifp->if_mtu = ifr->ifr_mtu;
3083                         ifp->if_flags &= ~IFF_RUNNING;
3084                         bge_init(sc);
3085                 }
3086                 break;
3087         case SIOCSIFFLAGS:
3088                 if (ifp->if_flags & IFF_UP) {
3089                         if (ifp->if_flags & IFF_RUNNING) {
3090                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3091
3092                                 /*
3093                                  * If only the state of the PROMISC flag
3094                                  * changed, then just use the 'set promisc
3095                                  * mode' command instead of reinitializing
3096                                  * the entire NIC. Doing a full re-init
3097                                  * means reloading the firmware and waiting
3098                                  * for it to start up, which may take a
3099                                  * second or two.  Similarly for ALLMULTI.
3100                                  */
3101                                 if (mask & IFF_PROMISC)
3102                                         bge_setpromisc(sc);
3103                                 if (mask & IFF_ALLMULTI)
3104                                         bge_setmulti(sc);
3105                         } else {
3106                                 bge_init(sc);
3107                         }
3108                 } else {
3109                         if (ifp->if_flags & IFF_RUNNING)
3110                                 bge_stop(sc);
3111                 }
3112                 sc->bge_if_flags = ifp->if_flags;
3113                 break;
3114         case SIOCADDMULTI:
3115         case SIOCDELMULTI:
3116                 if (ifp->if_flags & IFF_RUNNING)
3117                         bge_setmulti(sc);
3118                 break;
3119         case SIOCSIFMEDIA:
3120         case SIOCGIFMEDIA:
3121                 if (sc->bge_flags & BGE_FLAG_TBI) {
3122                         error = ifmedia_ioctl(ifp, ifr,
3123                             &sc->bge_ifmedia, command);
3124                 } else {
3125                         struct mii_data *mii;
3126
3127                         mii = device_get_softc(sc->bge_miibus);
3128                         error = ifmedia_ioctl(ifp, ifr,
3129                                               &mii->mii_media, command);
3130                 }
3131                 break;
3132         case SIOCSIFCAP:
3133                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3134                 if (mask & IFCAP_HWCSUM) {
3135                         ifp->if_capenable ^= IFCAP_HWCSUM;
3136                         if (IFCAP_HWCSUM & ifp->if_capenable)
3137                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
3138                         else
3139                                 ifp->if_hwassist = 0;
3140                 }
3141                 break;
3142         default:
3143                 error = ether_ioctl(ifp, command, data);
3144                 break;
3145         }
3146         return error;
3147 }
3148
3149 static void
3150 bge_watchdog(struct ifnet *ifp)
3151 {
3152         struct bge_softc *sc = ifp->if_softc;
3153
3154         if_printf(ifp, "watchdog timeout -- resetting\n");
3155
3156         ifp->if_flags &= ~IFF_RUNNING;
3157         bge_init(sc);
3158
3159         ifp->if_oerrors++;
3160
3161         if (!ifq_is_empty(&ifp->if_snd))
3162                 if_devstart(ifp);
3163 }
3164
3165 /*
3166  * Stop the adapter and free any mbufs allocated to the
3167  * RX and TX lists.
3168  */
3169 static void
3170 bge_stop(struct bge_softc *sc)
3171 {
3172         struct ifnet *ifp = &sc->arpcom.ac_if;
3173         struct ifmedia_entry *ifm;
3174         struct mii_data *mii = NULL;
3175         int mtmp, itmp;
3176
3177         ASSERT_SERIALIZED(ifp->if_serializer);
3178
3179         if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
3180                 mii = device_get_softc(sc->bge_miibus);
3181
3182         callout_stop(&sc->bge_stat_timer);
3183
3184         /*
3185          * Disable all of the receiver blocks
3186          */
3187         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3188         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3189         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3190         if (!BGE_IS_5705_PLUS(sc))
3191                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3192         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3193         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3194         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3195
3196         /*
3197          * Disable all of the transmit blocks
3198          */
3199         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3200         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3201         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3202         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3203         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3204         if (!BGE_IS_5705_PLUS(sc))
3205                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3206         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3207
3208         /*
3209          * Shut down all of the memory managers and related
3210          * state machines.
3211          */
3212         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3213         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3214         if (!BGE_IS_5705_PLUS(sc))
3215                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3216         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3217         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3218         if (!BGE_IS_5705_PLUS(sc)) {
3219                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3220                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3221         }
3222
3223         /* Disable host interrupts. */
3224         bge_disable_intr(sc);
3225
3226         /*
3227          * Tell firmware we're shutting down.
3228          */
3229         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3230
3231         /* Free the RX lists. */
3232         bge_free_rx_ring_std(sc);
3233
3234         /* Free jumbo RX list. */
3235         if (BGE_IS_JUMBO_CAPABLE(sc))
3236                 bge_free_rx_ring_jumbo(sc);
3237
3238         /* Free TX buffers. */
3239         bge_free_tx_ring(sc);
3240
3241         /*
3242          * Isolate/power down the PHY, but leave the media selection
3243          * unchanged so that things will be put back to normal when
3244          * we bring the interface back up.
3245          *
3246          * 'mii' may be NULL in the following cases:
3247          * - The device uses TBI.
3248          * - bge_stop() is called by bge_detach().
3249          */
3250         if (mii != NULL) {
3251                 itmp = ifp->if_flags;
3252                 ifp->if_flags |= IFF_UP;
3253                 ifm = mii->mii_media.ifm_cur;
3254                 mtmp = ifm->ifm_media;
3255                 ifm->ifm_media = IFM_ETHER|IFM_NONE;
3256                 mii_mediachg(mii);
3257                 ifm->ifm_media = mtmp;
3258                 ifp->if_flags = itmp;
3259         }
3260
3261         sc->bge_link = 0;
3262         sc->bge_coal_chg = 0;
3263
3264         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3265
3266         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3267         ifp->if_timer = 0;
3268 }
3269
3270 /*
3271  * Stop all chip I/O so that the kernel's probe routines don't
3272  * get confused by errant DMAs when rebooting.
3273  */
3274 static void
3275 bge_shutdown(device_t dev)
3276 {
3277         struct bge_softc *sc = device_get_softc(dev);
3278         struct ifnet *ifp = &sc->arpcom.ac_if;
3279
3280         lwkt_serialize_enter(ifp->if_serializer);
3281         bge_stop(sc);
3282         bge_reset(sc);
3283         lwkt_serialize_exit(ifp->if_serializer);
3284 }
3285
3286 static int
3287 bge_suspend(device_t dev)
3288 {
3289         struct bge_softc *sc = device_get_softc(dev);
3290         struct ifnet *ifp = &sc->arpcom.ac_if;
3291
3292         lwkt_serialize_enter(ifp->if_serializer);
3293         bge_stop(sc);
3294         lwkt_serialize_exit(ifp->if_serializer);
3295
3296         return 0;
3297 }
3298
3299 static int
3300 bge_resume(device_t dev)
3301 {
3302         struct bge_softc *sc = device_get_softc(dev);
3303         struct ifnet *ifp = &sc->arpcom.ac_if;
3304
3305         lwkt_serialize_enter(ifp->if_serializer);
3306
3307         if (ifp->if_flags & IFF_UP) {
3308                 bge_init(sc);
3309
3310                 if (!ifq_is_empty(&ifp->if_snd))
3311                         if_devstart(ifp);
3312         }
3313
3314         lwkt_serialize_exit(ifp->if_serializer);
3315
3316         return 0;
3317 }
3318
3319 static void
3320 bge_setpromisc(struct bge_softc *sc)
3321 {
3322         struct ifnet *ifp = &sc->arpcom.ac_if;
3323
3324         if (ifp->if_flags & IFF_PROMISC)
3325                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3326         else
3327                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3328 }
3329
3330 static void
3331 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3332 {
3333         struct bge_dmamap_arg *ctx = arg;
3334
3335         if (error)
3336                 return;
3337
3338         KASSERT(nsegs == 1 && ctx->bge_maxsegs == 1,
3339                 ("only one segment is allowed\n"));
3340
3341         ctx->bge_segs[0] = *segs;
3342 }
3343
3344 static void
3345 bge_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nsegs,
3346                  bus_size_t mapsz __unused, int error)
3347 {
3348         struct bge_dmamap_arg *ctx = arg;
3349         int i;
3350
3351         if (error)
3352                 return;
3353
3354         if (nsegs > ctx->bge_maxsegs) {
3355                 ctx->bge_maxsegs = 0;
3356                 return;
3357         }
3358
3359         ctx->bge_maxsegs = nsegs;
3360         for (i = 0; i < nsegs; ++i)
3361                 ctx->bge_segs[i] = segs[i];
3362 }
3363
3364 static void
3365 bge_dma_free(struct bge_softc *sc)
3366 {
3367         int i;
3368
3369         /* Destroy RX/TX mbuf DMA stuffs. */
3370         if (sc->bge_cdata.bge_mtag != NULL) {
3371                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3372                         if (sc->bge_cdata.bge_rx_std_dmamap[i]) {
3373                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3374                                     sc->bge_cdata.bge_rx_std_dmamap[i]);
3375                         }
3376                 }
3377
3378                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3379                         if (sc->bge_cdata.bge_tx_dmamap[i]) {
3380                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3381                                     sc->bge_cdata.bge_tx_dmamap[i]);
3382                         }
3383                 }
3384                 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3385         }
3386
3387         /* Destroy standard RX ring */
3388         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3389                            sc->bge_cdata.bge_rx_std_ring_map,
3390                            sc->bge_ldata.bge_rx_std_ring);
3391
3392         if (BGE_IS_JUMBO_CAPABLE(sc))
3393                 bge_free_jumbo_mem(sc);
3394
3395         /* Destroy RX return ring */
3396         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3397                            sc->bge_cdata.bge_rx_return_ring_map,
3398                            sc->bge_ldata.bge_rx_return_ring);
3399
3400         /* Destroy TX ring */
3401         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3402                            sc->bge_cdata.bge_tx_ring_map,
3403                            sc->bge_ldata.bge_tx_ring);
3404
3405         /* Destroy status block */
3406         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3407                            sc->bge_cdata.bge_status_map,
3408                            sc->bge_ldata.bge_status_block);
3409
3410         /* Destroy statistics block */
3411         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3412                            sc->bge_cdata.bge_stats_map,
3413                            sc->bge_ldata.bge_stats);
3414
3415         /* Destroy the parent tag */
3416         if (sc->bge_cdata.bge_parent_tag != NULL)
3417                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3418 }
3419
3420 static int
3421 bge_dma_alloc(struct bge_softc *sc)
3422 {
3423         struct ifnet *ifp = &sc->arpcom.ac_if;
3424         int nseg, i, error;
3425
3426         /*
3427          * Allocate the parent bus DMA tag appropriate for PCI.
3428          */
3429         error = bus_dma_tag_create(NULL, 1, 0,
3430                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3431                                    NULL, NULL,
3432                                    MAXBSIZE, BGE_NSEG_NEW,
3433                                    BUS_SPACE_MAXSIZE_32BIT,
3434                                    0, &sc->bge_cdata.bge_parent_tag);
3435         if (error) {
3436                 if_printf(ifp, "could not allocate parent dma tag\n");
3437                 return error;
3438         }
3439
3440         /*
3441          * Create DMA tag for mbufs.
3442          */
3443         nseg = BGE_NSEG_NEW;
3444         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3445                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3446                                    NULL, NULL,
3447                                    MCLBYTES * nseg, nseg, MCLBYTES,
3448                                    BUS_DMA_ALLOCNOW, &sc->bge_cdata.bge_mtag);
3449         if (error) {
3450                 if_printf(ifp, "could not allocate mbuf dma tag\n");
3451                 return error;
3452         }
3453
3454         /*
3455          * Create DMA maps for TX/RX mbufs.
3456          */
3457         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3458                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3459                                           &sc->bge_cdata.bge_rx_std_dmamap[i]);
3460                 if (error) {
3461                         int j;
3462
3463                         for (j = 0; j < i; ++j) {
3464                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3465                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3466                         }
3467                         bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3468                         sc->bge_cdata.bge_mtag = NULL;
3469
3470                         if_printf(ifp, "could not create DMA map for RX\n");
3471                         return error;
3472                 }
3473         }
3474
3475         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3476                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3477                                           &sc->bge_cdata.bge_tx_dmamap[i]);
3478                 if (error) {
3479                         int j;
3480
3481                         for (j = 0; j < BGE_STD_RX_RING_CNT; ++j) {
3482                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3483                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3484                         }
3485                         for (j = 0; j < i; ++j) {
3486                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3487                                         sc->bge_cdata.bge_tx_dmamap[j]);
3488                         }
3489                         bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3490                         sc->bge_cdata.bge_mtag = NULL;
3491
3492                         if_printf(ifp, "could not create DMA map for TX\n");
3493                         return error;
3494                 }
3495         }
3496
3497         /*
3498          * Create DMA stuffs for standard RX ring.
3499          */
3500         error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3501                                     &sc->bge_cdata.bge_rx_std_ring_tag,
3502                                     &sc->bge_cdata.bge_rx_std_ring_map,
3503                                     (void **)&sc->bge_ldata.bge_rx_std_ring,
3504                                     &sc->bge_ldata.bge_rx_std_ring_paddr);
3505         if (error) {
3506                 if_printf(ifp, "could not create std RX ring\n");
3507                 return error;
3508         }
3509
3510         /*
3511          * Create jumbo buffer pool.
3512          */
3513         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3514                 error = bge_alloc_jumbo_mem(sc);
3515                 if (error) {
3516                         if_printf(ifp, "could not create jumbo buffer pool\n");
3517                         return error;
3518                 }
3519         }
3520
3521         /*
3522          * Create DMA stuffs for RX return ring.
3523          */
3524         error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3525                                     &sc->bge_cdata.bge_rx_return_ring_tag,
3526                                     &sc->bge_cdata.bge_rx_return_ring_map,
3527                                     (void **)&sc->bge_ldata.bge_rx_return_ring,
3528                                     &sc->bge_ldata.bge_rx_return_ring_paddr);
3529         if (error) {
3530                 if_printf(ifp, "could not create RX ret ring\n");
3531                 return error;
3532         }
3533
3534         /*
3535          * Create DMA stuffs for TX ring.
3536          */
3537         error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3538                                     &sc->bge_cdata.bge_tx_ring_tag,
3539                                     &sc->bge_cdata.bge_tx_ring_map,
3540                                     (void **)&sc->bge_ldata.bge_tx_ring,
3541                                     &sc->bge_ldata.bge_tx_ring_paddr);
3542         if (error) {
3543                 if_printf(ifp, "could not create TX ring\n");
3544                 return error;
3545         }
3546
3547         /*
3548          * Create DMA stuffs for status block.
3549          */
3550         error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3551                                     &sc->bge_cdata.bge_status_tag,
3552                                     &sc->bge_cdata.bge_status_map,
3553                                     (void **)&sc->bge_ldata.bge_status_block,
3554                                     &sc->bge_ldata.bge_status_block_paddr);
3555         if (error) {
3556                 if_printf(ifp, "could not create status block\n");
3557                 return error;
3558         }
3559
3560         /*
3561          * Create DMA stuffs for statistics block.
3562          */
3563         error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3564                                     &sc->bge_cdata.bge_stats_tag,
3565                                     &sc->bge_cdata.bge_stats_map,
3566                                     (void **)&sc->bge_ldata.bge_stats,
3567                                     &sc->bge_ldata.bge_stats_paddr);
3568         if (error) {
3569                 if_printf(ifp, "could not create stats block\n");
3570                 return error;
3571         }
3572         return 0;
3573 }
3574
3575 static int
3576 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3577                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3578 {
3579         struct ifnet *ifp = &sc->arpcom.ac_if;
3580         struct bge_dmamap_arg ctx;
3581         bus_dma_segment_t seg;
3582         int error;
3583
3584         /*
3585          * Create DMA tag
3586          */
3587         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3588                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3589                                    NULL, NULL, size, 1, size, 0, tag);
3590         if (error) {
3591                 if_printf(ifp, "could not allocate dma tag\n");
3592                 return error;
3593         }
3594
3595         /*
3596          * Allocate DMA'able memory
3597          */
3598         error = bus_dmamem_alloc(*tag, addr, BUS_DMA_WAITOK | BUS_DMA_ZERO,
3599                                  map);
3600         if (error) {
3601                 if_printf(ifp, "could not allocate dma memory\n");
3602                 bus_dma_tag_destroy(*tag);
3603                 *tag = NULL;
3604                 return error;
3605         }
3606
3607         /*
3608          * Load the DMA'able memory
3609          */
3610         ctx.bge_maxsegs = 1;
3611         ctx.bge_segs = &seg;
3612         error = bus_dmamap_load(*tag, *map, *addr, size, bge_dma_map_addr, &ctx,
3613                                 BUS_DMA_WAITOK);
3614         if (error) {
3615                 if_printf(ifp, "could not load dma memory\n");
3616                 bus_dmamem_free(*tag, *addr, *map);
3617                 bus_dma_tag_destroy(*tag);
3618                 *tag = NULL;
3619                 return error;
3620         }
3621         *paddr = ctx.bge_segs[0].ds_addr;
3622
3623         return 0;
3624 }
3625
3626 static void
3627 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3628 {
3629         if (tag != NULL) {
3630                 bus_dmamap_unload(tag, map);
3631                 bus_dmamem_free(tag, addr, map);
3632                 bus_dma_tag_destroy(tag);
3633         }
3634 }
3635
3636 /*
3637  * Grrr. The link status word in the status block does
3638  * not work correctly on the BCM5700 rev AX and BX chips,
3639  * according to all available information. Hence, we have
3640  * to enable MII interrupts in order to properly obtain
3641  * async link changes. Unfortunately, this also means that
3642  * we have to read the MAC status register to detect link
3643  * changes, thereby adding an additional register access to
3644  * the interrupt handler.
3645  *
3646  * XXX: perhaps link state detection procedure used for
3647  * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
3648  */
3649 static void
3650 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
3651 {
3652         struct ifnet *ifp = &sc->arpcom.ac_if;
3653         struct mii_data *mii = device_get_softc(sc->bge_miibus);
3654
3655         mii_pollstat(mii);
3656
3657         if (!sc->bge_link &&
3658             (mii->mii_media_status & IFM_ACTIVE) &&
3659             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3660                 sc->bge_link++;
3661                 if (bootverbose)
3662                         if_printf(ifp, "link UP\n");
3663         } else if (sc->bge_link &&
3664             (!(mii->mii_media_status & IFM_ACTIVE) ||
3665             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3666                 sc->bge_link = 0;
3667                 if (bootverbose)
3668                         if_printf(ifp, "link DOWN\n");
3669         }
3670
3671         /* Clear the interrupt. */
3672         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
3673         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
3674         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
3675 }
3676
3677 static void
3678 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
3679 {
3680         struct ifnet *ifp = &sc->arpcom.ac_if;
3681
3682 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3683
3684         /*
3685          * Sometimes PCS encoding errors are detected in
3686          * TBI mode (on fiber NICs), and for some reason
3687          * the chip will signal them as link changes.
3688          * If we get a link change event, but the 'PCS
3689          * encoding error' bit in the MAC status register
3690          * is set, don't bother doing a link check.
3691          * This avoids spurious "gigabit link up" messages
3692          * that sometimes appear on fiber NICs during
3693          * periods of heavy traffic.
3694          */
3695         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3696                 if (!sc->bge_link) {
3697                         sc->bge_link++;
3698                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3699                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3700                                     BGE_MACMODE_TBI_SEND_CFGS);
3701                         }
3702                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3703
3704                         if (bootverbose)
3705                                 if_printf(ifp, "link UP\n");
3706
3707                         ifp->if_link_state = LINK_STATE_UP;
3708                         if_link_state_change(ifp);
3709                 }
3710         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3711                 if (sc->bge_link) {
3712                         sc->bge_link = 0;
3713
3714                         if (bootverbose)
3715                                 if_printf(ifp, "link DOWN\n");
3716
3717                         ifp->if_link_state = LINK_STATE_DOWN;
3718                         if_link_state_change(ifp);
3719                 }
3720         }
3721
3722 #undef PCS_ENCODE_ERR
3723
3724         /* Clear the attention. */
3725         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3726             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3727             BGE_MACSTAT_LINK_CHANGED);
3728 }
3729
3730 static void
3731 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
3732 {
3733         /*
3734          * Check that the AUTOPOLL bit is set before
3735          * processing the event as a real link change.
3736          * Turning AUTOPOLL on and off in the MII read/write
3737          * functions will often trigger a link status
3738          * interrupt for no reason.
3739          */
3740         if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
3741                 struct ifnet *ifp = &sc->arpcom.ac_if;
3742                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3743
3744                 mii_pollstat(mii);
3745
3746                 if (!sc->bge_link &&
3747                     (mii->mii_media_status & IFM_ACTIVE) &&
3748                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3749                         sc->bge_link++;
3750                         if (bootverbose)
3751                                 if_printf(ifp, "link UP\n");
3752                 } else if (sc->bge_link &&
3753                     (!(mii->mii_media_status & IFM_ACTIVE) ||
3754                     IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3755                         sc->bge_link = 0;
3756                         if (bootverbose)
3757                                 if_printf(ifp, "link DOWN\n");
3758                 }
3759         }
3760
3761         /* Clear the attention. */
3762         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3763             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3764             BGE_MACSTAT_LINK_CHANGED);
3765 }
3766
3767 static int
3768 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3769 {
3770         struct bge_softc *sc = arg1;
3771
3772         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3773                                    &sc->bge_rx_coal_ticks,
3774                                    BGE_RX_COAL_TICKS_CHG);
3775 }
3776
3777 static int
3778 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3779 {
3780         struct bge_softc *sc = arg1;
3781
3782         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3783                                    &sc->bge_tx_coal_ticks,
3784                                    BGE_TX_COAL_TICKS_CHG);
3785 }
3786
3787 static int
3788 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3789 {
3790         struct bge_softc *sc = arg1;
3791
3792         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3793                                    &sc->bge_rx_max_coal_bds,
3794                                    BGE_RX_MAX_COAL_BDS_CHG);
3795 }
3796
3797 static int
3798 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3799 {
3800         struct bge_softc *sc = arg1;
3801
3802         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3803                                    &sc->bge_tx_max_coal_bds,
3804                                    BGE_TX_MAX_COAL_BDS_CHG);
3805 }
3806
3807 static int
3808 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3809                     uint32_t coal_chg_mask)
3810 {
3811         struct bge_softc *sc = arg1;
3812         struct ifnet *ifp = &sc->arpcom.ac_if;
3813         int error = 0, v;
3814
3815         lwkt_serialize_enter(ifp->if_serializer);
3816
3817         v = *coal;
3818         error = sysctl_handle_int(oidp, &v, 0, req);
3819         if (!error && req->newptr != NULL) {
3820                 if (v < 0) {
3821                         error = EINVAL;
3822                 } else {
3823                         *coal = v;
3824                         sc->bge_coal_chg |= coal_chg_mask;
3825                 }
3826         }
3827
3828         lwkt_serialize_exit(ifp->if_serializer);
3829         return error;
3830 }
3831
3832 static void
3833 bge_coal_change(struct bge_softc *sc)
3834 {
3835         struct ifnet *ifp = &sc->arpcom.ac_if;
3836         uint32_t val;
3837
3838         ASSERT_SERIALIZED(ifp->if_serializer);
3839
3840         if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
3841                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3842                             sc->bge_rx_coal_ticks);
3843                 DELAY(10);
3844                 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3845
3846                 if (bootverbose) {
3847                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3848                                   sc->bge_rx_coal_ticks);
3849                 }
3850         }
3851
3852         if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
3853                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3854                             sc->bge_tx_coal_ticks);
3855                 DELAY(10);
3856                 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3857
3858                 if (bootverbose) {
3859                         if_printf(ifp, "tx_coal_ticks -> %u\n",
3860                                   sc->bge_tx_coal_ticks);
3861                 }
3862         }
3863
3864         if (sc->bge_coal_chg & BGE_RX_MAX_COAL_BDS_CHG) {
3865                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3866                             sc->bge_rx_max_coal_bds);
3867                 DELAY(10);
3868                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3869
3870                 if (bootverbose) {
3871                         if_printf(ifp, "rx_max_coal_bds -> %u\n",
3872                                   sc->bge_rx_max_coal_bds);
3873                 }
3874         }
3875
3876         if (sc->bge_coal_chg & BGE_TX_MAX_COAL_BDS_CHG) {
3877                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3878                             sc->bge_tx_max_coal_bds);
3879                 DELAY(10);
3880                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3881
3882                 if (bootverbose) {
3883                         if_printf(ifp, "tx_max_coal_bds -> %u\n",
3884                                   sc->bge_tx_max_coal_bds);
3885                 }
3886         }
3887
3888         sc->bge_coal_chg = 0;
3889 }
3890
3891 static void
3892 bge_enable_intr(struct bge_softc *sc)
3893 {
3894         struct ifnet *ifp = &sc->arpcom.ac_if;
3895
3896         lwkt_serialize_handler_enable(ifp->if_serializer);
3897
3898         /*
3899          * Enable interrupt.
3900          */
3901         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
3902
3903         /*
3904          * Unmask the interrupt when we stop polling.
3905          */
3906         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3907
3908         /*
3909          * Trigger another interrupt, since above writing
3910          * to interrupt mailbox0 may acknowledge pending
3911          * interrupt.
3912          */
3913         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3914 }
3915
3916 static void
3917 bge_disable_intr(struct bge_softc *sc)
3918 {
3919         struct ifnet *ifp = &sc->arpcom.ac_if;
3920
3921         /*
3922          * Mask the interrupt when we start polling.
3923          */
3924         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3925
3926         /*
3927          * Acknowledge possible asserted interrupt.
3928          */
3929         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
3930
3931         lwkt_serialize_handler_disable(ifp->if_serializer);
3932 }