2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/ata/ata-dma.c,v 1.35.2.31 2003/05/07 16:46:11 jhb Exp $
29 * $DragonFly: src/sys/dev/disk/ata/ata-dma.c,v 1.21 2004/03/29 16:22:23 dillon Exp $
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/mpipe.h>
40 #include <sys/devicestat.h>
43 #include <bus/pci/pcivar.h>
44 #include <machine/bus.h>
49 static void cyrix_timing(struct ata_device *, int, int);
50 static void promise_timing(struct ata_device *, int, int);
51 static void hpt_timing(struct ata_device *, int, int);
52 static int hpt_cable80(struct ata_device *);
57 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
59 #define ATAPI_DEVICE(atadev) \
60 ((atadev->unit == ATA_MASTER && \
61 atadev->channel->devices & ATA_ATAPI_MASTER) || \
62 (atadev->unit == ATA_SLAVE && \
63 atadev->channel->devices & ATA_ATAPI_SLAVE))
65 int ata_dma_debug = 0;
68 ata_dmaalloc(struct ata_device *atadev, int flags)
70 struct ata_channel *ch = atadev->channel;
72 if (atadev->dmastate.dmatab != NULL)
75 KKASSERT(ch->dma_mpipe.max_count != 0);
76 if (flags & M_RNOWAIT)
77 atadev->dmastate.dmatab = mpipe_alloc_nowait(&ch->dma_mpipe);
79 atadev->dmastate.dmatab = mpipe_alloc_waitok(&ch->dma_mpipe);
81 if (atadev->dmastate.dmatab != NULL) {
82 KKASSERT(((uintptr_t)atadev->dmastate.dmatab & PAGE_MASK) == 0);
89 ata_dmafree(struct ata_device *atadev)
91 struct ata_channel *ch = atadev->channel;
93 if (atadev->dmastate.dmatab) {
94 mpipe_free(&ch->dma_mpipe, atadev->dmastate.dmatab);
95 atadev->dmastate.dmatab = NULL;
100 ata_dmafreetags(struct ata_channel *ch)
105 ata_dmacreate(struct ata_device *atadev, int apiomode, int mode)
111 ata_dmainit(struct ata_device *atadev, int apiomode, int wdmamode, int udmamode)
113 device_t parent = device_get_parent(atadev->channel->dev);
114 int chiptype = atadev->channel->chiptype;
115 int chiprev = pci_get_revid(parent);
116 int channel = atadev->channel->unit;
117 int device = ATA_DEV(atadev->unit);
118 int devno = (channel << 1) + device;
121 /* set our most pessimistic default mode */
122 atadev->mode = ATA_PIO;
124 if (!atadev->channel->r_bmio)
127 /* if simplex controller, only allow DMA on primary channel */
129 ATA_OUTB(atadev->channel->r_bmio, ATA_BMSTAT_PORT,
130 ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
131 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
132 if (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
133 ATA_BMSTAT_DMA_SIMPLEX) {
134 ata_prtdev(atadev, "simplex device, DMA on primary only\n");
139 /* DMA engine address alignment is usually 1 word (2 bytes) */
140 atadev->channel->alignment = 0x1;
143 if (udmamode > 2 && !atadev->param->hwres_cblid) {
144 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
150 case 0x24db8086: /* Intel ICH5 */
151 case 0x24d18086: /* Intel ICH5 SATA */
152 case 0x24ca8086: /* Intel ICH4 mobile */
153 case 0x24cb8086: /* Intel ICH4 */
154 case 0x248a8086: /* Intel ICH3 mobile */
155 case 0x248b8086: /* Intel ICH3 */
156 case 0x244a8086: /* Intel ICH2 mobile */
157 case 0x244b8086: /* Intel ICH2 */
159 int32_t mask48, new48;
162 word54 = pci_read_config(parent, 0x54, 2);
163 if (word54 & (0x10 << devno)) {
164 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
165 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY);
167 ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n",
168 (error) ? "failed" : "success");
170 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
171 new48 = (1 << devno) + (1 << (16 + (devno << 2)));
172 pci_write_config(parent, 0x48,
173 (pci_read_config(parent, 0x48, 4) &
174 ~mask48) | new48, 4);
175 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2);
176 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
181 /* make sure eventual ATA100 mode from the BIOS is disabled */
182 pci_write_config(parent, 0x54,
183 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
186 case 0x24118086: /* Intel ICH */
187 case 0x76018086: /* Intel ICH */
189 int32_t mask48, new48;
192 word54 = pci_read_config(parent, 0x54, 2);
193 if (word54 & (0x10 << devno)) {
194 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
195 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
197 ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n",
198 (error) ? "failed" : "success");
200 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
201 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
202 pci_write_config(parent, 0x48,
203 (pci_read_config(parent, 0x48, 4) &
204 ~mask48) | new48, 4);
205 pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
206 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
211 /* make sure eventual ATA66 mode from the BIOS is disabled */
212 pci_write_config(parent, 0x54,
213 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
216 case 0x71118086: /* Intel PIIX4 */
217 case 0x84CA8086: /* Intel PIIX4 */
218 case 0x71998086: /* Intel PIIX4e */
219 case 0x24218086: /* Intel ICH0 */
221 int32_t mask48, new48;
223 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
224 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
226 ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n",
227 (error) ? "failed" : "success");
229 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
230 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
231 pci_write_config(parent, 0x48,
232 (pci_read_config(parent, 0x48, 4) &
233 ~mask48) | new48, 4);
234 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
238 /* make sure eventual ATA33 mode from the BIOS is disabled */
239 pci_write_config(parent, 0x48,
240 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
243 case 0x70108086: /* Intel PIIX3 */
244 if (wdmamode >= 2 && apiomode >= 4) {
245 int32_t mask40, new40, mask44, new44;
247 /* if SITRE not set doit for both channels */
248 if (!((pci_read_config(parent,0x40,4)>>(channel<<8))&0x4000)) {
249 new40 = pci_read_config(parent, 0x40, 4);
250 new44 = pci_read_config(parent, 0x44, 4);
251 if (!(new40 & 0x00004000)) {
252 new44 &= ~0x0000000f;
253 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
255 if (!(new40 & 0x40000000)) {
256 new44 &= ~0x000000f0;
257 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
260 pci_write_config(parent, 0x40, new40, 4);
261 pci_write_config(parent, 0x44, new44, 4);
263 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
264 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
266 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
267 (error) ? "failed" : "success");
269 if (device == ATA_MASTER) {
287 pci_write_config(parent, 0x40,
288 (pci_read_config(parent, 0x40, 4) & ~mask40)|
290 pci_write_config(parent, 0x44,
291 (pci_read_config(parent, 0x44, 4) & ~mask44)|
293 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
297 /* we could set PIO mode timings, but we assume the BIOS did that */
300 case 0x12308086: /* Intel PIIX */
301 if (wdmamode >= 2 && apiomode >= 4) {
304 word40 = pci_read_config(parent, 0x40, 4);
305 word40 >>= channel * 16;
307 /* Check for timing config usable for DMA on controller */
308 if (!((word40 & 0x3300) == 0x2300 &&
309 ((word40 >> (device ? 4 : 0)) & 1) == 1))
312 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
313 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
315 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
316 (error) ? "failed" : "success");
318 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
324 case 0x522910b9: /* AcerLabs Aladdin IV/V */
325 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */
326 if (chiprev < 0xc2 &&
327 atadev->channel->devices & ATA_ATAPI_MASTER &&
328 atadev->channel->devices & ATA_ATAPI_SLAVE) {
329 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n");
332 #if !defined(NO_ATANG)
333 pci_write_config(parent, 0x58 + (channel << 2), 0x00310001, 4);
335 if (udmamode >= 5 && chiprev >= 0xc4) {
336 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
337 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
339 ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n",
340 (error) ? "failed" : "success");
342 int32_t word54 = pci_read_config(parent, 0x54, 4);
344 pci_write_config(parent, 0x4b,
345 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
346 word54 &= ~(0x000f000f << (devno << 2));
347 word54 |= (0x000f0005 << (devno << 2));
348 pci_write_config(parent, 0x54, word54, 4);
349 pci_write_config(parent, 0x53,
350 pci_read_config(parent, 0x53, 1) | 0x03, 1);
351 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
355 if (udmamode >= 4 && chiprev >= 0xc2) {
356 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
357 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
359 ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n",
360 (error) ? "failed" : "success");
362 int32_t word54 = pci_read_config(parent, 0x54, 4);
364 pci_write_config(parent, 0x4b,
365 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
366 word54 &= ~(0x000f000f << (devno << 2));
367 word54 |= (0x00080005 << (devno << 2));
368 pci_write_config(parent, 0x54, word54, 4);
369 pci_write_config(parent, 0x53,
370 pci_read_config(parent, 0x53, 1) | 0x03, 1);
371 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
375 if (udmamode >= 2 && chiprev >= 0x20) {
376 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
377 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
379 ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n",
380 (error) ? "failed" : "success");
382 int32_t word54 = pci_read_config(parent, 0x54, 4);
384 word54 &= ~(0x000f000f << (devno << 2));
385 word54 |= (0x000a0005 << (devno << 2));
386 pci_write_config(parent, 0x54, word54, 4);
387 pci_write_config(parent, 0x53,
388 pci_read_config(parent, 0x53, 1) | 0x03, 1);
389 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
390 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
395 /* make sure eventual UDMA mode from the BIOS is disabled */
396 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) &
397 ~(0x0008 << (devno << 2)), 2);
399 if (wdmamode >= 2 && apiomode >= 4) {
400 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
401 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
403 ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n",
404 (error) ? "failed" : "success");
406 pci_write_config(parent, 0x53,
407 pci_read_config(parent, 0x53, 1) | 0x03, 1);
408 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
409 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
413 pci_write_config(parent, 0x53,
414 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
415 #if !defined(NO_ATANG)
416 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
418 ATA_C_F_SETXFER, ATA_WAIT_READY);
420 ata_prtdev(atadev, "%s setting PIO%d on Acer chip\n",
421 (error) ? "failed" : "success",
422 (apiomode >= 0) ? apiomode : 0);
424 int32_t word54 = pci_read_config(parent, 0x54, 4);
427 switch(ATA_PIO0 + apiomode) {
428 case ATA_PIO0: timing = 0x006d0003; break;
429 case ATA_PIO1: timing = 0x00580002; break;
430 case ATA_PIO2: timing = 0x00440001; break;
431 case ATA_PIO3: timing = 0x00330001; break;
432 case ATA_PIO4: timing = 0x00310001; break;
433 default: timing = 0x006d0003; break;
435 pci_write_config(parent, 0x58 + (channel << 2), timing, 4);
436 word54 &= ~(0x000f000f << (devno << 2));
437 word54 |= (0x00000004 << (devno << 2));
438 pci_write_config(parent, 0x54, word54, 4);
439 atadev->mode = ATA_PIO0 + apiomode;
445 case 0x31491106: /* VIA 8237 SATA part */
447 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
449 ATA_C_F_SETXFER, ATA_WAIT_READY);
451 ata_prtdev(atadev, "%s setting UDMA%d on VIA chip\n",
452 (error) ? "failed" : "success", udmamode);
454 ata_dmacreate(atadev, apiomode, ATA_UDMA + udmamode);
458 /* we could set PIO mode timings, but we assume the BIOS did that */
461 case 0x01bc10de: /* NVIDIA nForce */
462 case 0x006510de: /* NVIDIA nForce2 */
463 case 0x74691022: /* AMD 8111 */
464 case 0x74411022: /* AMD 768 */
465 case 0x74111022: /* AMD 766 */
466 case 0x74091022: /* AMD 756 */
467 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686, 8231,8233,8235 */
469 int via_modes[5][7] = {
470 { 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
471 { 0x00, 0x00, 0xea, 0x00, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
472 { 0x00, 0x00, 0xf4, 0x00, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
473 { 0x00, 0x00, 0xf6, 0x00, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
474 { 0x00, 0x00, 0xc0, 0x00, 0xc5, 0xc6, 0xc7 }}; /* AMD/NVIDIA */
479 if (ata_find_dev(parent, 0x31471106, 0) || /* 8233a */
480 ata_find_dev(parent, 0x31771106, 0) || /* 8235 */
481 ata_find_dev(parent, 0x31491106, 0)) { /* 8237 */
482 udmamode = imin(udmamode, 6);
483 reg_val = via_modes[3];
485 else if (ata_find_dev(parent, 0x06861106, 0x40) || /* 82C686b */
486 ata_find_dev(parent, 0x82311106, 0) || /* 8231 */
487 ata_find_dev(parent, 0x30741106, 0) || /* 8233 */
488 ata_find_dev(parent, 0x31091106, 0)) { /* 8233c */
489 udmamode = imin(udmamode, 5);
490 reg_val = via_modes[2];
492 else if (ata_find_dev(parent, 0x06861106, 0x10) || /* 82C686a */
493 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */
494 udmamode = imin(udmamode, 4);
495 reg_val = via_modes[1];
497 else if (ata_find_dev(parent, 0x06861106, 0)) { /* 82C686 */
498 udmamode = imin(udmamode, 2);
499 reg_val = via_modes[1];
501 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */
502 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */
503 udmamode = imin(udmamode, 2);
504 reg_val = via_modes[0];
506 else if (chiptype == 0x74691022 || /* AMD 8111 */
507 chiptype == 0x74411022 || /* AMD 768 */
508 chiptype == 0x74111022) { /* AMD 766 */
509 udmamode = imin(udmamode, 5);
510 reg_val = via_modes[4];
513 else if (chiptype == 0x74091022) { /* AMD 756 */
514 udmamode = imin(udmamode, 4);
515 reg_val = via_modes[4];
518 else if (chiptype == 0x01bc10de) { /* nForce */
519 udmamode = imin(udmamode, 5);
520 reg_val = via_modes[4];
521 #if !defined(NO_ATANG)
526 else if (chiptype == 0x006510de) { /* nForce2 */
527 udmamode = imin(udmamode, 6);
528 reg_val = via_modes[4];
529 #if !defined(NO_ATANG)
538 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
539 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
541 ata_prtdev(atadev, "%s setting UDMA6 on %s chip\n",
542 (error) ? "failed" : "success", chip);
544 pci_write_config(parent, reg_off - devno, reg_val[6], 1);
545 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
550 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
551 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
553 ata_prtdev(atadev, "%s setting UDMA5 on %s chip\n",
554 (error) ? "failed" : "success", chip);
556 pci_write_config(parent, reg_off - devno, reg_val[5], 1);
557 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
562 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
563 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
565 ata_prtdev(atadev, "%s setting UDMA4 on %s chip\n",
566 (error) ? "failed" : "success", chip);
568 pci_write_config(parent, reg_off - devno, reg_val[4], 1);
569 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
574 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
575 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
577 ata_prtdev(atadev, "%s setting UDMA2 on %s chip\n",
578 (error) ? "failed" : "success", chip);
580 pci_write_config(parent, reg_off - devno, reg_val[2], 1);
581 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
585 if (wdmamode >= 2 && apiomode >= 4) {
586 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
587 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
589 ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n",
590 (error) ? "failed" : "success", chip);
592 pci_write_config(parent, reg_off - devno, 0x0b, 1);
593 pci_write_config(parent, (reg_off - 8) - devno, 0x31, 1);
594 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
599 /* we could set PIO mode timings, but we assume the BIOS did that */
602 case 0x55131039: /* SiS 5591 */
603 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */
604 ata_find_dev(parent, 0x06331039, 0) || /* SiS 633 */
605 ata_find_dev(parent, 0x06351039, 0) || /* SiS 635 */
606 ata_find_dev(parent, 0x06401039, 0) || /* SiS 640 */
607 ata_find_dev(parent, 0x06451039, 0) || /* SiS 645 */
608 ata_find_dev(parent, 0x06461039, 0) || /* SiS 645DX */
609 ata_find_dev(parent, 0x06481039, 0) || /* SiS 648 */
610 ata_find_dev(parent, 0x06501039, 0) || /* SiS 650 */
611 ata_find_dev(parent, 0x07301039, 0) || /* SiS 730 */
612 ata_find_dev(parent, 0x07331039, 0) || /* SiS 733 */
613 ata_find_dev(parent, 0x07351039, 0) || /* SiS 735 */
614 ata_find_dev(parent, 0x07401039, 0) || /* SiS 740 */
615 ata_find_dev(parent, 0x07451039, 0) || /* SiS 745 */
616 ata_find_dev(parent, 0x07461039, 0) || /* SiS 746 */
617 ata_find_dev(parent, 0x07501039, 0)) { /* SiS 750 */
618 int8_t reg = 0x40 + (devno << 1);
619 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
622 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
623 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
625 ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n",
626 (error) ? "failed" : "success");
628 pci_write_config(parent, reg, val | 0x8000, 2);
629 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
634 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
635 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
637 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
638 (error) ? "failed" : "success");
640 pci_write_config(parent, reg, val | 0x9000, 2);
641 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
646 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
647 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
649 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
650 (error) ? "failed" : "success");
652 pci_write_config(parent, reg, val | 0xb000, 2);
653 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
657 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */
658 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */
659 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */
660 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */
661 int8_t reg = 0x40 + (devno << 1);
662 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
665 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
666 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
668 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
669 (error) ? "failed" : "success");
671 pci_write_config(parent, reg, val | 0x9000, 2);
672 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
677 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
678 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
680 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
681 (error) ? "failed" : "success");
683 pci_write_config(parent, reg, val | 0xa000, 2);
684 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
688 } else if (udmamode >= 2 && chiprev > 0xc1) {
689 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
690 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
692 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
693 (error) ? "failed" : "success");
695 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
696 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
700 if (wdmamode >=2 && apiomode >= 4) {
701 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
702 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
704 ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n",
705 (error) ? "failed" : "success");
707 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
708 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
712 /* we could set PIO mode timings, but we assume the BIOS did that */
715 case 0x35121095: /* SiI 3512 SATA controller */
716 /* EXPERIMENTAL! Works with FN85 AMD 64 3200+ motherboard */
718 case 0x31141095: /* SiI 3114 SATA controller */
719 case 0x06801095: /* SiI 0680 ATA133 controller */
721 u_int8_t ureg = 0xac + (device * 0x02) + (channel * 0x10);
722 u_int8_t uval = pci_read_config(parent, ureg, 1);
723 u_int8_t mreg = channel ? 0x84 : 0x80;
724 u_int8_t mask = device ? 0x30 : 0x03;
725 u_int8_t mode = pci_read_config(parent, mreg, 1);
727 /* enable UDMA mode */
728 pci_write_config(parent, mreg,
729 (mode & ~mask) | (device ? 0x30 : 0x03), 1);
731 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
732 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
734 ata_prtdev(atadev, "%s setting UDMA6 on SiI chip\n",
735 (error) ? "failed" : "success");
737 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x01, 1);
738 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
743 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
744 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
746 ata_prtdev(atadev, "%s setting UDMA5 on SiI chip\n",
747 (error) ? "failed" : "success");
749 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x02, 1);
750 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
755 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
756 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
758 ata_prtdev(atadev, "%s setting UDMA4 on SiI chip\n",
759 (error) ? "failed" : "success");
761 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x03, 1);
762 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
767 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
768 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
770 ata_prtdev(atadev, "%s setting UDMA2 on SiI chip\n",
771 (error) ? "failed" : "success");
773 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x07, 1);
774 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
779 /* disable UDMA mode and enable WDMA mode */
780 pci_write_config(parent, mreg,
781 (mode & ~mask) | (device ? 0x20 : 0x02), 1);
782 if (wdmamode >= 2 && apiomode >= 4) {
783 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
784 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
786 ata_prtdev(atadev, "%s setting WDMA2 on SiI chip\n",
787 (error) ? "failed" : "success");
789 pci_write_config(parent, ureg - 0x4, 0x10c1, 2);
790 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
795 /* restore PIO mode */
796 pci_write_config(parent, mreg, mode, 1);
798 /* we could set PIO mode timings, but we assume the BIOS did that */
801 case 0x06491095: /* CMD 649 ATA100 controller */
805 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
806 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
808 ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n",
809 (error) ? "failed" : "success");
811 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
812 umode &= ~(device ? 0xca : 0x35);
813 umode |= (device ? 0x0a : 0x05);
814 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
815 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
821 case 0x06481095: /* CMD 648 ATA66 controller */
825 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
826 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
828 ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n",
829 (error) ? "failed" : "success");
831 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
832 umode &= ~(device ? 0xca : 0x35);
833 umode |= (device ? 0x4a : 0x15);
834 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
835 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
842 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
843 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
845 ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n",
846 (error) ? "failed" : "success");
848 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
849 umode &= ~(device ? 0xca : 0x35);
850 umode |= (device ? 0x42 : 0x11);
851 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
852 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
856 /* make sure eventual UDMA mode from the BIOS is disabled */
857 pci_write_config(parent, channel ? 0x7b : 0x73,
858 pci_read_config(parent, channel ? 0x7b : 0x73, 1)&
859 #if !defined(NO_ATANG)
860 ~(device ? 0xca : 0x53), 1);
862 ~(device ? 0xca : 0x35), 1);
866 case 0x06461095: /* CMD 646 ATA controller */
867 if (wdmamode >= 2 && apiomode >= 4) {
868 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
869 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
871 ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n",
872 error ? "failed" : "success");
874 int32_t offset = (devno < 3) ? (devno << 1) : 7;
876 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
877 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
881 /* we could set PIO mode timings, but we assume the BIOS did that */
884 case 0xc6931080: /* Cypress 82c693 ATA controller */
885 if (wdmamode >= 2 && apiomode >= 4) {
886 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
887 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
889 ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n",
890 error ? "failed" : "success");
892 pci_write_config(atadev->channel->dev,
893 channel ? 0x4e:0x4c, 0x2020, 2);
894 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
898 /* we could set PIO mode timings, but we assume the BIOS did that */
901 case 0x01021078: /* Cyrix 5530 ATA33 controller */
902 atadev->channel->alignment = 0xf; /* DMA engine requires 16 byte alignment */
904 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
905 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
907 ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n",
908 (error) ? "failed" : "success");
910 cyrix_timing(atadev, devno, ATA_UDMA2);
911 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
915 if (wdmamode >= 2 && apiomode >= 4) {
916 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
917 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
919 ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n",
920 (error) ? "failed" : "success");
922 cyrix_timing(atadev, devno, ATA_WDMA2);
923 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
927 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
928 ATA_PIO0 + apiomode, ATA_C_F_SETXFER,
931 ata_prtdev(atadev, "%s setting %s on Cyrix chip\n",
932 (error) ? "failed" : "success",
933 ata_mode2str(ATA_PIO0 + apiomode));
934 cyrix_timing(atadev, devno, ATA_PIO0 + apiomode);
935 atadev->mode = ATA_PIO0 + apiomode;
938 #if !defined(NO_ATANG)
939 case 0x02131166: /* ServerWorks CSB6 ATA 100 controller (chan 0+1) */
941 case 0x02121166: /* ServerWorks CSB5 ATA66/100 controller */
942 #if !defined(NO_ATANG)
943 if (udmamode >= 5 && (chiptype == 0x02131166 ||
944 (chiptype == 0x02121166 &&
947 if (udmamode >= 5 && chiprev >= 0x92) {
949 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
950 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
952 ata_prtdev(atadev, "%s setting UDMA5 on ServerWorks chip\n",
953 (error) ? "failed" : "success");
957 pci_write_config(parent, 0x54,
958 pci_read_config(parent, 0x54, 1) |
960 reg56 = pci_read_config(parent, 0x56, 2);
961 reg56 &= ~(0xf << (devno * 4));
962 reg56 |= (0x5 << (devno * 4));
963 pci_write_config(parent, 0x56, reg56, 2);
964 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
968 #if !defined(NO_ATANG)
970 case 0x02171166: /* Server Works CSB6 ATA 66 controller chan 2 */
973 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
974 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
976 ata_prtdev(atadev, "%s setting UDMA4 on ServerWorks chip\n",
977 (error) ? "failed" : "success");
981 pci_write_config(parent, 0x54,
982 pci_read_config(parent, 0x54, 1) |
984 reg56 = pci_read_config(parent, 0x56, 2);
985 reg56 &= ~(0xf << (devno * 4));
986 reg56 |= (0x4 << (devno * 4));
987 pci_write_config(parent, 0x56, reg56, 2);
988 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
994 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */
996 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
997 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
999 ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n",
1000 (error) ? "failed" : "success");
1004 pci_write_config(parent, 0x54,
1005 pci_read_config(parent, 0x54, 1) |
1006 (0x01 << devno), 1);
1007 reg56 = pci_read_config(parent, 0x56, 2);
1008 reg56 &= ~(0xf << (devno * 4));
1009 reg56 |= (0x2 << (devno * 4));
1010 pci_write_config(parent, 0x56, reg56, 2);
1011 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1015 if (wdmamode >= 2 && apiomode >= 4) {
1016 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1017 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1019 ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n",
1020 (error) ? "failed" : "success");
1022 int offset = devno ^ 0x01; /* (chan*2) + (dev==ATA_MASTER)*/
1023 int word44 = pci_read_config(parent, 0x44, 4);
1025 pci_write_config(parent, 0x54,
1026 pci_read_config(parent, 0x54, 1) &
1027 ~(0x01 << devno), 1);
1028 word44 &= ~(0xff << (offset << 8));
1029 word44 |= (0x20 << (offset << 8));
1030 pci_write_config(parent, 0x44, 0x20, 4);
1031 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1035 /* we could set PIO mode timings, but we assume the BIOS did that */
1038 case 0x4d69105a: /* Promise TX2 ATA133 controllers */
1039 case 0x5275105a: /* Promise TX2 ATA133 controllers */
1040 case 0x6269105a: /* Promise TX2 ATA133 controllers */
1041 case 0x7275105a: /* Promise TX2 ATA133 controllers */
1042 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1043 if (udmamode >= 6 &&
1044 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1045 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1046 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
1048 ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n",
1049 (error) ? "failed" : "success");
1051 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
1057 case 0x4d68105a: /* Promise TX2 ATA100 controllers */
1058 case 0x6268105a: /* Promise TX2 ATA100 controllers */
1059 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1060 if (udmamode >= 5 &&
1061 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1062 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1063 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1065 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
1066 (error) ? "failed" : "success");
1068 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1072 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1073 if (udmamode >= 4 &&
1074 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1075 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1076 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1078 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
1079 (error) ? "failed" : "success");
1081 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1085 if (udmamode >= 2) {
1086 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1087 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1089 ata_prtdev(atadev, "%s setting UDMA on Promise chip\n",
1090 (error) ? "failed" : "success");
1092 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1096 if (wdmamode >= 2 && apiomode >= 4) {
1097 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1098 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1100 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
1101 (error) ? "failed" : "success");
1103 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1109 case 0x0d30105a: /* Promise OEM ATA100 controllers */
1110 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */
1111 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 &&
1112 !(pci_read_config(parent, 0x50, 2)&(channel ? 1<<11 : 1<<10))){
1113 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1114 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1116 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
1117 (error) ? "failed" : "success");
1119 promise_timing(atadev, devno, ATA_UDMA5);
1120 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1126 case 0x0d38105a: /* Promise FastTrak 66 controllers */
1127 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */
1128 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 &&
1129 !(pci_read_config(parent, 0x50, 2)&(channel ? 1<<11 : 1<<10))){
1130 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1131 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1133 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
1134 (error) ? "failed" : "success");
1136 promise_timing(atadev, devno, ATA_UDMA4);
1137 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1143 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */
1144 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) {
1145 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1146 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1148 ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n",
1149 (error) ? "failed" : "success");
1151 promise_timing(atadev, devno, ATA_UDMA2);
1152 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1156 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) {
1157 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1158 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1160 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
1161 (error) ? "failed" : "success");
1163 promise_timing(atadev, devno, ATA_WDMA2);
1164 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1168 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1169 ATA_PIO0 + apiomode,
1170 ATA_C_F_SETXFER, ATA_WAIT_READY);
1172 ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n",
1173 (error) ? "failed" : "success",
1174 (apiomode >= 0) ? apiomode : 0);
1175 promise_timing(atadev, devno, ATA_PIO0 + apiomode);
1176 atadev->mode = ATA_PIO0 + apiomode;
1179 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */
1180 case 0x00051103: /* HighPoint HPT372 controllers */
1181 case 0x00081103: /* HighPoint HPT374 controllers */
1182 if (!ATAPI_DEVICE(atadev) && udmamode >= 6 && hpt_cable80(atadev) &&
1183 ((chiptype == 0x00041103 && chiprev >= 0x05) ||
1184 (chiptype == 0x00051103 && chiprev >= 0x01) ||
1185 (chiptype == 0x00081103 && chiprev >= 0x07))) {
1186 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1187 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
1189 ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n",
1190 (error) ? "failed" : "success");
1192 hpt_timing(atadev, devno, ATA_UDMA6);
1193 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
1197 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 && hpt_cable80(atadev) &&
1198 ((chiptype == 0x00041103 && chiprev >= 0x03) ||
1199 (chiptype == 0x00051103 && chiprev >= 0x01) ||
1200 (chiptype == 0x00081103 && chiprev >= 0x07))) {
1201 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1202 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1204 ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n",
1205 (error) ? "failed" : "success");
1207 hpt_timing(atadev, devno, ATA_UDMA5);
1208 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1212 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 && hpt_cable80(atadev)) {
1213 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1214 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1216 ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n",
1217 (error) ? "failed" : "success");
1219 hpt_timing(atadev, devno, ATA_UDMA4);
1220 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1224 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) {
1225 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1226 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1228 ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n",
1229 (error) ? "failed" : "success");
1231 hpt_timing(atadev, devno, ATA_UDMA2);
1232 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1236 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) {
1237 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1238 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1240 ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n",
1241 (error) ? "failed" : "success");
1243 hpt_timing(atadev, devno, ATA_WDMA2);
1244 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1248 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1249 ATA_PIO0 + apiomode,
1250 ATA_C_F_SETXFER, ATA_WAIT_READY);
1252 ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n",
1253 (error) ? "failed" : "success",
1254 (apiomode >= 0) ? apiomode : 0);
1255 hpt_timing(atadev, devno, ATA_PIO0 + apiomode);
1256 atadev->mode = ATA_PIO0 + apiomode;
1259 case 0x000116ca: /* Cenatek Rocket Drive controller */
1260 if (wdmamode >= 0 &&
1261 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
1262 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER)))
1263 ata_dmacreate(atadev, apiomode, ATA_DMA);
1265 atadev->mode = ATA_PIO;
1268 default: /* unknown controller chip */
1269 /* better not try generic DMA on ATAPI devices it almost never works */
1270 if (ATAPI_DEVICE(atadev))
1273 /* if controller says its setup for DMA take the easy way out */
1274 /* the downside is we dont know what DMA mode we are in */
1275 if ((udmamode >= 0 || wdmamode >= 2) &&
1276 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
1277 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER))) {
1278 ata_dmacreate(atadev, apiomode, ATA_DMA);
1282 /* well, we have no support for this, but try anyways */
1283 if ((wdmamode >= 2 && apiomode >= 4) && atadev->channel->r_bmio) {
1284 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1285 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1287 ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n",
1288 (error) ? "failed" : "success");
1290 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1295 error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode,
1296 ATA_C_F_SETXFER, ATA_WAIT_READY);
1298 ata_prtdev(atadev, "%s setting PIO%d on generic chip\n",
1299 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
1301 atadev->mode = ATA_PIO0 + apiomode;
1304 ata_prtdev(atadev, "using PIO mode set by BIOS\n");
1305 atadev->mode = ATA_PIO;
1310 ata_dmasetup(struct ata_device *atadev, caddr_t data, int32_t count)
1312 struct ata_channel *ch = atadev->channel;
1313 struct ata_dmastate *ds = &atadev->dmastate;
1314 u_int32_t dma_count, dma_base;
1317 if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) {
1318 ata_prtdev(atadev, "non aligned DMA transfer attempted\n");
1323 ata_prtdev(atadev, "zero length DMA transfer attempted\n");
1327 dma_base = vtophys(data);
1328 dma_count = imin(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
1333 ds->dmatab[i].base = dma_base;
1334 ds->dmatab[i].count = (dma_count & 0xffff);
1336 if (i >= ATA_DMA_ENTRIES) {
1337 ata_prtdev(atadev, "too many segments in DMA table\n");
1340 dma_base = vtophys(data);
1341 dma_count = imin(count, PAGE_SIZE);
1342 data += imin(count, PAGE_SIZE);
1343 count -= imin(count, PAGE_SIZE);
1345 ds->dmatab[i].base = dma_base;
1346 ds->dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
1351 ata_dmastart(struct ata_device *atadev, caddr_t data, int32_t count, int dir)
1353 struct ata_channel *ch = atadev->channel;
1354 struct ata_dmastate *ds = &atadev->dmastate;
1356 ch->flags |= ATA_DMA_ACTIVE;
1357 ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, vtophys(ds->dmatab));
1358 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
1359 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1360 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) |
1361 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1362 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1363 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
1368 ata_dmadone(struct ata_device *atadev)
1370 struct ata_channel *ch;
1371 struct ata_dmastate *ds;
1374 ch = atadev->channel;
1375 ds = &atadev->dmastate;
1377 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1378 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1379 error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
1380 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1381 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1382 ch->flags &= ~ATA_DMA_ACTIVE;
1384 return error & ATA_BMSTAT_MASK;
1388 ata_dmastatus(struct ata_channel *ch)
1390 return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1394 cyrix_timing(struct ata_device *atadev, int devno, int mode)
1396 u_int32_t reg20 = 0x0000e132;
1397 u_int32_t reg24 = 0x00017771;
1400 case ATA_PIO0: reg20 = 0x0000e132; break;
1401 case ATA_PIO1: reg20 = 0x00018121; break;
1402 case ATA_PIO2: reg20 = 0x00024020; break;
1403 case ATA_PIO3: reg20 = 0x00032010; break;
1404 case ATA_PIO4: reg20 = 0x00040010; break;
1405 case ATA_WDMA2: reg24 = 0x00002020; break;
1406 case ATA_UDMA2: reg24 = 0x00911030; break;
1408 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x20, reg20);
1409 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x24, reg24);
1413 promise_timing(struct ata_device *atadev, int devno, int mode)
1415 u_int32_t timing = 0;
1416 /* XXX: Endianess */
1417 struct promise_timing {
1419 u_int8_t prefetch:1;
1430 u_int8_t reserved:8;
1431 } *t = (struct promise_timing*)&timing;
1433 t->iordy = 1; t->iordyp = 1;
1434 if (mode >= ATA_DMA) {
1435 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
1438 switch (atadev->channel->chiptype) {
1439 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
1442 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
1443 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
1444 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
1445 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
1446 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
1447 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
1448 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1452 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
1453 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
1454 case 0x0d30105a: /* Promise OEM ATA 100 */
1457 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
1458 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
1459 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
1460 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
1461 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
1462 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
1463 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
1464 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1465 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1469 pci_write_config(device_get_parent(atadev->channel->dev),
1470 0x60 + (devno<<2), timing, 4);
1474 hpt_timing(struct ata_device *atadev, int devno, int mode)
1476 device_t parent = device_get_parent(atadev->channel->dev);
1477 u_int32_t chiptype = atadev->channel->chiptype;
1478 int chiprev = pci_get_revid(parent);
1481 if (chiptype == 0x00081103 && chiprev >= 0x07) {
1482 switch (mode) { /* HPT374 */
1483 case ATA_PIO0: timing = 0x0ac1f48a; break;
1484 case ATA_PIO1: timing = 0x0ac1f465; break;
1485 case ATA_PIO2: timing = 0x0a81f454; break;
1486 case ATA_PIO3: timing = 0x0a81f443; break;
1487 case ATA_PIO4: timing = 0x0a81f442; break;
1488 case ATA_WDMA2: timing = 0x22808242; break;
1489 case ATA_UDMA2: timing = 0x120c8242; break;
1490 case ATA_UDMA4: timing = 0x12ac8242; break;
1491 case ATA_UDMA5: timing = 0x12848242; break;
1492 case ATA_UDMA6: timing = 0x12808242; break;
1493 default: timing = 0x0d029d5e;
1496 else if ((chiptype == 0x00041103 && chiprev >= 0x05) ||
1497 (chiptype == 0x00051103 && chiprev >= 0x01)) {
1498 switch (mode) { /* HPT372 */
1499 case ATA_PIO0: timing = 0x0d029d5e; break;
1500 case ATA_PIO1: timing = 0x0d029d26; break;
1501 case ATA_PIO2: timing = 0x0c829ca6; break;
1502 case ATA_PIO3: timing = 0x0c829c84; break;
1503 case ATA_PIO4: timing = 0x0c829c62; break;
1504 case ATA_WDMA2: timing = 0x2c829262; break;
1505 case ATA_UDMA2: timing = 0x1c91dc62; break;
1506 case ATA_UDMA4: timing = 0x1c8ddc62; break;
1507 case ATA_UDMA5: timing = 0x1c6ddc62; break;
1508 case ATA_UDMA6: timing = 0x1c81dc62; break;
1509 default: timing = 0x0d029d5e;
1512 else if (chiptype == 0x00041103 && chiprev >= 0x03) {
1513 switch (mode) { /* HPT370 */
1514 case ATA_PIO0: timing = 0x06914e57; break;
1515 case ATA_PIO1: timing = 0x06914e43; break;
1516 case ATA_PIO2: timing = 0x06514e33; break;
1517 case ATA_PIO3: timing = 0x06514e22; break;
1518 case ATA_PIO4: timing = 0x06514e21; break;
1519 case ATA_WDMA2: timing = 0x26514e21; break;
1520 case ATA_UDMA2: timing = 0x16494e31; break;
1521 case ATA_UDMA4: timing = 0x16454e31; break;
1522 case ATA_UDMA5: timing = 0x16454e31; break;
1523 default: timing = 0x06514e57;
1525 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1527 else { /* HPT36[68] */
1528 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
1529 case 0x85: /* 25Mhz */
1531 case ATA_PIO0: timing = 0x40d08585; break;
1532 case ATA_PIO1: timing = 0x40d08572; break;
1533 case ATA_PIO2: timing = 0x40ca8542; break;
1534 case ATA_PIO3: timing = 0x40ca8532; break;
1535 case ATA_PIO4: timing = 0x40ca8521; break;
1536 case ATA_WDMA2: timing = 0x20ca8521; break;
1537 case ATA_UDMA2: timing = 0x10cf8521; break;
1538 case ATA_UDMA4: timing = 0x10c98521; break;
1539 default: timing = 0x01208585;
1543 case 0xa7: /* 33MHz */
1545 case ATA_PIO0: timing = 0x40d0a7aa; break;
1546 case ATA_PIO1: timing = 0x40d0a7a3; break;
1547 case ATA_PIO2: timing = 0x40d0a753; break;
1548 case ATA_PIO3: timing = 0x40c8a742; break;
1549 case ATA_PIO4: timing = 0x40c8a731; break;
1550 case ATA_WDMA2: timing = 0x20c8a731; break;
1551 case ATA_UDMA2: timing = 0x10caa731; break;
1552 case ATA_UDMA4: timing = 0x10c9a731; break;
1553 default: timing = 0x0120a7a7;
1556 case 0xd9: /* 40Mhz */
1558 case ATA_PIO0: timing = 0x4018d9d9; break;
1559 case ATA_PIO1: timing = 0x4010d9c7; break;
1560 case ATA_PIO2: timing = 0x4010d997; break;
1561 case ATA_PIO3: timing = 0x4010d974; break;
1562 case ATA_PIO4: timing = 0x4008d963; break;
1563 case ATA_WDMA2: timing = 0x2008d943; break;
1564 case ATA_UDMA2: timing = 0x100bd943; break;
1565 case ATA_UDMA4: timing = 0x100fd943; break;
1566 default: timing = 0x0120d9d9;
1570 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1574 hpt_cable80(struct ata_device *atadev)
1576 device_t parent = device_get_parent(atadev->channel->dev);
1577 u_int8_t reg, val, res;
1579 if (atadev->channel->chiptype == 0x00081103 && pci_get_function(parent) == 1) {
1580 reg = atadev->channel->unit ? 0x57 : 0x53;
1581 val = pci_read_config(parent, reg, 1);
1582 pci_write_config(parent, reg, val | 0x80, 1);
1586 val = pci_read_config(parent, reg, 1);
1587 pci_write_config(parent, reg, val & 0xfe, 1);
1589 res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x01 : 0x02);
1590 pci_write_config(parent, reg, val, 1);