1 /* Instruction scheduling pass. Selective scheduler and pipeliner.
2 Copyright (C) 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
27 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "insn-attr.h"
40 #include "tree-pass.h"
41 #include "sched-int.h"
45 #include "langhooks.h"
46 #include "rtlhooks-def.h"
49 #ifdef INSN_SCHEDULING
50 #include "sel-sched-ir.h"
51 #include "sel-sched-dump.h"
52 #include "sel-sched.h"
55 /* Implementation of selective scheduling approach.
56 The below implementation follows the original approach with the following
59 o the scheduler works after register allocation (but can be also tuned
61 o some instructions are not copied or register renamed;
62 o conditional jumps are not moved with code duplication;
63 o several jumps in one parallel group are not supported;
64 o when pipelining outer loops, code motion through inner loops
66 o control and data speculation are supported;
67 o some improvements for better compile time/performance were made.
72 A vinsn, or virtual insn, is an insn with additional data characterizing
73 insn pattern, such as LHS, RHS, register sets used/set/clobbered, etc.
74 Vinsns also act as smart pointers to save memory by reusing them in
75 different expressions. A vinsn is described by vinsn_t type.
77 An expression is a vinsn with additional data characterizing its properties
78 at some point in the control flow graph. The data may be its usefulness,
79 priority, speculative status, whether it was renamed/subsituted, etc.
80 An expression is described by expr_t type.
82 Availability set (av_set) is a set of expressions at a given control flow
83 point. It is represented as av_set_t. The expressions in av sets are kept
84 sorted in the terms of expr_greater_p function. It allows to truncate
85 the set while leaving the best expressions.
87 A fence is a point through which code motion is prohibited. On each step,
88 we gather a parallel group of insns at a fence. It is possible to have
89 multiple fences. A fence is represented via fence_t.
91 A boundary is the border between the fence group and the rest of the code.
92 Currently, we never have more than one boundary per fence, as we finalize
93 the fence group when a jump is scheduled. A boundary is represented
99 The scheduler finds regions to schedule, schedules each one, and finalizes.
100 The regions are formed starting from innermost loops, so that when the inner
101 loop is pipelined, its prologue can be scheduled together with yet unprocessed
102 outer loop. The rest of acyclic regions are found using extend_rgns:
103 the blocks that are not yet allocated to any regions are traversed in top-down
104 order, and a block is added to a region to which all its predecessors belong;
105 otherwise, the block starts its own region.
107 The main scheduling loop (sel_sched_region_2) consists of just
108 scheduling on each fence and updating fences. For each fence,
109 we fill a parallel group of insns (fill_insns) until some insns can be added.
110 First, we compute available exprs (av-set) at the boundary of the current
111 group. Second, we choose the best expression from it. If the stall is
112 required to schedule any of the expressions, we advance the current cycle
113 appropriately. So, the final group does not exactly correspond to a VLIW
114 word. Third, we move the chosen expression to the boundary (move_op)
115 and update the intermediate av sets and liveness sets. We quit fill_insns
116 when either no insns left for scheduling or we have scheduled enough insns
117 so we feel like advancing a scheduling point.
119 Computing available expressions
120 ===============================
122 The computation (compute_av_set) is a bottom-up traversal. At each insn,
123 we're moving the union of its successors' sets through it via
124 moveup_expr_set. The dependent expressions are removed. Local
125 transformations (substitution, speculation) are applied to move more
126 exprs. Then the expr corresponding to the current insn is added.
127 The result is saved on each basic block header.
129 When traversing the CFG, we're moving down for no more than max_ws insns.
130 Also, we do not move down to ineligible successors (is_ineligible_successor),
131 which include moving along a back-edge, moving to already scheduled code,
132 and moving to another fence. The first two restrictions are lifted during
133 pipelining, which allows us to move insns along a back-edge. We always have
134 an acyclic region for scheduling because we forbid motion through fences.
136 Choosing the best expression
137 ============================
139 We sort the final availability set via sel_rank_for_schedule, then we remove
140 expressions which are not yet ready (tick_check_p) or which dest registers
141 cannot be used. For some of them, we choose another register via
142 find_best_reg. To do this, we run find_used_regs to calculate the set of
143 registers which cannot be used. The find_used_regs function performs
144 a traversal of code motion paths for an expr. We consider for renaming
145 only registers which are from the same regclass as the original one and
146 using which does not interfere with any live ranges. Finally, we convert
147 the resulting set to the ready list format and use max_issue and reorder*
148 hooks similarly to the Haifa scheduler.
150 Scheduling the best expression
151 ==============================
153 We run the move_op routine to perform the same type of code motion paths
154 traversal as in find_used_regs. (These are working via the same driver,
155 code_motion_path_driver.) When moving down the CFG, we look for original
156 instruction that gave birth to a chosen expression. We undo
157 the transformations performed on an expression via the history saved in it.
158 When found, we remove the instruction or leave a reg-reg copy/speculation
159 check if needed. On a way up, we insert bookkeeping copies at each join
160 point. If a copy is not needed, it will be removed later during this
161 traversal. We update the saved av sets and liveness sets on the way up, too.
163 Finalizing the schedule
164 =======================
166 When pipelining, we reschedule the blocks from which insns were pipelined
167 to get a tighter schedule. On Itanium, we also perform bundling via
168 the same routine from ia64.c.
170 Dependence analysis changes
171 ===========================
173 We augmented the sched-deps.c with hooks that get called when a particular
174 dependence is found in a particular part of an insn. Using these hooks, we
175 can do several actions such as: determine whether an insn can be moved through
176 another (has_dependence_p, moveup_expr); find out whether an insn can be
177 scheduled on the current cycle (tick_check_p); find out registers that
178 are set/used/clobbered by an insn and find out all the strange stuff that
179 restrict its movement, like SCHED_GROUP_P or CANT_MOVE (done in
180 init_global_and_expr_for_insn).
182 Initialization changes
183 ======================
185 There are parts of haifa-sched.c, sched-deps.c, and sched-rgn.c that are
186 reused in all of the schedulers. We have split up the initialization of data
187 of such parts into different functions prefixed with scheduler type and
188 postfixed with the type of data initialized: {,sel_,haifa_}sched_{init,finish},
189 sched_rgn_init/finish, sched_deps_init/finish, sched_init_{luids/bbs}, etc.
190 The same splitting is done with current_sched_info structure:
191 dependence-related parts are in sched_deps_info, common part is in
192 common_sched_info, and haifa/sel/etc part is in current_sched_info.
197 As we now have multiple-point scheduling, this would not work with backends
198 which save some of the scheduler state to use it in the target hooks.
199 For this purpose, we introduce a concept of target contexts, which
200 encapsulate such information. The backend should implement simple routines
201 of allocating/freeing/setting such a context. The scheduler calls these
202 as target hooks and handles the target context as an opaque pointer (similar
203 to the DFA state type, state_t).
208 As the correct data dependence graph is not supported during scheduling (which
209 is to be changed in mid-term), we cache as much of the dependence analysis
210 results as possible to avoid reanalyzing. This includes: bitmap caches on
211 each insn in stream of the region saying yes/no for a query with a pair of
212 UIDs; hashtables with the previously done transformations on each insn in
213 stream; a vector keeping a history of transformations on each expr.
215 Also, we try to minimize the dependence context used on each fence to check
216 whether the given expression is ready for scheduling by removing from it
217 insns that are definitely completed the execution. The results of
218 tick_check_p checks are also cached in a vector on each fence.
220 We keep a valid liveness set on each insn in a region to avoid the high
221 cost of recomputation on large basic blocks.
223 Finally, we try to minimize the number of needed updates to the availability
224 sets. The updates happen in two cases: when fill_insns terminates,
225 we advance all fences and increase the stage number to show that the region
226 has changed and the sets are to be recomputed; and when the next iteration
227 of a loop in fill_insns happens (but this one reuses the saved av sets
228 on bb headers.) Thus, we try to break the fill_insns loop only when
229 "significant" number of insns from the current scheduling window was
230 scheduled. This should be made a target param.
233 TODO: correctly support the data dependence graph at all stages and get rid
234 of all caches. This should speed up the scheduler.
235 TODO: implement moving cond jumps with bookkeeping copies on both targets.
236 TODO: tune the scheduler before RA so it does not create too much pseudos.
240 S.-M. Moon and K. Ebcioglu. Parallelizing nonnumerical code with
241 selective scheduling and software pipelining.
242 ACM TOPLAS, Vol 19, No. 6, pages 853--898, Nov. 1997.
244 Andrey Belevantsev, Maxim Kuvyrkov, Vladimir Makarov, Dmitry Melnik,
245 and Dmitry Zhurikhin. An interblock VLIW-targeted instruction scheduler
246 for GCC. In Proceedings of GCC Developers' Summit 2006.
248 Arutyun Avetisyan, Andrey Belevantsev, and Dmitry Melnik. GCC Instruction
249 Scheduler and Software Pipeliner on the Itanium Platform. EPIC-7 Workshop.
250 http://rogue.colorado.edu/EPIC7/.
254 /* True when pipelining is enabled. */
257 /* True if bookkeeping is enabled. */
260 /* Maximum number of insns that are eligible for renaming. */
261 int max_insns_to_rename;
264 /* Definitions of local types and macros. */
266 /* Represents possible outcomes of moving an expression through an insn. */
267 enum MOVEUP_EXPR_CODE
269 /* The expression is not changed. */
272 /* Not changed, but requires a new destination register. */
275 /* Cannot be moved. */
278 /* Changed (substituted or speculated). */
282 /* The container to be passed into rtx search & replace functions. */
283 struct rtx_search_arg
285 /* What we are searching for. */
288 /* The occurence counter. */
292 typedef struct rtx_search_arg *rtx_search_arg_p;
294 /* This struct contains precomputed hard reg sets that are needed when
295 computing registers available for renaming. */
296 struct hard_regs_data
298 /* For every mode, this stores registers available for use with
300 HARD_REG_SET regs_for_mode[NUM_MACHINE_MODES];
302 /* True when regs_for_mode[mode] is initialized. */
303 bool regs_for_mode_ok[NUM_MACHINE_MODES];
305 /* For every register, it has regs that are ok to rename into it.
306 The register in question is always set. If not, this means
307 that the whole set is not computed yet. */
308 HARD_REG_SET regs_for_rename[FIRST_PSEUDO_REGISTER];
310 /* For every mode, this stores registers not available due to
312 HARD_REG_SET regs_for_call_clobbered[NUM_MACHINE_MODES];
314 /* All registers that are used or call used. */
315 HARD_REG_SET regs_ever_used;
318 /* Stack registers. */
319 HARD_REG_SET stack_regs;
323 /* Holds the results of computation of available for renaming and
324 unavailable hard registers. */
327 /* These are unavailable due to calls crossing, globalness, etc. */
328 HARD_REG_SET unavailable_hard_regs;
330 /* These are *available* for renaming. */
331 HARD_REG_SET available_for_renaming;
333 /* Whether this code motion path crosses a call. */
337 /* A global structure that contains the needed information about harg
339 static struct hard_regs_data sel_hrd;
342 /* This structure holds local data used in code_motion_path_driver hooks on
343 the same or adjacent levels of recursion. Here we keep those parameters
344 that are not used in code_motion_path_driver routine itself, but only in
345 its hooks. Moreover, all parameters that can be modified in hooks are
346 in this structure, so all other parameters passed explicitly to hooks are
348 struct cmpd_local_params
350 /* Local params used in move_op_* functions. */
352 /* Edges for bookkeeping generation. */
355 /* C_EXPR merged from all successors and locally allocated temporary C_EXPR. */
356 expr_t c_expr_merged, c_expr_local;
358 /* Local params used in fur_* functions. */
359 /* Copy of the ORIGINAL_INSN list, stores the original insns already
360 found before entering the current level of code_motion_path_driver. */
361 def_list_t old_original_insns;
363 /* Local params used in move_op_* functions. */
364 /* True when we have removed last insn in the block which was
365 also a boundary. Do not update anything or create bookkeeping copies. */
366 BOOL_BITFIELD removed_last_insn : 1;
369 /* Stores the static parameters for move_op_* calls. */
370 struct moveop_static_params
372 /* Destination register. */
375 /* Current C_EXPR. */
378 /* An UID of expr_vliw which is to be moved up. If we find other exprs,
379 they are to be removed. */
382 #ifdef ENABLE_CHECKING
383 /* This is initialized to the insn on which the driver stopped its traversal. */
387 /* True if we scheduled an insn with different register. */
391 /* Stores the static parameters for fur_* calls. */
392 struct fur_static_params
394 /* Set of registers unavailable on the code motion path. */
397 /* Pointer to the list of original insns definitions. */
398 def_list_t *original_insns;
400 /* True if a code motion path contains a CALL insn. */
404 typedef struct fur_static_params *fur_static_params_p;
405 typedef struct cmpd_local_params *cmpd_local_params_p;
406 typedef struct moveop_static_params *moveop_static_params_p;
408 /* Set of hooks and parameters that determine behaviour specific to
409 move_op or find_used_regs functions. */
410 struct code_motion_path_driver_info_def
412 /* Called on enter to the basic block. */
413 int (*on_enter) (insn_t, cmpd_local_params_p, void *, bool);
415 /* Called when original expr is found. */
416 void (*orig_expr_found) (insn_t, expr_t, cmpd_local_params_p, void *);
418 /* Called while descending current basic block if current insn is not
419 the original EXPR we're searching for. */
420 bool (*orig_expr_not_found) (insn_t, av_set_t, void *);
422 /* Function to merge C_EXPRes from different successors. */
423 void (*merge_succs) (insn_t, insn_t, int, cmpd_local_params_p, void *);
425 /* Function to finalize merge from different successors and possibly
426 deallocate temporary data structures used for merging. */
427 void (*after_merge_succs) (cmpd_local_params_p, void *);
429 /* Called on the backward stage of recursion to do moveup_expr.
430 Used only with move_op_*. */
431 void (*ascend) (insn_t, void *);
433 /* Called on the ascending pass, before returning from the current basic
434 block or from the whole traversal. */
435 void (*at_first_insn) (insn_t, cmpd_local_params_p, void *);
437 /* When processing successors in move_op we need only descend into
438 SUCCS_NORMAL successors, while in find_used_regs we need SUCCS_ALL. */
441 /* The routine name to print in dumps ("move_op" of "find_used_regs"). */
442 const char *routine_name;
445 /* Global pointer to current hooks, either points to MOVE_OP_HOOKS or
447 struct code_motion_path_driver_info_def *code_motion_path_driver_info;
449 /* Set of hooks for performing move_op and find_used_regs routines with
450 code_motion_path_driver. */
451 struct code_motion_path_driver_info_def move_op_hooks, fur_hooks;
453 /* True if/when we want to emulate Haifa scheduler in the common code.
454 This is used in sched_rgn_local_init and in various places in
456 int sched_emulate_haifa_p;
458 /* GLOBAL_LEVEL is used to discard information stored in basic block headers
459 av_sets. Av_set of bb header is valid if its (bb header's) level is equal
460 to GLOBAL_LEVEL. And invalid if lesser. This is primarily used to advance
461 scheduling window. */
464 /* Current fences. */
467 /* True when separable insns should be scheduled as RHSes. */
468 static bool enable_schedule_as_rhs_p;
470 /* Used in verify_target_availability to assert that target reg is reported
471 unavailabile by both TARGET_UNAVAILABLE and find_used_regs only if
472 we haven't scheduled anything on the previous fence.
473 if scheduled_something_on_previous_fence is true, TARGET_UNAVAILABLE can
474 have more conservative value than the one returned by the
475 find_used_regs, thus we shouldn't assert that these values are equal. */
476 static bool scheduled_something_on_previous_fence;
478 /* All newly emitted insns will have their uids greater than this value. */
479 static int first_emitted_uid;
481 /* Set of basic blocks that are forced to start new ebbs. This is a subset
482 of all the ebb heads. */
483 static bitmap_head _forced_ebb_heads;
484 bitmap_head *forced_ebb_heads = &_forced_ebb_heads;
486 /* Blocks that need to be rescheduled after pipelining. */
487 bitmap blocks_to_reschedule = NULL;
489 /* True when the first lv set should be ignored when updating liveness. */
490 static bool ignore_first = false;
492 /* Number of insns max_issue has initialized data structures for. */
493 static int max_issue_size = 0;
495 /* Whether we can issue more instructions. */
496 static int can_issue_more;
498 /* Maximum software lookahead window size, reduced when rescheduling after
502 /* Number of insns scheduled in current region. */
503 static int num_insns_scheduled;
505 /* A vector of expressions is used to be able to sort them. */
507 DEF_VEC_ALLOC_P(expr_t,heap);
508 static VEC(expr_t, heap) *vec_av_set = NULL;
510 /* A vector of vinsns is used to hold temporary lists of vinsns. */
512 DEF_VEC_ALLOC_P(vinsn_t,heap);
513 typedef VEC(vinsn_t, heap) *vinsn_vec_t;
515 /* This vector has the exprs which may still present in av_sets, but actually
516 can't be moved up due to bookkeeping created during code motion to another
517 fence. See comment near the call to update_and_record_unavailable_insns
518 for the detailed explanations. */
519 static vinsn_vec_t vec_bookkeeping_blocked_vinsns = NULL;
521 /* This vector has vinsns which are scheduled with renaming on the first fence
522 and then seen on the second. For expressions with such vinsns, target
523 availability information may be wrong. */
524 static vinsn_vec_t vec_target_unavailable_vinsns = NULL;
526 /* Vector to store temporary nops inserted in move_op to prevent removal
529 DEF_VEC_ALLOC_P(insn_t,heap);
530 static VEC(insn_t, heap) *vec_temp_moveop_nops = NULL;
532 /* These bitmaps record original instructions scheduled on the current
533 iteration and bookkeeping copies created by them. */
534 static bitmap current_originators = NULL;
535 static bitmap current_copies = NULL;
537 /* This bitmap marks the blocks visited by code_motion_path_driver so we don't
538 visit them afterwards. */
539 static bitmap code_motion_visited_blocks = NULL;
541 /* Variables to accumulate different statistics. */
543 /* The number of bookkeeping copies created. */
544 static int stat_bookkeeping_copies;
546 /* The number of insns that required bookkeeiping for their scheduling. */
547 static int stat_insns_needed_bookkeeping;
549 /* The number of insns that got renamed. */
550 static int stat_renamed_scheduled;
552 /* The number of substitutions made during scheduling. */
553 static int stat_substitutions_total;
556 /* Forward declarations of static functions. */
557 static bool rtx_ok_for_substitution_p (rtx, rtx);
558 static int sel_rank_for_schedule (const void *, const void *);
559 static av_set_t find_sequential_best_exprs (bnd_t, expr_t, bool);
561 static rtx get_dest_from_orig_ops (av_set_t);
562 static basic_block generate_bookkeeping_insn (expr_t, edge, edge);
563 static bool find_used_regs (insn_t, av_set_t, regset, struct reg_rename *,
565 static bool move_op (insn_t, av_set_t, expr_t, rtx, expr_t, bool*);
566 static int code_motion_path_driver (insn_t, av_set_t, ilist_t,
567 cmpd_local_params_p, void *);
568 static void sel_sched_region_1 (void);
569 static void sel_sched_region_2 (int);
570 static av_set_t compute_av_set_inside_bb (insn_t, ilist_t, int, bool);
572 static void debug_state (state_t);
575 /* Functions that work with fences. */
577 /* Advance one cycle on FENCE. */
579 advance_one_cycle (fence_t fence)
585 advance_state (FENCE_STATE (fence));
586 cycle = ++FENCE_CYCLE (fence);
587 FENCE_ISSUED_INSNS (fence) = 0;
588 FENCE_STARTS_CYCLE_P (fence) = 1;
589 can_issue_more = issue_rate;
590 FENCE_ISSUE_MORE (fence) = can_issue_more;
592 for (i = 0; VEC_iterate (rtx, FENCE_EXECUTING_INSNS (fence), i, insn); )
594 if (INSN_READY_CYCLE (insn) < cycle)
596 remove_from_deps (FENCE_DC (fence), insn);
597 VEC_unordered_remove (rtx, FENCE_EXECUTING_INSNS (fence), i);
602 if (sched_verbose >= 2)
604 sel_print ("Finished a cycle. Current cycle = %d\n", FENCE_CYCLE (fence));
605 debug_state (FENCE_STATE (fence));
609 /* Returns true when SUCC in a fallthru bb of INSN, possibly
610 skipping empty basic blocks. */
612 in_fallthru_bb_p (rtx insn, rtx succ)
614 basic_block bb = BLOCK_FOR_INSN (insn);
616 if (bb == BLOCK_FOR_INSN (succ))
619 if (find_fallthru_edge (bb))
620 bb = find_fallthru_edge (bb)->dest;
624 while (sel_bb_empty_p (bb))
627 return bb == BLOCK_FOR_INSN (succ);
630 /* Construct successor fences from OLD_FENCEs and put them in NEW_FENCES.
631 When a successor will continue a ebb, transfer all parameters of a fence
632 to the new fence. ORIG_MAX_SEQNO is the maximal seqno before this round
633 of scheduling helping to distinguish between the old and the new code. */
635 extract_new_fences_from (flist_t old_fences, flist_tail_t new_fences,
638 bool was_here_p = false;
639 insn_t insn = NULL_RTX;
643 fence_t fence = FLIST_FENCE (old_fences);
646 /* Get the only element of FENCE_BNDS (fence). */
647 FOR_EACH_INSN (insn, ii, FENCE_BNDS (fence))
649 gcc_assert (!was_here_p);
652 gcc_assert (was_here_p && insn != NULL_RTX);
654 /* When in the "middle" of the block, just move this fence
656 bb = BLOCK_FOR_INSN (insn);
657 if (! sel_bb_end_p (insn)
658 || (single_succ_p (bb)
659 && single_pred_p (single_succ (bb))))
663 succ = (sel_bb_end_p (insn)
664 ? sel_bb_head (single_succ (bb))
667 if (INSN_SEQNO (succ) > 0
668 && INSN_SEQNO (succ) <= orig_max_seqno
669 && INSN_SCHED_TIMES (succ) <= 0)
671 FENCE_INSN (fence) = succ;
672 move_fence_to_fences (old_fences, new_fences);
674 if (sched_verbose >= 1)
675 sel_print ("Fence %d continues as %d[%d] (state continue)\n",
676 INSN_UID (insn), INSN_UID (succ), BLOCK_NUM (succ));
681 /* Otherwise copy fence's structures to (possibly) multiple successors. */
682 FOR_EACH_SUCC_1 (succ, si, insn, SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
684 int seqno = INSN_SEQNO (succ);
686 if (0 < seqno && seqno <= orig_max_seqno
687 && (pipelining_p || INSN_SCHED_TIMES (succ) <= 0))
689 bool b = (in_same_ebb_p (insn, succ)
690 || in_fallthru_bb_p (insn, succ));
692 if (sched_verbose >= 1)
693 sel_print ("Fence %d continues as %d[%d] (state %s)\n",
694 INSN_UID (insn), INSN_UID (succ),
695 BLOCK_NUM (succ), b ? "continue" : "reset");
698 add_dirty_fence_to_fences (new_fences, succ, fence);
701 /* Mark block of the SUCC as head of the new ebb. */
702 bitmap_set_bit (forced_ebb_heads, BLOCK_NUM (succ));
703 add_clean_fence_to_fences (new_fences, succ, fence);
710 /* Functions to support substitution. */
712 /* Returns whether INSN with dependence status DS is eligible for
713 substitution, i.e. it's a copy operation x := y, and RHS that is
714 moved up through this insn should be substituted. */
716 can_substitute_through_p (insn_t insn, ds_t ds)
718 /* We can substitute only true dependencies. */
719 if ((ds & DEP_OUTPUT)
722 || ! INSN_LHS (insn))
725 /* Now we just need to make sure the INSN_RHS consists of only one
727 if (REG_P (INSN_LHS (insn))
728 && REG_P (INSN_RHS (insn)))
733 /* Substitute all occurences of INSN's destination in EXPR' vinsn with INSN's
734 source (if INSN is eligible for substitution). Returns TRUE if
735 substitution was actually performed, FALSE otherwise. Substitution might
736 be not performed because it's either EXPR' vinsn doesn't contain INSN's
737 destination or the resulting insn is invalid for the target machine.
738 When UNDO is true, perform unsubstitution instead (the difference is in
739 the part of rtx on which validate_replace_rtx is called). */
741 substitute_reg_in_expr (expr_t expr, insn_t insn, bool undo)
745 vinsn_t *vi = &EXPR_VINSN (expr);
746 bool has_rhs = VINSN_RHS (*vi) != NULL;
749 /* Do not try to replace in SET_DEST. Although we'll choose new
750 register for the RHS, we don't want to change RHS' original reg.
751 If the insn is not SET, we may still be able to substitute something
752 in it, and if we're here (don't have deps), it doesn't write INSN's
756 : &PATTERN (VINSN_INSN_RTX (*vi)));
757 old = undo ? INSN_RHS (insn) : INSN_LHS (insn);
759 /* Substitute if INSN has a form of x:=y and LHS(INSN) occurs in *VI. */
760 if (rtx_ok_for_substitution_p (old, *where))
765 /* We should copy these rtxes before substitution. */
766 new_rtx = copy_rtx (undo ? INSN_LHS (insn) : INSN_RHS (insn));
767 new_insn = create_copy_of_insn_rtx (VINSN_INSN_RTX (*vi));
769 /* Where we'll replace.
770 WHERE_REPLACE should point inside NEW_INSN, so INSN_RHS couldn't be
771 used instead of SET_SRC. */
772 where_replace = (has_rhs
773 ? &SET_SRC (PATTERN (new_insn))
774 : &PATTERN (new_insn));
777 = validate_replace_rtx_part_nosimplify (old, new_rtx, where_replace,
780 /* ??? Actually, constrain_operands result depends upon choice of
781 destination register. E.g. if we allow single register to be an rhs,
782 and if we try to move dx=ax(as rhs) through ax=dx, we'll result
783 in invalid insn dx=dx, so we'll loose this rhs here.
784 Just can't come up with significant testcase for this, so just
785 leaving it for now. */
788 change_vinsn_in_expr (expr,
789 create_vinsn_from_insn_rtx (new_insn, false));
791 /* Do not allow clobbering the address register of speculative
793 if ((EXPR_SPEC_DONE_DS (expr) & SPECULATIVE)
794 && bitmap_bit_p (VINSN_REG_USES (EXPR_VINSN (expr)),
795 expr_dest_regno (expr)))
796 EXPR_TARGET_AVAILABLE (expr) = false;
807 /* Helper function for count_occurences_equiv. */
809 count_occurrences_1 (rtx *cur_rtx, void *arg)
811 rtx_search_arg_p p = (rtx_search_arg_p) arg;
813 /* The last param FOR_GCSE is true, because otherwise it performs excessive
817 for the last insn it presumes r33 equivalent to r8, so it changes it to
818 r33. Actually, there's no change, but it spoils debugging. */
819 if (exp_equiv_p (*cur_rtx, p->x, 0, true))
821 /* Bail out if we occupy more than one register. */
823 && HARD_REGISTER_P (*cur_rtx)
824 && hard_regno_nregs[REGNO(*cur_rtx)][GET_MODE (*cur_rtx)] > 1)
832 /* Do not traverse subexprs. */
836 if (GET_CODE (*cur_rtx) == SUBREG
838 && (!REG_P (SUBREG_REG (*cur_rtx))
839 || REGNO (SUBREG_REG (*cur_rtx)) == REGNO (p->x)))
841 /* ??? Do not support substituting regs inside subregs. In that case,
842 simplify_subreg will be called by validate_replace_rtx, and
843 unsubstitution will fail later. */
848 /* Continue search. */
852 /* Return the number of places WHAT appears within WHERE.
853 Bail out when we found a reference occupying several hard registers. */
855 count_occurrences_equiv (rtx what, rtx where)
857 struct rtx_search_arg arg;
862 for_each_rtx (&where, &count_occurrences_1, (void *) &arg);
867 /* Returns TRUE if WHAT is found in WHERE rtx tree. */
869 rtx_ok_for_substitution_p (rtx what, rtx where)
871 return (count_occurrences_equiv (what, where) > 0);
875 /* Functions to support register renaming. */
877 /* Substitute VI's set source with REGNO. Returns newly created pattern
878 that has REGNO as its source. */
880 create_insn_rtx_with_rhs (vinsn_t vi, rtx rhs_rtx)
886 lhs_rtx = copy_rtx (VINSN_LHS (vi));
888 pattern = gen_rtx_SET (VOIDmode, lhs_rtx, rhs_rtx);
889 insn_rtx = create_insn_rtx_from_pattern (pattern, NULL_RTX);
894 /* Returns whether INSN's src can be replaced with register number
895 NEW_SRC_REG. E.g. the following insn is valid for i386:
897 (insn:HI 2205 6585 2207 727 ../../gcc/libiberty/regex.c:3337
898 (set (mem/s:QI (plus:SI (plus:SI (reg/f:SI 7 sp)
899 (reg:SI 0 ax [orig:770 c1 ] [770]))
900 (const_int 288 [0x120])) [0 str S1 A8])
901 (const_int 0 [0x0])) 43 {*movqi_1} (nil)
904 But if we change (const_int 0 [0x0]) to (reg:QI 4 si), it will be invalid
905 because of operand constraints:
907 (define_insn "*movqi_1"
908 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
909 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn")
912 So do constrain_operands here, before choosing NEW_SRC_REG as best
916 replace_src_with_reg_ok_p (insn_t insn, rtx new_src_reg)
918 vinsn_t vi = INSN_VINSN (insn);
919 enum machine_mode mode;
923 gcc_assert (VINSN_SEPARABLE_P (vi));
925 get_dest_and_mode (insn, &dst_loc, &mode);
926 gcc_assert (mode == GET_MODE (new_src_reg));
928 if (REG_P (dst_loc) && REGNO (new_src_reg) == REGNO (dst_loc))
931 /* See whether SET_SRC can be replaced with this register. */
932 validate_change (insn, &SET_SRC (PATTERN (insn)), new_src_reg, 1);
933 res = verify_changes (0);
939 /* Returns whether INSN still be valid after replacing it's DEST with
942 replace_dest_with_reg_ok_p (insn_t insn, rtx new_reg)
944 vinsn_t vi = INSN_VINSN (insn);
947 /* We should deal here only with separable insns. */
948 gcc_assert (VINSN_SEPARABLE_P (vi));
949 gcc_assert (GET_MODE (VINSN_LHS (vi)) == GET_MODE (new_reg));
951 /* See whether SET_DEST can be replaced with this register. */
952 validate_change (insn, &SET_DEST (PATTERN (insn)), new_reg, 1);
953 res = verify_changes (0);
959 /* Create a pattern with rhs of VI and lhs of LHS_RTX. */
961 create_insn_rtx_with_lhs (vinsn_t vi, rtx lhs_rtx)
967 rhs_rtx = copy_rtx (VINSN_RHS (vi));
969 pattern = gen_rtx_SET (VOIDmode, lhs_rtx, rhs_rtx);
970 insn_rtx = create_insn_rtx_from_pattern (pattern, NULL_RTX);
975 /* Substitute lhs in the given expression EXPR for the register with number
976 NEW_REGNO. SET_DEST may be arbitrary rtx, not only register. */
978 replace_dest_with_reg_in_expr (expr_t expr, rtx new_reg)
983 insn_rtx = create_insn_rtx_with_lhs (EXPR_VINSN (expr), new_reg);
984 vinsn = create_vinsn_from_insn_rtx (insn_rtx, false);
986 change_vinsn_in_expr (expr, vinsn);
987 EXPR_WAS_RENAMED (expr) = 1;
988 EXPR_TARGET_AVAILABLE (expr) = 1;
991 /* Returns whether VI writes either one of the USED_REGS registers or,
992 if a register is a hard one, one of the UNAVAILABLE_HARD_REGS registers. */
994 vinsn_writes_one_of_regs_p (vinsn_t vi, regset used_regs,
995 HARD_REG_SET unavailable_hard_regs)
998 reg_set_iterator rsi;
1000 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_SETS (vi), 0, regno, rsi)
1002 if (REGNO_REG_SET_P (used_regs, regno))
1004 if (HARD_REGISTER_NUM_P (regno)
1005 && TEST_HARD_REG_BIT (unavailable_hard_regs, regno))
1009 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_CLOBBERS (vi), 0, regno, rsi)
1011 if (REGNO_REG_SET_P (used_regs, regno))
1013 if (HARD_REGISTER_NUM_P (regno)
1014 && TEST_HARD_REG_BIT (unavailable_hard_regs, regno))
1021 /* Returns register class of the output register in INSN.
1022 Returns NO_REGS for call insns because some targets have constraints on
1023 destination register of a call insn.
1025 Code adopted from regrename.c::build_def_use. */
1026 static enum reg_class
1027 get_reg_class (rtx insn)
1031 extract_insn (insn);
1032 if (! constrain_operands (1))
1033 fatal_insn_not_found (insn);
1034 preprocess_constraints ();
1035 alt = which_alternative;
1036 n_ops = recog_data.n_operands;
1038 for (i = 0; i < n_ops; ++i)
1040 int matches = recog_op_alt[i][alt].matches;
1042 recog_op_alt[i][alt].cl = recog_op_alt[matches][alt].cl;
1045 if (asm_noperands (PATTERN (insn)) > 0)
1047 for (i = 0; i < n_ops; i++)
1048 if (recog_data.operand_type[i] == OP_OUT)
1050 rtx *loc = recog_data.operand_loc[i];
1052 enum reg_class cl = recog_op_alt[i][alt].cl;
1055 && REGNO (op) == ORIGINAL_REGNO (op))
1061 else if (!CALL_P (insn))
1063 for (i = 0; i < n_ops + recog_data.n_dups; i++)
1065 int opn = i < n_ops ? i : recog_data.dup_num[i - n_ops];
1066 enum reg_class cl = recog_op_alt[opn][alt].cl;
1068 if (recog_data.operand_type[opn] == OP_OUT ||
1069 recog_data.operand_type[opn] == OP_INOUT)
1075 (insn (set (reg:CCZ 17 flags) (compare:CCZ ...)))
1076 may result in returning NO_REGS, cause flags is written implicitly through
1077 CMP insn, which has no OP_OUT | OP_INOUT operands. */
1081 #ifdef HARD_REGNO_RENAME_OK
1082 /* Calculate HARD_REGNO_RENAME_OK data for REGNO. */
1084 init_hard_regno_rename (int regno)
1088 SET_HARD_REG_BIT (sel_hrd.regs_for_rename[regno], regno);
1090 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1092 /* We are not interested in renaming in other regs. */
1093 if (!TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg))
1096 if (HARD_REGNO_RENAME_OK (regno, cur_reg))
1097 SET_HARD_REG_BIT (sel_hrd.regs_for_rename[regno], cur_reg);
1102 /* A wrapper around HARD_REGNO_RENAME_OK that will look into the hard regs
1105 sel_hard_regno_rename_ok (int from ATTRIBUTE_UNUSED, int to ATTRIBUTE_UNUSED)
1107 #ifdef HARD_REGNO_RENAME_OK
1108 /* Check whether this is all calculated. */
1109 if (TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], from))
1110 return TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], to);
1112 init_hard_regno_rename (from);
1114 return TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], to);
1120 /* Calculate set of registers that are capable of holding MODE. */
1122 init_regs_for_mode (enum machine_mode mode)
1126 CLEAR_HARD_REG_SET (sel_hrd.regs_for_mode[mode]);
1127 CLEAR_HARD_REG_SET (sel_hrd.regs_for_call_clobbered[mode]);
1129 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1131 int nregs = hard_regno_nregs[cur_reg][mode];
1134 for (i = nregs - 1; i >= 0; --i)
1135 if (fixed_regs[cur_reg + i]
1136 || global_regs[cur_reg + i]
1137 /* Can't use regs which aren't saved by
1139 || !TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg + i)
1140 #ifdef LEAF_REGISTERS
1141 /* We can't use a non-leaf register if we're in a
1143 || (current_function_is_leaf
1144 && !LEAF_REGISTERS[cur_reg + i])
1152 /* See whether it accepts all modes that occur in
1154 if (! HARD_REGNO_MODE_OK (cur_reg, mode))
1157 if (HARD_REGNO_CALL_PART_CLOBBERED (cur_reg, mode))
1158 SET_HARD_REG_BIT (sel_hrd.regs_for_call_clobbered[mode],
1161 /* If the CUR_REG passed all the checks above,
1163 SET_HARD_REG_BIT (sel_hrd.regs_for_mode[mode], cur_reg);
1166 sel_hrd.regs_for_mode_ok[mode] = true;
1169 /* Init all register sets gathered in HRD. */
1171 init_hard_regs_data (void)
1174 enum machine_mode cur_mode = 0;
1176 CLEAR_HARD_REG_SET (sel_hrd.regs_ever_used);
1177 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1178 if (df_regs_ever_live_p (cur_reg) || call_used_regs[cur_reg])
1179 SET_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg);
1181 /* Initialize registers that are valid based on mode when this is
1183 for (cur_mode = 0; cur_mode < NUM_MACHINE_MODES; cur_mode++)
1184 sel_hrd.regs_for_mode_ok[cur_mode] = false;
1186 /* Mark that all HARD_REGNO_RENAME_OK is not calculated. */
1187 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1188 CLEAR_HARD_REG_SET (sel_hrd.regs_for_rename[cur_reg]);
1191 CLEAR_HARD_REG_SET (sel_hrd.stack_regs);
1193 for (cur_reg = FIRST_STACK_REG; cur_reg <= LAST_STACK_REG; cur_reg++)
1194 SET_HARD_REG_BIT (sel_hrd.stack_regs, cur_reg);
1198 /* Mark hardware regs in REG_RENAME_P that are not suitable
1199 for renaming rhs in INSN due to hardware restrictions (register class,
1200 modes compatibility etc). This doesn't affect original insn's dest reg,
1201 if it isn't in USED_REGS. DEF is a definition insn of rhs for which the
1202 destination register is sought. LHS (DEF->ORIG_INSN) may be REG or MEM.
1203 Registers that are in used_regs are always marked in
1204 unavailable_hard_regs as well. */
1207 mark_unavailable_hard_regs (def_t def, struct reg_rename *reg_rename_p,
1208 regset used_regs ATTRIBUTE_UNUSED)
1210 enum machine_mode mode;
1211 enum reg_class cl = NO_REGS;
1213 unsigned cur_reg, regno;
1214 hard_reg_set_iterator hrsi;
1216 gcc_assert (GET_CODE (PATTERN (def->orig_insn)) == SET);
1217 gcc_assert (reg_rename_p);
1219 orig_dest = SET_DEST (PATTERN (def->orig_insn));
1221 /* We have decided not to rename 'mem = something;' insns, as 'something'
1222 is usually a register. */
1223 if (!REG_P (orig_dest))
1226 regno = REGNO (orig_dest);
1228 /* If before reload, don't try to work with pseudos. */
1229 if (!reload_completed && !HARD_REGISTER_NUM_P (regno))
1232 if (reload_completed)
1233 cl = get_reg_class (def->orig_insn);
1235 /* Stop if the original register is one of the fixed_regs, global_regs or
1236 frame pointer, or we could not discover its class. */
1237 if (fixed_regs[regno]
1238 || global_regs[regno]
1239 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1240 || (frame_pointer_needed && regno == HARD_FRAME_POINTER_REGNUM)
1242 || (frame_pointer_needed && regno == FRAME_POINTER_REGNUM)
1244 || (reload_completed && cl == NO_REGS))
1246 SET_HARD_REG_SET (reg_rename_p->unavailable_hard_regs);
1248 /* Give a chance for original register, if it isn't in used_regs. */
1249 if (!def->crosses_call)
1250 CLEAR_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs, regno);
1255 /* If something allocated on stack in this function, mark frame pointer
1256 register unavailable, considering also modes.
1257 FIXME: it is enough to do this once per all original defs. */
1258 if (frame_pointer_needed)
1262 for (i = hard_regno_nregs[FRAME_POINTER_REGNUM][Pmode]; i--;)
1263 SET_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs,
1264 FRAME_POINTER_REGNUM + i);
1266 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1267 for (i = hard_regno_nregs[HARD_FRAME_POINTER_REGNUM][Pmode]; i--;)
1268 SET_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs,
1269 HARD_FRAME_POINTER_REGNUM + i);
1274 /* For the stack registers the presence of FIRST_STACK_REG in USED_REGS
1275 is equivalent to as if all stack regs were in this set.
1276 I.e. no stack register can be renamed, and even if it's an original
1277 register here we make sure it won't be lifted over it's previous def
1278 (it's previous def will appear as if it's a FIRST_STACK_REG def.
1279 The HARD_REGNO_RENAME_OK covers other cases in condition below. */
1280 if (IN_RANGE (REGNO (orig_dest), FIRST_STACK_REG, LAST_STACK_REG)
1281 && REGNO_REG_SET_P (used_regs, FIRST_STACK_REG))
1282 IOR_HARD_REG_SET (reg_rename_p->unavailable_hard_regs,
1283 sel_hrd.stack_regs);
1286 /* If there's a call on this path, make regs from call_used_reg_set
1288 if (def->crosses_call)
1289 IOR_HARD_REG_SET (reg_rename_p->unavailable_hard_regs,
1292 /* Stop here before reload: we need FRAME_REGS, STACK_REGS, and crosses_call,
1293 but not register classes. */
1294 if (!reload_completed)
1297 /* Leave regs as 'available' only from the current
1299 COPY_HARD_REG_SET (reg_rename_p->available_for_renaming,
1300 reg_class_contents[cl]);
1302 mode = GET_MODE (orig_dest);
1304 /* Leave only registers available for this mode. */
1305 if (!sel_hrd.regs_for_mode_ok[mode])
1306 init_regs_for_mode (mode);
1307 AND_HARD_REG_SET (reg_rename_p->available_for_renaming,
1308 sel_hrd.regs_for_mode[mode]);
1310 /* Exclude registers that are partially call clobbered. */
1311 if (def->crosses_call
1312 && ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))
1313 AND_COMPL_HARD_REG_SET (reg_rename_p->available_for_renaming,
1314 sel_hrd.regs_for_call_clobbered[mode]);
1316 /* Leave only those that are ok to rename. */
1317 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p->available_for_renaming,
1323 nregs = hard_regno_nregs[cur_reg][mode];
1324 gcc_assert (nregs > 0);
1326 for (i = nregs - 1; i >= 0; --i)
1327 if (! sel_hard_regno_rename_ok (regno + i, cur_reg + i))
1331 CLEAR_HARD_REG_BIT (reg_rename_p->available_for_renaming,
1335 AND_COMPL_HARD_REG_SET (reg_rename_p->available_for_renaming,
1336 reg_rename_p->unavailable_hard_regs);
1338 /* Regno is always ok from the renaming part of view, but it really
1339 could be in *unavailable_hard_regs already, so set it here instead
1341 SET_HARD_REG_BIT (reg_rename_p->available_for_renaming, regno);
1344 /* reg_rename_tick[REG1] > reg_rename_tick[REG2] if REG1 was chosen as the
1345 best register more recently than REG2. */
1346 static int reg_rename_tick[FIRST_PSEUDO_REGISTER];
1348 /* Indicates the number of times renaming happened before the current one. */
1349 static int reg_rename_this_tick;
1351 /* Choose the register among free, that is suitable for storing
1354 ORIGINAL_INSNS is the list of insns where the operation (rhs)
1355 originally appears. There could be multiple original operations
1356 for single rhs since we moving it up and merging along different
1359 Some code is adapted from regrename.c (regrename_optimize).
1360 If original register is available, function returns it.
1361 Otherwise it performs the checks, so the new register should
1362 comply with the following:
1363 - it should not violate any live ranges (such registers are in
1364 REG_RENAME_P->available_for_renaming set);
1365 - it should not be in the HARD_REGS_USED regset;
1366 - it should be in the class compatible with original uses;
1367 - it should not be clobbered through reference with different mode;
1368 - if we're in the leaf function, then the new register should
1369 not be in the LEAF_REGISTERS;
1372 If several registers meet the conditions, the register with smallest
1373 tick is returned to achieve more even register allocation.
1375 If original register seems to be ok, we set *IS_ORIG_REG_P_PTR to true.
1377 If no register satisfies the above conditions, NULL_RTX is returned. */
1379 choose_best_reg_1 (HARD_REG_SET hard_regs_used,
1380 struct reg_rename *reg_rename_p,
1381 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1385 enum machine_mode mode = VOIDmode;
1386 unsigned regno, i, n;
1387 hard_reg_set_iterator hrsi;
1388 def_list_iterator di;
1391 /* If original register is available, return it. */
1392 *is_orig_reg_p_ptr = true;
1394 FOR_EACH_DEF (def, di, original_insns)
1396 rtx orig_dest = SET_DEST (PATTERN (def->orig_insn));
1398 gcc_assert (REG_P (orig_dest));
1400 /* Check that all original operations have the same mode.
1401 This is done for the next loop; if we'd return from this
1402 loop, we'd check only part of them, but in this case
1403 it doesn't matter. */
1404 if (mode == VOIDmode)
1405 mode = GET_MODE (orig_dest);
1406 gcc_assert (mode == GET_MODE (orig_dest));
1408 regno = REGNO (orig_dest);
1409 for (i = 0, n = hard_regno_nregs[regno][mode]; i < n; i++)
1410 if (TEST_HARD_REG_BIT (hard_regs_used, regno + i))
1413 /* All hard registers are available. */
1416 gcc_assert (mode != VOIDmode);
1418 /* Hard registers should not be shared. */
1419 return gen_rtx_REG (mode, regno);
1423 *is_orig_reg_p_ptr = false;
1426 /* Among all available regs choose the register that was
1427 allocated earliest. */
1428 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p->available_for_renaming,
1430 if (! TEST_HARD_REG_BIT (hard_regs_used, cur_reg))
1432 /* Check that all hard regs for mode are available. */
1433 for (i = 1, n = hard_regno_nregs[cur_reg][mode]; i < n; i++)
1434 if (TEST_HARD_REG_BIT (hard_regs_used, cur_reg + i)
1435 || !TEST_HARD_REG_BIT (reg_rename_p->available_for_renaming,
1442 /* All hard registers are available. */
1443 if (best_new_reg < 0
1444 || reg_rename_tick[cur_reg] < reg_rename_tick[best_new_reg])
1446 best_new_reg = cur_reg;
1448 /* Return immediately when we know there's no better reg. */
1449 if (! reg_rename_tick[best_new_reg])
1454 if (best_new_reg >= 0)
1456 /* Use the check from the above loop. */
1457 gcc_assert (mode != VOIDmode);
1458 return gen_rtx_REG (mode, best_new_reg);
1464 /* A wrapper around choose_best_reg_1 () to verify that we make correct
1465 assumptions about available registers in the function. */
1467 choose_best_reg (HARD_REG_SET hard_regs_used, struct reg_rename *reg_rename_p,
1468 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1470 rtx best_reg = choose_best_reg_1 (hard_regs_used, reg_rename_p,
1471 original_insns, is_orig_reg_p_ptr);
1473 /* FIXME loop over hard_regno_nregs here. */
1474 gcc_assert (best_reg == NULL_RTX
1475 || TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, REGNO (best_reg)));
1480 /* Choose the pseudo register for storing rhs value. As this is supposed
1481 to work before reload, we return either the original register or make
1482 the new one. The parameters are the same that in choose_nest_reg_1
1483 functions, except that USED_REGS may contain pseudos.
1484 If we work with hard regs, check also REG_RENAME_P->UNAVAILABLE_HARD_REGS.
1486 TODO: take into account register pressure while doing this. Up to this
1487 moment, this function would never return NULL for pseudos, but we should
1488 not rely on this. */
1490 choose_best_pseudo_reg (regset used_regs,
1491 struct reg_rename *reg_rename_p,
1492 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1494 def_list_iterator i;
1496 enum machine_mode mode = VOIDmode;
1497 bool bad_hard_regs = false;
1499 /* We should not use this after reload. */
1500 gcc_assert (!reload_completed);
1502 /* If original register is available, return it. */
1503 *is_orig_reg_p_ptr = true;
1505 FOR_EACH_DEF (def, i, original_insns)
1507 rtx dest = SET_DEST (PATTERN (def->orig_insn));
1510 gcc_assert (REG_P (dest));
1512 /* Check that all original operations have the same mode. */
1513 if (mode == VOIDmode)
1514 mode = GET_MODE (dest);
1516 gcc_assert (mode == GET_MODE (dest));
1517 orig_regno = REGNO (dest);
1519 if (!REGNO_REG_SET_P (used_regs, orig_regno))
1521 if (orig_regno < FIRST_PSEUDO_REGISTER)
1523 gcc_assert (df_regs_ever_live_p (orig_regno));
1525 /* For hard registers, we have to check hardware imposed
1526 limitations (frame/stack registers, calls crossed). */
1527 if (!TEST_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs,
1530 /* Don't let register cross a call if it doesn't already
1531 cross one. This condition is written in accordance with
1532 that in sched-deps.c sched_analyze_reg(). */
1533 if (!reg_rename_p->crosses_call
1534 || REG_N_CALLS_CROSSED (orig_regno) > 0)
1535 return gen_rtx_REG (mode, orig_regno);
1538 bad_hard_regs = true;
1545 *is_orig_reg_p_ptr = false;
1547 /* We had some original hard registers that couldn't be used.
1548 Those were likely special. Don't try to create a pseudo. */
1552 /* We haven't found a register from original operations. Get a new one.
1553 FIXME: control register pressure somehow. */
1555 rtx new_reg = gen_reg_rtx (mode);
1557 gcc_assert (mode != VOIDmode);
1559 max_regno = max_reg_num ();
1560 maybe_extend_reg_info_p ();
1561 REG_N_CALLS_CROSSED (REGNO (new_reg)) = reg_rename_p->crosses_call ? 1 : 0;
1567 /* True when target of EXPR is available due to EXPR_TARGET_AVAILABLE,
1568 USED_REGS and REG_RENAME_P->UNAVAILABLE_HARD_REGS. */
1570 verify_target_availability (expr_t expr, regset used_regs,
1571 struct reg_rename *reg_rename_p)
1573 unsigned n, i, regno;
1574 enum machine_mode mode;
1575 bool target_available, live_available, hard_available;
1577 if (!REG_P (EXPR_LHS (expr)) || EXPR_TARGET_AVAILABLE (expr) < 0)
1580 regno = expr_dest_regno (expr);
1581 mode = GET_MODE (EXPR_LHS (expr));
1582 target_available = EXPR_TARGET_AVAILABLE (expr) == 1;
1583 n = reload_completed ? hard_regno_nregs[regno][mode] : 1;
1585 live_available = hard_available = true;
1586 for (i = 0; i < n; i++)
1588 if (bitmap_bit_p (used_regs, regno + i))
1589 live_available = false;
1590 if (TEST_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs, regno + i))
1591 hard_available = false;
1594 /* When target is not available, it may be due to hard register
1595 restrictions, e.g. crosses calls, so we check hard_available too. */
1596 if (target_available)
1597 gcc_assert (live_available);
1599 /* Check only if we haven't scheduled something on the previous fence,
1600 cause due to MAX_SOFTWARE_LOOKAHEAD_WINDOW_SIZE issues
1601 and having more than one fence, we may end having targ_un in a block
1602 in which successors target register is actually available.
1604 The last condition handles the case when a dependence from a call insn
1605 was created in sched-deps.c for insns with destination registers that
1606 never crossed a call before, but do cross one after our code motion.
1608 FIXME: in the latter case, we just uselessly called find_used_regs,
1609 because we can't move this expression with any other register
1611 gcc_assert (scheduled_something_on_previous_fence || !live_available
1613 || (!reload_completed && reg_rename_p->crosses_call
1614 && REG_N_CALLS_CROSSED (regno) == 0));
1617 /* Collect unavailable registers due to liveness for EXPR from BNDS
1618 into USED_REGS. Save additional information about available
1619 registers and unavailable due to hardware restriction registers
1620 into REG_RENAME_P structure. Save original insns into ORIGINAL_INSNS
1623 collect_unavailable_regs_from_bnds (expr_t expr, blist_t bnds, regset used_regs,
1624 struct reg_rename *reg_rename_p,
1625 def_list_t *original_insns)
1627 for (; bnds; bnds = BLIST_NEXT (bnds))
1630 av_set_t orig_ops = NULL;
1631 bnd_t bnd = BLIST_BND (bnds);
1633 /* If the chosen best expr doesn't belong to current boundary,
1635 if (!av_set_is_in_p (BND_AV1 (bnd), EXPR_VINSN (expr)))
1638 /* Put in ORIG_OPS all exprs from this boundary that became
1640 orig_ops = find_sequential_best_exprs (bnd, expr, false);
1642 /* Compute used regs and OR it into the USED_REGS. */
1643 res = find_used_regs (BND_TO (bnd), orig_ops, used_regs,
1644 reg_rename_p, original_insns);
1646 /* FIXME: the assert is true until we'd have several boundaries. */
1648 av_set_clear (&orig_ops);
1652 /* Return TRUE if it is possible to replace LHSes of ORIG_INSNS with BEST_REG.
1653 If BEST_REG is valid, replace LHS of EXPR with it. */
1655 try_replace_dest_reg (ilist_t orig_insns, rtx best_reg, expr_t expr)
1657 /* Try whether we'll be able to generate the insn
1658 'dest := best_reg' at the place of the original operation. */
1659 for (; orig_insns; orig_insns = ILIST_NEXT (orig_insns))
1661 insn_t orig_insn = DEF_LIST_DEF (orig_insns)->orig_insn;
1663 gcc_assert (EXPR_SEPARABLE_P (INSN_EXPR (orig_insn)));
1665 if (REGNO (best_reg) != REGNO (INSN_LHS (orig_insn))
1666 && (! replace_src_with_reg_ok_p (orig_insn, best_reg)
1667 || ! replace_dest_with_reg_ok_p (orig_insn, best_reg)))
1671 /* Make sure that EXPR has the right destination
1673 if (expr_dest_regno (expr) != REGNO (best_reg))
1674 replace_dest_with_reg_in_expr (expr, best_reg);
1676 EXPR_TARGET_AVAILABLE (expr) = 1;
1681 /* Select and assign best register to EXPR searching from BNDS.
1682 Set *IS_ORIG_REG_P to TRUE if original register was selected.
1683 Return FALSE if no register can be chosen, which could happen when:
1684 * EXPR_SEPARABLE_P is true but we were unable to find suitable register;
1685 * EXPR_SEPARABLE_P is false but the insn sets/clobbers one of the registers
1686 that are used on the moving path. */
1688 find_best_reg_for_expr (expr_t expr, blist_t bnds, bool *is_orig_reg_p)
1690 static struct reg_rename reg_rename_data;
1693 def_list_t original_insns = NULL;
1696 *is_orig_reg_p = false;
1698 /* Don't bother to do anything if this insn doesn't set any registers. */
1699 if (bitmap_empty_p (VINSN_REG_SETS (EXPR_VINSN (expr)))
1700 && bitmap_empty_p (VINSN_REG_CLOBBERS (EXPR_VINSN (expr))))
1703 used_regs = get_clear_regset_from_pool ();
1704 CLEAR_HARD_REG_SET (reg_rename_data.unavailable_hard_regs);
1706 collect_unavailable_regs_from_bnds (expr, bnds, used_regs, ®_rename_data,
1709 #ifdef ENABLE_CHECKING
1710 /* If after reload, make sure we're working with hard regs here. */
1711 if (reload_completed)
1713 reg_set_iterator rsi;
1716 EXECUTE_IF_SET_IN_REG_SET (used_regs, FIRST_PSEUDO_REGISTER, i, rsi)
1721 if (EXPR_SEPARABLE_P (expr))
1723 rtx best_reg = NULL_RTX;
1724 /* Check that we have computed availability of a target register
1726 verify_target_availability (expr, used_regs, ®_rename_data);
1728 /* Turn everything in hard regs after reload. */
1729 if (reload_completed)
1731 HARD_REG_SET hard_regs_used;
1732 REG_SET_TO_HARD_REG_SET (hard_regs_used, used_regs);
1734 /* Join hard registers unavailable due to register class
1735 restrictions and live range intersection. */
1736 IOR_HARD_REG_SET (hard_regs_used,
1737 reg_rename_data.unavailable_hard_regs);
1739 best_reg = choose_best_reg (hard_regs_used, ®_rename_data,
1740 original_insns, is_orig_reg_p);
1743 best_reg = choose_best_pseudo_reg (used_regs, ®_rename_data,
1744 original_insns, is_orig_reg_p);
1748 else if (*is_orig_reg_p)
1750 /* In case of unification BEST_REG may be different from EXPR's LHS
1751 when EXPR's LHS is unavailable, and there is another LHS among
1753 reg_ok = try_replace_dest_reg (original_insns, best_reg, expr);
1757 /* Forbid renaming of low-cost insns. */
1758 if (sel_vinsn_cost (EXPR_VINSN (expr)) < 2)
1761 reg_ok = try_replace_dest_reg (original_insns, best_reg, expr);
1766 /* If !EXPR_SCHEDULE_AS_RHS (EXPR), just make sure INSN doesn't set
1767 any of the HARD_REGS_USED set. */
1768 if (vinsn_writes_one_of_regs_p (EXPR_VINSN (expr), used_regs,
1769 reg_rename_data.unavailable_hard_regs))
1772 gcc_assert (EXPR_TARGET_AVAILABLE (expr) <= 0);
1777 gcc_assert (EXPR_TARGET_AVAILABLE (expr) != 0);
1781 ilist_clear (&original_insns);
1782 return_regset_to_pool (used_regs);
1788 /* Return true if dependence described by DS can be overcomed. */
1790 can_speculate_dep_p (ds_t ds)
1792 if (spec_info == NULL)
1795 /* Leave only speculative data. */
1802 /* FIXME: make sched-deps.c produce only those non-hard dependencies,
1803 that we can overcome. */
1804 ds_t spec_mask = spec_info->mask;
1806 if ((ds & spec_mask) != ds)
1810 if (ds_weak (ds) < spec_info->data_weakness_cutoff)
1816 /* Get a speculation check instruction.
1817 C_EXPR is a speculative expression,
1818 CHECK_DS describes speculations that should be checked,
1819 ORIG_INSN is the original non-speculative insn in the stream. */
1821 create_speculation_check (expr_t c_expr, ds_t check_ds, insn_t orig_insn)
1826 basic_block recovery_block;
1829 /* Create a recovery block if target is going to emit branchy check, or if
1830 ORIG_INSN was speculative already. */
1831 if (targetm.sched.needs_block_p (check_ds)
1832 || EXPR_SPEC_DONE_DS (INSN_EXPR (orig_insn)) != 0)
1834 recovery_block = sel_create_recovery_block (orig_insn);
1835 label = BB_HEAD (recovery_block);
1839 recovery_block = NULL;
1843 /* Get pattern of the check. */
1844 check_pattern = targetm.sched.gen_spec_check (EXPR_INSN_RTX (c_expr), label,
1847 gcc_assert (check_pattern != NULL);
1850 insn_rtx = create_insn_rtx_from_pattern (check_pattern, label);
1852 insn = sel_gen_insn_from_rtx_after (insn_rtx, INSN_EXPR (orig_insn),
1853 INSN_SEQNO (orig_insn), orig_insn);
1855 /* Make check to be non-speculative. */
1856 EXPR_SPEC_DONE_DS (INSN_EXPR (insn)) = 0;
1857 INSN_SPEC_CHECKED_DS (insn) = check_ds;
1859 /* Decrease priority of check by difference of load/check instruction
1861 EXPR_PRIORITY (INSN_EXPR (insn)) -= (sel_vinsn_cost (INSN_VINSN (orig_insn))
1862 - sel_vinsn_cost (INSN_VINSN (insn)));
1864 /* Emit copy of original insn (though with replaced target register,
1865 if needed) to the recovery block. */
1866 if (recovery_block != NULL)
1871 twin_rtx = copy_rtx (PATTERN (EXPR_INSN_RTX (c_expr)));
1872 twin_rtx = create_insn_rtx_from_pattern (twin_rtx, NULL_RTX);
1873 twin = sel_gen_recovery_insn_from_rtx_after (twin_rtx,
1874 INSN_EXPR (orig_insn),
1876 bb_note (recovery_block));
1879 /* If we've generated a data speculation check, make sure
1880 that all the bookkeeping instruction we'll create during
1881 this move_op () will allocate an ALAT entry so that the
1883 In case of control speculation we must convert C_EXPR to control
1884 speculative mode, because failing to do so will bring us an exception
1885 thrown by the non-control-speculative load. */
1886 check_ds = ds_get_max_dep_weak (check_ds);
1887 speculate_expr (c_expr, check_ds);
1892 /* True when INSN is a "regN = regN" copy. */
1894 identical_copy_p (rtx insn)
1898 pat = PATTERN (insn);
1900 if (GET_CODE (pat) != SET)
1903 lhs = SET_DEST (pat);
1907 rhs = SET_SRC (pat);
1911 return REGNO (lhs) == REGNO (rhs);
1914 /* Undo all transformations on *AV_PTR that were done when
1915 moving through INSN. */
1917 undo_transformations (av_set_t *av_ptr, rtx insn)
1919 av_set_iterator av_iter;
1921 av_set_t new_set = NULL;
1923 /* First, kill any EXPR that uses registers set by an insn. This is
1924 required for correctness. */
1925 FOR_EACH_EXPR_1 (expr, av_iter, av_ptr)
1926 if (!sched_insns_conditions_mutex_p (insn, EXPR_INSN_RTX (expr))
1927 && bitmap_intersect_p (INSN_REG_SETS (insn),
1928 VINSN_REG_USES (EXPR_VINSN (expr)))
1929 /* When an insn looks like 'r1 = r1', we could substitute through
1930 it, but the above condition will still hold. This happened with
1931 gcc.c-torture/execute/961125-1.c. */
1932 && !identical_copy_p (insn))
1934 if (sched_verbose >= 6)
1935 sel_print ("Expr %d removed due to use/set conflict\n",
1936 INSN_UID (EXPR_INSN_RTX (expr)));
1937 av_set_iter_remove (&av_iter);
1940 /* Undo transformations looking at the history vector. */
1941 FOR_EACH_EXPR (expr, av_iter, *av_ptr)
1943 int index = find_in_history_vect (EXPR_HISTORY_OF_CHANGES (expr),
1944 insn, EXPR_VINSN (expr), true);
1948 expr_history_def *phist;
1950 phist = VEC_index (expr_history_def,
1951 EXPR_HISTORY_OF_CHANGES (expr),
1954 switch (phist->type)
1956 case TRANS_SPECULATION:
1958 ds_t old_ds, new_ds;
1960 /* Compute the difference between old and new speculative
1961 statuses: that's what we need to check.
1962 Earlier we used to assert that the status will really
1963 change. This no longer works because only the probability
1964 bits in the status may have changed during compute_av_set,
1965 and in the case of merging different probabilities of the
1966 same speculative status along different paths we do not
1967 record this in the history vector. */
1968 old_ds = phist->spec_ds;
1969 new_ds = EXPR_SPEC_DONE_DS (expr);
1971 old_ds &= SPECULATIVE;
1972 new_ds &= SPECULATIVE;
1975 EXPR_SPEC_TO_CHECK_DS (expr) |= new_ds;
1978 case TRANS_SUBSTITUTION:
1980 expr_def _tmp_expr, *tmp_expr = &_tmp_expr;
1984 new_vi = phist->old_expr_vinsn;
1986 gcc_assert (VINSN_SEPARABLE_P (new_vi)
1987 == EXPR_SEPARABLE_P (expr));
1988 copy_expr (tmp_expr, expr);
1990 if (vinsn_equal_p (phist->new_expr_vinsn,
1991 EXPR_VINSN (tmp_expr)))
1992 change_vinsn_in_expr (tmp_expr, new_vi);
1994 /* This happens when we're unsubstituting on a bookkeeping
1995 copy, which was in turn substituted. The history is wrong
1996 in this case. Do it the hard way. */
1997 add = substitute_reg_in_expr (tmp_expr, insn, true);
1999 av_set_add (&new_set, tmp_expr);
2000 clear_expr (tmp_expr);
2010 av_set_union_and_clear (av_ptr, &new_set, NULL);
2014 /* Moveup_* helpers for code motion and computing av sets. */
2016 /* Propagates EXPR inside an insn group through THROUGH_INSN.
2017 The difference from the below function is that only substitution is
2019 static enum MOVEUP_EXPR_CODE
2020 moveup_expr_inside_insn_group (expr_t expr, insn_t through_insn)
2022 vinsn_t vi = EXPR_VINSN (expr);
2026 /* Do this only inside insn group. */
2027 gcc_assert (INSN_SCHED_CYCLE (through_insn) > 0);
2029 full_ds = has_dependence_p (expr, through_insn, &has_dep_p);
2031 return MOVEUP_EXPR_SAME;
2033 /* Substitution is the possible choice in this case. */
2034 if (has_dep_p[DEPS_IN_RHS])
2036 /* Can't substitute UNIQUE VINSNs. */
2037 gcc_assert (!VINSN_UNIQUE_P (vi));
2039 if (can_substitute_through_p (through_insn,
2040 has_dep_p[DEPS_IN_RHS])
2041 && substitute_reg_in_expr (expr, through_insn, false))
2043 EXPR_WAS_SUBSTITUTED (expr) = true;
2044 return MOVEUP_EXPR_CHANGED;
2047 /* Don't care about this, as even true dependencies may be allowed
2048 in an insn group. */
2049 return MOVEUP_EXPR_SAME;
2052 /* This can catch output dependencies in COND_EXECs. */
2053 if (has_dep_p[DEPS_IN_INSN])
2054 return MOVEUP_EXPR_NULL;
2056 /* This is either an output or an anti dependence, which usually have
2057 a zero latency. Allow this here, if we'd be wrong, tick_check_p
2059 gcc_assert (has_dep_p[DEPS_IN_LHS]);
2060 return MOVEUP_EXPR_AS_RHS;
2063 /* True when a trapping EXPR cannot be moved through THROUGH_INSN. */
2064 #define CANT_MOVE_TRAPPING(expr, through_insn) \
2065 (VINSN_MAY_TRAP_P (EXPR_VINSN (expr)) \
2066 && !sel_insn_has_single_succ_p ((through_insn), SUCCS_ALL) \
2067 && !sel_insn_is_speculation_check (through_insn))
2069 /* True when a conflict on a target register was found during moveup_expr. */
2070 static bool was_target_conflict = false;
2072 /* Modifies EXPR so it can be moved through the THROUGH_INSN,
2073 performing necessary transformations. Record the type of transformation
2074 made in PTRANS_TYPE, when it is not NULL. When INSIDE_INSN_GROUP,
2075 permit all dependencies except true ones, and try to remove those
2076 too via forward substitution. All cases when a non-eliminable
2077 non-zero cost dependency exists inside an insn group will be fixed
2078 in tick_check_p instead. */
2079 static enum MOVEUP_EXPR_CODE
2080 moveup_expr (expr_t expr, insn_t through_insn, bool inside_insn_group,
2081 enum local_trans_type *ptrans_type)
2083 vinsn_t vi = EXPR_VINSN (expr);
2084 insn_t insn = VINSN_INSN_RTX (vi);
2085 bool was_changed = false;
2086 bool as_rhs = false;
2090 /* When inside_insn_group, delegate to the helper. */
2091 if (inside_insn_group)
2092 return moveup_expr_inside_insn_group (expr, through_insn);
2094 /* Deal with unique insns and control dependencies. */
2095 if (VINSN_UNIQUE_P (vi))
2097 /* We can move jumps without side-effects or jumps that are
2098 mutually exclusive with instruction THROUGH_INSN (all in cases
2099 dependencies allow to do so and jump is not speculative). */
2100 if (control_flow_insn_p (insn))
2102 basic_block fallthru_bb;
2104 /* Do not move checks and do not move jumps through other
2106 if (control_flow_insn_p (through_insn)
2107 || sel_insn_is_speculation_check (insn))
2108 return MOVEUP_EXPR_NULL;
2110 /* Don't move jumps through CFG joins. */
2111 if (bookkeeping_can_be_created_if_moved_through_p (through_insn))
2112 return MOVEUP_EXPR_NULL;
2114 /* The jump should have a clear fallthru block, and
2115 this block should be in the current region. */
2116 if ((fallthru_bb = fallthru_bb_of_jump (insn)) == NULL
2117 || ! in_current_region_p (fallthru_bb))
2118 return MOVEUP_EXPR_NULL;
2120 /* And it should be mutually exclusive with through_insn, or
2121 be an unconditional jump. */
2122 if (! any_uncondjump_p (insn)
2123 && ! sched_insns_conditions_mutex_p (insn, through_insn))
2124 return MOVEUP_EXPR_NULL;
2127 /* Don't move what we can't move. */
2128 if (EXPR_CANT_MOVE (expr)
2129 && BLOCK_FOR_INSN (through_insn) != BLOCK_FOR_INSN (insn))
2130 return MOVEUP_EXPR_NULL;
2132 /* Don't move SCHED_GROUP instruction through anything.
2133 If we don't force this, then it will be possible to start
2134 scheduling a sched_group before all its dependencies are
2136 ??? Haifa deals with this issue by delaying the SCHED_GROUP
2137 as late as possible through rank_for_schedule. */
2138 if (SCHED_GROUP_P (insn))
2139 return MOVEUP_EXPR_NULL;
2142 gcc_assert (!control_flow_insn_p (insn));
2144 /* Deal with data dependencies. */
2145 was_target_conflict = false;
2146 full_ds = has_dependence_p (expr, through_insn, &has_dep_p);
2149 if (!CANT_MOVE_TRAPPING (expr, through_insn))
2150 return MOVEUP_EXPR_SAME;
2154 /* We can move UNIQUE insn up only as a whole and unchanged,
2155 so it shouldn't have any dependencies. */
2156 if (VINSN_UNIQUE_P (vi))
2157 return MOVEUP_EXPR_NULL;
2160 if (full_ds != 0 && can_speculate_dep_p (full_ds))
2164 res = speculate_expr (expr, full_ds);
2167 /* Speculation was successful. */
2169 was_changed = (res > 0);
2171 was_target_conflict = true;
2173 *ptrans_type = TRANS_SPECULATION;
2174 sel_clear_has_dependence ();
2178 if (has_dep_p[DEPS_IN_INSN])
2179 /* We have some dependency that cannot be discarded. */
2180 return MOVEUP_EXPR_NULL;
2182 if (has_dep_p[DEPS_IN_LHS])
2184 /* Only separable insns can be moved up with the new register.
2185 Anyways, we should mark that the original register is
2187 if (!enable_schedule_as_rhs_p || !EXPR_SEPARABLE_P (expr))
2188 return MOVEUP_EXPR_NULL;
2190 EXPR_TARGET_AVAILABLE (expr) = false;
2191 was_target_conflict = true;
2195 /* At this point we have either separable insns, that will be lifted
2196 up only as RHSes, or non-separable insns with no dependency in lhs.
2197 If dependency is in RHS, then try to perform substitution and move up
2204 In Ex.1 y*2 can be substituted for x*2 and the whole operation can be
2205 moved above y=x assignment as z=x*2.
2207 In Ex.2 y*2 also can be substituted for x*2, but only the right hand
2208 side can be moved because of the output dependency. The operation was
2209 cropped to its rhs above. */
2210 if (has_dep_p[DEPS_IN_RHS])
2212 ds_t *rhs_dsp = &has_dep_p[DEPS_IN_RHS];
2214 /* Can't substitute UNIQUE VINSNs. */
2215 gcc_assert (!VINSN_UNIQUE_P (vi));
2217 if (can_speculate_dep_p (*rhs_dsp))
2221 res = speculate_expr (expr, *rhs_dsp);
2224 /* Speculation was successful. */
2226 was_changed = (res > 0);
2228 was_target_conflict = true;
2230 *ptrans_type = TRANS_SPECULATION;
2233 return MOVEUP_EXPR_NULL;
2235 else if (can_substitute_through_p (through_insn,
2237 && substitute_reg_in_expr (expr, through_insn, false))
2239 /* ??? We cannot perform substitution AND speculation on the same
2241 gcc_assert (!was_changed);
2244 *ptrans_type = TRANS_SUBSTITUTION;
2245 EXPR_WAS_SUBSTITUTED (expr) = true;
2248 return MOVEUP_EXPR_NULL;
2251 /* Don't move trapping insns through jumps.
2252 This check should be at the end to give a chance to control speculation
2253 to perform its duties. */
2254 if (CANT_MOVE_TRAPPING (expr, through_insn))
2255 return MOVEUP_EXPR_NULL;
2258 ? MOVEUP_EXPR_CHANGED
2260 ? MOVEUP_EXPR_AS_RHS
2261 : MOVEUP_EXPR_SAME));
2264 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2265 if successful. When INSIDE_INSN_GROUP, also try ignore dependencies
2266 that can exist within a parallel group. Write to RES the resulting
2267 code for moveup_expr. */
2269 try_bitmap_cache (expr_t expr, insn_t insn,
2270 bool inside_insn_group,
2271 enum MOVEUP_EXPR_CODE *res)
2273 int expr_uid = INSN_UID (EXPR_INSN_RTX (expr));
2275 /* First check whether we've analyzed this situation already. */
2276 if (bitmap_bit_p (INSN_ANALYZED_DEPS (insn), expr_uid))
2278 if (bitmap_bit_p (INSN_FOUND_DEPS (insn), expr_uid))
2280 if (sched_verbose >= 6)
2281 sel_print ("removed (cached)\n");
2282 *res = MOVEUP_EXPR_NULL;
2287 if (sched_verbose >= 6)
2288 sel_print ("unchanged (cached)\n");
2289 *res = MOVEUP_EXPR_SAME;
2293 else if (bitmap_bit_p (INSN_FOUND_DEPS (insn), expr_uid))
2295 if (inside_insn_group)
2297 if (sched_verbose >= 6)
2298 sel_print ("unchanged (as RHS, cached, inside insn group)\n");
2299 *res = MOVEUP_EXPR_SAME;
2304 EXPR_TARGET_AVAILABLE (expr) = false;
2306 /* This is the only case when propagation result can change over time,
2307 as we can dynamically switch off scheduling as RHS. In this case,
2308 just check the flag to reach the correct decision. */
2309 if (enable_schedule_as_rhs_p)
2311 if (sched_verbose >= 6)
2312 sel_print ("unchanged (as RHS, cached)\n");
2313 *res = MOVEUP_EXPR_AS_RHS;
2318 if (sched_verbose >= 6)
2319 sel_print ("removed (cached as RHS, but renaming"
2320 " is now disabled)\n");
2321 *res = MOVEUP_EXPR_NULL;
2329 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2330 if successful. Write to RES the resulting code for moveup_expr. */
2332 try_transformation_cache (expr_t expr, insn_t insn,
2333 enum MOVEUP_EXPR_CODE *res)
2335 struct transformed_insns *pti
2336 = (struct transformed_insns *)
2337 htab_find_with_hash (INSN_TRANSFORMED_INSNS (insn),
2339 VINSN_HASH_RTX (EXPR_VINSN (expr)));
2342 /* This EXPR was already moved through this insn and was
2343 changed as a result. Fetch the proper data from
2345 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr),
2346 INSN_UID (insn), pti->type,
2347 pti->vinsn_old, pti->vinsn_new,
2348 EXPR_SPEC_DONE_DS (expr));
2350 if (INSN_IN_STREAM_P (VINSN_INSN_RTX (pti->vinsn_new)))
2351 pti->vinsn_new = vinsn_copy (pti->vinsn_new, true);
2352 change_vinsn_in_expr (expr, pti->vinsn_new);
2353 if (pti->was_target_conflict)
2354 EXPR_TARGET_AVAILABLE (expr) = false;
2355 if (pti->type == TRANS_SPECULATION)
2359 ds = EXPR_SPEC_DONE_DS (expr);
2361 EXPR_SPEC_DONE_DS (expr) = pti->ds;
2362 EXPR_NEEDS_SPEC_CHECK_P (expr) |= pti->needs_check;
2365 if (sched_verbose >= 6)
2367 sel_print ("changed (cached): ");
2372 *res = MOVEUP_EXPR_CHANGED;
2379 /* Update bitmap caches on INSN with result RES of propagating EXPR. */
2381 update_bitmap_cache (expr_t expr, insn_t insn, bool inside_insn_group,
2382 enum MOVEUP_EXPR_CODE res)
2384 int expr_uid = INSN_UID (EXPR_INSN_RTX (expr));
2386 /* Do not cache result of propagating jumps through an insn group,
2387 as it is always true, which is not useful outside the group. */
2388 if (inside_insn_group)
2391 if (res == MOVEUP_EXPR_NULL)
2393 bitmap_set_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2394 bitmap_set_bit (INSN_FOUND_DEPS (insn), expr_uid);
2396 else if (res == MOVEUP_EXPR_SAME)
2398 bitmap_set_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2399 bitmap_clear_bit (INSN_FOUND_DEPS (insn), expr_uid);
2401 else if (res == MOVEUP_EXPR_AS_RHS)
2403 bitmap_clear_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2404 bitmap_set_bit (INSN_FOUND_DEPS (insn), expr_uid);
2410 /* Update hashtable on INSN with changed EXPR, old EXPR_OLD_VINSN
2411 and transformation type TRANS_TYPE. */
2413 update_transformation_cache (expr_t expr, insn_t insn,
2414 bool inside_insn_group,
2415 enum local_trans_type trans_type,
2416 vinsn_t expr_old_vinsn)
2418 struct transformed_insns *pti;
2420 if (inside_insn_group)
2423 pti = XNEW (struct transformed_insns);
2424 pti->vinsn_old = expr_old_vinsn;
2425 pti->vinsn_new = EXPR_VINSN (expr);
2426 pti->type = trans_type;
2427 pti->was_target_conflict = was_target_conflict;
2428 pti->ds = EXPR_SPEC_DONE_DS (expr);
2429 pti->needs_check = EXPR_NEEDS_SPEC_CHECK_P (expr);
2430 vinsn_attach (pti->vinsn_old);
2431 vinsn_attach (pti->vinsn_new);
2432 *((struct transformed_insns **)
2433 htab_find_slot_with_hash (INSN_TRANSFORMED_INSNS (insn),
2434 pti, VINSN_HASH_RTX (expr_old_vinsn),
2438 /* Same as moveup_expr, but first looks up the result of
2439 transformation in caches. */
2440 static enum MOVEUP_EXPR_CODE
2441 moveup_expr_cached (expr_t expr, insn_t insn, bool inside_insn_group)
2443 enum MOVEUP_EXPR_CODE res;
2444 bool got_answer = false;
2446 if (sched_verbose >= 6)
2448 sel_print ("Moving ");
2450 sel_print (" through %d: ", INSN_UID (insn));
2453 if (try_bitmap_cache (expr, insn, inside_insn_group, &res))
2454 /* When inside insn group, we do not want remove stores conflicting
2455 with previosly issued loads. */
2456 got_answer = ! inside_insn_group || res != MOVEUP_EXPR_NULL;
2457 else if (try_transformation_cache (expr, insn, &res))
2462 /* Invoke moveup_expr and record the results. */
2463 vinsn_t expr_old_vinsn = EXPR_VINSN (expr);
2464 ds_t expr_old_spec_ds = EXPR_SPEC_DONE_DS (expr);
2465 int expr_uid = INSN_UID (VINSN_INSN_RTX (expr_old_vinsn));
2466 bool unique_p = VINSN_UNIQUE_P (expr_old_vinsn);
2467 enum local_trans_type trans_type = TRANS_SUBSTITUTION;
2469 /* ??? Invent something better than this. We can't allow old_vinsn
2470 to go, we need it for the history vector. */
2471 vinsn_attach (expr_old_vinsn);
2473 res = moveup_expr (expr, insn, inside_insn_group,
2477 case MOVEUP_EXPR_NULL:
2478 update_bitmap_cache (expr, insn, inside_insn_group, res);
2479 if (sched_verbose >= 6)
2480 sel_print ("removed\n");
2483 case MOVEUP_EXPR_SAME:
2484 update_bitmap_cache (expr, insn, inside_insn_group, res);
2485 if (sched_verbose >= 6)
2486 sel_print ("unchanged\n");
2489 case MOVEUP_EXPR_AS_RHS:
2490 gcc_assert (!unique_p || inside_insn_group);
2491 update_bitmap_cache (expr, insn, inside_insn_group, res);
2492 if (sched_verbose >= 6)
2493 sel_print ("unchanged (as RHS)\n");
2496 case MOVEUP_EXPR_CHANGED:
2497 gcc_assert (INSN_UID (EXPR_INSN_RTX (expr)) != expr_uid
2498 || EXPR_SPEC_DONE_DS (expr) != expr_old_spec_ds);
2499 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr),
2500 INSN_UID (insn), trans_type,
2501 expr_old_vinsn, EXPR_VINSN (expr),
2503 update_transformation_cache (expr, insn, inside_insn_group,
2504 trans_type, expr_old_vinsn);
2505 if (sched_verbose >= 6)
2507 sel_print ("changed: ");
2516 vinsn_detach (expr_old_vinsn);
2522 /* Moves an av set AVP up through INSN, performing necessary
2525 moveup_set_expr (av_set_t *avp, insn_t insn, bool inside_insn_group)
2530 FOR_EACH_EXPR_1 (expr, i, avp)
2533 switch (moveup_expr_cached (expr, insn, inside_insn_group))
2535 case MOVEUP_EXPR_SAME:
2536 case MOVEUP_EXPR_AS_RHS:
2539 case MOVEUP_EXPR_NULL:
2540 av_set_iter_remove (&i);
2543 case MOVEUP_EXPR_CHANGED:
2544 expr = merge_with_other_exprs (avp, &i, expr);
2553 /* Moves AVP set along PATH. */
2555 moveup_set_inside_insn_group (av_set_t *avp, ilist_t path)
2559 if (sched_verbose >= 6)
2560 sel_print ("Moving expressions up in the insn group...\n");
2563 last_cycle = INSN_SCHED_CYCLE (ILIST_INSN (path));
2565 && INSN_SCHED_CYCLE (ILIST_INSN (path)) == last_cycle)
2567 moveup_set_expr (avp, ILIST_INSN (path), true);
2568 path = ILIST_NEXT (path);
2572 /* Returns true if after moving EXPR along PATH it equals to EXPR_VLIW. */
2574 equal_after_moveup_path_p (expr_t expr, ilist_t path, expr_t expr_vliw)
2576 expr_def _tmp, *tmp = &_tmp;
2580 copy_expr_onside (tmp, expr);
2581 last_cycle = path ? INSN_SCHED_CYCLE (ILIST_INSN (path)) : 0;
2584 && INSN_SCHED_CYCLE (ILIST_INSN (path)) == last_cycle)
2586 res = (moveup_expr_cached (tmp, ILIST_INSN (path), true)
2587 != MOVEUP_EXPR_NULL);
2588 path = ILIST_NEXT (path);
2593 vinsn_t tmp_vinsn = EXPR_VINSN (tmp);
2594 vinsn_t expr_vliw_vinsn = EXPR_VINSN (expr_vliw);
2596 if (tmp_vinsn != expr_vliw_vinsn)
2597 res = vinsn_equal_p (tmp_vinsn, expr_vliw_vinsn);
2605 /* Functions that compute av and lv sets. */
2607 /* Returns true if INSN is not a downward continuation of the given path P in
2608 the current stage. */
2610 is_ineligible_successor (insn_t insn, ilist_t p)
2614 /* Check if insn is not deleted. */
2615 if (PREV_INSN (insn) && NEXT_INSN (PREV_INSN (insn)) != insn)
2617 else if (NEXT_INSN (insn) && PREV_INSN (NEXT_INSN (insn)) != insn)
2620 /* If it's the first insn visited, then the successor is ok. */
2624 prev_insn = ILIST_INSN (p);
2626 if (/* a backward edge. */
2627 INSN_SEQNO (insn) < INSN_SEQNO (prev_insn)
2628 /* is already visited. */
2629 || (INSN_SEQNO (insn) == INSN_SEQNO (prev_insn)
2630 && (ilist_is_in_p (p, insn)
2631 /* We can reach another fence here and still seqno of insn
2632 would be equal to seqno of prev_insn. This is possible
2633 when prev_insn is a previously created bookkeeping copy.
2634 In that case it'd get a seqno of insn. Thus, check here
2635 whether insn is in current fence too. */
2636 || IN_CURRENT_FENCE_P (insn)))
2637 /* Was already scheduled on this round. */
2638 || (INSN_SEQNO (insn) > INSN_SEQNO (prev_insn)
2639 && IN_CURRENT_FENCE_P (insn))
2640 /* An insn from another fence could also be
2641 scheduled earlier even if this insn is not in
2642 a fence list right now. Check INSN_SCHED_CYCLE instead. */
2644 && INSN_SCHED_TIMES (insn) > 0))
2650 /* Computes the av_set below the last bb insn INSN, doing all the 'dirty work'
2651 of handling multiple successors and properly merging its av_sets. P is
2652 the current path traversed. WS is the size of lookahead window.
2653 Return the av set computed. */
2655 compute_av_set_at_bb_end (insn_t insn, ilist_t p, int ws)
2657 struct succs_info *sinfo;
2658 av_set_t expr_in_all_succ_branches = NULL;
2660 insn_t succ, zero_succ = NULL;
2661 av_set_t av1 = NULL;
2663 gcc_assert (sel_bb_end_p (insn));
2665 /* Find different kind of successors needed for correct computing of
2666 SPEC and TARGET_AVAILABLE attributes. */
2667 sinfo = compute_succs_info (insn, SUCCS_NORMAL);
2670 if (sched_verbose >= 6)
2672 sel_print ("successors of bb end (%d): ", INSN_UID (insn));
2673 dump_insn_vector (sinfo->succs_ok);
2675 if (sinfo->succs_ok_n != sinfo->all_succs_n)
2676 sel_print ("real successors num: %d\n", sinfo->all_succs_n);
2679 /* Add insn to to the tail of current path. */
2680 ilist_add (&p, insn);
2682 for (is = 0; VEC_iterate (rtx, sinfo->succs_ok, is, succ); is++)
2686 /* We will edit SUCC_SET and EXPR_SPEC field of its elements. */
2687 succ_set = compute_av_set_inside_bb (succ, p, ws, true);
2689 av_set_split_usefulness (succ_set,
2690 VEC_index (int, sinfo->probs_ok, is),
2693 if (sinfo->all_succs_n > 1)
2695 /* Find EXPR'es that came from *all* successors and save them
2696 into expr_in_all_succ_branches. This set will be used later
2697 for calculating speculation attributes of EXPR'es. */
2700 expr_in_all_succ_branches = av_set_copy (succ_set);
2702 /* Remember the first successor for later. */
2710 FOR_EACH_EXPR_1 (expr, i, &expr_in_all_succ_branches)
2711 if (!av_set_is_in_p (succ_set, EXPR_VINSN (expr)))
2712 av_set_iter_remove (&i);
2716 /* Union the av_sets. Check liveness restrictions on target registers
2717 in special case of two successors. */
2718 if (sinfo->succs_ok_n == 2 && is == 1)
2720 basic_block bb0 = BLOCK_FOR_INSN (zero_succ);
2721 basic_block bb1 = BLOCK_FOR_INSN (succ);
2723 gcc_assert (BB_LV_SET_VALID_P (bb0) && BB_LV_SET_VALID_P (bb1));
2724 av_set_union_and_live (&av1, &succ_set,
2730 av_set_union_and_clear (&av1, &succ_set, insn);
2733 /* Check liveness restrictions via hard way when there are more than
2735 if (sinfo->succs_ok_n > 2)
2736 for (is = 0; VEC_iterate (rtx, sinfo->succs_ok, is, succ); is++)
2738 basic_block succ_bb = BLOCK_FOR_INSN (succ);
2740 gcc_assert (BB_LV_SET_VALID_P (succ_bb));
2741 mark_unavailable_targets (av1, BB_AV_SET (succ_bb),
2742 BB_LV_SET (succ_bb));
2745 /* Finally, check liveness restrictions on paths leaving the region. */
2746 if (sinfo->all_succs_n > sinfo->succs_ok_n)
2747 for (is = 0; VEC_iterate (rtx, sinfo->succs_other, is, succ); is++)
2748 mark_unavailable_targets
2749 (av1, NULL, BB_LV_SET (BLOCK_FOR_INSN (succ)));
2751 if (sinfo->all_succs_n > 1)
2756 /* Increase the spec attribute of all EXPR'es that didn't come
2757 from all successors. */
2758 FOR_EACH_EXPR (expr, i, av1)
2759 if (!av_set_is_in_p (expr_in_all_succ_branches, EXPR_VINSN (expr)))
2762 av_set_clear (&expr_in_all_succ_branches);
2764 /* Do not move conditional branches through other
2765 conditional branches. So, remove all conditional
2766 branches from av_set if current operator is a conditional
2768 av_set_substract_cond_branches (&av1);
2772 free_succs_info (sinfo);
2774 if (sched_verbose >= 6)
2776 sel_print ("av_succs (%d): ", INSN_UID (insn));
2784 /* This function computes av_set for the FIRST_INSN by dragging valid
2785 av_set through all basic block insns either from the end of basic block
2786 (computed using compute_av_set_at_bb_end) or from the insn on which
2787 MAX_WS was exceeded. It uses compute_av_set_at_bb_end to compute av_set
2788 below the basic block and handling conditional branches.
2789 FIRST_INSN - the basic block head, P - path consisting of the insns
2790 traversed on the way to the FIRST_INSN (the path is sparse, only bb heads
2791 and bb ends are added to the path), WS - current window size,
2792 NEED_COPY_P - true if we'll make a copy of av_set before returning it. */
2794 compute_av_set_inside_bb (insn_t first_insn, ilist_t p, int ws,
2799 insn_t bb_end = sel_bb_end (BLOCK_FOR_INSN (first_insn));
2800 insn_t after_bb_end = NEXT_INSN (bb_end);
2803 basic_block cur_bb = BLOCK_FOR_INSN (first_insn);
2805 /* Return NULL if insn is not on the legitimate downward path. */
2806 if (is_ineligible_successor (first_insn, p))
2808 if (sched_verbose >= 6)
2809 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (first_insn));
2814 /* If insn already has valid av(insn) computed, just return it. */
2815 if (AV_SET_VALID_P (first_insn))
2819 if (sel_bb_head_p (first_insn))
2820 av_set = BB_AV_SET (BLOCK_FOR_INSN (first_insn));
2824 if (sched_verbose >= 6)
2826 sel_print ("Insn %d has a valid av set: ", INSN_UID (first_insn));
2827 dump_av_set (av_set);
2831 return need_copy_p ? av_set_copy (av_set) : av_set;
2834 ilist_add (&p, first_insn);
2836 /* As the result after this loop have completed, in LAST_INSN we'll
2837 have the insn which has valid av_set to start backward computation
2838 from: it either will be NULL because on it the window size was exceeded
2839 or other valid av_set as returned by compute_av_set for the last insn
2840 of the basic block. */
2841 for (last_insn = first_insn; last_insn != after_bb_end;
2842 last_insn = NEXT_INSN (last_insn))
2844 /* We may encounter valid av_set not only on bb_head, but also on
2845 those insns on which previously MAX_WS was exceeded. */
2846 if (AV_SET_VALID_P (last_insn))
2848 if (sched_verbose >= 6)
2849 sel_print ("Insn %d has a valid empty av set\n", INSN_UID (last_insn));
2853 /* The special case: the last insn of the BB may be an
2854 ineligible_successor due to its SEQ_NO that was set on
2855 it as a bookkeeping. */
2856 if (last_insn != first_insn
2857 && is_ineligible_successor (last_insn, p))
2859 if (sched_verbose >= 6)
2860 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (last_insn));
2864 if (end_ws > max_ws)
2866 /* We can reach max lookahead size at bb_header, so clean av_set
2868 INSN_WS_LEVEL (last_insn) = global_level;
2870 if (sched_verbose >= 6)
2871 sel_print ("Insn %d is beyond the software lookahead window size\n",
2872 INSN_UID (last_insn));
2879 /* Get the valid av_set into AV above the LAST_INSN to start backward
2880 computation from. It either will be empty av_set or av_set computed from
2881 the successors on the last insn of the current bb. */
2882 if (last_insn != after_bb_end)
2886 /* This is needed only to obtain av_sets that are identical to
2887 those computed by the old compute_av_set version. */
2888 if (last_insn == first_insn && !INSN_NOP_P (last_insn))
2889 av_set_add (&av, INSN_EXPR (last_insn));
2892 /* END_WS is always already increased by 1 if LAST_INSN == AFTER_BB_END. */
2893 av = compute_av_set_at_bb_end (bb_end, p, end_ws);
2895 /* Compute av_set in AV starting from below the LAST_INSN up to
2896 location above the FIRST_INSN. */
2897 for (cur_insn = PREV_INSN (last_insn); cur_insn != PREV_INSN (first_insn);
2898 cur_insn = PREV_INSN (cur_insn))
2899 if (!INSN_NOP_P (cur_insn))
2903 moveup_set_expr (&av, cur_insn, false);
2905 /* If the expression for CUR_INSN is already in the set,
2906 replace it by the new one. */
2907 expr = av_set_lookup (av, INSN_VINSN (cur_insn));
2911 copy_expr (expr, INSN_EXPR (cur_insn));
2914 av_set_add (&av, INSN_EXPR (cur_insn));
2917 /* Clear stale bb_av_set. */
2918 if (sel_bb_head_p (first_insn))
2920 av_set_clear (&BB_AV_SET (cur_bb));
2921 BB_AV_SET (cur_bb) = need_copy_p ? av_set_copy (av) : av;
2922 BB_AV_LEVEL (cur_bb) = global_level;
2925 if (sched_verbose >= 6)
2927 sel_print ("Computed av set for insn %d: ", INSN_UID (first_insn));
2936 /* Compute av set before INSN.
2937 INSN - the current operation (actual rtx INSN)
2938 P - the current path, which is list of insns visited so far
2939 WS - software lookahead window size.
2940 UNIQUE_P - TRUE, if returned av_set will be changed, hence
2941 if we want to save computed av_set in s_i_d, we should make a copy of it.
2943 In the resulting set we will have only expressions that don't have delay
2944 stalls and nonsubstitutable dependences. */
2946 compute_av_set (insn_t insn, ilist_t p, int ws, bool unique_p)
2948 return compute_av_set_inside_bb (insn, p, ws, unique_p);
2951 /* Propagate a liveness set LV through INSN. */
2953 propagate_lv_set (regset lv, insn_t insn)
2955 gcc_assert (INSN_P (insn));
2957 if (INSN_NOP_P (insn))
2960 df_simulate_one_insn_backwards (BLOCK_FOR_INSN (insn), insn, lv);
2963 /* Return livness set at the end of BB. */
2965 compute_live_after_bb (basic_block bb)
2969 regset lv = get_clear_regset_from_pool ();
2971 gcc_assert (!ignore_first);
2973 FOR_EACH_EDGE (e, ei, bb->succs)
2974 if (sel_bb_empty_p (e->dest))
2976 if (! BB_LV_SET_VALID_P (e->dest))
2979 gcc_assert (BB_LV_SET (e->dest) == NULL);
2980 BB_LV_SET (e->dest) = compute_live_after_bb (e->dest);
2981 BB_LV_SET_VALID_P (e->dest) = true;
2983 IOR_REG_SET (lv, BB_LV_SET (e->dest));
2986 IOR_REG_SET (lv, compute_live (sel_bb_head (e->dest)));
2991 /* Compute the set of all live registers at the point before INSN and save
2992 it at INSN if INSN is bb header. */
2994 compute_live (insn_t insn)
2996 basic_block bb = BLOCK_FOR_INSN (insn);
3000 /* Return the valid set if we're already on it. */
3005 if (sel_bb_head_p (insn) && BB_LV_SET_VALID_P (bb))
3006 src = BB_LV_SET (bb);
3009 gcc_assert (in_current_region_p (bb));
3010 if (INSN_LIVE_VALID_P (insn))
3011 src = INSN_LIVE (insn);
3016 lv = get_regset_from_pool ();
3017 COPY_REG_SET (lv, src);
3019 if (sel_bb_head_p (insn) && ! BB_LV_SET_VALID_P (bb))
3021 COPY_REG_SET (BB_LV_SET (bb), lv);
3022 BB_LV_SET_VALID_P (bb) = true;
3025 return_regset_to_pool (lv);
3030 /* We've skipped the wrong lv_set. Don't skip the right one. */
3031 ignore_first = false;
3032 gcc_assert (in_current_region_p (bb));
3034 /* Find a valid LV set in this block or below, if needed.
3035 Start searching from the next insn: either ignore_first is true, or
3036 INSN doesn't have a correct live set. */
3037 temp = NEXT_INSN (insn);
3038 final = NEXT_INSN (BB_END (bb));
3039 while (temp != final && ! INSN_LIVE_VALID_P (temp))
3040 temp = NEXT_INSN (temp);
3043 lv = compute_live_after_bb (bb);
3044 temp = PREV_INSN (temp);
3048 lv = get_regset_from_pool ();
3049 COPY_REG_SET (lv, INSN_LIVE (temp));
3052 /* Put correct lv sets on the insns which have bad sets. */
3053 final = PREV_INSN (insn);
3054 while (temp != final)
3056 propagate_lv_set (lv, temp);
3057 COPY_REG_SET (INSN_LIVE (temp), lv);
3058 INSN_LIVE_VALID_P (temp) = true;
3059 temp = PREV_INSN (temp);
3062 /* Also put it in a BB. */
3063 if (sel_bb_head_p (insn))
3065 basic_block bb = BLOCK_FOR_INSN (insn);
3067 COPY_REG_SET (BB_LV_SET (bb), lv);
3068 BB_LV_SET_VALID_P (bb) = true;
3071 /* We return LV to the pool, but will not clear it there. Thus we can
3072 legimatelly use LV till the next use of regset_pool_get (). */
3073 return_regset_to_pool (lv);
3077 /* Update liveness sets for INSN. */
3079 update_liveness_on_insn (rtx insn)
3081 ignore_first = true;
3082 compute_live (insn);
3085 /* Compute liveness below INSN and write it into REGS. */
3087 compute_live_below_insn (rtx insn, regset regs)
3092 FOR_EACH_SUCC_1 (succ, si, insn, SUCCS_ALL)
3093 IOR_REG_SET (regs, compute_live (succ));
3096 /* Update the data gathered in av and lv sets starting from INSN. */
3098 update_data_sets (rtx insn)
3100 update_liveness_on_insn (insn);
3101 if (sel_bb_head_p (insn))
3103 gcc_assert (AV_LEVEL (insn) != 0);
3104 BB_AV_LEVEL (BLOCK_FOR_INSN (insn)) = -1;
3105 compute_av_set (insn, NULL, 0, 0);
3110 /* Helper for move_op () and find_used_regs ().
3111 Return speculation type for which a check should be created on the place
3112 of INSN. EXPR is one of the original ops we are searching for. */
3114 get_spec_check_type_for_insn (insn_t insn, expr_t expr)
3117 ds_t already_checked_ds = EXPR_SPEC_DONE_DS (INSN_EXPR (insn));
3119 to_check_ds = EXPR_SPEC_TO_CHECK_DS (expr);
3121 if (targetm.sched.get_insn_checked_ds)
3122 already_checked_ds |= targetm.sched.get_insn_checked_ds (insn);
3124 if (spec_info != NULL
3125 && (spec_info->flags & SEL_SCHED_SPEC_DONT_CHECK_CONTROL))
3126 already_checked_ds |= BEGIN_CONTROL;
3128 already_checked_ds = ds_get_speculation_types (already_checked_ds);
3130 to_check_ds &= ~already_checked_ds;
3135 /* Find the set of registers that are unavailable for storing expres
3136 while moving ORIG_OPS up on the path starting from INSN due to
3137 liveness (USED_REGS) or hardware restrictions (REG_RENAME_P).
3139 All the original operations found during the traversal are saved in the
3140 ORIGINAL_INSNS list.
3142 REG_RENAME_P denotes the set of hardware registers that
3143 can not be used with renaming due to the register class restrictions,
3144 mode restrictions and other (the register we'll choose should be
3145 compatible class with the original uses, shouldn't be in call_used_regs,
3146 should be HARD_REGNO_RENAME_OK etc).
3148 Returns TRUE if we've found all original insns, FALSE otherwise.
3150 This function utilizes code_motion_path_driver (formerly find_used_regs_1)
3151 to traverse the code motion paths. This helper function finds registers
3152 that are not available for storing expres while moving ORIG_OPS up on the
3153 path starting from INSN. A register considered as used on the moving path,
3154 if one of the following conditions is not satisfied:
3156 (1) a register not set or read on any path from xi to an instance of
3157 the original operation,
3158 (2) not among the live registers of the point immediately following the
3159 first original operation on a given downward path, except for the
3160 original target register of the operation,
3161 (3) not live on the other path of any conditional branch that is passed
3162 by the operation, in case original operations are not present on
3163 both paths of the conditional branch.
3165 All the original operations found during the traversal are saved in the
3166 ORIGINAL_INSNS list.
3168 REG_RENAME_P->CROSSES_CALL is true, if there is a call insn on the path
3169 from INSN to original insn. In this case CALL_USED_REG_SET will be added
3170 to unavailable hard regs at the point original operation is found. */
3173 find_used_regs (insn_t insn, av_set_t orig_ops, regset used_regs,
3174 struct reg_rename *reg_rename_p, def_list_t *original_insns)
3176 def_list_iterator i;
3179 bool needs_spec_check_p = false;
3181 av_set_iterator expr_iter;
3182 struct fur_static_params sparams;
3183 struct cmpd_local_params lparams;
3185 /* We haven't visited any blocks yet. */
3186 bitmap_clear (code_motion_visited_blocks);
3188 /* Init parameters for code_motion_path_driver. */
3189 sparams.crosses_call = false;
3190 sparams.original_insns = original_insns;
3191 sparams.used_regs = used_regs;
3193 /* Set the appropriate hooks and data. */
3194 code_motion_path_driver_info = &fur_hooks;
3196 res = code_motion_path_driver (insn, orig_ops, NULL, &lparams, &sparams);
3198 reg_rename_p->crosses_call |= sparams.crosses_call;
3200 gcc_assert (res == 1);
3201 gcc_assert (original_insns && *original_insns);
3203 /* ??? We calculate whether an expression needs a check when computing
3204 av sets. This information is not as precise as it could be due to
3205 merging this bit in merge_expr. We can do better in find_used_regs,
3206 but we want to avoid multiple traversals of the same code motion
3208 FOR_EACH_EXPR (expr, expr_iter, orig_ops)
3209 needs_spec_check_p |= EXPR_NEEDS_SPEC_CHECK_P (expr);
3211 /* Mark hardware regs in REG_RENAME_P that are not suitable
3212 for renaming expr in INSN due to hardware restrictions (register class,
3213 modes compatibility etc). */
3214 FOR_EACH_DEF (def, i, *original_insns)
3216 vinsn_t vinsn = INSN_VINSN (def->orig_insn);
3218 if (VINSN_SEPARABLE_P (vinsn))
3219 mark_unavailable_hard_regs (def, reg_rename_p, used_regs);
3221 /* Do not allow clobbering of ld.[sa] address in case some of the
3222 original operations need a check. */
3223 if (needs_spec_check_p)
3224 IOR_REG_SET (used_regs, VINSN_REG_USES (vinsn));
3231 /* Functions to choose the best insn from available ones. */
3233 /* Adjusts the priority for EXPR using the backend *_adjust_priority hook. */
3235 sel_target_adjust_priority (expr_t expr)
3237 int priority = EXPR_PRIORITY (expr);
3240 if (targetm.sched.adjust_priority)
3241 new_priority = targetm.sched.adjust_priority (EXPR_INSN_RTX (expr), priority);
3243 new_priority = priority;
3245 /* If the priority has changed, adjust EXPR_PRIORITY_ADJ accordingly. */
3246 EXPR_PRIORITY_ADJ (expr) = new_priority - EXPR_PRIORITY (expr);
3248 gcc_assert (EXPR_PRIORITY_ADJ (expr) >= 0);
3250 if (sched_verbose >= 4)
3251 sel_print ("sel_target_adjust_priority: insn %d, %d+%d = %d.\n",
3252 INSN_UID (EXPR_INSN_RTX (expr)), EXPR_PRIORITY (expr),
3253 EXPR_PRIORITY_ADJ (expr), new_priority);
3255 return new_priority;
3258 /* Rank two available exprs for schedule. Never return 0 here. */
3260 sel_rank_for_schedule (const void *x, const void *y)
3262 expr_t tmp = *(const expr_t *) y;
3263 expr_t tmp2 = *(const expr_t *) x;
3264 insn_t tmp_insn, tmp2_insn;
3265 vinsn_t tmp_vinsn, tmp2_vinsn;
3268 tmp_vinsn = EXPR_VINSN (tmp);
3269 tmp2_vinsn = EXPR_VINSN (tmp2);
3270 tmp_insn = EXPR_INSN_RTX (tmp);
3271 tmp2_insn = EXPR_INSN_RTX (tmp2);
3273 /* Prefer SCHED_GROUP_P insns to any others. */
3274 if (SCHED_GROUP_P (tmp_insn) != SCHED_GROUP_P (tmp2_insn))
3276 if (VINSN_UNIQUE_P (tmp_vinsn) && VINSN_UNIQUE_P (tmp2_vinsn))
3277 return SCHED_GROUP_P (tmp2_insn) ? 1 : -1;
3279 /* Now uniqueness means SCHED_GROUP_P is set, because schedule groups
3280 cannot be cloned. */
3281 if (VINSN_UNIQUE_P (tmp2_vinsn))
3286 /* Discourage scheduling of speculative checks. */
3287 val = (sel_insn_is_speculation_check (tmp_insn)
3288 - sel_insn_is_speculation_check (tmp2_insn));
3292 /* Prefer not scheduled insn over scheduled one. */
3293 if (EXPR_SCHED_TIMES (tmp) > 0 || EXPR_SCHED_TIMES (tmp2) > 0)
3295 val = EXPR_SCHED_TIMES (tmp) - EXPR_SCHED_TIMES (tmp2);
3300 /* Prefer jump over non-jump instruction. */
3301 if (control_flow_insn_p (tmp_insn) && !control_flow_insn_p (tmp2_insn))
3303 else if (control_flow_insn_p (tmp2_insn) && !control_flow_insn_p (tmp_insn))
3306 /* Prefer an expr with greater priority. */
3307 if (EXPR_USEFULNESS (tmp) != 0 && EXPR_USEFULNESS (tmp2) != 0)
3309 int p2 = EXPR_PRIORITY (tmp2) + EXPR_PRIORITY_ADJ (tmp2),
3310 p1 = EXPR_PRIORITY (tmp) + EXPR_PRIORITY_ADJ (tmp);
3312 val = p2 * EXPR_USEFULNESS (tmp2) - p1 * EXPR_USEFULNESS (tmp);
3315 val = EXPR_PRIORITY (tmp2) - EXPR_PRIORITY (tmp)
3316 + EXPR_PRIORITY_ADJ (tmp2) - EXPR_PRIORITY_ADJ (tmp);
3320 if (spec_info != NULL && spec_info->mask != 0)
3321 /* This code was taken from haifa-sched.c: rank_for_schedule (). */
3327 ds1 = EXPR_SPEC_DONE_DS (tmp);
3329 dw1 = ds_weak (ds1);
3333 ds2 = EXPR_SPEC_DONE_DS (tmp2);
3335 dw2 = ds_weak (ds2);
3340 if (dw > (NO_DEP_WEAK / 8) || dw < -(NO_DEP_WEAK / 8))
3344 tmp_insn = EXPR_INSN_RTX (tmp);
3345 tmp2_insn = EXPR_INSN_RTX (tmp2);
3347 /* Prefer an old insn to a bookkeeping insn. */
3348 if (INSN_UID (tmp_insn) < first_emitted_uid
3349 && INSN_UID (tmp2_insn) >= first_emitted_uid)
3351 if (INSN_UID (tmp_insn) >= first_emitted_uid
3352 && INSN_UID (tmp2_insn) < first_emitted_uid)
3355 /* Prefer an insn with smaller UID, as a last resort.
3356 We can't safely use INSN_LUID as it is defined only for those insns
3357 that are in the stream. */
3358 return INSN_UID (tmp_insn) - INSN_UID (tmp2_insn);
3361 /* Filter out expressions from av set pointed to by AV_PTR
3362 that are pipelined too many times. */
3364 process_pipelined_exprs (av_set_t *av_ptr)
3369 /* Don't pipeline already pipelined code as that would increase
3370 number of unnecessary register moves. */
3371 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3373 if (EXPR_SCHED_TIMES (expr)
3374 >= PARAM_VALUE (PARAM_SELSCHED_MAX_SCHED_TIMES))
3375 av_set_iter_remove (&si);
3379 /* Filter speculative insns from AV_PTR if we don't want them. */
3381 process_spec_exprs (av_set_t *av_ptr)
3383 bool try_data_p = true;
3384 bool try_control_p = true;
3388 if (spec_info == NULL)
3391 /* Scan *AV_PTR to find out if we want to consider speculative
3392 instructions for scheduling. */
3393 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3397 ds = EXPR_SPEC_DONE_DS (expr);
3399 /* The probability of a success is too low - don't speculate. */
3400 if ((ds & SPECULATIVE)
3401 && (ds_weak (ds) < spec_info->data_weakness_cutoff
3402 || EXPR_USEFULNESS (expr) < spec_info->control_weakness_cutoff
3403 || (pipelining_p && false
3405 && (ds & CONTROL_SPEC))))
3407 av_set_iter_remove (&si);
3411 if ((spec_info->flags & PREFER_NON_DATA_SPEC)
3412 && !(ds & BEGIN_DATA))
3415 if ((spec_info->flags & PREFER_NON_CONTROL_SPEC)
3416 && !(ds & BEGIN_CONTROL))
3417 try_control_p = false;
3420 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3424 ds = EXPR_SPEC_DONE_DS (expr);
3426 if (ds & SPECULATIVE)
3428 if ((ds & BEGIN_DATA) && !try_data_p)
3429 /* We don't want any data speculative instructions right
3431 av_set_iter_remove (&si);
3433 if ((ds & BEGIN_CONTROL) && !try_control_p)
3434 /* We don't want any control speculative instructions right
3436 av_set_iter_remove (&si);
3441 /* Search for any use-like insns in AV_PTR and decide on scheduling
3442 them. Return one when found, and NULL otherwise.
3443 Note that we check here whether a USE could be scheduled to avoid
3444 an infinite loop later. */
3446 process_use_exprs (av_set_t *av_ptr)
3450 bool uses_present_p = false;
3451 bool try_uses_p = true;
3453 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3455 /* This will also initialize INSN_CODE for later use. */
3456 if (recog_memoized (EXPR_INSN_RTX (expr)) < 0)
3458 /* If we have a USE in *AV_PTR that was not scheduled yet,
3459 do so because it will do good only. */
3460 if (EXPR_SCHED_TIMES (expr) <= 0)
3462 if (EXPR_TARGET_AVAILABLE (expr) == 1)
3465 av_set_iter_remove (&si);
3469 gcc_assert (pipelining_p);
3471 uses_present_p = true;
3480 /* If we don't want to schedule any USEs right now and we have some
3481 in *AV_PTR, remove them, else just return the first one found. */
3484 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3485 if (INSN_CODE (EXPR_INSN_RTX (expr)) < 0)
3486 av_set_iter_remove (&si);
3490 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3492 gcc_assert (INSN_CODE (EXPR_INSN_RTX (expr)) < 0);
3494 if (EXPR_TARGET_AVAILABLE (expr) == 1)
3497 av_set_iter_remove (&si);
3505 /* Lookup EXPR in VINSN_VEC and return TRUE if found. */
3507 vinsn_vec_has_expr_p (vinsn_vec_t vinsn_vec, expr_t expr)
3512 for (n = 0; VEC_iterate (vinsn_t, vinsn_vec, n, vinsn); n++)
3513 if (VINSN_SEPARABLE_P (vinsn))
3515 if (vinsn_equal_p (vinsn, EXPR_VINSN (expr)))
3520 /* For non-separable instructions, the blocking insn can have
3521 another pattern due to substitution, and we can't choose
3522 different register as in the above case. Check all registers
3523 being written instead. */
3524 if (bitmap_intersect_p (VINSN_REG_SETS (vinsn),
3525 VINSN_REG_SETS (EXPR_VINSN (expr))))
3532 #ifdef ENABLE_CHECKING
3533 /* Return true if either of expressions from ORIG_OPS can be blocked
3534 by previously created bookkeeping code. STATIC_PARAMS points to static
3535 parameters of move_op. */
3537 av_set_could_be_blocked_by_bookkeeping_p (av_set_t orig_ops, void *static_params)
3540 av_set_iterator iter;
3541 moveop_static_params_p sparams;
3543 /* This checks that expressions in ORIG_OPS are not blocked by bookkeeping
3544 created while scheduling on another fence. */
3545 FOR_EACH_EXPR (expr, iter, orig_ops)
3546 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns, expr))
3549 gcc_assert (code_motion_path_driver_info == &move_op_hooks);
3550 sparams = (moveop_static_params_p) static_params;
3552 /* Expressions can be also blocked by bookkeeping created during current
3554 if (bitmap_bit_p (current_copies, INSN_UID (sparams->failed_insn)))
3555 FOR_EACH_EXPR (expr, iter, orig_ops)
3556 if (moveup_expr_cached (expr, sparams->failed_insn, false) != MOVEUP_EXPR_NULL)
3559 /* Expressions in ORIG_OPS may have wrong destination register due to
3560 renaming. Check with the right register instead. */
3561 if (sparams->dest && REG_P (sparams->dest))
3563 unsigned regno = REGNO (sparams->dest);
3564 vinsn_t failed_vinsn = INSN_VINSN (sparams->failed_insn);
3566 if (bitmap_bit_p (VINSN_REG_SETS (failed_vinsn), regno)
3567 || bitmap_bit_p (VINSN_REG_USES (failed_vinsn), regno)
3568 || bitmap_bit_p (VINSN_REG_CLOBBERS (failed_vinsn), regno))
3576 /* Clear VINSN_VEC and detach vinsns. */
3578 vinsn_vec_clear (vinsn_vec_t *vinsn_vec)
3580 unsigned len = VEC_length (vinsn_t, *vinsn_vec);
3586 for (n = 0; VEC_iterate (vinsn_t, *vinsn_vec, n, vinsn); n++)
3587 vinsn_detach (vinsn);
3588 VEC_block_remove (vinsn_t, *vinsn_vec, 0, len);
3592 /* Add the vinsn of EXPR to the VINSN_VEC. */
3594 vinsn_vec_add (vinsn_vec_t *vinsn_vec, expr_t expr)
3596 vinsn_attach (EXPR_VINSN (expr));
3597 VEC_safe_push (vinsn_t, heap, *vinsn_vec, EXPR_VINSN (expr));
3600 /* Free the vector representing blocked expressions. */
3602 vinsn_vec_free (vinsn_vec_t *vinsn_vec)
3605 VEC_free (vinsn_t, heap, *vinsn_vec);
3608 /* Increase EXPR_PRIORITY_ADJ for INSN by AMOUNT. */
3610 void sel_add_to_insn_priority (rtx insn, int amount)
3612 EXPR_PRIORITY_ADJ (INSN_EXPR (insn)) += amount;
3614 if (sched_verbose >= 2)
3615 sel_print ("sel_add_to_insn_priority: insn %d, by %d (now %d+%d).\n",
3616 INSN_UID (insn), amount, EXPR_PRIORITY (INSN_EXPR (insn)),
3617 EXPR_PRIORITY_ADJ (INSN_EXPR (insn)));
3620 /* Turn AV into a vector, filter inappropriate insns and sort it. Return
3621 true if there is something to schedule. BNDS and FENCE are current
3622 boundaries and fence, respectively. If we need to stall for some cycles
3623 before an expr from AV would become available, write this number to
3626 fill_vec_av_set (av_set_t av, blist_t bnds, fence_t fence,
3631 int sched_next_worked = 0, stalled, n;
3632 static int av_max_prio, est_ticks_till_branch;
3633 int min_need_stall = -1;
3634 deps_t dc = BND_DC (BLIST_BND (bnds));
3636 /* Bail out early when the ready list contained only USEs/CLOBBERs that are
3637 already scheduled. */
3641 /* Empty vector from the previous stuff. */
3642 if (VEC_length (expr_t, vec_av_set) > 0)
3643 VEC_block_remove (expr_t, vec_av_set, 0, VEC_length (expr_t, vec_av_set));
3645 /* Turn the set into a vector for sorting and call sel_target_adjust_priority
3647 gcc_assert (VEC_empty (expr_t, vec_av_set));
3648 FOR_EACH_EXPR (expr, si, av)
3650 VEC_safe_push (expr_t, heap, vec_av_set, expr);
3652 gcc_assert (EXPR_PRIORITY_ADJ (expr) == 0 || *pneed_stall);
3654 /* Adjust priority using target backend hook. */
3655 sel_target_adjust_priority (expr);
3658 /* Sort the vector. */
3659 qsort (VEC_address (expr_t, vec_av_set), VEC_length (expr_t, vec_av_set),
3660 sizeof (expr_t), sel_rank_for_schedule);
3662 /* We record maximal priority of insns in av set for current instruction
3664 if (FENCE_STARTS_CYCLE_P (fence))
3665 av_max_prio = est_ticks_till_branch = INT_MIN;
3667 /* Filter out inappropriate expressions. Loop's direction is reversed to
3668 visit "best" instructions first. We assume that VEC_unordered_remove
3669 moves last element in place of one being deleted. */
3670 for (n = VEC_length (expr_t, vec_av_set) - 1, stalled = 0; n >= 0; n--)
3672 expr_t expr = VEC_index (expr_t, vec_av_set, n);
3673 insn_t insn = EXPR_INSN_RTX (expr);
3674 char target_available;
3675 bool is_orig_reg_p = true;
3676 int need_cycles, new_prio;
3678 /* Don't allow any insns other than from SCHED_GROUP if we have one. */
3679 if (FENCE_SCHED_NEXT (fence) && insn != FENCE_SCHED_NEXT (fence))
3681 VEC_unordered_remove (expr_t, vec_av_set, n);
3685 /* Set number of sched_next insns (just in case there
3686 could be several). */
3687 if (FENCE_SCHED_NEXT (fence))
3688 sched_next_worked++;
3690 /* Check all liveness requirements and try renaming.
3691 FIXME: try to minimize calls to this. */
3692 target_available = EXPR_TARGET_AVAILABLE (expr);
3694 /* If insn was already scheduled on the current fence,
3695 set TARGET_AVAILABLE to -1 no matter what expr's attribute says. */
3696 if (vinsn_vec_has_expr_p (vec_target_unavailable_vinsns, expr))
3697 target_available = -1;
3699 /* If the availability of the EXPR is invalidated by the insertion of
3700 bookkeeping earlier, make sure that we won't choose this expr for
3701 scheduling if it's not separable, and if it is separable, then
3702 we have to recompute the set of available registers for it. */
3703 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns, expr))
3705 VEC_unordered_remove (expr_t, vec_av_set, n);
3706 if (sched_verbose >= 4)
3707 sel_print ("Expr %d is blocked by bookkeeping inserted earlier\n",
3712 if (target_available == true)
3714 /* Do nothing -- we can use an existing register. */
3715 is_orig_reg_p = EXPR_SEPARABLE_P (expr);
3717 else if (/* Non-separable instruction will never
3718 get another register. */
3719 (target_available == false
3720 && !EXPR_SEPARABLE_P (expr))
3721 /* Don't try to find a register for low-priority expression. */
3722 || (int) VEC_length (expr_t, vec_av_set) - 1 - n >= max_insns_to_rename
3723 /* ??? FIXME: Don't try to rename data speculation. */
3724 || (EXPR_SPEC_DONE_DS (expr) & BEGIN_DATA)
3725 || ! find_best_reg_for_expr (expr, bnds, &is_orig_reg_p))
3727 VEC_unordered_remove (expr_t, vec_av_set, n);
3728 if (sched_verbose >= 4)
3729 sel_print ("Expr %d has no suitable target register\n",
3734 /* Filter expressions that need to be renamed or speculated when
3735 pipelining, because compensating register copies or speculation
3736 checks are likely to be placed near the beginning of the loop,
3738 if (pipelining_p && EXPR_ORIG_SCHED_CYCLE (expr) > 0
3739 && (!is_orig_reg_p || EXPR_SPEC_DONE_DS (expr) != 0))
3741 /* Estimation of number of cycles until loop branch for
3742 renaming/speculation to be successful. */
3743 int need_n_ticks_till_branch = sel_vinsn_cost (EXPR_VINSN (expr));
3745 if ((int) current_loop_nest->ninsns < 9)
3747 VEC_unordered_remove (expr_t, vec_av_set, n);
3748 if (sched_verbose >= 4)
3749 sel_print ("Pipelining expr %d will likely cause stall\n",
3754 if ((int) current_loop_nest->ninsns - num_insns_scheduled
3755 < need_n_ticks_till_branch * issue_rate / 2
3756 && est_ticks_till_branch < need_n_ticks_till_branch)
3758 VEC_unordered_remove (expr_t, vec_av_set, n);
3759 if (sched_verbose >= 4)
3760 sel_print ("Pipelining expr %d will likely cause stall\n",
3766 /* We want to schedule speculation checks as late as possible. Discard
3767 them from av set if there are instructions with higher priority. */
3768 if (sel_insn_is_speculation_check (insn)
3769 && EXPR_PRIORITY (expr) < av_max_prio)
3772 min_need_stall = min_need_stall < 0 ? 1 : MIN (min_need_stall, 1);
3773 VEC_unordered_remove (expr_t, vec_av_set, n);
3774 if (sched_verbose >= 4)
3775 sel_print ("Delaying speculation check %d until its first use\n",
3780 /* Ignore EXPRs available from pipelining to update AV_MAX_PRIO. */
3781 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3782 av_max_prio = MAX (av_max_prio, EXPR_PRIORITY (expr));
3784 /* Don't allow any insns whose data is not yet ready.
3785 Check first whether we've already tried them and failed. */
3786 if (INSN_UID (insn) < FENCE_READY_TICKS_SIZE (fence))
3788 need_cycles = (FENCE_READY_TICKS (fence)[INSN_UID (insn)]
3789 - FENCE_CYCLE (fence));
3790 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3791 est_ticks_till_branch = MAX (est_ticks_till_branch,
3792 EXPR_PRIORITY (expr) + need_cycles);
3794 if (need_cycles > 0)
3797 min_need_stall = (min_need_stall < 0
3799 : MIN (min_need_stall, need_cycles));
3800 VEC_unordered_remove (expr_t, vec_av_set, n);
3802 if (sched_verbose >= 4)
3803 sel_print ("Expr %d is not ready until cycle %d (cached)\n",
3805 FENCE_READY_TICKS (fence)[INSN_UID (insn)]);
3810 /* Now resort to dependence analysis to find whether EXPR might be
3811 stalled due to dependencies from FENCE's context. */
3812 need_cycles = tick_check_p (expr, dc, fence);
3813 new_prio = EXPR_PRIORITY (expr) + EXPR_PRIORITY_ADJ (expr) + need_cycles;
3815 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3816 est_ticks_till_branch = MAX (est_ticks_till_branch,
3819 if (need_cycles > 0)
3821 if (INSN_UID (insn) >= FENCE_READY_TICKS_SIZE (fence))
3823 int new_size = INSN_UID (insn) * 3 / 2;
3825 FENCE_READY_TICKS (fence)
3826 = (int *) xrecalloc (FENCE_READY_TICKS (fence),
3827 new_size, FENCE_READY_TICKS_SIZE (fence),
3830 FENCE_READY_TICKS (fence)[INSN_UID (insn)]
3831 = FENCE_CYCLE (fence) + need_cycles;
3834 min_need_stall = (min_need_stall < 0
3836 : MIN (min_need_stall, need_cycles));
3838 VEC_unordered_remove (expr_t, vec_av_set, n);
3840 if (sched_verbose >= 4)
3841 sel_print ("Expr %d is not ready yet until cycle %d\n",
3843 FENCE_READY_TICKS (fence)[INSN_UID (insn)]);
3847 if (sched_verbose >= 4)
3848 sel_print ("Expr %d is ok\n", INSN_UID (insn));
3852 /* Clear SCHED_NEXT. */
3853 if (FENCE_SCHED_NEXT (fence))
3855 gcc_assert (sched_next_worked == 1);
3856 FENCE_SCHED_NEXT (fence) = NULL_RTX;
3859 /* No need to stall if this variable was not initialized. */
3860 if (min_need_stall < 0)
3863 if (VEC_empty (expr_t, vec_av_set))
3865 /* We need to set *pneed_stall here, because later we skip this code
3866 when ready list is empty. */
3867 *pneed_stall = min_need_stall;
3871 gcc_assert (min_need_stall == 0);
3873 /* Sort the vector. */
3874 qsort (VEC_address (expr_t, vec_av_set), VEC_length (expr_t, vec_av_set),
3875 sizeof (expr_t), sel_rank_for_schedule);
3877 if (sched_verbose >= 4)
3879 sel_print ("Total ready exprs: %d, stalled: %d\n",
3880 VEC_length (expr_t, vec_av_set), stalled);
3881 sel_print ("Sorted av set (%d): ", VEC_length (expr_t, vec_av_set));
3882 for (n = 0; VEC_iterate (expr_t, vec_av_set, n, expr); n++)
3891 /* Convert a vectored and sorted av set to the ready list that
3892 the rest of the backend wants to see. */
3894 convert_vec_av_set_to_ready (void)
3899 /* Allocate and fill the ready list from the sorted vector. */
3900 ready.n_ready = VEC_length (expr_t, vec_av_set);
3901 ready.first = ready.n_ready - 1;
3903 gcc_assert (ready.n_ready > 0);
3905 if (ready.n_ready > max_issue_size)
3907 max_issue_size = ready.n_ready;
3908 sched_extend_ready_list (ready.n_ready);
3911 for (n = 0; VEC_iterate (expr_t, vec_av_set, n, expr); n++)
3913 vinsn_t vi = EXPR_VINSN (expr);
3914 insn_t insn = VINSN_INSN_RTX (vi);
3917 ready.vec[n] = insn;
3921 /* Initialize ready list from *AV_PTR for the max_issue () call.
3922 If any unrecognizable insn found in *AV_PTR, return it (and skip
3923 max_issue). BND and FENCE are current boundary and fence,
3924 respectively. If we need to stall for some cycles before an expr
3925 from *AV_PTR would become available, write this number to *PNEED_STALL. */
3927 fill_ready_list (av_set_t *av_ptr, blist_t bnds, fence_t fence,
3932 /* We do not support multiple boundaries per fence. */
3933 gcc_assert (BLIST_NEXT (bnds) == NULL);
3935 /* Process expressions required special handling, i.e. pipelined,
3936 speculative and recog() < 0 expressions first. */
3937 process_pipelined_exprs (av_ptr);
3938 process_spec_exprs (av_ptr);
3940 /* A USE could be scheduled immediately. */
3941 expr = process_use_exprs (av_ptr);
3948 /* Turn the av set to a vector for sorting. */
3949 if (! fill_vec_av_set (*av_ptr, bnds, fence, pneed_stall))
3955 /* Build the final ready list. */
3956 convert_vec_av_set_to_ready ();
3960 /* Wrapper for dfa_new_cycle (). Returns TRUE if cycle was advanced. */
3962 sel_dfa_new_cycle (insn_t insn, fence_t fence)
3964 int last_scheduled_cycle = FENCE_LAST_SCHEDULED_INSN (fence)
3965 ? INSN_SCHED_CYCLE (FENCE_LAST_SCHEDULED_INSN (fence))
3966 : FENCE_CYCLE (fence) - 1;
3970 if (!targetm.sched.dfa_new_cycle)
3973 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
3975 while (!sort_p && targetm.sched.dfa_new_cycle (sched_dump, sched_verbose,
3976 insn, last_scheduled_cycle,
3977 FENCE_CYCLE (fence), &sort_p))
3979 memcpy (FENCE_STATE (fence), curr_state, dfa_state_size);
3980 advance_one_cycle (fence);
3981 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
3988 /* Invoke reorder* target hooks on the ready list. Return the number of insns
3989 we can issue. FENCE is the current fence. */
3991 invoke_reorder_hooks (fence_t fence)
3994 bool ran_hook = false;
3996 /* Call the reorder hook at the beginning of the cycle, and call
3997 the reorder2 hook in the middle of the cycle. */
3998 if (FENCE_ISSUED_INSNS (fence) == 0)
4000 if (targetm.sched.reorder
4001 && !SCHED_GROUP_P (ready_element (&ready, 0))
4002 && ready.n_ready > 1)
4004 /* Don't give reorder the most prioritized insn as it can break
4010 = targetm.sched.reorder (sched_dump, sched_verbose,
4011 ready_lastpos (&ready),
4012 &ready.n_ready, FENCE_CYCLE (fence));
4020 /* Initialize can_issue_more for variable_issue. */
4021 issue_more = issue_rate;
4023 else if (targetm.sched.reorder2
4024 && !SCHED_GROUP_P (ready_element (&ready, 0)))
4026 if (ready.n_ready == 1)
4028 targetm.sched.reorder2 (sched_dump, sched_verbose,
4029 ready_lastpos (&ready),
4030 &ready.n_ready, FENCE_CYCLE (fence));
4037 targetm.sched.reorder2 (sched_dump, sched_verbose,
4039 ? ready_lastpos (&ready) : NULL,
4040 &ready.n_ready, FENCE_CYCLE (fence));
4049 issue_more = FENCE_ISSUE_MORE (fence);
4051 /* Ensure that ready list and vec_av_set are in line with each other,
4052 i.e. vec_av_set[i] == ready_element (&ready, i). */
4053 if (issue_more && ran_hook)
4056 rtx *arr = ready.vec;
4057 expr_t *vec = VEC_address (expr_t, vec_av_set);
4059 for (i = 0, n = ready.n_ready; i < n; i++)
4060 if (EXPR_INSN_RTX (vec[i]) != arr[i])
4064 for (j = i; j < n; j++)
4065 if (EXPR_INSN_RTX (vec[j]) == arr[i])
4078 /* Return an EXPR correponding to INDEX element of ready list, if
4079 FOLLOW_READY_ELEMENT is true (i.e., an expr of
4080 ready_element (&ready, INDEX) will be returned), and to INDEX element of
4081 ready.vec otherwise. */
4082 static inline expr_t
4083 find_expr_for_ready (int index, bool follow_ready_element)
4088 real_index = follow_ready_element ? ready.first - index : index;
4090 expr = VEC_index (expr_t, vec_av_set, real_index);
4091 gcc_assert (ready.vec[real_index] == EXPR_INSN_RTX (expr));
4096 /* Calculate insns worth trying via lookahead_guard hook. Return a number
4097 of such insns found. */
4099 invoke_dfa_lookahead_guard (void)
4103 = targetm.sched.first_cycle_multipass_dfa_lookahead_guard != NULL;
4105 if (sched_verbose >= 2)
4106 sel_print ("ready after reorder: ");
4108 for (i = 0, n = 0; i < ready.n_ready; i++)
4114 /* In this loop insn is Ith element of the ready list given by
4115 ready_element, not Ith element of ready.vec. */
4116 insn = ready_element (&ready, i);
4118 if (! have_hook || i == 0)
4121 r = !targetm.sched.first_cycle_multipass_dfa_lookahead_guard (insn);
4123 gcc_assert (INSN_CODE (insn) >= 0);
4125 /* Only insns with ready_try = 0 can get here
4126 from fill_ready_list. */
4127 gcc_assert (ready_try [i] == 0);
4132 expr = find_expr_for_ready (i, true);
4134 if (sched_verbose >= 2)
4136 dump_vinsn (EXPR_VINSN (expr));
4137 sel_print (":%d; ", ready_try[i]);
4141 if (sched_verbose >= 2)
4146 /* Calculate the number of privileged insns and return it. */
4148 calculate_privileged_insns (void)
4150 expr_t cur_expr, min_spec_expr = NULL;
4151 insn_t cur_insn, min_spec_insn;
4152 int privileged_n = 0, i;
4154 for (i = 0; i < ready.n_ready; i++)
4159 if (! min_spec_expr)
4161 min_spec_insn = ready_element (&ready, i);
4162 min_spec_expr = find_expr_for_ready (i, true);
4165 cur_insn = ready_element (&ready, i);
4166 cur_expr = find_expr_for_ready (i, true);
4168 if (EXPR_SPEC (cur_expr) > EXPR_SPEC (min_spec_expr))
4174 if (i == ready.n_ready)
4177 if (sched_verbose >= 2)
4178 sel_print ("privileged_n: %d insns with SPEC %d\n",
4179 privileged_n, privileged_n ? EXPR_SPEC (min_spec_expr) : -1);
4180 return privileged_n;
4183 /* Call the rest of the hooks after the choice was made. Return
4184 the number of insns that still can be issued given that the current
4185 number is ISSUE_MORE. FENCE and BEST_INSN are the current fence
4186 and the insn chosen for scheduling, respectively. */
4188 invoke_aftermath_hooks (fence_t fence, rtx best_insn, int issue_more)
4190 gcc_assert (INSN_P (best_insn));
4192 /* First, call dfa_new_cycle, and then variable_issue, if available. */
4193 sel_dfa_new_cycle (best_insn, fence);
4195 if (targetm.sched.variable_issue)
4197 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
4199 targetm.sched.variable_issue (sched_dump, sched_verbose, best_insn,
4201 memcpy (FENCE_STATE (fence), curr_state, dfa_state_size);
4203 else if (GET_CODE (PATTERN (best_insn)) != USE
4204 && GET_CODE (PATTERN (best_insn)) != CLOBBER)
4210 /* Estimate the cost of issuing INSN on DFA state STATE. */
4212 estimate_insn_cost (rtx insn, state_t state)
4214 static state_t temp = NULL;
4218 temp = xmalloc (dfa_state_size);
4220 memcpy (temp, state, dfa_state_size);
4221 cost = state_transition (temp, insn);
4230 /* Return the cost of issuing EXPR on the FENCE as estimated by DFA.
4231 This function properly handles ASMs, USEs etc. */
4233 get_expr_cost (expr_t expr, fence_t fence)
4235 rtx insn = EXPR_INSN_RTX (expr);
4237 if (recog_memoized (insn) < 0)
4239 if (!FENCE_STARTS_CYCLE_P (fence)
4240 && INSN_ASM_P (insn))
4241 /* This is asm insn which is tryed to be issued on the
4242 cycle not first. Issue it on the next cycle. */
4245 /* A USE insn, or something else we don't need to
4246 understand. We can't pass these directly to
4247 state_transition because it will trigger a
4248 fatal error for unrecognizable insns. */
4252 return estimate_insn_cost (insn, FENCE_STATE (fence));
4255 /* Find the best insn for scheduling, either via max_issue or just take
4256 the most prioritized available. */
4258 choose_best_insn (fence_t fence, int privileged_n, int *index)
4262 if (dfa_lookahead > 0)
4264 cycle_issued_insns = FENCE_ISSUED_INSNS (fence);
4265 can_issue = max_issue (&ready, privileged_n,
4266 FENCE_STATE (fence), index);
4267 if (sched_verbose >= 2)
4268 sel_print ("max_issue: we can issue %d insns, already did %d insns\n",
4269 can_issue, FENCE_ISSUED_INSNS (fence));
4273 /* We can't use max_issue; just return the first available element. */
4276 for (i = 0; i < ready.n_ready; i++)
4278 expr_t expr = find_expr_for_ready (i, true);
4280 if (get_expr_cost (expr, fence) < 1)
4282 can_issue = can_issue_more;
4285 if (sched_verbose >= 2)
4286 sel_print ("using %dth insn from the ready list\n", i + 1);
4292 if (i == ready.n_ready)
4302 /* Choose the best expr from *AV_VLIW_PTR and a suitable register for it.
4303 BNDS and FENCE are current boundaries and scheduling fence respectively.
4304 Return the expr found and NULL if nothing can be issued atm.
4305 Write to PNEED_STALL the number of cycles to stall if no expr was found. */
4307 find_best_expr (av_set_t *av_vliw_ptr, blist_t bnds, fence_t fence,
4312 /* Choose the best insn for scheduling via:
4313 1) sorting the ready list based on priority;
4314 2) calling the reorder hook;
4315 3) calling max_issue. */
4316 best = fill_ready_list (av_vliw_ptr, bnds, fence, pneed_stall);
4317 if (best == NULL && ready.n_ready > 0)
4319 int privileged_n, index, avail_n;
4321 can_issue_more = invoke_reorder_hooks (fence);
4322 if (can_issue_more > 0)
4324 /* Try choosing the best insn until we find one that is could be
4325 scheduled due to liveness restrictions on its destination register.
4326 In the future, we'd like to choose once and then just probe insns
4327 in the order of their priority. */
4328 avail_n = invoke_dfa_lookahead_guard ();
4329 privileged_n = calculate_privileged_insns ();
4330 can_issue_more = choose_best_insn (fence, privileged_n, &index);
4332 best = find_expr_for_ready (index, true);
4334 /* We had some available insns, so if we can't issue them,
4336 if (can_issue_more == 0)
4345 can_issue_more = invoke_aftermath_hooks (fence, EXPR_INSN_RTX (best),
4347 if (can_issue_more == 0)
4351 if (sched_verbose >= 2)
4355 sel_print ("Best expression (vliw form): ");
4357 sel_print ("; cycle %d\n", FENCE_CYCLE (fence));
4360 sel_print ("No best expr found!\n");
4367 /* Functions that implement the core of the scheduler. */
4370 /* Emit an instruction from EXPR with SEQNO and VINSN after
4373 emit_insn_from_expr_after (expr_t expr, vinsn_t vinsn, int seqno,
4374 insn_t place_to_insert)
4376 /* This assert fails when we have identical instructions
4377 one of which dominates the other. In this case move_op ()
4378 finds the first instruction and doesn't search for second one.
4379 The solution would be to compute av_set after the first found
4380 insn and, if insn present in that set, continue searching.
4381 For now we workaround this issue in move_op. */
4382 gcc_assert (!INSN_IN_STREAM_P (EXPR_INSN_RTX (expr)));
4384 if (EXPR_WAS_RENAMED (expr))
4386 unsigned regno = expr_dest_regno (expr);
4388 if (HARD_REGISTER_NUM_P (regno))
4390 df_set_regs_ever_live (regno, true);
4391 reg_rename_tick[regno] = ++reg_rename_this_tick;
4395 return sel_gen_insn_from_expr_after (expr, vinsn, seqno,
4399 /* Return TRUE if BB can hold bookkeeping code. */
4401 block_valid_for_bookkeeping_p (basic_block bb)
4403 insn_t bb_end = BB_END (bb);
4405 if (!in_current_region_p (bb) || EDGE_COUNT (bb->succs) > 1)
4408 if (INSN_P (bb_end))
4410 if (INSN_SCHED_TIMES (bb_end) > 0)
4414 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (bb_end));
4419 /* Attempt to find a block that can hold bookkeeping code for path(s) incoming
4420 into E2->dest, except from E1->src (there may be a sequence of empty basic
4421 blocks between E1->src and E2->dest). Return found block, or NULL if new
4422 one must be created. */
4424 find_block_for_bookkeeping (edge e1, edge e2)
4426 basic_block candidate_block = NULL;
4429 /* Loop over edges from E1 to E2, inclusive. */
4430 for (e = e1; ; e = EDGE_SUCC (e->dest, 0))
4432 if (EDGE_COUNT (e->dest->preds) == 2)
4434 if (candidate_block == NULL)
4435 candidate_block = (EDGE_PRED (e->dest, 0) == e
4436 ? EDGE_PRED (e->dest, 1)->src
4437 : EDGE_PRED (e->dest, 0)->src);
4439 /* Found additional edge leading to path from e1 to e2
4443 else if (EDGE_COUNT (e->dest->preds) > 2)
4444 /* Several edges leading to path from e1 to e2 from aside. */
4448 return (block_valid_for_bookkeeping_p (candidate_block)
4455 /* Create new basic block for bookkeeping code for path(s) incoming into
4456 E2->dest, except from E1->src. Return created block. */
4458 create_block_for_bookkeeping (edge e1, edge e2)
4460 basic_block new_bb, bb = e2->dest;
4462 /* Check that we don't spoil the loop structure. */
4463 if (current_loop_nest)
4465 basic_block latch = current_loop_nest->latch;
4467 /* We do not split header. */
4468 gcc_assert (e2->dest != current_loop_nest->header);
4470 /* We do not redirect the only edge to the latch block. */
4471 gcc_assert (e1->dest != latch
4472 || !single_pred_p (latch)
4473 || e1 != single_pred_edge (latch));
4476 /* Split BB to insert BOOK_INSN there. */
4477 new_bb = sched_split_block (bb, NULL);
4479 /* Move note_list from the upper bb. */
4480 gcc_assert (BB_NOTE_LIST (new_bb) == NULL_RTX);
4481 BB_NOTE_LIST (new_bb) = BB_NOTE_LIST (bb);
4482 BB_NOTE_LIST (bb) = NULL_RTX;
4484 gcc_assert (e2->dest == bb);
4486 /* Skip block for bookkeeping copy when leaving E1->src. */
4487 if (e1->flags & EDGE_FALLTHRU)
4488 sel_redirect_edge_and_branch_force (e1, new_bb);
4490 sel_redirect_edge_and_branch (e1, new_bb);
4492 gcc_assert (e1->dest == new_bb);
4493 gcc_assert (sel_bb_empty_p (bb));
4498 /* Return insn after which we must insert bookkeeping code for path(s) incoming
4499 into E2->dest, except from E1->src. */
4501 find_place_for_bookkeeping (edge e1, edge e2)
4503 insn_t place_to_insert;
4504 /* Find a basic block that can hold bookkeeping. If it can be found, do not
4505 create new basic block, but insert bookkeeping there. */
4506 basic_block book_block = find_block_for_bookkeeping (e1, e2);
4509 book_block = create_block_for_bookkeeping (e1, e2);
4511 place_to_insert = BB_END (book_block);
4513 /* If basic block ends with a jump, insert bookkeeping code right before it. */
4514 if (INSN_P (place_to_insert) && control_flow_insn_p (place_to_insert))
4515 place_to_insert = PREV_INSN (place_to_insert);
4517 return place_to_insert;
4520 /* Find a proper seqno for bookkeeing insn inserted at PLACE_TO_INSERT
4523 find_seqno_for_bookkeeping (insn_t place_to_insert, insn_t join_point)
4528 /* Check if we are about to insert bookkeeping copy before a jump, and use
4529 jump's seqno for the copy; otherwise, use JOIN_POINT's seqno. */
4530 next = NEXT_INSN (place_to_insert);
4533 && BLOCK_FOR_INSN (next) == BLOCK_FOR_INSN (place_to_insert))
4535 gcc_assert (INSN_SCHED_TIMES (next) == 0);
4536 seqno = INSN_SEQNO (next);
4538 else if (INSN_SEQNO (join_point) > 0)
4539 seqno = INSN_SEQNO (join_point);
4542 seqno = get_seqno_by_preds (place_to_insert);
4544 /* Sometimes the fences can move in such a way that there will be
4545 no instructions with positive seqno around this bookkeeping.
4546 This means that there will be no way to get to it by a regular
4547 fence movement. Never mind because we pick up such pieces for
4548 rescheduling anyways, so any positive value will do for now. */
4551 gcc_assert (pipelining_p);
4556 gcc_assert (seqno > 0);
4560 /* Insert bookkeeping copy of C_EXPS's insn after PLACE_TO_INSERT, assigning
4561 NEW_SEQNO to it. Return created insn. */
4563 emit_bookkeeping_insn (insn_t place_to_insert, expr_t c_expr, int new_seqno)
4565 rtx new_insn_rtx = create_copy_of_insn_rtx (EXPR_INSN_RTX (c_expr));
4568 = create_vinsn_from_insn_rtx (new_insn_rtx,
4569 VINSN_UNIQUE_P (EXPR_VINSN (c_expr)));
4571 insn_t new_insn = emit_insn_from_expr_after (c_expr, new_vinsn, new_seqno,
4574 INSN_SCHED_TIMES (new_insn) = 0;
4575 bitmap_set_bit (current_copies, INSN_UID (new_insn));
4580 /* Generate a bookkeeping copy of C_EXPR's insn for path(s) incoming into to
4581 E2->dest, except from E1->src (there may be a sequence of empty blocks
4582 between E1->src and E2->dest). Return block containing the copy.
4583 All scheduler data is initialized for the newly created insn. */
4585 generate_bookkeeping_insn (expr_t c_expr, edge e1, edge e2)
4587 insn_t join_point, place_to_insert, new_insn;
4589 bool need_to_exchange_data_sets;
4591 if (sched_verbose >= 4)
4592 sel_print ("Generating bookkeeping insn (%d->%d)\n", e1->src->index,
4595 join_point = sel_bb_head (e2->dest);
4596 place_to_insert = find_place_for_bookkeeping (e1, e2);
4597 new_seqno = find_seqno_for_bookkeeping (place_to_insert, join_point);
4598 need_to_exchange_data_sets
4599 = sel_bb_empty_p (BLOCK_FOR_INSN (place_to_insert));
4601 new_insn = emit_bookkeeping_insn (place_to_insert, c_expr, new_seqno);
4603 /* When inserting bookkeeping insn in new block, av sets should be
4604 following: old basic block (that now holds bookkeeping) data sets are
4605 the same as was before generation of bookkeeping, and new basic block
4606 (that now hold all other insns of old basic block) data sets are
4607 invalid. So exchange data sets for these basic blocks as sel_split_block
4608 mistakenly exchanges them in this case. Cannot do it earlier because
4609 when single instruction is added to new basic block it should hold NULL
4611 if (need_to_exchange_data_sets)
4612 exchange_data_sets (BLOCK_FOR_INSN (new_insn),
4613 BLOCK_FOR_INSN (join_point));
4615 stat_bookkeeping_copies++;
4616 return BLOCK_FOR_INSN (new_insn);
4619 /* Remove from AV_PTR all insns that may need bookkeeping when scheduling
4620 on FENCE, but we are unable to copy them. */
4622 remove_insns_that_need_bookkeeping (fence_t fence, av_set_t *av_ptr)
4627 /* An expression does not need bookkeeping if it is available on all paths
4628 from current block to original block and current block dominates
4629 original block. We check availability on all paths by examining
4630 EXPR_SPEC; this is not equivalent, because it may be positive even
4631 if expr is available on all paths (but if expr is not available on
4632 any path, EXPR_SPEC will be positive). */
4634 FOR_EACH_EXPR_1 (expr, i, av_ptr)
4636 if (!control_flow_insn_p (EXPR_INSN_RTX (expr))
4637 && (!bookkeeping_p || VINSN_UNIQUE_P (EXPR_VINSN (expr)))
4638 && (EXPR_SPEC (expr)
4639 || !EXPR_ORIG_BB_INDEX (expr)
4640 || !dominated_by_p (CDI_DOMINATORS,
4641 BASIC_BLOCK (EXPR_ORIG_BB_INDEX (expr)),
4642 BLOCK_FOR_INSN (FENCE_INSN (fence)))))
4644 if (sched_verbose >= 4)
4645 sel_print ("Expr %d removed because it would need bookkeeping, which "
4646 "cannot be created\n", INSN_UID (EXPR_INSN_RTX (expr)));
4647 av_set_iter_remove (&i);
4652 /* Moving conditional jump through some instructions.
4656 ... <- current scheduling point
4657 NOTE BASIC BLOCK: <- bb header
4658 (p8) add r14=r14+0x9;;
4664 We can schedule jump one cycle earlier, than mov, because they cannot be
4665 executed together as their predicates are mutually exclusive.
4667 This is done in this way: first, new fallthrough basic block is created
4668 after jump (it is always can be done, because there already should be a
4669 fallthrough block, where control flow goes in case of predicate being true -
4670 in our example; otherwise there should be a dependence between those
4671 instructions and jump and we cannot schedule jump right now);
4672 next, all instructions between jump and current scheduling point are moved
4673 to this new block. And the result is this:
4676 (!p8) jump L1 <- current scheduling point
4677 NOTE BASIC BLOCK: <- bb header
4678 (p8) add r14=r14+0x9;;
4684 move_cond_jump (rtx insn, bnd_t bnd)
4687 basic_block block_from, block_next, block_new, block_bnd, bb;
4688 rtx next, prev, link, head;
4690 block_from = BLOCK_FOR_INSN (insn);
4691 block_bnd = BLOCK_FOR_INSN (BND_TO (bnd));
4692 prev = BND_TO (bnd);
4694 #ifdef ENABLE_CHECKING
4695 /* Moving of jump should not cross any other jumps or beginnings of new
4696 basic blocks. The only exception is when we move a jump through
4697 mutually exclusive insns along fallthru edges. */
4698 if (block_from != block_bnd)
4701 for (link = PREV_INSN (insn); link != PREV_INSN (prev);
4702 link = PREV_INSN (link))
4705 gcc_assert (sched_insns_conditions_mutex_p (insn, link));
4706 if (BLOCK_FOR_INSN (link) && BLOCK_FOR_INSN (link) != bb)
4708 gcc_assert (single_pred (bb) == BLOCK_FOR_INSN (link));
4709 bb = BLOCK_FOR_INSN (link);
4715 /* Jump is moved to the boundary. */
4716 next = PREV_INSN (insn);
4717 BND_TO (bnd) = insn;
4719 ft_edge = find_fallthru_edge (block_from);
4720 block_next = ft_edge->dest;
4721 /* There must be a fallthrough block (or where should go
4722 control flow in case of false jump predicate otherwise?). */
4723 gcc_assert (block_next);
4725 /* Create new empty basic block after source block. */
4726 block_new = sel_split_edge (ft_edge);
4727 gcc_assert (block_new->next_bb == block_next
4728 && block_from->next_bb == block_new);
4730 /* Move all instructions except INSN to BLOCK_NEW. */
4732 head = BB_HEAD (block_new);
4733 while (bb != block_from->next_bb)
4736 from = bb == block_bnd ? prev : sel_bb_head (bb);
4737 to = bb == block_from ? next : sel_bb_end (bb);
4739 /* The jump being moved can be the first insn in the block.
4740 In this case we don't have to move anything in this block. */
4741 if (NEXT_INSN (to) != from)
4743 reorder_insns (from, to, head);
4745 for (link = to; link != head; link = PREV_INSN (link))
4746 EXPR_ORIG_BB_INDEX (INSN_EXPR (link)) = block_new->index;
4750 /* Cleanup possibly empty blocks left. */
4751 block_next = bb->next_bb;
4752 if (bb != block_from)
4753 tidy_control_flow (bb, false);
4757 /* Assert there is no jump to BLOCK_NEW, only fallthrough edge. */
4758 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (BB_HEAD (block_new)));
4760 gcc_assert (!sel_bb_empty_p (block_from)
4761 && !sel_bb_empty_p (block_new));
4763 /* Update data sets for BLOCK_NEW to represent that INSN and
4764 instructions from the other branch of INSN is no longer
4765 available at BLOCK_NEW. */
4766 BB_AV_LEVEL (block_new) = global_level;
4767 gcc_assert (BB_LV_SET (block_new) == NULL);
4768 BB_LV_SET (block_new) = get_clear_regset_from_pool ();
4769 update_data_sets (sel_bb_head (block_new));
4771 /* INSN is a new basic block header - so prepare its data
4772 structures and update availability and liveness sets. */
4773 update_data_sets (insn);
4775 if (sched_verbose >= 4)
4776 sel_print ("Moving jump %d\n", INSN_UID (insn));
4779 /* Remove nops generated during move_op for preventing removal of empty
4782 remove_temp_moveop_nops (void)
4787 for (i = 0; VEC_iterate (insn_t, vec_temp_moveop_nops, i, insn); i++)
4789 gcc_assert (INSN_NOP_P (insn));
4790 return_nop_to_pool (insn);
4793 /* Empty the vector. */
4794 if (VEC_length (insn_t, vec_temp_moveop_nops) > 0)
4795 VEC_block_remove (insn_t, vec_temp_moveop_nops, 0,
4796 VEC_length (insn_t, vec_temp_moveop_nops));
4799 /* Records the maximal UID before moving up an instruction. Used for
4800 distinguishing between bookkeeping copies and original insns. */
4801 static int max_uid_before_move_op = 0;
4803 /* Remove from AV_VLIW_P all instructions but next when debug counter
4804 tells us so. Next instruction is fetched from BNDS. */
4806 remove_insns_for_debug (blist_t bnds, av_set_t *av_vliw_p)
4808 if (! dbg_cnt (sel_sched_insn_cnt))
4809 /* Leave only the next insn in av_vliw. */
4811 av_set_iterator av_it;
4813 bnd_t bnd = BLIST_BND (bnds);
4814 insn_t next = BND_TO (bnd);
4816 gcc_assert (BLIST_NEXT (bnds) == NULL);
4818 FOR_EACH_EXPR_1 (expr, av_it, av_vliw_p)
4819 if (EXPR_INSN_RTX (expr) != next)
4820 av_set_iter_remove (&av_it);
4824 /* Compute available instructions on BNDS. FENCE is the current fence. Write
4825 the computed set to *AV_VLIW_P. */
4827 compute_av_set_on_boundaries (fence_t fence, blist_t bnds, av_set_t *av_vliw_p)
4829 if (sched_verbose >= 2)
4831 sel_print ("Boundaries: ");
4836 for (; bnds; bnds = BLIST_NEXT (bnds))
4838 bnd_t bnd = BLIST_BND (bnds);
4840 insn_t bnd_to = BND_TO (bnd);
4842 /* Rewind BND->TO to the basic block header in case some bookkeeping
4843 instructions were inserted before BND->TO and it needs to be
4845 if (sel_bb_head_p (bnd_to))
4846 gcc_assert (INSN_SCHED_TIMES (bnd_to) == 0);
4848 while (INSN_SCHED_TIMES (PREV_INSN (bnd_to)) == 0)
4850 bnd_to = PREV_INSN (bnd_to);
4851 if (sel_bb_head_p (bnd_to))
4855 if (BND_TO (bnd) != bnd_to)
4857 gcc_assert (FENCE_INSN (fence) == BND_TO (bnd));
4858 FENCE_INSN (fence) = bnd_to;
4859 BND_TO (bnd) = bnd_to;
4862 av_set_clear (&BND_AV (bnd));
4863 BND_AV (bnd) = compute_av_set (BND_TO (bnd), NULL, 0, true);
4865 av_set_clear (&BND_AV1 (bnd));
4866 BND_AV1 (bnd) = av_set_copy (BND_AV (bnd));
4868 moveup_set_inside_insn_group (&BND_AV1 (bnd), NULL);
4870 av1_copy = av_set_copy (BND_AV1 (bnd));
4871 av_set_union_and_clear (av_vliw_p, &av1_copy, NULL);
4874 if (sched_verbose >= 2)
4876 sel_print ("Available exprs (vliw form): ");
4877 dump_av_set (*av_vliw_p);
4882 /* Calculate the sequential av set on BND corresponding to the EXPR_VLIW
4883 expression. When FOR_MOVEOP is true, also replace the register of
4884 expressions found with the register from EXPR_VLIW. */
4886 find_sequential_best_exprs (bnd_t bnd, expr_t expr_vliw, bool for_moveop)
4888 av_set_t expr_seq = NULL;
4892 FOR_EACH_EXPR (expr, i, BND_AV (bnd))
4894 if (equal_after_moveup_path_p (expr, NULL, expr_vliw))
4898 /* The sequential expression has the right form to pass
4899 to move_op except when renaming happened. Put the
4900 correct register in EXPR then. */
4901 if (EXPR_SEPARABLE_P (expr) && REG_P (EXPR_LHS (expr)))
4903 if (expr_dest_regno (expr) != expr_dest_regno (expr_vliw))
4905 replace_dest_with_reg_in_expr (expr, EXPR_LHS (expr_vliw));
4906 stat_renamed_scheduled++;
4908 /* Also put the correct TARGET_AVAILABLE bit on the expr.
4909 This is needed when renaming came up with original
4911 else if (EXPR_TARGET_AVAILABLE (expr)
4912 != EXPR_TARGET_AVAILABLE (expr_vliw))
4914 gcc_assert (EXPR_TARGET_AVAILABLE (expr_vliw) == 1);
4915 EXPR_TARGET_AVAILABLE (expr) = 1;
4918 if (EXPR_WAS_SUBSTITUTED (expr))
4919 stat_substitutions_total++;
4922 av_set_add (&expr_seq, expr);
4924 /* With substitution inside insn group, it is possible
4925 that more than one expression in expr_seq will correspond
4926 to expr_vliw. In this case, choose one as the attempt to
4927 move both leads to miscompiles. */
4932 if (for_moveop && sched_verbose >= 2)
4934 sel_print ("Best expression(s) (sequential form): ");
4935 dump_av_set (expr_seq);
4943 /* Move nop to previous block. */
4944 static void ATTRIBUTE_UNUSED
4945 move_nop_to_previous_block (insn_t nop, basic_block prev_bb)
4947 insn_t prev_insn, next_insn, note;
4949 gcc_assert (sel_bb_head_p (nop)
4950 && prev_bb == BLOCK_FOR_INSN (nop)->prev_bb);
4951 note = bb_note (BLOCK_FOR_INSN (nop));
4952 prev_insn = sel_bb_end (prev_bb);
4953 next_insn = NEXT_INSN (nop);
4954 gcc_assert (prev_insn != NULL_RTX
4955 && PREV_INSN (note) == prev_insn);
4957 NEXT_INSN (prev_insn) = nop;
4958 PREV_INSN (nop) = prev_insn;
4960 PREV_INSN (note) = nop;
4961 NEXT_INSN (note) = next_insn;
4963 NEXT_INSN (nop) = note;
4964 PREV_INSN (next_insn) = note;
4966 BB_END (prev_bb) = nop;
4967 BLOCK_FOR_INSN (nop) = prev_bb;
4970 /* Prepare a place to insert the chosen expression on BND. */
4972 prepare_place_to_insert (bnd_t bnd)
4974 insn_t place_to_insert;
4976 /* Init place_to_insert before calling move_op, as the later
4977 can possibly remove BND_TO (bnd). */
4978 if (/* If this is not the first insn scheduled. */
4981 /* Add it after last scheduled. */
4982 place_to_insert = ILIST_INSN (BND_PTR (bnd));
4986 /* Add it before BND_TO. The difference is in the
4987 basic block, where INSN will be added. */
4988 place_to_insert = get_nop_from_pool (BND_TO (bnd));
4989 gcc_assert (BLOCK_FOR_INSN (place_to_insert)
4990 == BLOCK_FOR_INSN (BND_TO (bnd)));
4993 return place_to_insert;
4996 /* Find original instructions for EXPR_SEQ and move it to BND boundary.
4997 Return the expression to emit in C_EXPR. */
4999 move_exprs_to_boundary (bnd_t bnd, expr_t expr_vliw,
5000 av_set_t expr_seq, expr_t c_expr)
5002 bool b, should_move;
5005 int n_bookkeeping_copies_before_moveop;
5007 /* Make a move. This call will remove the original operation,
5008 insert all necessary bookkeeping instructions and update the
5009 data sets. After that all we have to do is add the operation
5010 at before BND_TO (BND). */
5011 n_bookkeeping_copies_before_moveop = stat_bookkeeping_copies;
5012 max_uid_before_move_op = get_max_uid ();
5013 bitmap_clear (current_copies);
5014 bitmap_clear (current_originators);
5016 b = move_op (BND_TO (bnd), expr_seq, expr_vliw,
5017 get_dest_from_orig_ops (expr_seq), c_expr, &should_move);
5019 /* We should be able to find the expression we've chosen for
5023 if (stat_bookkeeping_copies > n_bookkeeping_copies_before_moveop)
5024 stat_insns_needed_bookkeeping++;
5026 EXECUTE_IF_SET_IN_BITMAP (current_copies, 0, book_uid, bi)
5031 /* We allocate these bitmaps lazily. */
5032 if (! INSN_ORIGINATORS_BY_UID (book_uid))
5033 INSN_ORIGINATORS_BY_UID (book_uid) = BITMAP_ALLOC (NULL);
5035 bitmap_copy (INSN_ORIGINATORS_BY_UID (book_uid),
5036 current_originators);
5038 /* Transitively add all originators' originators. */
5039 EXECUTE_IF_SET_IN_BITMAP (current_originators, 0, uid, bi)
5040 if (INSN_ORIGINATORS_BY_UID (uid))
5041 bitmap_ior_into (INSN_ORIGINATORS_BY_UID (book_uid),
5042 INSN_ORIGINATORS_BY_UID (uid));
5049 /* Debug a DFA state as an array of bytes. */
5051 debug_state (state_t state)
5054 unsigned int i, size = dfa_state_size;
5056 sel_print ("state (%u):", size);
5057 for (i = 0, p = (unsigned char *) state; i < size; i++)
5058 sel_print (" %d", p[i]);
5062 /* Advance state on FENCE with INSN. Return true if INSN is
5063 an ASM, and we should advance state once more. */
5065 advance_state_on_fence (fence_t fence, insn_t insn)
5069 if (recog_memoized (insn) >= 0)
5072 state_t temp_state = alloca (dfa_state_size);
5074 gcc_assert (!INSN_ASM_P (insn));
5077 memcpy (temp_state, FENCE_STATE (fence), dfa_state_size);
5078 res = state_transition (FENCE_STATE (fence), insn);
5079 gcc_assert (res < 0);
5081 if (memcmp (temp_state, FENCE_STATE (fence), dfa_state_size))
5083 FENCE_ISSUED_INSNS (fence)++;
5085 /* We should never issue more than issue_rate insns. */
5086 if (FENCE_ISSUED_INSNS (fence) > issue_rate)
5092 /* This could be an ASM insn which we'd like to schedule
5093 on the next cycle. */
5094 asm_p = INSN_ASM_P (insn);
5095 if (!FENCE_STARTS_CYCLE_P (fence) && asm_p)
5096 advance_one_cycle (fence);
5099 if (sched_verbose >= 2)
5100 debug_state (FENCE_STATE (fence));
5101 FENCE_STARTS_CYCLE_P (fence) = 0;
5102 FENCE_ISSUE_MORE (fence) = can_issue_more;
5106 /* Update FENCE on which INSN was scheduled and this INSN, too. NEED_STALL
5107 is nonzero if we need to stall after issuing INSN. */
5109 update_fence_and_insn (fence_t fence, insn_t insn, int need_stall)
5113 /* First, reflect that something is scheduled on this fence. */
5114 asm_p = advance_state_on_fence (fence, insn);
5115 FENCE_LAST_SCHEDULED_INSN (fence) = insn;
5116 VEC_safe_push (rtx, gc, FENCE_EXECUTING_INSNS (fence), insn);
5117 if (SCHED_GROUP_P (insn))
5119 FENCE_SCHED_NEXT (fence) = INSN_SCHED_NEXT (insn);
5120 SCHED_GROUP_P (insn) = 0;
5123 FENCE_SCHED_NEXT (fence) = NULL_RTX;
5124 if (INSN_UID (insn) < FENCE_READY_TICKS_SIZE (fence))
5125 FENCE_READY_TICKS (fence) [INSN_UID (insn)] = 0;
5127 /* Set instruction scheduling info. This will be used in bundling,
5128 pipelining, tick computations etc. */
5129 ++INSN_SCHED_TIMES (insn);
5130 EXPR_TARGET_AVAILABLE (INSN_EXPR (insn)) = true;
5131 EXPR_ORIG_SCHED_CYCLE (INSN_EXPR (insn)) = FENCE_CYCLE (fence);
5132 INSN_AFTER_STALL_P (insn) = FENCE_AFTER_STALL_P (fence);
5133 INSN_SCHED_CYCLE (insn) = FENCE_CYCLE (fence);
5135 /* This does not account for adjust_cost hooks, just add the biggest
5136 constant the hook may add to the latency. TODO: make this
5137 a target dependent constant. */
5138 INSN_READY_CYCLE (insn)
5139 = INSN_SCHED_CYCLE (insn) + (INSN_CODE (insn) < 0
5141 : maximal_insn_latency (insn) + 1);
5143 /* Change these fields last, as they're used above. */
5144 FENCE_AFTER_STALL_P (fence) = 0;
5145 if (asm_p || need_stall)
5146 advance_one_cycle (fence);
5148 /* Indicate that we've scheduled something on this fence. */
5149 FENCE_SCHEDULED_P (fence) = true;
5150 scheduled_something_on_previous_fence = true;
5152 /* Print debug information when insn's fields are updated. */
5153 if (sched_verbose >= 2)
5155 sel_print ("Scheduling insn: ");
5156 dump_insn_1 (insn, 1);
5161 /* Update boundary BND with INSN, remove the old boundary from
5162 BNDSP, add new boundaries to BNDS_TAIL_P and return it. */
5164 update_boundaries (bnd_t bnd, insn_t insn, blist_t *bndsp,
5165 blist_t *bnds_tailp)
5170 advance_deps_context (BND_DC (bnd), insn);
5171 FOR_EACH_SUCC_1 (succ, si, insn,
5172 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
5174 ilist_t ptr = ilist_copy (BND_PTR (bnd));
5176 ilist_add (&ptr, insn);
5177 blist_add (bnds_tailp, succ, ptr, BND_DC (bnd));
5178 bnds_tailp = &BLIST_NEXT (*bnds_tailp);
5181 blist_remove (bndsp);
5185 /* Schedule EXPR_VLIW on BND. Return the insn emitted. */
5187 schedule_expr_on_boundary (bnd_t bnd, expr_t expr_vliw, int seqno)
5190 expr_t c_expr = XALLOCA (expr_def);
5191 insn_t place_to_insert;
5195 expr_seq = find_sequential_best_exprs (bnd, expr_vliw, true);
5197 /* In case of scheduling a jump skipping some other instructions,
5198 prepare CFG. After this, jump is at the boundary and can be
5199 scheduled as usual insn by MOVE_OP. */
5200 if (vinsn_cond_branch_p (EXPR_VINSN (expr_vliw)))
5202 insn = EXPR_INSN_RTX (expr_vliw);
5204 /* Speculative jumps are not handled. */
5205 if (insn != BND_TO (bnd)
5206 && !sel_insn_is_speculation_check (insn))
5207 move_cond_jump (insn, bnd);
5210 /* Find a place for C_EXPR to schedule. */
5211 place_to_insert = prepare_place_to_insert (bnd);
5212 should_move = move_exprs_to_boundary (bnd, expr_vliw, expr_seq, c_expr);
5213 clear_expr (c_expr);
5215 /* Add the instruction. The corner case to care about is when
5216 the expr_seq set has more than one expr, and we chose the one that
5217 is not equal to expr_vliw. Then expr_vliw may be insn in stream, and
5218 we can't use it. Generate the new vinsn. */
5219 if (INSN_IN_STREAM_P (EXPR_INSN_RTX (expr_vliw)))
5223 vinsn_new = vinsn_copy (EXPR_VINSN (expr_vliw), false);
5224 change_vinsn_in_expr (expr_vliw, vinsn_new);
5225 should_move = false;
5228 insn = sel_move_insn (expr_vliw, seqno, place_to_insert);
5230 insn = emit_insn_from_expr_after (expr_vliw, NULL, seqno,
5233 /* Return the nops generated for preserving of data sets back
5235 if (INSN_NOP_P (place_to_insert))
5236 return_nop_to_pool (place_to_insert);
5237 remove_temp_moveop_nops ();
5239 av_set_clear (&expr_seq);
5241 /* Save the expression scheduled so to reset target availability if we'll
5242 meet it later on the same fence. */
5243 if (EXPR_WAS_RENAMED (expr_vliw))
5244 vinsn_vec_add (&vec_target_unavailable_vinsns, INSN_EXPR (insn));
5246 /* Check that the recent movement didn't destroyed loop
5248 gcc_assert (!pipelining_p
5249 || current_loop_nest == NULL
5250 || loop_latch_edge (current_loop_nest));
5254 /* Stall for N cycles on FENCE. */
5256 stall_for_cycles (fence_t fence, int n)
5260 could_more = n > 1 || FENCE_ISSUED_INSNS (fence) < issue_rate;
5262 advance_one_cycle (fence);
5264 FENCE_AFTER_STALL_P (fence) = 1;
5267 /* Gather a parallel group of insns at FENCE and assign their seqno
5268 to SEQNO. All scheduled insns are gathered in SCHEDULED_INSNS_TAILPP
5269 list for later recalculation of seqnos. */
5271 fill_insns (fence_t fence, int seqno, ilist_t **scheduled_insns_tailpp)
5273 blist_t bnds = NULL, *bnds_tailp;
5274 av_set_t av_vliw = NULL;
5275 insn_t insn = FENCE_INSN (fence);
5277 if (sched_verbose >= 2)
5278 sel_print ("Starting fill_insns for insn %d, cycle %d\n",
5279 INSN_UID (insn), FENCE_CYCLE (fence));
5281 blist_add (&bnds, insn, NULL, FENCE_DC (fence));
5282 bnds_tailp = &BLIST_NEXT (bnds);
5283 set_target_context (FENCE_TC (fence));
5284 can_issue_more = FENCE_ISSUE_MORE (fence);
5285 target_bb = INSN_BB (insn);
5287 /* Do while we can add any operation to the current group. */
5290 blist_t *bnds_tailp1, *bndsp;
5293 int was_stall = 0, scheduled_insns = 0, stall_iterations = 0;
5294 int max_insns = pipelining_p ? issue_rate : 2 * issue_rate;
5295 int max_stall = pipelining_p ? 1 : 3;
5297 compute_av_set_on_boundaries (fence, bnds, &av_vliw);
5298 remove_insns_that_need_bookkeeping (fence, &av_vliw);
5299 remove_insns_for_debug (bnds, &av_vliw);
5301 /* Return early if we have nothing to schedule. */
5302 if (av_vliw == NULL)
5305 /* Choose the best expression and, if needed, destination register
5309 expr_vliw = find_best_expr (&av_vliw, bnds, fence, &need_stall);
5310 if (!expr_vliw && need_stall)
5312 /* All expressions required a stall. Do not recompute av sets
5313 as we'll get the same answer (modulo the insns between
5314 the fence and its boundary, which will not be available for
5316 gcc_assert (! expr_vliw && stall_iterations < 2);
5318 /* If we are going to stall for too long, break to recompute av
5319 sets and bring more insns for pipelining. */
5320 if (need_stall <= 3)
5321 stall_for_cycles (fence, need_stall);
5324 stall_for_cycles (fence, 1);
5329 while (! expr_vliw && need_stall);
5331 /* Now either we've selected expr_vliw or we have nothing to schedule. */
5334 av_set_clear (&av_vliw);
5339 bnds_tailp1 = bnds_tailp;
5342 /* This code will be executed only once until we'd have several
5343 boundaries per fence. */
5345 bnd_t bnd = BLIST_BND (*bndsp);
5347 if (!av_set_is_in_p (BND_AV1 (bnd), EXPR_VINSN (expr_vliw)))
5349 bndsp = &BLIST_NEXT (*bndsp);
5353 insn = schedule_expr_on_boundary (bnd, expr_vliw, seqno);
5354 update_fence_and_insn (fence, insn, need_stall);
5355 bnds_tailp = update_boundaries (bnd, insn, bndsp, bnds_tailp);
5357 /* Add insn to the list of scheduled on this cycle instructions. */
5358 ilist_add (*scheduled_insns_tailpp, insn);
5359 *scheduled_insns_tailpp = &ILIST_NEXT (**scheduled_insns_tailpp);
5361 while (*bndsp != *bnds_tailp1);
5363 av_set_clear (&av_vliw);
5366 /* We currently support information about candidate blocks only for
5367 one 'target_bb' block. Hence we can't schedule after jump insn,
5368 as this will bring two boundaries and, hence, necessity to handle
5369 information for two or more blocks concurrently. */
5370 if (sel_bb_end_p (insn)
5372 && (was_stall >= max_stall
5373 || scheduled_insns >= max_insns)))
5378 gcc_assert (!FENCE_BNDS (fence));
5380 /* Update boundaries of the FENCE. */
5383 ilist_t ptr = BND_PTR (BLIST_BND (bnds));
5387 insn = ILIST_INSN (ptr);
5389 if (!ilist_is_in_p (FENCE_BNDS (fence), insn))
5390 ilist_add (&FENCE_BNDS (fence), insn);
5393 blist_remove (&bnds);
5396 /* Update target context on the fence. */
5397 reset_target_context (FENCE_TC (fence), false);
5400 /* All exprs in ORIG_OPS must have the same destination register or memory.
5401 Return that destination. */
5403 get_dest_from_orig_ops (av_set_t orig_ops)
5405 rtx dest = NULL_RTX;
5406 av_set_iterator av_it;
5408 bool first_p = true;
5410 FOR_EACH_EXPR (expr, av_it, orig_ops)
5412 rtx x = EXPR_LHS (expr);
5420 gcc_assert (dest == x
5421 || (dest != NULL_RTX && x != NULL_RTX
5422 && rtx_equal_p (dest, x)));
5428 /* Update data sets for the bookkeeping block and record those expressions
5429 which become no longer available after inserting this bookkeeping. */
5431 update_and_record_unavailable_insns (basic_block book_block)
5434 av_set_t old_av_set = NULL;
5436 rtx bb_end = sel_bb_end (book_block);
5438 /* First, get correct liveness in the bookkeeping block. The problem is
5439 the range between the bookeeping insn and the end of block. */
5440 update_liveness_on_insn (bb_end);
5441 if (control_flow_insn_p (bb_end))
5442 update_liveness_on_insn (PREV_INSN (bb_end));
5444 /* If there's valid av_set on BOOK_BLOCK, then there might exist another
5445 fence above, where we may choose to schedule an insn which is
5446 actually blocked from moving up with the bookkeeping we create here. */
5447 if (AV_SET_VALID_P (sel_bb_head (book_block)))
5449 old_av_set = av_set_copy (BB_AV_SET (book_block));
5450 update_data_sets (sel_bb_head (book_block));
5452 /* Traverse all the expressions in the old av_set and check whether
5453 CUR_EXPR is in new AV_SET. */
5454 FOR_EACH_EXPR (cur_expr, i, old_av_set)
5456 expr_t new_expr = av_set_lookup (BB_AV_SET (book_block),
5457 EXPR_VINSN (cur_expr));
5460 /* In this case, we can just turn off the E_T_A bit, but we can't
5461 represent this information with the current vector. */
5462 || EXPR_TARGET_AVAILABLE (new_expr)
5463 != EXPR_TARGET_AVAILABLE (cur_expr))
5464 /* Unfortunately, the below code could be also fired up on
5466 FIXME: add an example of how this could happen. */
5467 vinsn_vec_add (&vec_bookkeeping_blocked_vinsns, cur_expr);
5470 av_set_clear (&old_av_set);
5474 /* The main effect of this function is that sparams->c_expr is merged
5475 with (or copied to) lparams->c_expr_merged. If there's only one successor,
5476 we avoid merging anything by copying sparams->c_expr to lparams->c_expr_merged.
5477 lparams->c_expr_merged is copied back to sparams->c_expr after all
5478 successors has been traversed. lparams->c_expr_local is an expr allocated
5479 on stack in the caller function, and is used if there is more than one
5482 SUCC is one of the SUCCS_NORMAL successors of INSN,
5483 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ,
5484 LPARAMS and STATIC_PARAMS contain the parameters described above. */
5486 move_op_merge_succs (insn_t insn ATTRIBUTE_UNUSED,
5487 insn_t succ ATTRIBUTE_UNUSED,
5488 int moveop_drv_call_res,
5489 cmpd_local_params_p lparams, void *static_params)
5491 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
5493 /* Nothing to do, if original expr wasn't found below. */
5494 if (moveop_drv_call_res != 1)
5497 /* If this is a first successor. */
5498 if (!lparams->c_expr_merged)
5500 lparams->c_expr_merged = sparams->c_expr;
5501 sparams->c_expr = lparams->c_expr_local;
5505 /* We must merge all found expressions to get reasonable
5506 EXPR_SPEC_DONE_DS for the resulting insn. If we don't
5507 do so then we can first find the expr with epsilon
5508 speculation success probability and only then with the
5509 good probability. As a result the insn will get epsilon
5510 probability and will never be scheduled because of
5511 weakness_cutoff in find_best_expr.
5513 We call merge_expr_data here instead of merge_expr
5514 because due to speculation C_EXPR and X may have the
5515 same insns with different speculation types. And as of
5516 now such insns are considered non-equal.
5518 However, EXPR_SCHED_TIMES is different -- we must get
5519 SCHED_TIMES from a real insn, not a bookkeeping copy.
5520 We force this here. Instead, we may consider merging
5521 SCHED_TIMES to the maximum instead of minimum in the
5523 int old_times = EXPR_SCHED_TIMES (lparams->c_expr_merged);
5525 merge_expr_data (lparams->c_expr_merged, sparams->c_expr, NULL);
5526 if (EXPR_SCHED_TIMES (sparams->c_expr) == 0)
5527 EXPR_SCHED_TIMES (lparams->c_expr_merged) = old_times;
5529 clear_expr (sparams->c_expr);
5533 /* Add used regs for the successor SUCC into SPARAMS->USED_REGS.
5535 SUCC is one of the SUCCS_NORMAL successors of INSN,
5536 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ or 0,
5537 if SUCC is one of SUCCS_BACK or SUCCS_OUT.
5538 STATIC_PARAMS contain USED_REGS set. */
5540 fur_merge_succs (insn_t insn ATTRIBUTE_UNUSED, insn_t succ,
5541 int moveop_drv_call_res,
5542 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
5543 void *static_params)
5546 fur_static_params_p sparams = (fur_static_params_p) static_params;
5548 /* Here we compute live regsets only for branches that do not lie
5549 on the code motion paths. These branches correspond to value
5550 MOVEOP_DRV_CALL_RES==0 and include SUCCS_BACK and SUCCS_OUT, though
5551 for such branches code_motion_path_driver is not called. */
5552 if (moveop_drv_call_res != 0)
5555 /* Mark all registers that do not meet the following condition:
5556 (3) not live on the other path of any conditional branch
5557 that is passed by the operation, in case original
5558 operations are not present on both paths of the
5559 conditional branch. */
5560 succ_live = compute_live (succ);
5561 IOR_REG_SET (sparams->used_regs, succ_live);
5564 /* This function is called after the last successor. Copies LP->C_EXPR_MERGED
5567 move_op_after_merge_succs (cmpd_local_params_p lp, void *sparams)
5569 moveop_static_params_p sp = (moveop_static_params_p) sparams;
5571 sp->c_expr = lp->c_expr_merged;
5574 /* Track bookkeeping copies created, insns scheduled, and blocks for
5575 rescheduling when INSN is found by move_op. */
5577 track_scheduled_insns_and_blocks (rtx insn)
5579 /* Even if this insn can be a copy that will be removed during current move_op,
5580 we still need to count it as an originator. */
5581 bitmap_set_bit (current_originators, INSN_UID (insn));
5583 if (!bitmap_bit_p (current_copies, INSN_UID (insn)))
5585 /* Note that original block needs to be rescheduled, as we pulled an
5586 instruction out of it. */
5587 if (INSN_SCHED_TIMES (insn) > 0)
5588 bitmap_set_bit (blocks_to_reschedule, BLOCK_FOR_INSN (insn)->index);
5589 else if (INSN_UID (insn) < first_emitted_uid)
5590 num_insns_scheduled++;
5593 bitmap_clear_bit (current_copies, INSN_UID (insn));
5595 /* For instructions we must immediately remove insn from the
5596 stream, so subsequent update_data_sets () won't include this
5598 For expr we must make insn look like "INSN_REG (insn) := c_expr". */
5599 if (INSN_UID (insn) > max_uid_before_move_op)
5600 stat_bookkeeping_copies--;
5603 /* Emit a register-register copy for INSN if needed. Return true if
5604 emitted one. PARAMS is the move_op static parameters. */
5606 maybe_emit_renaming_copy (rtx insn,
5607 moveop_static_params_p params)
5609 bool insn_emitted = false;
5612 /* Bail out early when expression can not be renamed at all. */
5613 if (!EXPR_SEPARABLE_P (params->c_expr))
5616 cur_reg = expr_dest_reg (params->c_expr);
5617 gcc_assert (cur_reg && params->dest && REG_P (params->dest));
5619 /* If original operation has expr and the register chosen for
5620 that expr is not original operation's dest reg, substitute
5621 operation's right hand side with the register chosen. */
5622 if (REGNO (params->dest) != REGNO (cur_reg))
5624 insn_t reg_move_insn, reg_move_insn_rtx;
5626 reg_move_insn_rtx = create_insn_rtx_with_rhs (INSN_VINSN (insn),
5628 reg_move_insn = sel_gen_insn_from_rtx_after (reg_move_insn_rtx,
5632 EXPR_SPEC_DONE_DS (INSN_EXPR (reg_move_insn)) = 0;
5633 replace_dest_with_reg_in_expr (params->c_expr, params->dest);
5635 insn_emitted = true;
5636 params->was_renamed = true;
5639 return insn_emitted;
5642 /* Emit a speculative check for INSN speculated as EXPR if needed.
5643 Return true if we've emitted one. PARAMS is the move_op static
5646 maybe_emit_speculative_check (rtx insn, expr_t expr,
5647 moveop_static_params_p params)
5649 bool insn_emitted = false;
5653 check_ds = get_spec_check_type_for_insn (insn, expr);
5656 /* A speculation check should be inserted. */
5657 x = create_speculation_check (params->c_expr, check_ds, insn);
5658 insn_emitted = true;
5662 EXPR_SPEC_DONE_DS (INSN_EXPR (insn)) = 0;
5666 gcc_assert (EXPR_SPEC_DONE_DS (INSN_EXPR (x)) == 0
5667 && EXPR_SPEC_TO_CHECK_DS (INSN_EXPR (x)) == 0);
5668 return insn_emitted;
5671 /* Handle transformations that leave an insn in place of original
5672 insn such as renaming/speculation. Return true if one of such
5673 transformations actually happened, and we have emitted this insn. */
5675 handle_emitting_transformations (rtx insn, expr_t expr,
5676 moveop_static_params_p params)
5678 bool insn_emitted = false;
5680 insn_emitted = maybe_emit_renaming_copy (insn, params);
5681 insn_emitted |= maybe_emit_speculative_check (insn, expr, params);
5683 return insn_emitted;
5686 /* Remove INSN from stream. When ONLY_DISCONNECT is true, its data
5687 is not removed but reused when INSN is re-emitted. */
5689 remove_insn_from_stream (rtx insn, bool only_disconnect)
5691 insn_t nop, bb_head, bb_end;
5692 bool need_nop_to_preserve_bb;
5693 basic_block bb = BLOCK_FOR_INSN (insn);
5695 /* If INSN is the only insn in the basic block (not counting JUMP,
5696 which may be a jump to next insn), leave NOP there till the
5697 return to fill_insns. */
5698 bb_head = sel_bb_head (bb);
5699 bb_end = sel_bb_end (bb);
5700 need_nop_to_preserve_bb = ((bb_head == bb_end)
5701 || (NEXT_INSN (bb_head) == bb_end
5703 || IN_CURRENT_FENCE_P (NEXT_INSN (insn)));
5705 /* If there's only one insn in the BB, make sure that a nop is
5706 inserted into it, so the basic block won't disappear when we'll
5707 delete INSN below with sel_remove_insn. It should also survive
5708 till the return to fill_insns. */
5709 if (need_nop_to_preserve_bb)
5711 nop = get_nop_from_pool (insn);
5712 gcc_assert (INSN_NOP_P (nop));
5713 VEC_safe_push (insn_t, heap, vec_temp_moveop_nops, nop);
5716 sel_remove_insn (insn, only_disconnect, false);
5719 /* This function is called when original expr is found.
5720 INSN - current insn traversed, EXPR - the corresponding expr found.
5721 LPARAMS is the local parameters of code modion driver, STATIC_PARAMS
5722 is static parameters of move_op. */
5724 move_op_orig_expr_found (insn_t insn, expr_t expr,
5725 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
5726 void *static_params)
5728 bool only_disconnect, insn_emitted;
5729 moveop_static_params_p params = (moveop_static_params_p) static_params;
5731 copy_expr_onside (params->c_expr, INSN_EXPR (insn));
5732 track_scheduled_insns_and_blocks (insn);
5733 insn_emitted = handle_emitting_transformations (insn, expr, params);
5734 only_disconnect = (params->uid == INSN_UID (insn)
5735 && ! insn_emitted && ! EXPR_WAS_CHANGED (expr));
5737 /* Mark that we've disconnected an insn. */
5738 if (only_disconnect)
5740 remove_insn_from_stream (insn, only_disconnect);
5743 /* The function is called when original expr is found.
5744 INSN - current insn traversed, EXPR - the corresponding expr found,
5745 crosses_call and original_insns in STATIC_PARAMS are updated. */
5747 fur_orig_expr_found (insn_t insn, expr_t expr ATTRIBUTE_UNUSED,
5748 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
5749 void *static_params)
5751 fur_static_params_p params = (fur_static_params_p) static_params;
5755 params->crosses_call = true;
5757 def_list_add (params->original_insns, insn, params->crosses_call);
5759 /* Mark the registers that do not meet the following condition:
5760 (2) not among the live registers of the point
5761 immediately following the first original operation on
5762 a given downward path, except for the original target
5763 register of the operation. */
5764 tmp = get_clear_regset_from_pool ();
5765 compute_live_below_insn (insn, tmp);
5766 AND_COMPL_REG_SET (tmp, INSN_REG_SETS (insn));
5767 AND_COMPL_REG_SET (tmp, INSN_REG_CLOBBERS (insn));
5768 IOR_REG_SET (params->used_regs, tmp);
5769 return_regset_to_pool (tmp);
5771 /* (*1) We need to add to USED_REGS registers that are read by
5772 INSN's lhs. This may lead to choosing wrong src register.
5773 E.g. (scheduling const expr enabled):
5775 429: ax=0x0 <- Can't use AX for this expr (0x0)
5782 /* FIXME: see comment above and enable MEM_P
5783 in vinsn_separable_p. */
5784 gcc_assert (!VINSN_SEPARABLE_P (INSN_VINSN (insn))
5785 || !MEM_P (INSN_LHS (insn)));
5788 /* This function is called on the ascending pass, before returning from
5789 current basic block. */
5791 move_op_at_first_insn (insn_t insn, cmpd_local_params_p lparams,
5792 void *static_params)
5794 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
5795 basic_block book_block = NULL;
5797 /* When we have removed the boundary insn for scheduling, which also
5798 happened to be the end insn in its bb, we don't need to update sets. */
5799 if (!lparams->removed_last_insn
5801 && sel_bb_head_p (insn))
5803 /* We should generate bookkeeping code only if we are not at the
5804 top level of the move_op. */
5805 if (sel_num_cfg_preds_gt_1 (insn))
5806 book_block = generate_bookkeeping_insn (sparams->c_expr,
5807 lparams->e1, lparams->e2);
5808 /* Update data sets for the current insn. */
5809 update_data_sets (insn);
5812 /* If bookkeeping code was inserted, we need to update av sets of basic
5813 block that received bookkeeping. After generation of bookkeeping insn,
5814 bookkeeping block does not contain valid av set because we are not following
5815 the original algorithm in every detail with regards to e.g. renaming
5816 simple reg-reg copies. Consider example:
5818 bookkeeping block scheduling fence
5828 We try to schedule insn "r1 := r3" on the current
5829 scheduling fence. Also, note that av set of bookkeeping block
5830 contain both insns "r1 := r2" and "r1 := r3". When the insn has
5831 been scheduled, the CFG is as follows:
5834 bookkeeping block scheduling fence
5844 Here, insn "r1 := r3" was scheduled at the current scheduling point
5845 and bookkeeping code was generated at the bookeeping block. This
5846 way insn "r1 := r2" is no longer available as a whole instruction
5847 (but only as expr) ahead of insn "r1 := r3" in bookkeeping block.
5848 This situation is handled by calling update_data_sets.
5850 Since update_data_sets is called only on the bookkeeping block, and
5851 it also may have predecessors with av_sets, containing instructions that
5852 are no longer available, we save all such expressions that become
5853 unavailable during data sets update on the bookkeeping block in
5854 VEC_BOOKKEEPING_BLOCKED_VINSNS. Later we avoid selecting such
5855 expressions for scheduling. This allows us to avoid recomputation of
5856 av_sets outside the code motion path. */
5859 update_and_record_unavailable_insns (book_block);
5861 /* If INSN was previously marked for deletion, it's time to do it. */
5862 if (lparams->removed_last_insn)
5863 insn = PREV_INSN (insn);
5865 /* Do not tidy control flow at the topmost moveop, as we can erroneously
5866 kill a block with a single nop in which the insn should be emitted. */
5868 tidy_control_flow (BLOCK_FOR_INSN (insn), true);
5871 /* This function is called on the ascending pass, before returning from the
5872 current basic block. */
5874 fur_at_first_insn (insn_t insn,
5875 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
5876 void *static_params ATTRIBUTE_UNUSED)
5878 gcc_assert (!sel_bb_head_p (insn) || AV_SET_VALID_P (insn)
5879 || AV_LEVEL (insn) == -1);
5882 /* Called on the backward stage of recursion to call moveup_expr for insn
5883 and sparams->c_expr. */
5885 move_op_ascend (insn_t insn, void *static_params)
5887 enum MOVEUP_EXPR_CODE res;
5888 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
5890 if (! INSN_NOP_P (insn))
5892 res = moveup_expr_cached (sparams->c_expr, insn, false);
5893 gcc_assert (res != MOVEUP_EXPR_NULL);
5896 /* Update liveness for this insn as it was invalidated. */
5897 update_liveness_on_insn (insn);
5900 /* This function is called on enter to the basic block.
5901 Returns TRUE if this block already have been visited and
5902 code_motion_path_driver should return 1, FALSE otherwise. */
5904 fur_on_enter (insn_t insn ATTRIBUTE_UNUSED, cmpd_local_params_p local_params,
5905 void *static_params, bool visited_p)
5907 fur_static_params_p sparams = (fur_static_params_p) static_params;
5911 /* If we have found something below this block, there should be at
5912 least one insn in ORIGINAL_INSNS. */
5913 gcc_assert (*sparams->original_insns);
5915 /* Adjust CROSSES_CALL, since we may have come to this block along
5917 DEF_LIST_DEF (*sparams->original_insns)->crosses_call
5918 |= sparams->crosses_call;
5921 local_params->old_original_insns = *sparams->original_insns;
5926 /* Same as above but for move_op. */
5928 move_op_on_enter (insn_t insn ATTRIBUTE_UNUSED,
5929 cmpd_local_params_p local_params ATTRIBUTE_UNUSED,
5930 void *static_params ATTRIBUTE_UNUSED, bool visited_p)
5937 /* This function is called while descending current basic block if current
5938 insn is not the original EXPR we're searching for.
5940 Return value: FALSE, if code_motion_path_driver should perform a local
5941 cleanup and return 0 itself;
5942 TRUE, if code_motion_path_driver should continue. */
5944 move_op_orig_expr_not_found (insn_t insn, av_set_t orig_ops ATTRIBUTE_UNUSED,
5945 void *static_params)
5947 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
5949 #ifdef ENABLE_CHECKING
5950 sparams->failed_insn = insn;
5953 /* If we're scheduling separate expr, in order to generate correct code
5954 we need to stop the search at bookkeeping code generated with the
5955 same destination register or memory. */
5956 if (lhs_of_insn_equals_to_dest_p (insn, sparams->dest))
5961 /* This function is called while descending current basic block if current
5962 insn is not the original EXPR we're searching for.
5964 Return value: TRUE (code_motion_path_driver should continue). */
5966 fur_orig_expr_not_found (insn_t insn, av_set_t orig_ops, void *static_params)
5970 av_set_iterator avi;
5971 fur_static_params_p sparams = (fur_static_params_p) static_params;
5974 sparams->crosses_call = true;
5976 /* If current insn we are looking at cannot be executed together
5977 with original insn, then we can skip it safely.
5979 Example: ORIG_OPS = { (p6) r14 = sign_extend (r15); }
5980 INSN = (!p6) r14 = r14 + 1;
5982 Here we can schedule ORIG_OP with lhs = r14, though only
5983 looking at the set of used and set registers of INSN we must
5984 forbid it. So, add set/used in INSN registers to the
5985 untouchable set only if there is an insn in ORIG_OPS that can
5988 FOR_EACH_EXPR (r, avi, orig_ops)
5989 if (!sched_insns_conditions_mutex_p (insn, EXPR_INSN_RTX (r)))
5995 /* Mark all registers that do not meet the following condition:
5996 (1) Not set or read on any path from xi to an instance of the
5997 original operation. */
6000 IOR_REG_SET (sparams->used_regs, INSN_REG_SETS (insn));
6001 IOR_REG_SET (sparams->used_regs, INSN_REG_USES (insn));
6002 IOR_REG_SET (sparams->used_regs, INSN_REG_CLOBBERS (insn));
6008 /* Hooks and data to perform move_op operations with code_motion_path_driver. */
6009 struct code_motion_path_driver_info_def move_op_hooks = {
6011 move_op_orig_expr_found,
6012 move_op_orig_expr_not_found,
6013 move_op_merge_succs,
6014 move_op_after_merge_succs,
6016 move_op_at_first_insn,
6021 /* Hooks and data to perform find_used_regs operations
6022 with code_motion_path_driver. */
6023 struct code_motion_path_driver_info_def fur_hooks = {
6025 fur_orig_expr_found,
6026 fur_orig_expr_not_found,
6028 NULL, /* fur_after_merge_succs */
6029 NULL, /* fur_ascend */
6035 /* Traverse all successors of INSN. For each successor that is SUCCS_NORMAL
6036 code_motion_path_driver is called recursively. Original operation
6037 was found at least on one path that is starting with one of INSN's
6038 successors (this fact is asserted). ORIG_OPS is expressions we're looking
6039 for, PATH is the path we've traversed, STATIC_PARAMS is the parameters
6040 of either move_op or find_used_regs depending on the caller.
6042 Return 0 if we haven't found expression, 1 if we found it, -1 if we don't
6043 know for sure at this point. */
6045 code_motion_process_successors (insn_t insn, av_set_t orig_ops,
6046 ilist_t path, void *static_params)
6049 succ_iterator succ_i;
6055 struct cmpd_local_params lparams;
6058 lparams.c_expr_local = &_x;
6059 lparams.c_expr_merged = NULL;
6061 /* We need to process only NORMAL succs for move_op, and collect live
6062 registers from ALL branches (including those leading out of the
6063 region) for find_used_regs.
6065 In move_op, there can be a case when insn's bb number has changed
6066 due to created bookkeeping. This happens very rare, as we need to
6067 move expression from the beginning to the end of the same block.
6068 Rescan successors in this case. */
6071 bb = BLOCK_FOR_INSN (insn);
6072 old_index = bb->index;
6073 old_succs = EDGE_COUNT (bb->succs);
6075 FOR_EACH_SUCC_1 (succ, succ_i, insn, code_motion_path_driver_info->succ_flags)
6079 lparams.e1 = succ_i.e1;
6080 lparams.e2 = succ_i.e2;
6082 /* Go deep into recursion only for NORMAL edges (non-backedges within the
6084 if (succ_i.current_flags == SUCCS_NORMAL)
6085 b = code_motion_path_driver (succ, orig_ops, path, &lparams,
6090 /* Merge c_expres found or unify live register sets from different
6092 code_motion_path_driver_info->merge_succs (insn, succ, b, &lparams,
6096 else if (b == -1 && res != 1)
6099 /* We have simplified the control flow below this point. In this case,
6100 the iterator becomes invalid. We need to try again. */
6101 if (BLOCK_FOR_INSN (insn)->index != old_index
6102 || EDGE_COUNT (bb->succs) != old_succs)
6106 #ifdef ENABLE_CHECKING
6107 /* Here, RES==1 if original expr was found at least for one of the
6108 successors. After the loop, RES may happen to have zero value
6109 only if at some point the expr searched is present in av_set, but is
6110 not found below. In most cases, this situation is an error.
6111 The exception is when the original operation is blocked by
6112 bookkeeping generated for another fence or for another path in current
6114 gcc_assert (res == 1
6116 && av_set_could_be_blocked_by_bookkeeping_p (orig_ops,
6121 /* Merge data, clean up, etc. */
6122 if (res != -1 && code_motion_path_driver_info->after_merge_succs)
6123 code_motion_path_driver_info->after_merge_succs (&lparams, static_params);
6129 /* Perform a cleanup when the driver is about to terminate. ORIG_OPS_P
6130 is the pointer to the av set with expressions we were looking for,
6131 PATH_P is the pointer to the traversed path. */
6133 code_motion_path_driver_cleanup (av_set_t *orig_ops_p, ilist_t *path_p)
6135 ilist_remove (path_p);
6136 av_set_clear (orig_ops_p);
6139 /* The driver function that implements move_op or find_used_regs
6140 functionality dependent whether code_motion_path_driver_INFO is set to
6141 &MOVE_OP_HOOKS or &FUR_HOOKS. This function implements the common parts
6142 of code (CFG traversal etc) that are shared among both functions. INSN
6143 is the insn we're starting the search from, ORIG_OPS are the expressions
6144 we're searching for, PATH is traversed path, LOCAL_PARAMS_IN are local
6145 parameters of the driver, and STATIC_PARAMS are static parameters of
6148 Returns whether original instructions were found. Note that top-level
6149 code_motion_path_driver always returns true. */
6151 code_motion_path_driver (insn_t insn, av_set_t orig_ops, ilist_t path,
6152 cmpd_local_params_p local_params_in,
6153 void *static_params)
6156 basic_block bb = BLOCK_FOR_INSN (insn);
6157 insn_t first_insn, bb_tail, before_first;
6158 bool removed_last_insn = false;
6160 if (sched_verbose >= 6)
6162 sel_print ("%s (", code_motion_path_driver_info->routine_name);
6165 dump_av_set (orig_ops);
6169 gcc_assert (orig_ops);
6171 /* If no original operations exist below this insn, return immediately. */
6172 if (is_ineligible_successor (insn, path))
6174 if (sched_verbose >= 6)
6175 sel_print ("Insn %d is ineligible successor\n", INSN_UID (insn));
6179 /* The block can have invalid av set, in which case it was created earlier
6180 during move_op. Return immediately. */
6181 if (sel_bb_head_p (insn))
6183 if (! AV_SET_VALID_P (insn))
6185 if (sched_verbose >= 6)
6186 sel_print ("Returned from block %d as it had invalid av set\n",
6191 if (bitmap_bit_p (code_motion_visited_blocks, bb->index))
6193 /* We have already found an original operation on this branch, do not
6194 go any further and just return TRUE here. If we don't stop here,
6195 function can have exponential behaviour even on the small code
6196 with many different paths (e.g. with data speculation and
6197 recovery blocks). */
6198 if (sched_verbose >= 6)
6199 sel_print ("Block %d already visited in this traversal\n", bb->index);
6200 if (code_motion_path_driver_info->on_enter)
6201 return code_motion_path_driver_info->on_enter (insn,
6208 if (code_motion_path_driver_info->on_enter)
6209 code_motion_path_driver_info->on_enter (insn, local_params_in,
6210 static_params, false);
6211 orig_ops = av_set_copy (orig_ops);
6213 /* Filter the orig_ops set. */
6214 if (AV_SET_VALID_P (insn))
6215 av_set_intersect (&orig_ops, AV_SET (insn));
6217 /* If no more original ops, return immediately. */
6220 if (sched_verbose >= 6)
6221 sel_print ("No intersection with av set of block %d\n", bb->index);
6225 /* For non-speculative insns we have to leave only one form of the
6226 original operation, because if we don't, we may end up with
6227 different C_EXPRes and, consequently, with bookkeepings for different
6228 expression forms along the same code motion path. That may lead to
6229 generation of incorrect code. So for each code motion we stick to
6230 the single form of the instruction, except for speculative insns
6231 which we need to keep in different forms with all speculation
6233 av_set_leave_one_nonspec (&orig_ops);
6235 /* It is not possible that all ORIG_OPS are filtered out. */
6236 gcc_assert (orig_ops);
6238 /* It is enough to place only heads and tails of visited basic blocks into
6240 ilist_add (&path, insn);
6242 bb_tail = sel_bb_end (bb);
6244 /* Descend the basic block in search of the original expr; this part
6245 corresponds to the part of the original move_op procedure executed
6246 before the recursive call. */
6249 /* Look at the insn and decide if it could be an ancestor of currently
6250 scheduling operation. If it is so, then the insn "dest = op" could
6251 either be replaced with "dest = reg", because REG now holds the result
6252 of OP, or just removed, if we've scheduled the insn as a whole.
6254 If this insn doesn't contain currently scheduling OP, then proceed
6255 with searching and look at its successors. Operations we're searching
6256 for could have changed when moving up through this insn via
6257 substituting. In this case, perform unsubstitution on them first.
6259 When traversing the DAG below this insn is finished, insert
6260 bookkeeping code, if the insn is a joint point, and remove
6263 expr = av_set_lookup (orig_ops, INSN_VINSN (insn));
6266 insn_t last_insn = PREV_INSN (insn);
6268 /* We have found the original operation. */
6269 if (sched_verbose >= 6)
6270 sel_print ("Found original operation at insn %d\n", INSN_UID (insn));
6272 code_motion_path_driver_info->orig_expr_found
6273 (insn, expr, local_params_in, static_params);
6275 /* Step back, so on the way back we'll start traversing from the
6276 previous insn (or we'll see that it's bb_note and skip that
6278 if (insn == first_insn)
6280 first_insn = NEXT_INSN (last_insn);
6281 removed_last_insn = sel_bb_end_p (last_insn);
6288 /* We haven't found the original expr, continue descending the basic
6290 if (code_motion_path_driver_info->orig_expr_not_found
6291 (insn, orig_ops, static_params))
6293 /* Av set ops could have been changed when moving through this
6294 insn. To find them below it, we have to un-substitute them. */
6295 undo_transformations (&orig_ops, insn);
6299 /* Clean up and return, if the hook tells us to do so. It may
6300 happen if we've encountered the previously created
6302 code_motion_path_driver_cleanup (&orig_ops, &path);
6306 gcc_assert (orig_ops);
6309 /* Stop at insn if we got to the end of BB. */
6310 if (insn == bb_tail)
6313 insn = NEXT_INSN (insn);
6316 /* Here INSN either points to the insn before the original insn (may be
6317 bb_note, if original insn was a bb_head) or to the bb_end. */
6322 gcc_assert (insn == sel_bb_end (bb));
6324 /* Add bb tail to PATH (but it doesn't make any sense if it's a bb_head -
6325 it's already in PATH then). */
6326 if (insn != first_insn)
6327 ilist_add (&path, insn);
6329 /* Process_successors should be able to find at least one
6330 successor for which code_motion_path_driver returns TRUE. */
6331 res = code_motion_process_successors (insn, orig_ops,
6332 path, static_params);
6334 /* Remove bb tail from path. */
6335 if (insn != first_insn)
6336 ilist_remove (&path);
6340 /* This is the case when one of the original expr is no longer available
6341 due to bookkeeping created on this branch with the same register.
6342 In the original algorithm, which doesn't have update_data_sets call
6343 on a bookkeeping block, it would simply result in returning
6344 FALSE when we've encountered a previously generated bookkeeping
6345 insn in moveop_orig_expr_not_found. */
6346 code_motion_path_driver_cleanup (&orig_ops, &path);
6351 /* Don't need it any more. */
6352 av_set_clear (&orig_ops);
6354 /* Backward pass: now, when we have C_EXPR computed, we'll drag it to
6355 the beginning of the basic block. */
6356 before_first = PREV_INSN (first_insn);
6357 while (insn != before_first)
6359 if (code_motion_path_driver_info->ascend)
6360 code_motion_path_driver_info->ascend (insn, static_params);
6362 insn = PREV_INSN (insn);
6365 /* Now we're at the bb head. */
6367 ilist_remove (&path);
6368 local_params_in->removed_last_insn = removed_last_insn;
6369 code_motion_path_driver_info->at_first_insn (insn, local_params_in, static_params);
6371 /* This should be the very last operation as at bb head we could change
6372 the numbering by creating bookkeeping blocks. */
6373 if (removed_last_insn)
6374 insn = PREV_INSN (insn);
6375 bitmap_set_bit (code_motion_visited_blocks, BLOCK_FOR_INSN (insn)->index);
6379 /* Move up the operations from ORIG_OPS set traversing the dag starting
6380 from INSN. PATH represents the edges traversed so far.
6381 DEST is the register chosen for scheduling the current expr. Insert
6382 bookkeeping code in the join points. EXPR_VLIW is the chosen expression,
6383 C_EXPR is how it looks like at the given cfg point.
6384 Set *SHOULD_MOVE to indicate whether we have only disconnected
6385 one of the insns found.
6387 Returns whether original instructions were found, which is asserted
6388 to be true in the caller. */
6390 move_op (insn_t insn, av_set_t orig_ops, expr_t expr_vliw,
6391 rtx dest, expr_t c_expr, bool *should_move)
6393 struct moveop_static_params sparams;
6394 struct cmpd_local_params lparams;
6397 /* Init params for code_motion_path_driver. */
6398 sparams.dest = dest;
6399 sparams.c_expr = c_expr;
6400 sparams.uid = INSN_UID (EXPR_INSN_RTX (expr_vliw));
6401 #ifdef ENABLE_CHECKING
6402 sparams.failed_insn = NULL;
6404 sparams.was_renamed = false;
6407 /* We haven't visited any blocks yet. */
6408 bitmap_clear (code_motion_visited_blocks);
6410 /* Set appropriate hooks and data. */
6411 code_motion_path_driver_info = &move_op_hooks;
6412 res = code_motion_path_driver (insn, orig_ops, NULL, &lparams, &sparams);
6414 if (sparams.was_renamed)
6415 EXPR_WAS_RENAMED (expr_vliw) = true;
6417 *should_move = (sparams.uid == -1);
6423 /* Functions that work with regions. */
6425 /* Current number of seqno used in init_seqno and init_seqno_1. */
6426 static int cur_seqno;
6428 /* A helper for init_seqno. Traverse the region starting from BB and
6429 compute seqnos for visited insns, marking visited bbs in VISITED_BBS.
6430 Clear visited blocks from BLOCKS_TO_RESCHEDULE. */
6432 init_seqno_1 (basic_block bb, sbitmap visited_bbs, bitmap blocks_to_reschedule)
6434 int bbi = BLOCK_TO_BB (bb->index);
6435 insn_t insn, note = bb_note (bb);
6439 SET_BIT (visited_bbs, bbi);
6440 if (blocks_to_reschedule)
6441 bitmap_clear_bit (blocks_to_reschedule, bb->index);
6443 FOR_EACH_SUCC_1 (succ_insn, si, BB_END (bb),
6444 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
6446 basic_block succ = BLOCK_FOR_INSN (succ_insn);
6447 int succ_bbi = BLOCK_TO_BB (succ->index);
6449 gcc_assert (in_current_region_p (succ));
6451 if (!TEST_BIT (visited_bbs, succ_bbi))
6453 gcc_assert (succ_bbi > bbi);
6455 init_seqno_1 (succ, visited_bbs, blocks_to_reschedule);
6459 for (insn = BB_END (bb); insn != note; insn = PREV_INSN (insn))
6460 INSN_SEQNO (insn) = cur_seqno--;
6463 /* Initialize seqnos for the current region. NUMBER_OF_INSNS is the number
6464 of instructions in the region, BLOCKS_TO_RESCHEDULE contains blocks on
6465 which we're rescheduling when pipelining, FROM is the block where
6466 traversing region begins (it may not be the head of the region when
6467 pipelining, but the head of the loop instead).
6469 Returns the maximal seqno found. */
6471 init_seqno (int number_of_insns, bitmap blocks_to_reschedule, basic_block from)
6473 sbitmap visited_bbs;
6477 visited_bbs = sbitmap_alloc (current_nr_blocks);
6479 if (blocks_to_reschedule)
6481 sbitmap_ones (visited_bbs);
6482 EXECUTE_IF_SET_IN_BITMAP (blocks_to_reschedule, 0, bbi, bi)
6484 gcc_assert (BLOCK_TO_BB (bbi) < current_nr_blocks);
6485 RESET_BIT (visited_bbs, BLOCK_TO_BB (bbi));
6490 sbitmap_zero (visited_bbs);
6491 from = EBB_FIRST_BB (0);
6494 cur_seqno = number_of_insns > 0 ? number_of_insns : sched_max_luid - 1;
6495 init_seqno_1 (from, visited_bbs, blocks_to_reschedule);
6496 gcc_assert (cur_seqno == 0 || number_of_insns == 0);
6498 sbitmap_free (visited_bbs);
6499 return sched_max_luid - 1;
6502 /* Initialize scheduling parameters for current region. */
6504 sel_setup_region_sched_flags (void)
6506 enable_schedule_as_rhs_p = 1;
6508 pipelining_p = (bookkeeping_p
6509 && (flag_sel_sched_pipelining != 0)
6510 && current_loop_nest != NULL);
6511 max_insns_to_rename = PARAM_VALUE (PARAM_SELSCHED_INSNS_TO_RENAME);
6515 /* Return true if all basic blocks of current region are empty. */
6517 current_region_empty_p (void)
6520 for (i = 0; i < current_nr_blocks; i++)
6521 if (! sel_bb_empty_p (BASIC_BLOCK (BB_TO_BLOCK (i))))
6527 /* Prepare and verify loop nest for pipelining. */
6529 setup_current_loop_nest (int rgn)
6531 current_loop_nest = get_loop_nest_for_rgn (rgn);
6533 if (!current_loop_nest)
6536 /* If this loop has any saved loop preheaders from nested loops,
6537 add these basic blocks to the current region. */
6538 sel_add_loop_preheaders ();
6540 /* Check that we're starting with a valid information. */
6541 gcc_assert (loop_latch_edge (current_loop_nest));
6542 gcc_assert (LOOP_MARKED_FOR_PIPELINING_P (current_loop_nest));
6545 /* Compute instruction priorities for current region. */
6547 sel_compute_priorities (int rgn)
6549 sched_rgn_compute_dependencies (rgn);
6551 /* Compute insn priorities in haifa style. Then free haifa style
6552 dependencies that we've calculated for this. */
6553 compute_priorities ();
6555 if (sched_verbose >= 5)
6556 debug_rgn_dependencies (0);
6561 /* Init scheduling data for RGN. Returns true when this region should not
6564 sel_region_init (int rgn)
6569 rgn_setup_region (rgn);
6571 /* Even if sched_is_disabled_for_current_region_p() is true, we still
6572 do region initialization here so the region can be bundled correctly,
6573 but we'll skip the scheduling in sel_sched_region (). */
6574 if (current_region_empty_p ())
6577 if (flag_sel_sched_pipelining)
6578 setup_current_loop_nest (rgn);
6580 sel_setup_region_sched_flags ();
6582 bbs = VEC_alloc (basic_block, heap, current_nr_blocks);
6584 for (i = 0; i < current_nr_blocks; i++)
6585 VEC_quick_push (basic_block, bbs, BASIC_BLOCK (BB_TO_BLOCK (i)));
6587 sel_init_bbs (bbs, NULL);
6589 /* Initialize luids and dependence analysis which both sel-sched and haifa
6591 sched_init_luids (bbs, NULL, NULL, NULL);
6592 sched_deps_init (false);
6594 /* Initialize haifa data. */
6595 rgn_setup_sched_infos ();
6596 sel_set_sched_flags ();
6597 haifa_init_h_i_d (bbs, NULL, NULL, NULL);
6599 sel_compute_priorities (rgn);
6600 init_deps_global ();
6602 /* Main initialization. */
6603 sel_setup_sched_infos ();
6604 sel_init_global_and_expr (bbs);
6606 VEC_free (basic_block, heap, bbs);
6608 blocks_to_reschedule = BITMAP_ALLOC (NULL);
6610 /* Init correct liveness sets on each instruction of a single-block loop.
6611 This is the only situation when we can't update liveness when calling
6612 compute_live for the first insn of the loop. */
6613 if (current_loop_nest)
6615 int header = (sel_is_loop_preheader_p (BASIC_BLOCK (BB_TO_BLOCK (0)))
6619 if (current_nr_blocks == header + 1)
6620 update_liveness_on_insn
6621 (sel_bb_head (BASIC_BLOCK (BB_TO_BLOCK (header))));
6624 /* Set hooks so that no newly generated insn will go out unnoticed. */
6625 sel_register_cfg_hooks ();
6627 /* !!! We call target.sched.md_init () for the whole region, but we invoke
6628 targetm.sched.md_finish () for every ebb. */
6629 if (targetm.sched.md_init)
6630 /* None of the arguments are actually used in any target. */
6631 targetm.sched.md_init (sched_dump, sched_verbose, -1);
6633 first_emitted_uid = get_max_uid () + 1;
6634 preheader_removed = false;
6636 /* Reset register allocation ticks array. */
6637 memset (reg_rename_tick, 0, sizeof reg_rename_tick);
6638 reg_rename_this_tick = 0;
6640 bitmap_initialize (forced_ebb_heads, 0);
6641 bitmap_clear (forced_ebb_heads);
6644 current_copies = BITMAP_ALLOC (NULL);
6645 current_originators = BITMAP_ALLOC (NULL);
6646 code_motion_visited_blocks = BITMAP_ALLOC (NULL);
6651 /* Simplify insns after the scheduling. */
6653 simplify_changed_insns (void)
6657 for (i = 0; i < current_nr_blocks; i++)
6659 basic_block bb = BASIC_BLOCK (BB_TO_BLOCK (i));
6662 FOR_BB_INSNS (bb, insn)
6665 expr_t expr = INSN_EXPR (insn);
6667 if (EXPR_WAS_SUBSTITUTED (expr))
6668 validate_simplify_insn (insn);
6673 /* Find boundaries of the EBB starting from basic block BB, marking blocks of
6674 this EBB in SCHEDULED_BLOCKS and appropriately filling in HEAD, TAIL,
6675 PREV_HEAD, and NEXT_TAIL fields of CURRENT_SCHED_INFO structure. */
6677 find_ebb_boundaries (basic_block bb, bitmap scheduled_blocks)
6680 basic_block bb1 = bb;
6681 if (sched_verbose >= 2)
6682 sel_print ("Finishing schedule in bbs: ");
6686 bitmap_set_bit (scheduled_blocks, BLOCK_TO_BB (bb1->index));
6688 if (sched_verbose >= 2)
6689 sel_print ("%d; ", bb1->index);
6691 while (!bb_ends_ebb_p (bb1) && (bb1 = bb_next_bb (bb1)));
6693 if (sched_verbose >= 2)
6696 get_ebb_head_tail (bb, bb1, &head, &tail);
6698 current_sched_info->head = head;
6699 current_sched_info->tail = tail;
6700 current_sched_info->prev_head = PREV_INSN (head);
6701 current_sched_info->next_tail = NEXT_INSN (tail);
6704 /* Regenerate INSN_SCHED_CYCLEs for insns of current EBB. */
6706 reset_sched_cycles_in_current_ebb (void)
6709 int haifa_last_clock = -1;
6710 int haifa_clock = 0;
6713 if (targetm.sched.md_init)
6715 /* None of the arguments are actually used in any target.
6716 NB: We should have md_reset () hook for cases like this. */
6717 targetm.sched.md_init (sched_dump, sched_verbose, -1);
6720 state_reset (curr_state);
6721 advance_state (curr_state);
6723 for (insn = current_sched_info->head;
6724 insn != current_sched_info->next_tail;
6725 insn = NEXT_INSN (insn))
6727 int cost, haifa_cost;
6729 bool asm_p, real_insn, after_stall;
6736 real_insn = recog_memoized (insn) >= 0;
6737 clock = INSN_SCHED_CYCLE (insn);
6739 cost = clock - last_clock;
6741 /* Initialize HAIFA_COST. */
6744 asm_p = INSN_ASM_P (insn);
6747 /* This is asm insn which *had* to be scheduled first
6751 /* This is a use/clobber insn. It should not change
6756 haifa_cost = estimate_insn_cost (insn, curr_state);
6758 /* Stall for whatever cycles we've stalled before. */
6760 if (INSN_AFTER_STALL_P (insn) && cost > haifa_cost)
6770 while (haifa_cost--)
6772 advance_state (curr_state);
6775 if (sched_verbose >= 2)
6777 sel_print ("advance_state (state_transition)\n");
6778 debug_state (curr_state);
6781 /* The DFA may report that e.g. insn requires 2 cycles to be
6782 issued, but on the next cycle it says that insn is ready
6783 to go. Check this here. */
6787 && estimate_insn_cost (insn, curr_state) == 0)
6794 gcc_assert (haifa_cost == 0);
6796 if (sched_verbose >= 2)
6797 sel_print ("Haifa cost for insn %d: %d\n", INSN_UID (insn), haifa_cost);
6799 if (targetm.sched.dfa_new_cycle)
6800 while (targetm.sched.dfa_new_cycle (sched_dump, sched_verbose, insn,
6801 haifa_last_clock, haifa_clock,
6804 advance_state (curr_state);
6806 if (sched_verbose >= 2)
6808 sel_print ("advance_state (dfa_new_cycle)\n");
6809 debug_state (curr_state);
6815 cost = state_transition (curr_state, insn);
6817 if (sched_verbose >= 2)
6818 debug_state (curr_state);
6820 gcc_assert (cost < 0);
6823 if (targetm.sched.variable_issue)
6824 targetm.sched.variable_issue (sched_dump, sched_verbose, insn, 0);
6826 INSN_SCHED_CYCLE (insn) = haifa_clock;
6829 haifa_last_clock = haifa_clock;
6833 /* Put TImode markers on insns starting a new issue group. */
6837 int last_clock = -1;
6840 for (insn = current_sched_info->head; insn != current_sched_info->next_tail;
6841 insn = NEXT_INSN (insn))
6848 clock = INSN_SCHED_CYCLE (insn);
6849 cost = (last_clock == -1) ? 1 : clock - last_clock;
6851 gcc_assert (cost >= 0);
6854 && GET_CODE (PATTERN (insn)) != USE
6855 && GET_CODE (PATTERN (insn)) != CLOBBER)
6857 if (reload_completed && cost > 0)
6858 PUT_MODE (insn, TImode);
6863 if (sched_verbose >= 2)
6864 sel_print ("Cost for insn %d is %d\n", INSN_UID (insn), cost);
6868 /* Perform MD_FINISH on EBBs comprising current region. When
6869 RESET_SCHED_CYCLES_P is true, run a pass emulating the scheduler
6870 to produce correct sched cycles on insns. */
6872 sel_region_target_finish (bool reset_sched_cycles_p)
6875 bitmap scheduled_blocks = BITMAP_ALLOC (NULL);
6877 for (i = 0; i < current_nr_blocks; i++)
6879 if (bitmap_bit_p (scheduled_blocks, i))
6882 /* While pipelining outer loops, skip bundling for loop
6883 preheaders. Those will be rescheduled in the outer loop. */
6884 if (sel_is_loop_preheader_p (EBB_FIRST_BB (i)))
6887 find_ebb_boundaries (EBB_FIRST_BB (i), scheduled_blocks);
6889 if (no_real_insns_p (current_sched_info->head, current_sched_info->tail))
6892 if (reset_sched_cycles_p)
6893 reset_sched_cycles_in_current_ebb ();
6895 if (targetm.sched.md_init)
6896 targetm.sched.md_init (sched_dump, sched_verbose, -1);
6900 if (targetm.sched.md_finish)
6902 targetm.sched.md_finish (sched_dump, sched_verbose);
6904 /* Extend luids so that insns generated by the target will
6906 sched_init_luids (NULL, NULL, NULL, NULL);
6910 BITMAP_FREE (scheduled_blocks);
6913 /* Free the scheduling data for the current region. When RESET_SCHED_CYCLES_P
6914 is true, make an additional pass emulating scheduler to get correct insn
6915 cycles for md_finish calls. */
6917 sel_region_finish (bool reset_sched_cycles_p)
6919 simplify_changed_insns ();
6920 sched_finish_ready_list ();
6923 /* Free the vectors. */
6925 VEC_free (expr_t, heap, vec_av_set);
6926 BITMAP_FREE (current_copies);
6927 BITMAP_FREE (current_originators);
6928 BITMAP_FREE (code_motion_visited_blocks);
6929 vinsn_vec_free (&vec_bookkeeping_blocked_vinsns);
6930 vinsn_vec_free (&vec_target_unavailable_vinsns);
6932 /* If LV_SET of the region head should be updated, do it now because
6933 there will be no other chance. */
6938 FOR_EACH_SUCC_1 (insn, si, bb_note (EBB_FIRST_BB (0)),
6939 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
6941 basic_block bb = BLOCK_FOR_INSN (insn);
6943 if (!BB_LV_SET_VALID_P (bb))
6944 compute_live (insn);
6948 /* Emulate the Haifa scheduler for bundling. */
6949 if (reload_completed)
6950 sel_region_target_finish (reset_sched_cycles_p);
6952 sel_finish_global_and_expr ();
6954 bitmap_clear (forced_ebb_heads);
6958 finish_deps_global ();
6959 sched_finish_luids ();
6962 BITMAP_FREE (blocks_to_reschedule);
6964 sel_unregister_cfg_hooks ();
6970 /* Functions that implement the scheduler driver. */
6972 /* Schedule a parallel instruction group on each of FENCES. MAX_SEQNO
6973 is the current maximum seqno. SCHEDULED_INSNS_TAILPP is the list
6974 of insns scheduled -- these would be postprocessed later. */
6976 schedule_on_fences (flist_t fences, int max_seqno,
6977 ilist_t **scheduled_insns_tailpp)
6979 flist_t old_fences = fences;
6981 if (sched_verbose >= 1)
6983 sel_print ("\nScheduling on fences: ");
6984 dump_flist (fences);
6988 scheduled_something_on_previous_fence = false;
6989 for (; fences; fences = FLIST_NEXT (fences))
6991 fence_t fence = NULL;
6994 bool first_p = true;
6996 /* Choose the next fence group to schedule.
6997 The fact that insn can be scheduled only once
6998 on the cycle is guaranteed by two properties:
6999 1. seqnos of parallel groups decrease with each iteration.
7000 2. If is_ineligible_successor () sees the larger seqno, it
7001 checks if candidate insn is_in_current_fence_p (). */
7002 for (fences2 = old_fences; fences2; fences2 = FLIST_NEXT (fences2))
7004 fence_t f = FLIST_FENCE (fences2);
7006 if (!FENCE_PROCESSED_P (f))
7008 int i = INSN_SEQNO (FENCE_INSN (f));
7010 if (first_p || i > seqno)
7017 /* ??? Seqnos of different groups should be different. */
7018 gcc_assert (1 || i != seqno);
7024 /* As FENCE is nonnull, SEQNO is initialized. */
7025 seqno -= max_seqno + 1;
7026 fill_insns (fence, seqno, scheduled_insns_tailpp);
7027 FENCE_PROCESSED_P (fence) = true;
7030 /* All av_sets are invalidated by GLOBAL_LEVEL increase, thus we
7031 don't need to keep bookkeeping-invalidated and target-unavailable
7033 vinsn_vec_clear (&vec_bookkeeping_blocked_vinsns);
7034 vinsn_vec_clear (&vec_target_unavailable_vinsns);
7037 /* Calculate MIN_SEQNO and MAX_SEQNO. */
7039 find_min_max_seqno (flist_t fences, int *min_seqno, int *max_seqno)
7041 *min_seqno = *max_seqno = INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences)));
7043 /* The first element is already processed. */
7044 while ((fences = FLIST_NEXT (fences)))
7046 int seqno = INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences)));
7048 if (*min_seqno > seqno)
7050 else if (*max_seqno < seqno)
7055 /* Calculate new fences from FENCES. */
7057 calculate_new_fences (flist_t fences, int orig_max_seqno)
7059 flist_t old_fences = fences;
7060 struct flist_tail_def _new_fences, *new_fences = &_new_fences;
7062 flist_tail_init (new_fences);
7063 for (; fences; fences = FLIST_NEXT (fences))
7065 fence_t fence = FLIST_FENCE (fences);
7068 if (!FENCE_BNDS (fence))
7070 /* This fence doesn't have any successors. */
7071 if (!FENCE_SCHEDULED_P (fence))
7073 /* Nothing was scheduled on this fence. */
7076 insn = FENCE_INSN (fence);
7077 seqno = INSN_SEQNO (insn);
7078 gcc_assert (seqno > 0 && seqno <= orig_max_seqno);
7080 if (sched_verbose >= 1)
7081 sel_print ("Fence %d[%d] has not changed\n",
7084 move_fence_to_fences (fences, new_fences);
7088 extract_new_fences_from (fences, new_fences, orig_max_seqno);
7091 flist_clear (&old_fences);
7092 return FLIST_TAIL_HEAD (new_fences);
7095 /* Update seqnos of insns given by PSCHEDULED_INSNS. MIN_SEQNO and MAX_SEQNO
7096 are the miminum and maximum seqnos of the group, HIGHEST_SEQNO_IN_USE is
7097 the highest seqno used in a region. Return the updated highest seqno. */
7099 update_seqnos_and_stage (int min_seqno, int max_seqno,
7100 int highest_seqno_in_use,
7101 ilist_t *pscheduled_insns)
7107 /* Actually, new_hs is the seqno of the instruction, that was
7108 scheduled first (i.e. it is the first one in SCHEDULED_INSNS). */
7109 if (*pscheduled_insns)
7111 new_hs = (INSN_SEQNO (ILIST_INSN (*pscheduled_insns))
7112 + highest_seqno_in_use + max_seqno - min_seqno + 2);
7113 gcc_assert (new_hs > highest_seqno_in_use);
7116 new_hs = highest_seqno_in_use;
7118 FOR_EACH_INSN (insn, ii, *pscheduled_insns)
7120 gcc_assert (INSN_SEQNO (insn) < 0);
7121 INSN_SEQNO (insn) += highest_seqno_in_use + max_seqno - min_seqno + 2;
7122 gcc_assert (INSN_SEQNO (insn) <= new_hs);
7124 /* When not pipelining, purge unneeded insn info on the scheduled insns.
7125 For example, having reg_last array of INSN_DEPS_CONTEXT in memory may
7126 require > 1GB of memory e.g. on limit-fnargs.c. */
7128 free_data_for_scheduled_insn (insn);
7131 ilist_clear (pscheduled_insns);
7137 /* The main driver for scheduling a region. This function is responsible
7138 for correct propagation of fences (i.e. scheduling points) and creating
7139 a group of parallel insns at each of them. It also supports
7140 pipelining. ORIG_MAX_SEQNO is the maximal seqno before this pass
7143 sel_sched_region_2 (int orig_max_seqno)
7145 int highest_seqno_in_use = orig_max_seqno;
7147 stat_bookkeeping_copies = 0;
7148 stat_insns_needed_bookkeeping = 0;
7149 stat_renamed_scheduled = 0;
7150 stat_substitutions_total = 0;
7151 num_insns_scheduled = 0;
7155 int min_seqno, max_seqno;
7156 ilist_t scheduled_insns = NULL;
7157 ilist_t *scheduled_insns_tailp = &scheduled_insns;
7159 find_min_max_seqno (fences, &min_seqno, &max_seqno);
7160 schedule_on_fences (fences, max_seqno, &scheduled_insns_tailp);
7161 fences = calculate_new_fences (fences, orig_max_seqno);
7162 highest_seqno_in_use = update_seqnos_and_stage (min_seqno, max_seqno,
7163 highest_seqno_in_use,
7167 if (sched_verbose >= 1)
7168 sel_print ("Scheduled %d bookkeeping copies, %d insns needed "
7169 "bookkeeping, %d insns renamed, %d insns substituted\n",
7170 stat_bookkeeping_copies,
7171 stat_insns_needed_bookkeeping,
7172 stat_renamed_scheduled,
7173 stat_substitutions_total);
7176 /* Schedule a region. When pipelining, search for possibly never scheduled
7177 bookkeeping code and schedule it. Reschedule pipelined code without
7178 pipelining after. */
7180 sel_sched_region_1 (void)
7182 int number_of_insns;
7185 /* Remove empty blocks that might be in the region from the beginning.
7186 We need to do save sched_max_luid before that, as it actually shows
7187 the number of insns in the region, and purge_empty_blocks can
7189 number_of_insns = sched_max_luid - 1;
7190 purge_empty_blocks ();
7192 orig_max_seqno = init_seqno (number_of_insns, NULL, NULL);
7193 gcc_assert (orig_max_seqno >= 1);
7195 /* When pipelining outer loops, create fences on the loop header,
7198 if (current_loop_nest)
7199 init_fences (BB_END (EBB_FIRST_BB (0)));
7201 init_fences (bb_note (EBB_FIRST_BB (0)));
7204 sel_sched_region_2 (orig_max_seqno);
7206 gcc_assert (fences == NULL);
7212 struct flist_tail_def _new_fences;
7213 flist_tail_t new_fences = &_new_fences;
7216 pipelining_p = false;
7217 max_ws = MIN (max_ws, issue_rate * 3 / 2);
7218 bookkeeping_p = false;
7219 enable_schedule_as_rhs_p = false;
7221 /* Schedule newly created code, that has not been scheduled yet. */
7228 for (i = 0; i < current_nr_blocks; i++)
7230 basic_block bb = EBB_FIRST_BB (i);
7232 if (sel_bb_empty_p (bb))
7234 bitmap_clear_bit (blocks_to_reschedule, bb->index);
7238 if (bitmap_bit_p (blocks_to_reschedule, bb->index))
7240 clear_outdated_rtx_info (bb);
7241 if (sel_insn_is_speculation_check (BB_END (bb))
7242 && JUMP_P (BB_END (bb)))
7243 bitmap_set_bit (blocks_to_reschedule,
7244 BRANCH_EDGE (bb)->dest->index);
7246 else if (INSN_SCHED_TIMES (sel_bb_head (bb)) <= 0)
7247 bitmap_set_bit (blocks_to_reschedule, bb->index);
7250 for (i = 0; i < current_nr_blocks; i++)
7252 bb = EBB_FIRST_BB (i);
7254 /* While pipelining outer loops, skip bundling for loop
7255 preheaders. Those will be rescheduled in the outer
7257 if (sel_is_loop_preheader_p (bb))
7259 clear_outdated_rtx_info (bb);
7263 if (bitmap_bit_p (blocks_to_reschedule, bb->index))
7265 flist_tail_init (new_fences);
7267 orig_max_seqno = init_seqno (0, blocks_to_reschedule, bb);
7269 /* Mark BB as head of the new ebb. */
7270 bitmap_set_bit (forced_ebb_heads, bb->index);
7272 bitmap_clear_bit (blocks_to_reschedule, bb->index);
7274 gcc_assert (fences == NULL);
7276 init_fences (bb_note (bb));
7278 sel_sched_region_2 (orig_max_seqno);
7288 /* Schedule the RGN region. */
7290 sel_sched_region (int rgn)
7293 bool reset_sched_cycles_p;
7295 if (sel_region_init (rgn))
7298 if (sched_verbose >= 1)
7299 sel_print ("Scheduling region %d\n", rgn);
7301 schedule_p = (!sched_is_disabled_for_current_region_p ()
7302 && dbg_cnt (sel_sched_region_cnt));
7303 reset_sched_cycles_p = pipelining_p;
7305 sel_sched_region_1 ();
7307 /* Force initialization of INSN_SCHED_CYCLEs for correct bundling. */
7308 reset_sched_cycles_p = true;
7310 sel_region_finish (reset_sched_cycles_p);
7313 /* Perform global init for the scheduler. */
7315 sel_global_init (void)
7317 calculate_dominance_info (CDI_DOMINATORS);
7318 alloc_sched_pools ();
7320 /* Setup the infos for sched_init. */
7321 sel_setup_sched_infos ();
7322 setup_sched_dump ();
7324 sched_rgn_init (false);
7328 /* Reset AFTER_RECOVERY if it has been set by the 1st scheduler pass. */
7330 can_issue_more = issue_rate;
7332 sched_extend_target ();
7333 sched_deps_init (true);
7334 setup_nop_and_exit_insns ();
7335 sel_extend_global_bb_info ();
7337 init_hard_regs_data ();
7340 /* Free the global data of the scheduler. */
7342 sel_global_finish (void)
7344 free_bb_note_pool ();
7346 sel_finish_global_bb_info ();
7348 free_regset_pool ();
7349 free_nop_and_exit_insns ();
7351 sched_rgn_finish ();
7352 sched_deps_finish ();
7356 sel_finish_pipelining ();
7358 free_sched_pools ();
7359 free_dominance_info (CDI_DOMINATORS);
7362 /* Return true when we need to skip selective scheduling. Used for debugging. */
7364 maybe_skip_selective_scheduling (void)
7366 return ! dbg_cnt (sel_sched_cnt);
7369 /* The entry point. */
7371 run_selective_scheduling (void)
7375 if (n_basic_blocks == NUM_FIXED_BLOCKS)
7380 for (rgn = 0; rgn < nr_regions; rgn++)
7381 sel_sched_region (rgn);
7383 sel_global_finish ();