2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.22 2004/02/17 19:38:53 dillon Exp $
32 #include <machine/smptests.h>
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/sysctl.h>
41 #include <sys/malloc.h>
42 #include <sys/memrange.h>
43 #include <sys/cons.h> /* cngetc() */
46 #include <vm/vm_param.h>
48 #include <vm/vm_kern.h>
49 #include <vm/vm_extern.h>
51 #include <vm/vm_map.h>
57 #include <machine/smp.h>
58 #include <machine/apic.h>
59 #include <machine/atomic.h>
60 #include <machine/cpufunc.h>
61 #include <machine/mpapic.h>
62 #include <machine/psl.h>
63 #include <machine/segments.h>
64 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
65 #include <machine/tss.h>
66 #include <machine/specialreg.h>
67 #include <machine/globaldata.h>
70 #include <machine/md_var.h> /* setidt() */
71 #include <i386/isa/icu.h> /* IPIs */
72 #include <i386/isa/intr_machdep.h> /* IPIs */
75 #if defined(TEST_DEFAULT_CONFIG)
76 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
78 #define MPFPS_MPFB1 mpfps->mpfb1
79 #endif /* TEST_DEFAULT_CONFIG */
81 #define WARMBOOT_TARGET 0
82 #define WARMBOOT_OFF (KERNBASE + 0x0467)
83 #define WARMBOOT_SEG (KERNBASE + 0x0469)
86 #define BIOS_BASE (0xe8000)
87 #define BIOS_SIZE (0x18000)
89 #define BIOS_BASE (0xf0000)
90 #define BIOS_SIZE (0x10000)
92 #define BIOS_COUNT (BIOS_SIZE/4)
94 #define CMOS_REG (0x70)
95 #define CMOS_DATA (0x71)
96 #define BIOS_RESET (0x0f)
97 #define BIOS_WARM (0x0a)
99 #define PROCENTRY_FLAG_EN 0x01
100 #define PROCENTRY_FLAG_BP 0x02
101 #define IOAPICENTRY_FLAG_EN 0x01
104 /* MP Floating Pointer Structure */
105 typedef struct MPFPS {
118 /* MP Configuration Table Header */
119 typedef struct MPCTH {
121 u_short base_table_length;
125 u_char product_id[12];
126 void *oem_table_pointer;
127 u_short oem_table_size;
130 u_short extended_table_length;
131 u_char extended_table_checksum;
136 typedef struct PROCENTRY {
141 u_long cpu_signature;
142 u_long feature_flags;
147 typedef struct BUSENTRY {
153 typedef struct IOAPICENTRY {
159 } *io_apic_entry_ptr;
161 typedef struct INTENTRY {
171 /* descriptions of MP basetable entries */
172 typedef struct BASETABLE_ENTRY {
179 * this code MUST be enabled here and in mpboot.s.
180 * it follows the very early stages of AP boot by placing values in CMOS ram.
181 * it NORMALLY will never be needed and thus the primitive method for enabling.
184 #if defined(CHECK_POINTS) && !defined(PC98)
185 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
186 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
188 #define CHECK_INIT(D); \
189 CHECK_WRITE(0x34, (D)); \
190 CHECK_WRITE(0x35, (D)); \
191 CHECK_WRITE(0x36, (D)); \
192 CHECK_WRITE(0x37, (D)); \
193 CHECK_WRITE(0x38, (D)); \
194 CHECK_WRITE(0x39, (D));
196 #define CHECK_PRINT(S); \
197 printf("%s: %d, %d, %d, %d, %d, %d\n", \
206 #else /* CHECK_POINTS */
208 #define CHECK_INIT(D)
209 #define CHECK_PRINT(S)
211 #endif /* CHECK_POINTS */
214 * Values to send to the POST hardware.
216 #define MP_BOOTADDRESS_POST 0x10
217 #define MP_PROBE_POST 0x11
218 #define MPTABLE_PASS1_POST 0x12
220 #define MP_START_POST 0x13
221 #define MP_ENABLE_POST 0x14
222 #define MPTABLE_PASS2_POST 0x15
224 #define START_ALL_APS_POST 0x16
225 #define INSTALL_AP_TRAMP_POST 0x17
226 #define START_AP_POST 0x18
228 #define MP_ANNOUNCE_POST 0x19
230 static int need_hyperthreading_fixup;
231 static u_int logical_cpus;
232 u_int logical_cpus_mask;
234 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
235 int current_postcode;
237 /** XXX FIXME: what system files declare these??? */
238 extern struct region_descriptor r_gdt, r_idt;
240 int bsp_apic_ready = 0; /* flags useability of BSP apic */
241 int mp_naps; /* # of Applications processors */
242 int mp_nbusses; /* # of busses */
243 int mp_napics; /* # of IO APICs */
244 int boot_cpu_id; /* designated BSP */
245 vm_offset_t cpu_apic_address;
246 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
249 u_int32_t cpu_apic_versions[MAXCPU];
250 u_int32_t *io_apic_versions;
252 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
254 #ifdef APIC_INTR_REORDER
256 volatile int *location;
258 } apic_isrbit_location[32];
263 * APIC ID logical/physical mapping structures.
264 * We oversize these to simplify boot-time config.
266 int cpu_num_to_apic_id[NAPICID];
267 int io_num_to_apic_id[NAPICID];
268 int apic_id_to_logical[NAPICID];
270 /* AP uses this during bootstrap. Do not staticize. */
274 /* Hotwire a 0->4MB V==P mapping */
275 extern pt_entry_t *KPTphys;
277 /* SMP page table page */
278 extern pt_entry_t *SMPpt;
280 struct pcb stoppcbs[MAXCPU];
283 * Local data and functions.
286 static int mp_capable;
287 static u_int boot_address;
288 static u_int base_memory;
289 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
291 static int picmode; /* 0: virtual wire mode, 1: PIC mode */
292 static mpfps_t mpfps;
293 static int search_for_sig(u_int32_t target, int count);
294 static void mp_enable(u_int boot_addr);
296 static void mptable_hyperthread_fixup(u_int id_mask);
297 static void mptable_pass1(void);
298 static int mptable_pass2(void);
299 static void default_mp_table(int type);
300 static void fix_mp_table(void);
301 static void setup_apic_irq_mapping(void);
302 static int start_all_aps(u_int boot_addr);
303 static void install_ap_tramp(u_int boot_addr);
304 static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
305 static int apic_int_is_bus_type(int intr, int bus_type);
307 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
308 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
311 * Calculate usable address in base memory for AP trampoline code.
314 mp_bootaddress(u_int basemem)
316 POSTCODE(MP_BOOTADDRESS_POST);
318 base_memory = basemem * 1024; /* convert to bytes */
320 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
321 if ((base_memory - boot_address) < bootMP_size)
322 boot_address -= 4096; /* not enough, lower by 4k */
329 * Look for an Intel MP spec table (ie, SMP capable hardware).
338 POSTCODE(MP_PROBE_POST);
340 /* see if EBDA exists */
341 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
342 /* search first 1K of EBDA */
343 target = (u_int32_t) (segment << 4);
344 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
347 /* last 1K of base memory, effective 'top of base' passed in */
348 target = (u_int32_t) (base_memory - 0x400);
349 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
353 /* search the BIOS */
354 target = (u_int32_t) BIOS_BASE;
355 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
364 /* calculate needed resources */
368 /* flag fact that we are running multiple processors */
375 * Startup the SMP processors.
380 POSTCODE(MP_START_POST);
382 /* look for MP capable motherboard */
384 mp_enable(boot_address);
386 panic("MP hardware not found!");
391 * Print various information about the SMP system hardware and setup.
398 POSTCODE(MP_ANNOUNCE_POST);
400 printf("FreeBSD/SMP: Multiprocessor motherboard\n");
401 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
402 printf(", version: 0x%08x", cpu_apic_versions[0]);
403 printf(", at 0x%08x\n", cpu_apic_address);
404 for (x = 1; x <= mp_naps; ++x) {
405 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
406 printf(", version: 0x%08x", cpu_apic_versions[x]);
407 printf(", at 0x%08x\n", cpu_apic_address);
411 for (x = 0; x < mp_napics; ++x) {
412 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
413 printf(", version: 0x%08x", io_apic_versions[x]);
414 printf(", at 0x%08x\n", io_apic_address[x]);
417 printf(" Warning: APIC I/O disabled\n");
422 * AP cpu's call this to sync up protected mode.
428 int x, myid = bootAP;
430 struct mdglobaldata *md;
431 struct privatespace *ps;
433 ps = &CPU_prvspace[myid];
435 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
436 gdt_segs[GPROC0_SEL].ssd_base =
437 (int) &ps->mdglobaldata.gd_common_tss;
438 ps->mdglobaldata.mi.gd_prvspace = ps;
440 for (x = 0; x < NGDT; x++) {
441 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
444 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
445 r_gdt.rd_base = (int) &gdt[myid * NGDT];
446 lgdt(&r_gdt); /* does magic intra-segment return */
451 mdcpu->gd_currentldt = _default_ldt;
453 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
454 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
456 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
458 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
459 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
460 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
461 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
462 md->gd_common_tssd = *md->gd_tss_gdt;
466 * Set to a known state:
467 * Set by mpboot.s: CR0_PG, CR0_PE
468 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
471 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
480 * Final configuration of the BSP's local APIC:
481 * - disable 'pic mode'.
482 * - disable 'virtual wire mode'.
486 bsp_apic_configure(void)
491 /* leave 'pic mode' if necessary */
493 outb(0x22, 0x70); /* select IMCR */
494 byte = inb(0x23); /* current contents */
495 byte |= 0x01; /* mask external INTR */
496 outb(0x23, byte); /* disconnect 8259s/NMI */
499 /* mask lint0 (the 8259 'virtual wire' connection) */
500 temp = lapic.lvt_lint0;
501 temp |= APIC_LVT_M; /* set the mask */
502 lapic.lvt_lint0 = temp;
504 /* setup lint1 to handle NMI */
505 temp = lapic.lvt_lint1;
506 temp &= ~APIC_LVT_M; /* clear the mask */
507 lapic.lvt_lint1 = temp;
510 apic_dump("bsp_apic_configure()");
515 /*******************************************************************
516 * local functions and data
520 * start the SMP system
523 mp_enable(u_int boot_addr)
531 POSTCODE(MP_ENABLE_POST);
533 /* turn on 4MB of V == P addressing so we can get to MP table */
534 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
537 /* examine the MP table for needed info, uses physical addresses */
543 /* can't process default configs till the CPU APIC is pmapped */
547 /* post scan cleanup */
549 setup_apic_irq_mapping();
553 /* fill the LOGICAL io_apic_versions table */
554 for (apic = 0; apic < mp_napics; ++apic) {
555 ux = io_apic_read(apic, IOAPIC_VER);
556 io_apic_versions[apic] = ux;
557 io_apic_set_id(apic, IO_TO_ID(apic));
560 /* program each IO APIC in the system */
561 for (apic = 0; apic < mp_napics; ++apic)
562 if (io_apic_setup(apic) < 0)
563 panic("IO APIC setup failure");
565 /* install a 'Spurious INTerrupt' vector */
566 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
567 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
569 /* install an inter-CPU IPI for TLB invalidation */
570 setidt(XINVLTLB_OFFSET, Xinvltlb,
571 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
573 /* install an inter-CPU IPI for IPIQ messaging */
574 setidt(XIPIQ_OFFSET, Xipiq,
575 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
577 /* install an inter-CPU IPI for all-CPU rendezvous */
578 setidt(XRENDEZVOUS_OFFSET, Xrendezvous,
579 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
581 /* install an inter-CPU IPI for CPU stop/restart */
582 setidt(XCPUSTOP_OFFSET, Xcpustop,
583 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
585 #if defined(TEST_TEST1)
586 /* install a "fake hardware INTerrupt" vector */
587 setidt(XTEST1_OFFSET, Xtest1,
588 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
589 #endif /** TEST_TEST1 */
593 /* start each Application Processor */
594 start_all_aps(boot_addr);
599 * look for the MP spec signature
602 /* string defined by the Intel MP Spec as identifying the MP table */
603 #define MP_SIG 0x5f504d5f /* _MP_ */
604 #define NEXT(X) ((X) += 4)
606 search_for_sig(u_int32_t target, int count)
609 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
611 for (x = 0; x < count; NEXT(x))
612 if (addr[x] == MP_SIG)
613 /* make array index a byte index */
614 return (target + (x * sizeof(u_int32_t)));
620 static basetable_entry basetable_entry_types[] =
622 {0, 20, "Processor"},
629 typedef struct BUSDATA {
631 enum busTypes bus_type;
634 typedef struct INTDATA {
644 typedef struct BUSTYPENAME {
649 static bus_type_name bus_type_table[] =
655 {UNKNOWN_BUSTYPE, "---"},
658 {UNKNOWN_BUSTYPE, "---"},
659 {UNKNOWN_BUSTYPE, "---"},
660 {UNKNOWN_BUSTYPE, "---"},
661 {UNKNOWN_BUSTYPE, "---"},
662 {UNKNOWN_BUSTYPE, "---"},
664 {UNKNOWN_BUSTYPE, "---"},
665 {UNKNOWN_BUSTYPE, "---"},
666 {UNKNOWN_BUSTYPE, "---"},
667 {UNKNOWN_BUSTYPE, "---"},
669 {UNKNOWN_BUSTYPE, "---"}
671 /* from MP spec v1.4, table 5-1 */
672 static int default_data[7][5] =
674 /* nbus, id0, type0, id1, type1 */
675 {1, 0, ISA, 255, 255},
676 {1, 0, EISA, 255, 255},
677 {1, 0, EISA, 255, 255},
678 {1, 0, MCA, 255, 255},
680 {2, 0, EISA, 1, PCI},
686 static bus_datum *bus_data;
688 /* the IO INT data, one entry per possible APIC INTerrupt */
689 static io_int *io_apic_ints;
693 static int processor_entry (proc_entry_ptr entry, int cpu);
694 static int bus_entry (bus_entry_ptr entry, int bus);
695 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
696 static int int_entry (int_entry_ptr entry, int intr);
697 static int lookup_bus_type (char *name);
701 * 1st pass on motherboard's Intel MP specification table.
707 * cpu_apic_address (common to all CPUs)
725 POSTCODE(MPTABLE_PASS1_POST);
727 /* clear various tables */
728 for (x = 0; x < NAPICID; ++x) {
729 io_apic_address[x] = ~0; /* IO APIC address table */
732 /* init everything to empty */
739 /* check for use of 'default' configuration */
740 if (MPFPS_MPFB1 != 0) {
741 /* use default addresses */
742 cpu_apic_address = DEFAULT_APIC_BASE;
743 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
745 /* fill in with defaults */
746 mp_naps = 2; /* includes BSP */
747 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
754 if ((cth = mpfps->pap) == 0)
755 panic("MP Configuration Table Header MISSING!");
757 cpu_apic_address = (vm_offset_t) cth->apic_address;
759 /* walk the table, recording info of interest */
760 totalSize = cth->base_table_length - sizeof(struct MPCTH);
761 position = (u_char *) cth + sizeof(struct MPCTH);
762 count = cth->entry_count;
765 switch (type = *(u_char *) position) {
766 case 0: /* processor_entry */
767 if (((proc_entry_ptr)position)->cpu_flags
768 & PROCENTRY_FLAG_EN) {
771 ((proc_entry_ptr)position)->apic_id;
774 case 1: /* bus_entry */
777 case 2: /* io_apic_entry */
778 if (((io_apic_entry_ptr)position)->apic_flags
779 & IOAPICENTRY_FLAG_EN)
780 io_apic_address[mp_napics++] =
781 (vm_offset_t)((io_apic_entry_ptr)
782 position)->apic_address;
784 case 3: /* int_entry */
787 case 4: /* int_entry */
790 panic("mpfps Base Table HOSED!");
794 totalSize -= basetable_entry_types[type].length;
795 (u_char*)position += basetable_entry_types[type].length;
799 /* qualify the numbers */
800 if (mp_naps > MAXCPU) {
801 printf("Warning: only using %d of %d available CPUs!\n",
806 /* See if we need to fixup HT logical CPUs. */
807 mptable_hyperthread_fixup(id_mask);
811 * This is also used as a counter while starting the APs.
815 --mp_naps; /* subtract the BSP */
820 * 2nd pass on motherboard's Intel MP specification table.
824 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
825 * CPU_TO_ID(N), logical CPU to APIC ID table
826 * IO_TO_ID(N), logical IO to APIC ID table
833 struct PROCENTRY proc;
840 int apic, bus, cpu, intr;
844 POSTCODE(MPTABLE_PASS2_POST);
846 /* Initialize fake proc entry for use with HT fixup. */
847 bzero(&proc, sizeof(proc));
849 proc.cpu_flags = PROCENTRY_FLAG_EN;
851 pgeflag = 0; /* XXX - Not used under SMP yet. */
853 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
855 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
857 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + 1),
859 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
862 bzero(ioapic, sizeof(ioapic_t *) * mp_napics);
864 for (i = 0; i < mp_napics; i++) {
865 for (j = 0; j < mp_napics; j++) {
866 /* same page frame as a previous IO apic? */
867 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) ==
868 (io_apic_address[i] & PG_FRAME)) {
869 ioapic[i] = (ioapic_t *)((u_int)CPU_prvspace
870 + (NPTEPG-2-j) * PAGE_SIZE
871 + (io_apic_address[i] & PAGE_MASK));
874 /* use this slot if available */
875 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) {
876 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW |
877 pgeflag | (io_apic_address[i] & PG_FRAME));
878 ioapic[i] = (ioapic_t *)((u_int)CPU_prvspace
879 + (NPTEPG-2-j) * PAGE_SIZE
880 + (io_apic_address[i] & PAGE_MASK));
886 /* clear various tables */
887 for (x = 0; x < NAPICID; ++x) {
888 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
889 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
890 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
893 /* clear bus data table */
894 for (x = 0; x < mp_nbusses; ++x)
895 bus_data[x].bus_id = 0xff;
897 /* clear IO APIC INT table */
898 for (x = 0; x < (nintrs + 1); ++x) {
899 io_apic_ints[x].int_type = 0xff;
900 io_apic_ints[x].int_vector = 0xff;
903 /* setup the cpu/apic mapping arrays */
906 /* record whether PIC or virtual-wire mode */
907 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
909 /* check for use of 'default' configuration */
910 if (MPFPS_MPFB1 != 0)
911 return MPFPS_MPFB1; /* return default configuration type */
913 if ((cth = mpfps->pap) == 0)
914 panic("MP Configuration Table Header MISSING!");
916 /* walk the table, recording info of interest */
917 totalSize = cth->base_table_length - sizeof(struct MPCTH);
918 position = (u_char *) cth + sizeof(struct MPCTH);
919 count = cth->entry_count;
920 apic = bus = intr = 0;
921 cpu = 1; /* pre-count the BSP */
924 switch (type = *(u_char *) position) {
926 if (processor_entry(position, cpu))
929 if (need_hyperthreading_fixup) {
931 * Create fake mptable processor entries
932 * and feed them to processor_entry() to
933 * enumerate the logical CPUs.
935 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
936 for (i = 1; i < logical_cpus; i++) {
938 (void)processor_entry(&proc, cpu);
939 logical_cpus_mask |= (1 << cpu);
945 if (bus_entry(position, bus))
949 if (io_apic_entry(position, apic))
953 if (int_entry(position, intr))
957 /* int_entry(position); */
960 panic("mpfps Base Table HOSED!");
964 totalSize -= basetable_entry_types[type].length;
965 (u_char *) position += basetable_entry_types[type].length;
968 if (boot_cpu_id == -1)
969 panic("NO BSP found!");
971 /* report fact that its NOT a default configuration */
976 * Check if we should perform a hyperthreading "fix-up" to
977 * enumerate any logical CPU's that aren't already listed
980 * XXX: We assume that all of the physical CPUs in the
981 * system have the same number of logical CPUs.
983 * XXX: We assume that APIC ID's are allocated such that
984 * the APIC ID's for a physical processor are aligned
985 * with the number of logical CPU's in the processor.
988 mptable_hyperthread_fixup(u_int id_mask)
992 /* Nothing to do if there is no HTT support. */
993 if ((cpu_feature & CPUID_HTT) == 0)
995 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
996 if (logical_cpus <= 1)
1000 * For each APIC ID of a CPU that is set in the mask,
1001 * scan the other candidate APIC ID's for this
1002 * physical processor. If any of those ID's are
1003 * already in the table, then kill the fixup.
1005 for (id = 0; id <= MAXCPU; id++) {
1006 if ((id_mask & 1 << id) == 0)
1008 /* First, make sure we are on a logical_cpus boundary. */
1009 if (id % logical_cpus != 0)
1011 for (i = id + 1; i < id + logical_cpus; i++)
1012 if ((id_mask & 1 << i) != 0)
1017 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1018 * mp_naps right now.
1020 need_hyperthreading_fixup = 1;
1021 mp_naps *= logical_cpus;
1025 assign_apic_irq(int apic, int intpin, int irq)
1029 if (int_to_apicintpin[irq].ioapic != -1)
1030 panic("assign_apic_irq: inconsistent table");
1032 int_to_apicintpin[irq].ioapic = apic;
1033 int_to_apicintpin[irq].int_pin = intpin;
1034 int_to_apicintpin[irq].apic_address = ioapic[apic];
1035 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1037 for (x = 0; x < nintrs; x++) {
1038 if ((io_apic_ints[x].int_type == 0 ||
1039 io_apic_ints[x].int_type == 3) &&
1040 io_apic_ints[x].int_vector == 0xff &&
1041 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1042 io_apic_ints[x].dst_apic_int == intpin)
1043 io_apic_ints[x].int_vector = irq;
1048 revoke_apic_irq(int irq)
1054 if (int_to_apicintpin[irq].ioapic == -1)
1055 panic("revoke_apic_irq: inconsistent table");
1057 oldapic = int_to_apicintpin[irq].ioapic;
1058 oldintpin = int_to_apicintpin[irq].int_pin;
1060 int_to_apicintpin[irq].ioapic = -1;
1061 int_to_apicintpin[irq].int_pin = 0;
1062 int_to_apicintpin[irq].apic_address = NULL;
1063 int_to_apicintpin[irq].redirindex = 0;
1065 for (x = 0; x < nintrs; x++) {
1066 if ((io_apic_ints[x].int_type == 0 ||
1067 io_apic_ints[x].int_type == 3) &&
1068 io_apic_ints[x].int_vector != 0xff &&
1069 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1070 io_apic_ints[x].dst_apic_int == oldintpin)
1071 io_apic_ints[x].int_vector = 0xff;
1077 allocate_apic_irq(int intr)
1083 if (io_apic_ints[intr].int_vector != 0xff)
1084 return; /* Interrupt handler already assigned */
1086 if (io_apic_ints[intr].int_type != 0 &&
1087 (io_apic_ints[intr].int_type != 3 ||
1088 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1089 io_apic_ints[intr].dst_apic_int == 0)))
1090 return; /* Not INT or ExtInt on != (0, 0) */
1093 while (irq < APIC_INTMAPSIZE &&
1094 int_to_apicintpin[irq].ioapic != -1)
1097 if (irq >= APIC_INTMAPSIZE)
1098 return; /* No free interrupt handlers */
1100 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1101 intpin = io_apic_ints[intr].dst_apic_int;
1103 assign_apic_irq(apic, intpin, irq);
1104 io_apic_setup_intpin(apic, intpin);
1109 swap_apic_id(int apic, int oldid, int newid)
1116 return; /* Nothing to do */
1118 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1119 apic, oldid, newid);
1121 /* Swap physical APIC IDs in interrupt entries */
1122 for (x = 0; x < nintrs; x++) {
1123 if (io_apic_ints[x].dst_apic_id == oldid)
1124 io_apic_ints[x].dst_apic_id = newid;
1125 else if (io_apic_ints[x].dst_apic_id == newid)
1126 io_apic_ints[x].dst_apic_id = oldid;
1129 /* Swap physical APIC IDs in IO_TO_ID mappings */
1130 for (oapic = 0; oapic < mp_napics; oapic++)
1131 if (IO_TO_ID(oapic) == newid)
1134 if (oapic < mp_napics) {
1135 printf("Changing APIC ID for IO APIC #%d from "
1136 "%d to %d in MP table\n",
1137 oapic, newid, oldid);
1138 IO_TO_ID(oapic) = oldid;
1140 IO_TO_ID(apic) = newid;
1145 fix_id_to_io_mapping(void)
1149 for (x = 0; x < NAPICID; x++)
1152 for (x = 0; x <= mp_naps; x++)
1153 if (CPU_TO_ID(x) < NAPICID)
1154 ID_TO_IO(CPU_TO_ID(x)) = x;
1156 for (x = 0; x < mp_napics; x++)
1157 if (IO_TO_ID(x) < NAPICID)
1158 ID_TO_IO(IO_TO_ID(x)) = x;
1163 first_free_apic_id(void)
1167 for (freeid = 0; freeid < NAPICID; freeid++) {
1168 for (x = 0; x <= mp_naps; x++)
1169 if (CPU_TO_ID(x) == freeid)
1173 for (x = 0; x < mp_napics; x++)
1174 if (IO_TO_ID(x) == freeid)
1185 io_apic_id_acceptable(int apic, int id)
1187 int cpu; /* Logical CPU number */
1188 int oapic; /* Logical IO APIC number for other IO APIC */
1191 return 0; /* Out of range */
1193 for (cpu = 0; cpu <= mp_naps; cpu++)
1194 if (CPU_TO_ID(cpu) == id)
1195 return 0; /* Conflict with CPU */
1197 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1198 if (IO_TO_ID(oapic) == id)
1199 return 0; /* Conflict with other APIC */
1201 return 1; /* ID is acceptable for IO APIC */
1206 * parse an Intel MP specification table
1213 int bus_0 = 0; /* Stop GCC warning */
1214 int bus_pci = 0; /* Stop GCC warning */
1216 int apic; /* IO APIC unit number */
1217 int freeid; /* Free physical APIC ID */
1218 int physid; /* Current physical IO APIC ID */
1221 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1222 * did it wrong. The MP spec says that when more than 1 PCI bus
1223 * exists the BIOS must begin with bus entries for the PCI bus and use
1224 * actual PCI bus numbering. This implies that when only 1 PCI bus
1225 * exists the BIOS can choose to ignore this ordering, and indeed many
1226 * MP motherboards do ignore it. This causes a problem when the PCI
1227 * sub-system makes requests of the MP sub-system based on PCI bus
1228 * numbers. So here we look for the situation and renumber the
1229 * busses and associated INTs in an effort to "make it right".
1232 /* find bus 0, PCI bus, count the number of PCI busses */
1233 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1234 if (bus_data[x].bus_id == 0) {
1237 if (bus_data[x].bus_type == PCI) {
1243 * bus_0 == slot of bus with ID of 0
1244 * bus_pci == slot of last PCI bus encountered
1247 /* check the 1 PCI bus case for sanity */
1248 /* if it is number 0 all is well */
1249 if (num_pci_bus == 1 &&
1250 bus_data[bus_pci].bus_id != 0) {
1252 /* mis-numbered, swap with whichever bus uses slot 0 */
1254 /* swap the bus entry types */
1255 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1256 bus_data[bus_0].bus_type = PCI;
1258 /* swap each relavant INTerrupt entry */
1259 id = bus_data[bus_pci].bus_id;
1260 for (x = 0; x < nintrs; ++x) {
1261 if (io_apic_ints[x].src_bus_id == id) {
1262 io_apic_ints[x].src_bus_id = 0;
1264 else if (io_apic_ints[x].src_bus_id == 0) {
1265 io_apic_ints[x].src_bus_id = id;
1270 /* Assign IO APIC IDs.
1272 * First try the existing ID. If a conflict is detected, try
1273 * the ID in the MP table. If a conflict is still detected, find
1276 * We cannot use the ID_TO_IO table before all conflicts has been
1277 * resolved and the table has been corrected.
1279 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1281 /* First try to use the value set by the BIOS */
1282 physid = io_apic_get_id(apic);
1283 if (io_apic_id_acceptable(apic, physid)) {
1284 if (IO_TO_ID(apic) != physid)
1285 swap_apic_id(apic, IO_TO_ID(apic), physid);
1289 /* Then check if the value in the MP table is acceptable */
1290 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1293 /* Last resort, find a free APIC ID and use it */
1294 freeid = first_free_apic_id();
1295 if (freeid >= NAPICID)
1296 panic("No free physical APIC IDs found");
1298 if (io_apic_id_acceptable(apic, freeid)) {
1299 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1302 panic("Free physical APIC ID not usable");
1304 fix_id_to_io_mapping();
1306 /* detect and fix broken Compaq MP table */
1307 if (apic_int_type(0, 0) == -1) {
1308 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1309 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1310 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1311 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1312 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1313 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1319 /* Assign low level interrupt handlers */
1321 setup_apic_irq_mapping(void)
1327 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1328 int_to_apicintpin[x].ioapic = -1;
1329 int_to_apicintpin[x].int_pin = 0;
1330 int_to_apicintpin[x].apic_address = NULL;
1331 int_to_apicintpin[x].redirindex = 0;
1334 /* First assign ISA/EISA interrupts */
1335 for (x = 0; x < nintrs; x++) {
1336 int_vector = io_apic_ints[x].src_bus_irq;
1337 if (int_vector < APIC_INTMAPSIZE &&
1338 io_apic_ints[x].int_vector == 0xff &&
1339 int_to_apicintpin[int_vector].ioapic == -1 &&
1340 (apic_int_is_bus_type(x, ISA) ||
1341 apic_int_is_bus_type(x, EISA)) &&
1342 io_apic_ints[x].int_type == 0) {
1343 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1344 io_apic_ints[x].dst_apic_int,
1349 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1350 for (x = 0; x < nintrs; x++) {
1351 if (io_apic_ints[x].dst_apic_int == 0 &&
1352 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1353 io_apic_ints[x].int_vector == 0xff &&
1354 int_to_apicintpin[0].ioapic == -1 &&
1355 io_apic_ints[x].int_type == 3) {
1356 assign_apic_irq(0, 0, 0);
1360 /* PCI interrupt assignment is deferred */
1365 processor_entry(proc_entry_ptr entry, int cpu)
1367 /* check for usability */
1368 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1371 if(entry->apic_id >= NAPICID)
1372 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1373 /* check for BSP flag */
1374 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1375 boot_cpu_id = entry->apic_id;
1376 CPU_TO_ID(0) = entry->apic_id;
1377 ID_TO_CPU(entry->apic_id) = 0;
1378 return 0; /* its already been counted */
1381 /* add another AP to list, if less than max number of CPUs */
1382 else if (cpu < MAXCPU) {
1383 CPU_TO_ID(cpu) = entry->apic_id;
1384 ID_TO_CPU(entry->apic_id) = cpu;
1393 bus_entry(bus_entry_ptr entry, int bus)
1398 /* encode the name into an index */
1399 for (x = 0; x < 6; ++x) {
1400 if ((c = entry->bus_type[x]) == ' ')
1406 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1407 panic("unknown bus type: '%s'", name);
1409 bus_data[bus].bus_id = entry->bus_id;
1410 bus_data[bus].bus_type = x;
1417 io_apic_entry(io_apic_entry_ptr entry, int apic)
1419 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1422 IO_TO_ID(apic) = entry->apic_id;
1423 if (entry->apic_id < NAPICID)
1424 ID_TO_IO(entry->apic_id) = apic;
1431 lookup_bus_type(char *name)
1435 for (x = 0; x < MAX_BUSTYPE; ++x)
1436 if (strcmp(bus_type_table[x].name, name) == 0)
1437 return bus_type_table[x].type;
1439 return UNKNOWN_BUSTYPE;
1444 int_entry(int_entry_ptr entry, int intr)
1448 io_apic_ints[intr].int_type = entry->int_type;
1449 io_apic_ints[intr].int_flags = entry->int_flags;
1450 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1451 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1452 if (entry->dst_apic_id == 255) {
1453 /* This signal goes to all IO APICS. Select an IO APIC
1454 with sufficient number of interrupt pins */
1455 for (apic = 0; apic < mp_napics; apic++)
1456 if (((io_apic_read(apic, IOAPIC_VER) &
1457 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1458 entry->dst_apic_int)
1460 if (apic < mp_napics)
1461 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1463 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1465 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1466 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1473 apic_int_is_bus_type(int intr, int bus_type)
1477 for (bus = 0; bus < mp_nbusses; ++bus)
1478 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1479 && ((int) bus_data[bus].bus_type == bus_type))
1487 * Given a traditional ISA INT mask, return an APIC mask.
1490 isa_apic_mask(u_int isa_mask)
1495 #if defined(SKIP_IRQ15_REDIRECT)
1496 if (isa_mask == (1 << 15)) {
1497 printf("skipping ISA IRQ15 redirect\n");
1500 #endif /* SKIP_IRQ15_REDIRECT */
1502 isa_irq = ffs(isa_mask); /* find its bit position */
1503 if (isa_irq == 0) /* doesn't exist */
1505 --isa_irq; /* make it zero based */
1507 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1511 return (1 << apic_pin); /* convert pin# to a mask */
1516 * Determine which APIC pin an ISA/EISA INT is attached to.
1518 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1519 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1520 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1521 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1523 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1525 isa_apic_irq(int isa_irq)
1529 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1530 if (INTTYPE(intr) == 0) { /* standard INT */
1531 if (SRCBUSIRQ(intr) == isa_irq) {
1532 if (apic_int_is_bus_type(intr, ISA) ||
1533 apic_int_is_bus_type(intr, EISA)) {
1534 if (INTIRQ(intr) == 0xff)
1535 return -1; /* unassigned */
1536 return INTIRQ(intr); /* found */
1541 return -1; /* NOT found */
1546 * Determine which APIC pin a PCI INT is attached to.
1548 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1549 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1550 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1552 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1556 --pciInt; /* zero based */
1558 for (intr = 0; intr < nintrs; ++intr) /* check each record */
1559 if ((INTTYPE(intr) == 0) /* standard INT */
1560 && (SRCBUSID(intr) == pciBus)
1561 && (SRCBUSDEVICE(intr) == pciDevice)
1562 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
1563 if (apic_int_is_bus_type(intr, PCI)) {
1564 if (INTIRQ(intr) == 0xff)
1565 allocate_apic_irq(intr);
1566 if (INTIRQ(intr) == 0xff)
1567 return -1; /* unassigned */
1568 return INTIRQ(intr); /* exact match */
1571 return -1; /* NOT found */
1575 next_apic_irq(int irq)
1582 for (intr = 0; intr < nintrs; intr++) {
1583 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1585 bus = SRCBUSID(intr);
1586 bustype = apic_bus_type(bus);
1587 if (bustype != ISA &&
1593 if (intr >= nintrs) {
1596 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1597 if (INTTYPE(ointr) != 0)
1599 if (bus != SRCBUSID(ointr))
1601 if (bustype == PCI) {
1602 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1604 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1607 if (bustype == ISA || bustype == EISA) {
1608 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1611 if (INTPIN(intr) == INTPIN(ointr))
1615 if (ointr >= nintrs) {
1618 return INTIRQ(ointr);
1632 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1635 * Exactly what this means is unclear at this point. It is a solution
1636 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1637 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1638 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1642 undirect_isa_irq(int rirq)
1646 printf("Freeing redirected ISA irq %d.\n", rirq);
1647 /** FIXME: tickle the MB redirector chip */
1651 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1658 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1661 undirect_pci_irq(int rirq)
1665 printf("Freeing redirected PCI irq %d.\n", rirq);
1667 /** FIXME: tickle the MB redirector chip */
1671 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1679 * given a bus ID, return:
1680 * the bus type if found
1684 apic_bus_type(int id)
1688 for (x = 0; x < mp_nbusses; ++x)
1689 if (bus_data[x].bus_id == id)
1690 return bus_data[x].bus_type;
1697 * given a LOGICAL APIC# and pin#, return:
1698 * the associated src bus ID if found
1702 apic_src_bus_id(int apic, int pin)
1706 /* search each of the possible INTerrupt sources */
1707 for (x = 0; x < nintrs; ++x)
1708 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1709 (pin == io_apic_ints[x].dst_apic_int))
1710 return (io_apic_ints[x].src_bus_id);
1712 return -1; /* NOT found */
1717 * given a LOGICAL APIC# and pin#, return:
1718 * the associated src bus IRQ if found
1722 apic_src_bus_irq(int apic, int pin)
1726 for (x = 0; x < nintrs; x++)
1727 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1728 (pin == io_apic_ints[x].dst_apic_int))
1729 return (io_apic_ints[x].src_bus_irq);
1731 return -1; /* NOT found */
1736 * given a LOGICAL APIC# and pin#, return:
1737 * the associated INTerrupt type if found
1741 apic_int_type(int apic, int pin)
1745 /* search each of the possible INTerrupt sources */
1746 for (x = 0; x < nintrs; ++x)
1747 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1748 (pin == io_apic_ints[x].dst_apic_int))
1749 return (io_apic_ints[x].int_type);
1751 return -1; /* NOT found */
1755 apic_irq(int apic, int pin)
1760 for (x = 0; x < nintrs; ++x)
1761 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1762 (pin == io_apic_ints[x].dst_apic_int)) {
1763 res = io_apic_ints[x].int_vector;
1766 if (apic != int_to_apicintpin[res].ioapic)
1767 panic("apic_irq: inconsistent table");
1768 if (pin != int_to_apicintpin[res].int_pin)
1769 panic("apic_irq inconsistent table (2)");
1777 * given a LOGICAL APIC# and pin#, return:
1778 * the associated trigger mode if found
1782 apic_trigger(int apic, int pin)
1786 /* search each of the possible INTerrupt sources */
1787 for (x = 0; x < nintrs; ++x)
1788 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1789 (pin == io_apic_ints[x].dst_apic_int))
1790 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1792 return -1; /* NOT found */
1797 * given a LOGICAL APIC# and pin#, return:
1798 * the associated 'active' level if found
1802 apic_polarity(int apic, int pin)
1806 /* search each of the possible INTerrupt sources */
1807 for (x = 0; x < nintrs; ++x)
1808 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1809 (pin == io_apic_ints[x].dst_apic_int))
1810 return (io_apic_ints[x].int_flags & 0x03);
1812 return -1; /* NOT found */
1817 * set data according to MP defaults
1818 * FIXME: probably not complete yet...
1821 default_mp_table(int type)
1824 #if defined(APIC_IO)
1827 #endif /* APIC_IO */
1830 printf(" MP default config type: %d\n", type);
1833 printf(" bus: ISA, APIC: 82489DX\n");
1836 printf(" bus: EISA, APIC: 82489DX\n");
1839 printf(" bus: EISA, APIC: 82489DX\n");
1842 printf(" bus: MCA, APIC: 82489DX\n");
1845 printf(" bus: ISA+PCI, APIC: Integrated\n");
1848 printf(" bus: EISA+PCI, APIC: Integrated\n");
1851 printf(" bus: MCA+PCI, APIC: Integrated\n");
1854 printf(" future type\n");
1860 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1861 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1864 CPU_TO_ID(0) = boot_cpu_id;
1865 ID_TO_CPU(boot_cpu_id) = 0;
1867 /* one and only AP */
1868 CPU_TO_ID(1) = ap_cpu_id;
1869 ID_TO_CPU(ap_cpu_id) = 1;
1871 #if defined(APIC_IO)
1872 /* one and only IO APIC */
1873 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1876 * sanity check, refer to MP spec section 3.6.6, last paragraph
1877 * necessary as some hardware isn't properly setting up the IO APIC
1879 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1880 if (io_apic_id != 2) {
1882 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1883 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1884 io_apic_set_id(0, 2);
1887 IO_TO_ID(0) = io_apic_id;
1888 ID_TO_IO(io_apic_id) = 0;
1889 #endif /* APIC_IO */
1891 /* fill out bus entries */
1900 bus_data[0].bus_id = default_data[type - 1][1];
1901 bus_data[0].bus_type = default_data[type - 1][2];
1902 bus_data[1].bus_id = default_data[type - 1][3];
1903 bus_data[1].bus_type = default_data[type - 1][4];
1906 /* case 4: case 7: MCA NOT supported */
1907 default: /* illegal/reserved */
1908 panic("BAD default MP config: %d", type);
1912 #if defined(APIC_IO)
1913 /* general cases from MP v1.4, table 5-2 */
1914 for (pin = 0; pin < 16; ++pin) {
1915 io_apic_ints[pin].int_type = 0;
1916 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1917 io_apic_ints[pin].src_bus_id = 0;
1918 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1919 io_apic_ints[pin].dst_apic_id = io_apic_id;
1920 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1923 /* special cases from MP v1.4, table 5-2 */
1925 io_apic_ints[2].int_type = 0xff; /* N/C */
1926 io_apic_ints[13].int_type = 0xff; /* N/C */
1927 #if !defined(APIC_MIXED_MODE)
1929 panic("sorry, can't support type 2 default yet");
1930 #endif /* APIC_MIXED_MODE */
1933 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1936 io_apic_ints[0].int_type = 0xff; /* N/C */
1938 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1939 #endif /* APIC_IO */
1943 * start each AP in our list
1946 start_all_aps(u_int boot_addr)
1949 u_char mpbiosreason;
1950 u_long mpbioswarmvec;
1951 struct mdglobaldata *gd;
1952 struct privatespace *ps;
1956 POSTCODE(START_ALL_APS_POST);
1958 /* initialize BSP's local APIC */
1962 /* install the AP 1st level boot code */
1963 install_ap_tramp(boot_addr);
1966 /* save the current value of the warm-start vector */
1967 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
1969 outb(CMOS_REG, BIOS_RESET);
1970 mpbiosreason = inb(CMOS_DATA);
1973 /* set up temporary P==V mapping for AP boot */
1974 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
1975 kptbase = (uintptr_t)(void *)KPTphys;
1976 for (x = 0; x < NKPT; x++)
1977 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
1978 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
1982 for (x = 1; x <= mp_naps; ++x) {
1984 /* This is a bit verbose, it will go away soon. */
1986 /* first page of AP's private space */
1987 pg = x * i386_btop(sizeof(struct privatespace));
1989 /* allocate a new private data page */
1990 gd = (struct mdglobaldata *)kmem_alloc(kernel_map, PAGE_SIZE);
1992 /* wire it into the private page table page */
1993 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys_pte(gd));
1995 /* allocate and set up an idle stack data page */
1996 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE);
1997 for (i = 0; i < UPAGES; i++) {
1998 SMPpt[pg + 5 + i] = (pt_entry_t)
1999 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2002 SMPpt[pg + 1] = 0; /* *gd_CMAP1 */
2003 SMPpt[pg + 2] = 0; /* *gd_CMAP2 */
2004 SMPpt[pg + 3] = 0; /* *gd_CMAP3 */
2005 SMPpt[pg + 4] = 0; /* *gd_PMAP1 */
2007 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2008 bzero(gd, sizeof(*gd));
2009 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2011 /* prime data page for it to use */
2012 mi_gdinit(&gd->mi, x);
2014 gd->gd_CMAP1 = &SMPpt[pg + 1];
2015 gd->gd_CMAP2 = &SMPpt[pg + 2];
2016 gd->gd_CMAP3 = &SMPpt[pg + 3];
2017 gd->gd_PMAP1 = &SMPpt[pg + 4];
2018 gd->gd_CADDR1 = ps->CPAGE1;
2019 gd->gd_CADDR2 = ps->CPAGE2;
2020 gd->gd_CADDR3 = ps->CPAGE3;
2021 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2022 gd->mi.gd_ipiq = (void *)kmem_alloc(kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2023 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2025 /* setup a vector to our boot code */
2026 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2027 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2029 outb(CMOS_REG, BIOS_RESET);
2030 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2034 * Setup the AP boot stack
2036 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2039 /* attempt to start the Application Processor */
2040 CHECK_INIT(99); /* setup checkpoints */
2041 if (!start_ap(gd, boot_addr)) {
2042 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2043 CHECK_PRINT("trace"); /* show checkpoints */
2044 /* better panic as the AP may be running loose */
2045 printf("panic y/n? [y] ");
2046 if (cngetc() != 'n')
2049 CHECK_PRINT("trace"); /* show checkpoints */
2051 /* record its version info */
2052 cpu_apic_versions[x] = cpu_apic_versions[0];
2055 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2058 /* build our map of 'other' CPUs */
2059 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2060 mycpu->gd_ipiq = (void *)kmem_alloc(kernel_map, sizeof(lwkt_ipiq) * ncpus);
2061 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2063 /* fill in our (BSP) APIC version */
2064 cpu_apic_versions[0] = lapic.version;
2066 /* restore the warmstart vector */
2067 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2069 outb(CMOS_REG, BIOS_RESET);
2070 outb(CMOS_DATA, mpbiosreason);
2074 * NOTE! The idlestack for the BSP was setup by locore. Finish
2075 * up, clean out the P==V mapping we did earlier.
2077 for (x = 0; x < NKPT; x++)
2081 /* number of APs actually started */
2087 * load the 1st level AP boot code into base memory.
2090 /* targets for relocation */
2091 extern void bigJump(void);
2092 extern void bootCodeSeg(void);
2093 extern void bootDataSeg(void);
2094 extern void MPentry(void);
2095 extern u_int MP_GDT;
2096 extern u_int mp_gdtbase;
2099 install_ap_tramp(u_int boot_addr)
2102 int size = *(int *) ((u_long) & bootMP_size);
2103 u_char *src = (u_char *) ((u_long) bootMP);
2104 u_char *dst = (u_char *) boot_addr + KERNBASE;
2105 u_int boot_base = (u_int) bootMP;
2110 POSTCODE(INSTALL_AP_TRAMP_POST);
2112 for (x = 0; x < size; ++x)
2116 * modify addresses in code we just moved to basemem. unfortunately we
2117 * need fairly detailed info about mpboot.s for this to work. changes
2118 * to mpboot.s might require changes here.
2121 /* boot code is located in KERNEL space */
2122 dst = (u_char *) boot_addr + KERNBASE;
2124 /* modify the lgdt arg */
2125 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2126 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2128 /* modify the ljmp target for MPentry() */
2129 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2130 *dst32 = ((u_int) MPentry - KERNBASE);
2132 /* modify the target for boot code segment */
2133 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2134 dst8 = (u_int8_t *) (dst16 + 1);
2135 *dst16 = (u_int) boot_addr & 0xffff;
2136 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2138 /* modify the target for boot data segment */
2139 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2140 dst8 = (u_int8_t *) (dst16 + 1);
2141 *dst16 = (u_int) boot_addr & 0xffff;
2142 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2147 * this function starts the AP (application processor) identified
2148 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2149 * to accomplish this. This is necessary because of the nuances
2150 * of the different hardware we might encounter. It ain't pretty,
2151 * but it seems to work.
2153 * NOTE: eventually an AP gets to ap_init(), which is called just
2154 * before the AP goes into the LWKT scheduler's idle loop.
2157 start_ap(struct mdglobaldata *gd, u_int boot_addr)
2161 u_long icr_lo, icr_hi;
2163 POSTCODE(START_AP_POST);
2165 /* get the PHYSICAL APIC ID# */
2166 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2168 /* calculate the vector */
2169 vector = (boot_addr >> 12) & 0xff;
2171 /* Make sure the target cpu sees everything */
2175 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2176 * and running the target CPU. OR this INIT IPI might be latched (P5
2177 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2181 /* setup the address for the target AP */
2182 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2183 icr_hi |= (physical_cpu << 24);
2184 lapic.icr_hi = icr_hi;
2186 /* do an INIT IPI: assert RESET */
2187 icr_lo = lapic.icr_lo & 0xfff00000;
2188 lapic.icr_lo = icr_lo | 0x0000c500;
2190 /* wait for pending status end */
2191 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2194 /* do an INIT IPI: deassert RESET */
2195 lapic.icr_lo = icr_lo | 0x00008500;
2197 /* wait for pending status end */
2198 u_sleep(10000); /* wait ~10mS */
2199 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2203 * next we do a STARTUP IPI: the previous INIT IPI might still be
2204 * latched, (P5 bug) this 1st STARTUP would then terminate
2205 * immediately, and the previously started INIT IPI would continue. OR
2206 * the previous INIT IPI has already run. and this STARTUP IPI will
2207 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2211 /* do a STARTUP IPI */
2212 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2213 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2215 u_sleep(200); /* wait ~200uS */
2218 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2219 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2220 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2221 * recognized after hardware RESET or INIT IPI.
2224 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2225 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2227 u_sleep(200); /* wait ~200uS */
2229 /* wait for it to start, see ap_init() */
2230 set_apic_timer(5000000);/* == 5 seconds */
2231 while (read_apic_timer()) {
2232 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2233 return 1; /* return SUCCESS */
2235 return 0; /* return FAILURE */
2240 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2242 * If for some reason we were unable to start all cpus we cannot safely
2243 * use broadcast IPIs.
2248 #if defined(APIC_IO)
2249 if (smp_startup_mask == smp_active_mask) {
2250 all_but_self_ipi(XINVLTLB_OFFSET);
2252 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2253 APIC_DELMODE_FIXED);
2255 #endif /* APIC_IO */
2259 * When called the executing CPU will send an IPI to all other CPUs
2260 * requesting that they halt execution.
2262 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2264 * - Signals all CPUs in map to stop.
2265 * - Waits for each to stop.
2272 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2273 * from executing at same time.
2276 stop_cpus(u_int map)
2278 map &= smp_active_mask;
2280 /* send the Xcpustop IPI to all CPUs in map */
2281 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2283 while ((stopped_cpus & map) != map)
2291 * Called by a CPU to restart stopped CPUs.
2293 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2295 * - Signals all CPUs in map to restart.
2296 * - Waits for each to restart.
2304 restart_cpus(u_int map)
2306 /* signal other cpus to restart */
2307 started_cpus = map & smp_active_mask;
2309 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2316 * This is called once the mpboot code has gotten us properly relocated
2317 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2318 * and when it returns the scheduler will call the real cpu_idle() main
2319 * loop for the idlethread. Interrupts are disabled on entry and should
2320 * remain disabled at return.
2329 * Adjust smp_startup_mask to signal the BSP that we have started
2330 * up successfully. Note that we do not yet hold the BGL. The BSP
2331 * is waiting for our signal.
2333 * We can't set our bit in smp_active_mask yet because we are holding
2334 * interrupts physically disabled and remote cpus could deadlock
2335 * trying to send us an IPI.
2337 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2341 * Get the MP lock so we can finish initializing. Note: we are
2342 * in a critical section. td_mpcount must always be bumped prior
2343 * to obtaining the actual lock.
2345 ++curthread->td_mpcount;
2346 while (cpu_try_mplock() == 0)
2349 /* BSP may have changed PTD while we're waiting for the lock */
2351 smp_active_mask |= 1 << mycpu->gd_cpuid;
2353 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2357 /* Build our map of 'other' CPUs. */
2358 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2360 printf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2362 /* set up CPU registers and state */
2365 /* set up FPU state on the AP */
2366 npxinit(__INITIAL_NPXCW__);
2368 /* set up SSE registers */
2371 /* A quick check from sanity claus */
2372 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2373 if (mycpu->gd_cpuid != apic_id) {
2374 printf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2375 printf("SMP: apic_id = %d\n", apic_id);
2376 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2377 panic("cpuid mismatch! boom!!");
2380 /* Init local apic for irq's */
2383 /* Set memory range attributes for this CPU to match the BSP */
2384 mem_range_AP_init();
2387 * AP helper function for kernel memory support. This will create
2388 * a memory reserve for the AP that is necessary to avoid certain
2389 * memory deadlock situations, such as when the kernel_map needs
2390 * a vm_map_entry and zalloc has no free entries and tries to allocate
2391 * a new one from the ... kernel_map :-)
2395 sched_thread_init(); /* startup helper thread(s) one per cpu */
2396 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2399 * The idle loop doesn't expect the BGL to be held and while
2400 * lwkt_switch() normally cleans things up this is a special case
2401 * because we returning almost directly into the idle loop.
2403 KKASSERT(curthread->td_mpcount == 1);
2407 #ifdef APIC_INTR_REORDER
2409 * Maintain mapping from softintr vector to isr bit in local apic.
2412 set_lapic_isrloc(int intr, int vector)
2414 if (intr < 0 || intr > 32)
2415 panic("set_apic_isrloc: bad intr argument: %d",intr);
2416 if (vector < ICU_OFFSET || vector > 255)
2417 panic("set_apic_isrloc: bad vector argument: %d",vector);
2418 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2419 apic_isrbit_location[intr].bit = (1<<(vector & 31));
2426 * All-CPU rendezvous. CPUs are signalled, all execute the setup function
2427 * (if specified), rendezvous, execute the action function (if specified),
2428 * rendezvous again, execute the teardown function (if specified), and then
2431 * Note that the supplied external functions _must_ be reentrant and aware
2432 * that they are running in parallel and in an unknown lock context.
2434 static void (*smp_rv_setup_func)(void *arg);
2435 static void (*smp_rv_action_func)(void *arg);
2436 static void (*smp_rv_teardown_func)(void *arg);
2437 static void *smp_rv_func_arg;
2438 static volatile int smp_rv_waiters[2];
2441 smp_rendezvous_action(void)
2443 /* setup function */
2444 if (smp_rv_setup_func != NULL)
2445 smp_rv_setup_func(smp_rv_func_arg);
2446 /* spin on entry rendezvous */
2447 atomic_add_int(&smp_rv_waiters[0], 1);
2448 while (smp_rv_waiters[0] < ncpus)
2450 /* action function */
2451 if (smp_rv_action_func != NULL)
2452 smp_rv_action_func(smp_rv_func_arg);
2453 /* spin on exit rendezvous */
2454 atomic_add_int(&smp_rv_waiters[1], 1);
2455 while (smp_rv_waiters[1] < ncpus)
2457 /* teardown function */
2458 if (smp_rv_teardown_func != NULL)
2459 smp_rv_teardown_func(smp_rv_func_arg);
2463 smp_rendezvous(void (* setup_func)(void *),
2464 void (* action_func)(void *),
2465 void (* teardown_func)(void *),
2468 /* obtain rendezvous lock. This disables interrupts */
2469 spin_lock(&smp_rv_spinlock); /* XXX sleep here? NOWAIT flag? */
2471 /* set static function pointers */
2472 smp_rv_setup_func = setup_func;
2473 smp_rv_action_func = action_func;
2474 smp_rv_teardown_func = teardown_func;
2475 smp_rv_func_arg = arg;
2476 smp_rv_waiters[0] = 0;
2477 smp_rv_waiters[1] = 0;
2480 * Signal other processors which will enter the IPI with interrupts
2481 * disabled. We cannot safely use broadcast IPIs if some of our
2482 * cpus failed to start.
2484 if (smp_startup_mask == smp_active_mask) {
2485 all_but_self_ipi(XRENDEZVOUS_OFFSET);
2487 selected_apic_ipi(smp_active_mask, XRENDEZVOUS_OFFSET,
2488 APIC_DELMODE_FIXED);
2491 /* call executor function */
2492 smp_rendezvous_action();
2495 spin_unlock(&smp_rv_spinlock);
2499 cpu_send_ipiq(int dcpu)
2501 if ((1 << dcpu) & smp_active_mask)
2502 selected_apic_ipi(1 << dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);