2 * Copyright (c) 1996, by Steve Passe
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25 * $FreeBSD: src/sys/i386/include/smptests.h,v 1.33.2.1 2000/05/16 06:58:10 dillon Exp $
26 * $DragonFly: src/sys/platform/pc32/include/Attic/smptests.h,v 1.4 2004/02/17 19:38:54 dillon Exp $
29 #ifndef _MACHINE_SMPTESTS_H_
30 #define _MACHINE_SMPTESTS_H_
34 * Various 'tests in progress' and configuration parameters.
38 * Control the "giant lock" pushdown by logical steps.
40 #define PUSHDOWN_LEVEL_1
41 #define PUSHDOWN_LEVEL_2
42 #define PUSHDOWN_LEVEL_3_NOT
43 #define PUSHDOWN_LEVEL_4_NOT
46 * Put FAST_INTR() ISRs at an APIC priority above the regular INTs.
47 * Allow the mp_lock() routines to handle FAST interrupts while spinning.
49 #ifdef PUSHDOWN_LEVEL_1
55 * These defines enable critical region locking of areas that were
56 * protected via cli/sti in the UP kernel.
58 * MPINTRLOCK protects all the generic areas.
59 * COMLOCK protects the sio/cy drivers.
60 * CLOCKLOCK protects clock hardware and data
61 * known to be incomplete:
65 #ifdef PUSHDOWN_LEVEL_1
66 #define USE_MPINTRLOCK
73 * INTR_SIMPLELOCK has been removed, as the interrupt mechanism will likely
74 * not use this sort of optimization if we move to interrupt threads.
76 #ifdef PUSHDOWN_LEVEL_4
81 * CPL_AND_CML has been removed. Interrupt threads will eventually not
82 * use either mechanism so there is no point trying to optimize it.
84 #ifdef PUSHDOWN_LEVEL_3
89 * SPL_DEBUG_POSTCODE/INTR_SPL/SPL_DEBUG - removed
91 * These functions were too expensive for the standard case but, more
92 * importantly, we should be able to come up with a much cleaner way
93 * to handle the cpl. Having to do any locking at all is a mistake
94 * for something that is modified as often as cpl is.
98 * FAST_WITHOUTCPL - now made the default (define removed). Text below
99 * contains the current discussion. I am confident we can find a solution
100 * that does not require us to process softints from a hard int, which can
101 * kill serial performance due to the lack of true hardware ipl's.
105 * Ignore the ipending bits when exiting FAST_INTR() routines.
107 * according to Bruce:
109 * setsoft*() may set ipending. setsofttty() is actually used in the
110 * FAST_INTR handler in some serial drivers. This is necessary to get
111 * output completions and other urgent events handled as soon as possible.
112 * The flag(s) could be set in a variable other than ipending, but they
113 * needs to be checked against cpl to decide whether the software interrupt
114 * handler can/should run.
116 * (FAST_INTR used to just return
117 * in all cases until rev.1.7 of vector.s. This worked OK provided there
118 * were no user-mode CPU hogs. CPU hogs caused an average latency of 1/2
119 * clock tick for output completions...)
122 * So I need to restore cpl handling someday, but AFTER
123 * I finish making spl/cpl MP-safe.
125 #ifdef PUSHDOWN_LEVEL_1
130 * FAST_SIMPLELOCK no longer exists, because it doesn't help us. The cpu
131 * is likely to already hold the MP lock and recursive MP locks are now
132 * very cheap, so we do not need this optimization. Eventually *ALL*
133 * interrupts will run in their own thread, so there is no sense complicating
136 #ifdef PUSHDOWN_LEVEL_1
141 * Portions of the old TEST_LOPRIO code, back from the grave!
147 * Send CPUSTOP IPI for stop/restart of other CPUs on DDB break.
149 #define VERBOSE_CPUSTOP_ON_DDBBREAK
151 #define CPUSTOP_ON_DDBBREAK
155 * Bracket code/comments relevant to the current 'giant lock' model.
156 * Everything is now the 'giant lock' model, but we will use this as
157 * we start to "push down" the lock.
164 * Don't assume that slow interrupt handler X is called from vector
167 #define APIC_INTR_REORDER
170 * Redirect clock interrupts to a higher priority (fast intr) vector,
171 * while still using the slow interrupt handler. Only effective when
172 * APIC_INTR_REORDER is defined.
174 #define APIC_INTR_HIGHPRI_CLOCK
181 #define COUNT_XINVLTLB_HITS
186 * Hack to "fake-out" kernel into thinking it is running on a 'default config'.
188 * value == default type
189 #define TEST_DEFAULT_CONFIG 6
194 * Simple test code for IPI interaction, save for future...
197 #define IPI_TARGET_TEST1 1
202 * Address of POST hardware port.
203 * Defining this enables POSTCODE macros.
205 #define POST_ADDR 0x80
210 * POST hardware macros.
213 #define ASMPOSTCODE_INC \
215 movl _current_postcode, %eax ; \
218 movl %eax, _current_postcode ; \
219 outb %al, $POST_ADDR ; \
223 * Overwrite the current_postcode value.
225 #define ASMPOSTCODE(X) \
228 movl %eax, _current_postcode ; \
229 outb %al, $POST_ADDR ; \
233 * Overwrite the current_postcode low nibble.
235 #define ASMPOSTCODE_LO(X) \
237 movl _current_postcode, %eax ; \
240 movl %eax, _current_postcode ; \
241 outb %al, $POST_ADDR ; \
245 * Overwrite the current_postcode high nibble.
247 #define ASMPOSTCODE_HI(X) \
249 movl _current_postcode, %eax ; \
251 orl $(X<<4), %eax ; \
252 movl %eax, _current_postcode ; \
253 outb %al, $POST_ADDR ; \
256 #define ASMPOSTCODE_INC
257 #define ASMPOSTCODE(X)
258 #define ASMPOSTCODE_LO(X)
259 #define ASMPOSTCODE_HI(X)
260 #endif /* POST_ADDR */
264 * These are all temps for debugging...
270 * This macro traps unexpected INTs to a specific CPU, eg. GUARD_CPU.
274 #define MAYBE_PANIC(irq_num) \
275 cmpl $GUARD_CPU, _cpuid ; \
277 cmpl $1, _ok_test1 ; \
294 #define MAYBE_PANIC(irq_num)
295 #endif /* GUARD_INTS */
297 #endif /* _MACHINE_SMPTESTS_H_ */