2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by the University of
17 * California, Berkeley and its contributors.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
35 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $
36 * $DragonFly: src/sys/platform/pc32/isa/npx.c,v 1.30 2006/04/02 20:43:27 dillon Exp $
40 #include "opt_debug_npx.h"
41 #include "opt_math_emulate.h"
43 #include <sys/param.h>
44 #include <sys/systm.h>
46 #include <sys/kernel.h>
47 #include <sys/malloc.h>
48 #include <sys/module.h>
49 #include <sys/sysctl.h>
51 #include <machine/bus.h>
54 #include <sys/syslog.h>
56 #include <sys/signalvar.h>
57 #include <sys/thread2.h>
60 #include <machine/asmacros.h>
62 #include <machine/cputypes.h>
63 #include <machine/frame.h>
64 #include <machine/ipl.h>
65 #include <machine/md_var.h>
66 #include <machine/pcb.h>
67 #include <machine/psl.h>
69 #include <machine/clock.h>
71 #include <machine/resource.h>
72 #include <machine/specialreg.h>
73 #include <machine/segments.h>
74 #include <machine/globaldata.h>
77 #include <i386/icu/icu.h>
78 #include <i386/isa/intr_machdep.h>
79 #include <bus/isa/i386/isa.h>
83 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
86 /* Configuration flags. */
87 #define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0)
88 #define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1)
89 #define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2)
90 #define NPX_PREFER_EMULATOR (1 << 3)
94 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr)))
95 #define fnclex() __asm("fnclex")
96 #define fninit() __asm("fninit")
97 #define fnop() __asm("fnop")
98 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr)))
99 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
100 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr)))
101 #define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop")
102 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr)))
103 #ifndef CPU_DISABLE_SSE
104 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr)))
105 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
107 #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
108 : : "n" (CR0_TS) : "ax")
109 #define stop_emulating() __asm("clts")
111 #else /* not __GNUC__ */
113 void fldcw (caddr_t addr);
117 void fnsave (caddr_t addr);
118 void fnstcw (caddr_t addr);
119 void fnstsw (caddr_t addr);
120 void fp_divide_by_0 (void);
121 void frstor (caddr_t addr);
122 #ifndef CPU_DISABLE_SSE
123 void fxsave (caddr_t addr);
124 void fxrstor (caddr_t addr);
126 void start_emulating (void);
127 void stop_emulating (void);
129 #endif /* __GNUC__ */
131 #ifndef CPU_DISABLE_SSE
132 #define GET_FPU_EXSW_PTR(td) \
134 &(td)->td_savefpu->sv_xmm.sv_ex_sw : \
135 &(td)->td_savefpu->sv_87.sv_ex_sw)
136 #else /* CPU_DISABLE_SSE */
137 #define GET_FPU_EXSW_PTR(td) \
138 (&(td)->td_savefpu->sv_87.sv_ex_sw)
139 #endif /* CPU_DISABLE_SSE */
141 typedef u_char bool_t;
143 static int npx_attach (device_t dev);
144 void npx_intr (void *);
145 static int npx_probe (device_t dev);
146 static int npx_probe1 (device_t dev);
147 static void fpusave (union savefpu *);
148 static void fpurstor (union savefpu *);
150 int hw_float; /* XXX currently just alias for npx_exists */
152 SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
153 CTLFLAG_RD, &hw_float, 0,
154 "Floatingpoint instructions executed in hardware");
155 #if (defined(I586_CPU) || defined(I686_CPU)) && !defined(CPU_DISABLE_SSE)
157 SYSCTL_INT(_kern, OID_AUTO, mmxopt, CTLFLAG_RD, &mmxopt, 0,
158 "MMX/XMM optimized bcopy/copyin/copyout support");
162 static u_int npx0_imask;
163 static struct gate_descriptor npx_idt_probeintr;
164 static int npx_intrno;
165 static volatile u_int npx_intrs_while_probing;
166 static volatile u_int npx_traps_while_probing;
169 static bool_t npx_ex16;
170 static bool_t npx_exists;
171 static bool_t npx_irq13;
172 static int npx_irq; /* irq number */
176 * Special interrupt handlers. Someday intr0-intr15 will be used to count
177 * interrupts. We'll still need a special exception 16 handler. The busy
178 * latch stuff in probeintr() can be moved to npxprobe().
184 .type " __XSTRING(CNAME(probeintr)) ",@function \n\
185 " __XSTRING(CNAME(probeintr)) ": \n\
187 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " \n\
189 movb $0x20,%al # EOI (asm in strings loses cpp features) \n\
190 outb %al,$0xa0 # IO_ICU2 \n\
191 outb %al,$0x20 # IO_ICU1 \n\
193 outb %al,$0xf0 # clear BUSY# latch \n\
202 .type " __XSTRING(CNAME(probetrap)) ",@function \n\
203 " __XSTRING(CNAME(probetrap)) ": \n\
205 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\
212 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait
213 * whether the device exists or not (XXX should be elsewhere). Set flags
214 * to tell npxattach() what to do. Modify device struct if npx doesn't
215 * need to use interrupts. Return 1 if device exists.
218 npx_probe(device_t dev)
222 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
224 return npx_probe1(dev);
230 u_char save_icu1_mask;
231 u_char save_icu2_mask;
232 struct gate_descriptor save_idt_npxintr;
233 struct gate_descriptor save_idt_npxtrap;
235 * This routine is now just a wrapper for npxprobe1(), to install
236 * special npx interrupt and trap handlers, to enable npx interrupts
237 * and to disable other interrupts. Someday isa_configure() will
238 * install suitable handlers and run with interrupts enabled so we
239 * won't need to do so much here.
241 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
243 npx_intrno = IDT_OFFSET + npx_irq;
244 save_eflags = read_eflags();
246 save_icu1_mask = inb(IO_ICU1 + 1);
247 save_icu2_mask = inb(IO_ICU2 + 1);
248 save_idt_npxintr = idt[npx_intrno];
249 save_idt_npxtrap = idt[16];
250 outb(IO_ICU1 + 1, ~(1 << ICU_IRQ_SLAVE));
251 outb(IO_ICU2 + 1, ~(1 << (npx_irq - 8)));
252 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
253 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
254 npx_idt_probeintr = idt[npx_intrno];
256 result = npx_probe1(dev);
258 outb(IO_ICU1 + 1, save_icu1_mask);
259 outb(IO_ICU2 + 1, save_icu2_mask);
260 idt[npx_intrno] = save_idt_npxintr;
261 idt[16] = save_idt_npxtrap;
262 write_eflags(save_eflags);
269 npx_probe1(device_t dev)
277 * Partially reset the coprocessor, if any. Some BIOS's don't reset
278 * it after a warm boot.
280 outb(0xf1, 0); /* full reset on some systems, NOP on others */
281 outb(0xf0, 0); /* clear BUSY# latch */
283 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT
284 * instructions. We must set the CR0_MP bit and use the CR0_TS
285 * bit to control the trap, because setting the CR0_EM bit does
286 * not cause WAIT instructions to trap. It's important to trap
287 * WAIT instructions - otherwise the "wait" variants of no-wait
288 * control instructions would degenerate to the "no-wait" variants
289 * after FP context switches but work correctly otherwise. It's
290 * particularly important to trap WAITs when there is no NPX -
291 * otherwise the "wait" variants would always degenerate.
293 * Try setting CR0_NE to get correct error reporting on 486DX's.
294 * Setting it should fail or do nothing on lesser processors.
296 load_cr0(rcr0() | CR0_MP | CR0_NE);
298 * But don't trap while we're probing.
302 * Finish resetting the coprocessor, if any. If there is an error
303 * pending, then we may get a bogus IRQ13, but probeintr() will handle
304 * it OK. Bogus halts have never been observed, but we enabled
305 * IRQ13 and cleared the BUSY# latch early to handle them anyway.
311 * Exception 16 MUST work for SMP.
314 npx_ex16 = hw_float = npx_exists = 1;
315 device_set_desc(dev, "math processor");
319 device_set_desc(dev, "math processor");
322 * Don't use fwait here because it might hang.
323 * Don't use fnop here because it usually hangs if there is no FPU.
325 DELAY(1000); /* wait for any IRQ13 */
327 if (npx_intrs_while_probing != 0)
328 printf("fninit caused %u bogus npx interrupt(s)\n",
329 npx_intrs_while_probing);
330 if (npx_traps_while_probing != 0)
331 printf("fninit caused %u bogus npx trap(s)\n",
332 npx_traps_while_probing);
335 * Check for a status of mostly zero.
339 if ((status & 0xb8ff) == 0) {
341 * Good, now check for a proper control word.
345 if ((control & 0x1f3f) == 0x033f) {
346 hw_float = npx_exists = 1;
348 * We have an npx, now divide by 0 to see if exception
351 control &= ~(1 << 2); /* enable divide by 0 trap */
353 npx_traps_while_probing = npx_intrs_while_probing = 0;
355 if (npx_traps_while_probing != 0) {
357 * Good, exception 16 works.
362 if (npx_intrs_while_probing != 0) {
367 * Bad, we are stuck with IRQ13.
371 * npxattach would be too late to set npx0_imask
373 npx0_imask |= (1 << npx_irq);
376 * We allocate these resources permanently,
377 * so there is no need to keep track of them.
380 r = bus_alloc_resource(dev, SYS_RES_IOPORT,
381 &rid, IO_NPX, IO_NPX,
382 IO_NPXSIZE, RF_ACTIVE);
384 panic("npx: can't get ports");
386 r = bus_alloc_resource(dev, SYS_RES_IRQ,
387 &rid, npx_irq, npx_irq,
390 panic("npx: can't get IRQ");
391 BUS_SETUP_INTR(device_get_parent(dev),
393 npx_intr, 0, &intr, NULL);
395 panic("npx: can't create intr");
400 * Worse, even IRQ13 is broken. Use emulator.
405 * Probe failed, but we want to get to npxattach to initialize the
406 * emulator and say that it has been installed. XXX handle devices
407 * that aren't really devices better.
414 * Attach routine - announce which it is, and wire into system
417 npx_attach(device_t dev)
421 if (resource_int_value("npx", 0, "flags", &flags) != 0)
425 device_printf(dev, "flags 0x%x ", flags);
427 device_printf(dev, "using IRQ 13 interface\n");
429 #if defined(MATH_EMULATE)
431 if (!(flags & NPX_PREFER_EMULATOR))
432 device_printf(dev, "INT 16 interface\n");
434 device_printf(dev, "FPU exists, but flags request "
436 hw_float = npx_exists = 0;
438 } else if (npx_exists) {
439 device_printf(dev, "error reporting broken; using 387 emulator\n");
440 hw_float = npx_exists = 0;
442 device_printf(dev, "387 emulator\n");
445 device_printf(dev, "INT 16 interface\n");
446 if (flags & NPX_PREFER_EMULATOR) {
447 device_printf(dev, "emulator requested, but none compiled "
448 "into kernel, using FPU\n");
451 device_printf(dev, "no 387 emulator in kernel and no FPU!\n");
454 npxinit(__INITIAL_NPXCW__);
456 #if (defined(I586_CPU) || defined(I686_CPU)) && !defined(CPU_DISABLE_SSE)
458 * The asm_mmx_*() routines actually use XMM as well, so only
459 * enable them if we have SSE2 and are using FXSR (fxsave/fxrstore).
461 TUNABLE_INT_FETCH("kern.mmxopt", &mmxopt);
462 if ((cpu_feature & CPUID_MMX) && (cpu_feature & CPUID_SSE) &&
463 (cpu_feature & CPUID_SSE2) &&
464 npx_ex16 && npx_exists && mmxopt && cpu_fxsr
466 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY) == 0) {
467 bcopy_vector = (void **)asm_xmm_bcopy;
468 ovbcopy_vector = (void **)asm_xmm_bcopy;
469 memcpy_vector = (void **)asm_xmm_memcpy;
470 printf("Using XMM optimized bcopy/copyin/copyout\n");
472 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BZERO) == 0) {
475 } else if ((cpu_feature & CPUID_MMX) && (cpu_feature & CPUID_SSE) &&
476 npx_ex16 && npx_exists && mmxopt && cpu_fxsr
478 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY) == 0) {
479 bcopy_vector = (void **)asm_mmx_bcopy;
480 ovbcopy_vector = (void **)asm_mmx_bcopy;
481 memcpy_vector = (void **)asm_mmx_memcpy;
482 printf("Using MMX optimized bcopy/copyin/copyout\n");
484 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BZERO) == 0) {
490 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists &&
491 timezero("i586_bzero()", i586_bzero) <
492 timezero("bzero()", bzero) * 4 / 5) {
493 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) {
494 bcopy_vector = i586_bcopy;
495 ovbcopy_vector = i586_bcopy;
497 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO))
499 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) {
500 copyin_vector = i586_copyin;
501 copyout_vector = i586_copyout;
505 return (0); /* XXX unused */
509 * Initialize the floating point unit.
512 npxinit(u_short control)
514 static union savefpu dummy;
519 * fninit has the same h/w bugs as fnsave. Use the detoxified
520 * fnsave to throw away any junk in the fpu. npxsave() initializes
521 * the fpu and sets npxthread = NULL as important side effects.
527 fpusave(curthread->td_savefpu);
528 mdcpu->gd_npxthread = NULL;
534 * Free coprocessor (if we have it).
537 npxexit(struct proc *p)
539 if (p->p_thread == mdcpu->gd_npxthread)
540 npxsave(curthread->td_savefpu);
543 u_int masked_exceptions;
546 curthread->td_savefpu->sv_87.sv_env.en_cw
547 & curthread->td_savefpu->sv_87.sv_env.en_sw & 0x7f;
549 * Log exceptions that would have trapped with the old
550 * control word (overflow, divide by 0, and invalid operand).
552 if (masked_exceptions & 0x0d)
554 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
555 p->p_pid, p->p_comm, masked_exceptions);
561 * The following mechanism is used to ensure that the FPE_... value
562 * that is passed as a trapcode to the signal handler of the user
563 * process does not have more than one bit set.
565 * Multiple bits may be set if the user process modifies the control
566 * word while a status word bit is already set. While this is a sign
567 * of bad coding, we have no choise than to narrow them down to one
568 * bit, since we must not send a trapcode that is not exactly one of
571 * The mechanism has a static table with 127 entries. Each combination
572 * of the 7 FPU status word exception bits directly translates to a
573 * position in this table, where a single FPE_... value is stored.
574 * This FPE_... value stored there is considered the "most important"
575 * of the exception bits and will be sent as the signal code. The
576 * precedence of the bits is based upon Intel Document "Numerical
577 * Applications", Chapter "Special Computational Situations".
579 * The macro to choose one of these values does these steps: 1) Throw
580 * away status word bits that cannot be masked. 2) Throw away the bits
581 * currently masked in the control word, assuming the user isn't
582 * interested in them anymore. 3) Reinsert status word bit 7 (stack
583 * fault) if it is set, which cannot be masked but must be presered.
584 * 4) Use the remaining bits to point into the trapcode table.
586 * The 6 maskable bits in order of their preference, as stated in the
587 * above referenced Intel manual:
588 * 1 Invalid operation (FP_X_INV)
591 * 1c Operand of unsupported format
593 * 2 QNaN operand (not an exception, irrelavant here)
594 * 3 Any other invalid-operation not mentioned above or zero divide
595 * (FP_X_INV, FP_X_DZ)
596 * 4 Denormal operand (FP_X_DNML)
597 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
598 * 6 Inexact result (FP_X_IMP)
600 static char fpetable[128] = {
602 FPE_FLTINV, /* 1 - INV */
603 FPE_FLTUND, /* 2 - DNML */
604 FPE_FLTINV, /* 3 - INV | DNML */
605 FPE_FLTDIV, /* 4 - DZ */
606 FPE_FLTINV, /* 5 - INV | DZ */
607 FPE_FLTDIV, /* 6 - DNML | DZ */
608 FPE_FLTINV, /* 7 - INV | DNML | DZ */
609 FPE_FLTOVF, /* 8 - OFL */
610 FPE_FLTINV, /* 9 - INV | OFL */
611 FPE_FLTUND, /* A - DNML | OFL */
612 FPE_FLTINV, /* B - INV | DNML | OFL */
613 FPE_FLTDIV, /* C - DZ | OFL */
614 FPE_FLTINV, /* D - INV | DZ | OFL */
615 FPE_FLTDIV, /* E - DNML | DZ | OFL */
616 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
617 FPE_FLTUND, /* 10 - UFL */
618 FPE_FLTINV, /* 11 - INV | UFL */
619 FPE_FLTUND, /* 12 - DNML | UFL */
620 FPE_FLTINV, /* 13 - INV | DNML | UFL */
621 FPE_FLTDIV, /* 14 - DZ | UFL */
622 FPE_FLTINV, /* 15 - INV | DZ | UFL */
623 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
624 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
625 FPE_FLTOVF, /* 18 - OFL | UFL */
626 FPE_FLTINV, /* 19 - INV | OFL | UFL */
627 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
628 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
629 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
630 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
631 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
632 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
633 FPE_FLTRES, /* 20 - IMP */
634 FPE_FLTINV, /* 21 - INV | IMP */
635 FPE_FLTUND, /* 22 - DNML | IMP */
636 FPE_FLTINV, /* 23 - INV | DNML | IMP */
637 FPE_FLTDIV, /* 24 - DZ | IMP */
638 FPE_FLTINV, /* 25 - INV | DZ | IMP */
639 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
640 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
641 FPE_FLTOVF, /* 28 - OFL | IMP */
642 FPE_FLTINV, /* 29 - INV | OFL | IMP */
643 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
644 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
645 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
646 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
647 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
648 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
649 FPE_FLTUND, /* 30 - UFL | IMP */
650 FPE_FLTINV, /* 31 - INV | UFL | IMP */
651 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
652 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
653 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
654 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
655 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
656 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
657 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
658 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
659 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
660 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
661 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
662 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
663 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
664 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
665 FPE_FLTSUB, /* 40 - STK */
666 FPE_FLTSUB, /* 41 - INV | STK */
667 FPE_FLTUND, /* 42 - DNML | STK */
668 FPE_FLTSUB, /* 43 - INV | DNML | STK */
669 FPE_FLTDIV, /* 44 - DZ | STK */
670 FPE_FLTSUB, /* 45 - INV | DZ | STK */
671 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
672 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
673 FPE_FLTOVF, /* 48 - OFL | STK */
674 FPE_FLTSUB, /* 49 - INV | OFL | STK */
675 FPE_FLTUND, /* 4A - DNML | OFL | STK */
676 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
677 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
678 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
679 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
680 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
681 FPE_FLTUND, /* 50 - UFL | STK */
682 FPE_FLTSUB, /* 51 - INV | UFL | STK */
683 FPE_FLTUND, /* 52 - DNML | UFL | STK */
684 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
685 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
686 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
687 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
688 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
689 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
690 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
691 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
692 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
693 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
694 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
695 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
696 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
697 FPE_FLTRES, /* 60 - IMP | STK */
698 FPE_FLTSUB, /* 61 - INV | IMP | STK */
699 FPE_FLTUND, /* 62 - DNML | IMP | STK */
700 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
701 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
702 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
703 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
704 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
705 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
706 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
707 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
708 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
709 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
710 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
711 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
712 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
713 FPE_FLTUND, /* 70 - UFL | IMP | STK */
714 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
715 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
716 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
717 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
718 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
719 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
720 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
721 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
722 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
723 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
724 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
725 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
726 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
727 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
728 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
732 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
734 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now
735 * depend on longjmp() restoring a usable state. Restoring the state
736 * or examining it might fail if we didn't clear exceptions.
738 * The error code chosen will be one of the FPE_... macros. It will be
739 * sent as the second argument to old BSD-style signal handlers and as
740 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
742 * XXX the FP state is not preserved across signal handlers. So signal
743 * handlers cannot afford to do FP unless they preserve the state or
744 * longjmp() out. Both preserving the state and longjmp()ing may be
745 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable
746 * solution for signals other than SIGFPE.
748 * The MP lock is not held on entry (see i386/i386/exception.s) and
749 * should not be held on exit. Interrupts are enabled. We must enter
750 * a critical section to stabilize the FP system and prevent an interrupt
751 * or preemption from changing the FP state out from under us.
754 npx_intr(void *dummy)
758 struct intrframe *frame;
764 * This exception can only occur with CR0_TS clear, otherwise we
765 * would get a DNA exception. However, since interrupts were
766 * enabled a preemption could have sneaked in and used the FP system
767 * before we entered our critical section. If that occured, the
768 * TS bit will be set and npxthread will be NULL.
770 if (npx_exists && (rcr0() & CR0_TS)) {
771 KASSERT(mdcpu->gd_npxthread == NULL, ("gd_npxthread was %p with TS set!", mdcpu->gd_npxthread));
776 if (mdcpu->gd_npxthread == NULL || !npx_exists) {
778 printf("npxintr: npxthread = %p, curthread = %p, npx_exists = %d\n",
779 mdcpu->gd_npxthread, curthread, npx_exists);
780 panic("npxintr from nowhere");
782 if (mdcpu->gd_npxthread != curthread) {
784 printf("npxintr: npxthread = %p, curthread = %p, npx_exists = %d\n",
785 mdcpu->gd_npxthread, curthread, npx_exists);
786 panic("npxintr from non-current process");
789 exstat = GET_FPU_EXSW_PTR(curthread);
798 * Pass exception to process.
800 frame = (struct intrframe *)&dummy; /* XXX */
801 if ((ISPL(frame->if_cs) == SEL_UPL) || (frame->if_eflags & PSL_VM)) {
803 * Interrupt is essentially a trap, so we can afford to call
804 * the SIGFPE handler (if any) as soon as the interrupt
807 * XXX little or nothing is gained from this, and plenty is
808 * lost - the interrupt frame has to contain the trap frame
809 * (this is otherwise only necessary for the rescheduling trap
810 * in doreti, and the frame for that could easily be set up
811 * just before it is used).
813 curproc->p_md.md_regs = INTR_TO_TRAPFRAME(frame);
815 * Encode the appropriate code for detailed information on
819 fpetable[(*exstat & ~control & 0x3f) | (*exstat & 0x40)];
820 trapsignal(curproc, SIGFPE, code);
823 * Nested interrupt. These losers occur when:
824 * o an IRQ13 is bogusly generated at a bogus time, e.g.:
825 * o immediately after an fnsave or frstor of an
827 * o a couple of 386 instructions after
828 * "fstpl _memvar" causes a stack overflow.
829 * These are especially nasty when combined with a
831 * o an IRQ13 occurs at the same time as another higher-
832 * priority interrupt.
834 * Treat them like a true async interrupt.
836 psignal(curproc, SIGFPE);
843 * Implement the device not available (DNA) exception. gd_npxthread had
844 * better be NULL. Restore the current thread's FP state and set gd_npxthread
847 * Interrupts are enabled and preemption can occur. Enter a critical
848 * section to stabilize the FP state.
857 if (mdcpu->gd_npxthread != NULL) {
858 printf("npxdna: npxthread = %p, curthread = %p\n",
859 mdcpu->gd_npxthread, curthread);
863 * The setting of gd_npxthread and the call to fpurstor() must not
864 * be preempted by an interrupt thread or we will take an npxdna
865 * trap and potentially save our current fpstate (which is garbage)
866 * and then restore the garbage rather then the originally saved
872 * Record new context early in case frstor causes an IRQ13.
874 mdcpu->gd_npxthread = curthread;
875 exstat = GET_FPU_EXSW_PTR(curthread);
878 * The following frstor may cause an IRQ13 when the state being
879 * restored has a pending error. The error will appear to have been
880 * triggered by the current (npx) user instruction even when that
881 * instruction is a no-wait instruction that should not trigger an
882 * error (e.g., fnclex). On at least one 486 system all of the
883 * no-wait instructions are broken the same as frstor, so our
884 * treatment does not amplify the breakage. On at least one
885 * 386/Cyrix 387 system, fnclex works correctly while frstor and
886 * fnsave are broken, so our treatment breaks fnclex if it is the
887 * first FPU instruction after a context switch.
889 fpurstor(curthread->td_savefpu);
896 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error
897 * pending, then fnsave generates a bogus IRQ13 on some systems. Force
898 * any IRQ13 to be handled immediately, and then ignore it. This routine is
899 * often called at splhigh so it must not use many system services. In
900 * particular, it's much easier to install a special handler than to
901 * guarantee that it's safe to use npxintr() and its supporting code.
903 * WARNING! This call is made during a switch and the MP lock will be
904 * setup for the new target thread rather then the current thread, so we
905 * cannot do anything here that depends on the *_mplock() functions as
906 * we may trip over their assertions.
908 * WARNING! When using fxsave we MUST fninit after saving the FP state. The
909 * kernel will always assume that the FP state is 'safe' (will not cause
910 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still
911 * setup a custom save area before actually using the FP unit, but it will
912 * not bother calling fninit. This greatly improves kernel performance when
913 * it wishes to use the FP unit.
916 npxsave(union savefpu *addr)
918 #if defined(SMP) || !defined(CPU_DISABLE_SSE)
923 mdcpu->gd_npxthread = NULL;
928 #else /* !SMP and CPU_DISABLE_SSE */
932 u_char old_icu1_mask;
933 u_char old_icu2_mask;
934 struct gate_descriptor save_idt_npxintr;
937 save_eflags = read_eflags();
939 old_icu1_mask = inb(IO_ICU1 + 1);
940 old_icu2_mask = inb(IO_ICU2 + 1);
941 save_idt_npxintr = idt[npx_intrno];
942 outb(IO_ICU1 + 1, old_icu1_mask & ~((1 << ICU_IRQ_SLAVE) | npx0_imask));
943 outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8));
944 idt[npx_intrno] = npx_idt_probeintr;
950 mdcpu->gd_npxthread = NULL;
952 icu1_mask = inb(IO_ICU1 + 1); /* masks may have changed */
953 icu2_mask = inb(IO_ICU2 + 1);
955 (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask));
957 (icu2_mask & ~(npx0_imask >> 8))
958 | (old_icu2_mask & (npx0_imask >> 8)));
959 idt[npx_intrno] = save_idt_npxintr;
960 write_eflags(save_eflags); /* back to usual state */
966 fpusave(union savefpu *addr)
968 #ifndef CPU_DISABLE_SSE
977 fpurstor(union savefpu *addr)
979 #ifndef CPU_DISABLE_SSE
988 * Because npx is a static device that always exists under nexus,
989 * and is not scanned by the nexus device, we need an identify
990 * function to install the device.
992 static device_method_t npx_methods[] = {
993 /* Device interface */
994 DEVMETHOD(device_identify, bus_generic_identify),
995 DEVMETHOD(device_probe, npx_probe),
996 DEVMETHOD(device_attach, npx_attach),
997 DEVMETHOD(device_detach, bus_generic_detach),
998 DEVMETHOD(device_shutdown, bus_generic_shutdown),
999 DEVMETHOD(device_suspend, bus_generic_suspend),
1000 DEVMETHOD(device_resume, bus_generic_resume),
1005 static driver_t npx_driver = {
1011 static devclass_t npx_devclass;
1014 * We prefer to attach to the root nexus so that the usual case (exception 16)
1015 * doesn't describe the processor as being `on isa'.
1017 DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0);