sys/dev/drm/i915/i915_drv.c

   1 /* i915_drv.c -- Intel i915 driver -*- linux-c -*-
   2  * Created: Wed Feb 14 17:10:04 2001 by gareth@valinux.com
   3  */
   4 /*-
   5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  25  * OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Gareth Hughes <gareth@valinux.com>
  29  *
  30  * $FreeBSD: src/sys/dev/drm2/i915/i915_drv.c,v 1.1 2012/05/22 11:07:44 kib Exp $
  31  */
  32
  33 #include <drm/drmP.h>
  34 #include <drm/i915_drm.h>
  35 #include "i915_drv.h"
  36 #include <drm/drm_pciids.h>
  37 #include "intel_drv.h"
  38
  39 /* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
  40 static drm_pci_id_list_t i915_pciidlist[] = {
  41         i915_PCI_IDS
  42 };
  43
  44 #define INTEL_VGA_DEVICE(id, info_) {           \
  45         .device = id,                           \
  46         .info = info_,                          \
  47 }
  48
  49 static const struct intel_device_info intel_i830_info = {
  50         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
  51         .has_overlay = 1, .overlay_needs_physical = 1,
  52 };
  53
  54 static const struct intel_device_info intel_845g_info = {
  55         .gen = 2,
  56         .has_overlay = 1, .overlay_needs_physical = 1,
  57 };
  58
  59 static const struct intel_device_info intel_i85x_info = {
  60         .gen = 2, .is_i85x = 1, .is_mobile = 1,
  61         .cursor_needs_physical = 1,
  62         .has_overlay = 1, .overlay_needs_physical = 1,
  63 };
  64
  65 static const struct intel_device_info intel_i865g_info = {
  66         .gen = 2,
  67         .has_overlay = 1, .overlay_needs_physical = 1,
  68 };
  69
  70 static const struct intel_device_info intel_i915g_info = {
  71         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
  72         .has_overlay = 1, .overlay_needs_physical = 1,
  73 };
  74 static const struct intel_device_info intel_i915gm_info = {
  75         .gen = 3, .is_mobile = 1,
  76         .cursor_needs_physical = 1,
  77         .has_overlay = 1, .overlay_needs_physical = 1,
  78         .supports_tv = 1,
  79 };
  80 static const struct intel_device_info intel_i945g_info = {
  81         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
  82         .has_overlay = 1, .overlay_needs_physical = 1,
  83 };
  84 static const struct intel_device_info intel_i945gm_info = {
  85         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
  86         .has_hotplug = 1, .cursor_needs_physical = 1,
  87         .has_overlay = 1, .overlay_needs_physical = 1,
  88         .supports_tv = 1,
  89 };
  90
  91 static const struct intel_device_info intel_i965g_info = {
  92         .gen = 4, .is_broadwater = 1,
  93         .has_hotplug = 1,
  94         .has_overlay = 1,
  95 };
  96
  97 static const struct intel_device_info intel_i965gm_info = {
  98         .gen = 4, .is_crestline = 1,
  99         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 100         .has_overlay = 1,
 101         .supports_tv = 1,
 102 };
 103
 104 static const struct intel_device_info intel_g33_info = {
 105         .gen = 3, .is_g33 = 1,
 106         .need_gfx_hws = 1, .has_hotplug = 1,
 107         .has_overlay = 1,
 108 };
 109
 110 static const struct intel_device_info intel_g45_info = {
 111         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 112         .has_pipe_cxsr = 1, .has_hotplug = 1,
 113         .has_bsd_ring = 1,
 114 };
 115
 116 static const struct intel_device_info intel_gm45_info = {
 117         .gen = 4, .is_g4x = 1,
 118         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 119         .has_pipe_cxsr = 1, .has_hotplug = 1,
 120         .supports_tv = 1,
 121         .has_bsd_ring = 1,
 122 };
 123
 124 static const struct intel_device_info intel_pineview_info = {
 125         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 126         .need_gfx_hws = 1, .has_hotplug = 1,
 127         .has_overlay = 1,
 128 };
 129
 130 static const struct intel_device_info intel_ironlake_d_info = {
 131         .gen = 5,
 132         .need_gfx_hws = 1, .has_hotplug = 1,
 133         .has_bsd_ring = 1,
 134 };
 135
 136 static const struct intel_device_info intel_ironlake_m_info = {
 137         .gen = 5, .is_mobile = 1,
 138         .need_gfx_hws = 1, .has_hotplug = 1,
 139         .has_fbc = 0, /* disabled due to buggy hardware */
 140         .has_bsd_ring = 1,
 141 };
 142
 143 static const struct intel_device_info intel_sandybridge_d_info = {
 144         .gen = 6,
 145         .need_gfx_hws = 1, .has_hotplug = 1,
 146         .has_bsd_ring = 1,
 147         .has_blt_ring = 1,
 148         .has_llc = 1,
 149         .has_force_wake = 1,
 150 };
 151
 152 static const struct intel_device_info intel_sandybridge_m_info = {
 153         .gen = 6, .is_mobile = 1,
 154         .need_gfx_hws = 1, .has_hotplug = 1,
 155         .has_fbc = 1,
 156         .has_bsd_ring = 1,
 157         .has_blt_ring = 1,
 158         .has_llc = 1,
 159         .has_force_wake = 1,
 160 };
 161
 162 static const struct intel_device_info intel_ivybridge_d_info = {
 163         .is_ivybridge = 1, .gen = 7,
 164         .need_gfx_hws = 1, .has_hotplug = 1,
 165         .has_bsd_ring = 1,
 166         .has_blt_ring = 1,
 167         .has_llc = 1,
 168         .has_force_wake = 1,
 169 };
 170
 171 static const struct intel_device_info intel_ivybridge_m_info = {
 172         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 173         .need_gfx_hws = 1, .has_hotplug = 1,
 174         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 175         .has_bsd_ring = 1,
 176         .has_blt_ring = 1,
 177         .has_llc = 1,
 178         .has_force_wake = 1,
 179 };
 180
 181 static const struct intel_device_info intel_valleyview_m_info = {
 182         .gen = 7, .is_mobile = 1,
 183         .need_gfx_hws = 1, .has_hotplug = 1,
 184         .has_fbc = 0,
 185         .has_bsd_ring = 1,
 186         .has_blt_ring = 1,
 187         .is_valleyview = 1,
 188 };
 189
 190 static const struct intel_device_info intel_valleyview_d_info = {
 191         .gen = 7,
 192         .need_gfx_hws = 1, .has_hotplug = 1,
 193         .has_fbc = 0,
 194         .has_bsd_ring = 1,
 195         .has_blt_ring = 1,
 196         .is_valleyview = 1,
 197 };
 198
 199 static const struct intel_device_info intel_haswell_d_info = {
 200         .is_haswell = 1, .gen = 7,
 201         .need_gfx_hws = 1, .has_hotplug = 1,
 202         .has_bsd_ring = 1,
 203         .has_blt_ring = 1,
 204         .has_llc = 1,
 205         .has_force_wake = 1,
 206 };
 207
 208 static const struct intel_device_info intel_haswell_m_info = {
 209         .is_haswell = 1, .gen = 7, .is_mobile = 1,
 210         .need_gfx_hws = 1, .has_hotplug = 1,
 211         .has_bsd_ring = 1,
 212         .has_blt_ring = 1,
 213         .has_llc = 1,
 214         .has_force_wake = 1,
 215 };
 216
 217 static const struct intel_gfx_device_id {
 218         int device;
 219         const struct intel_device_info *info;
 220 } pciidlist[] = {               /* aka */
 221         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 222         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 223         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 224         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 225         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 226         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 227         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 228         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 229         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 230         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 231         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 232         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 233         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 234         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 235         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 236         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 237         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 238         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 239         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 240         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 241         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 242         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 243         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 244         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 245         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 246         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 247         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 248         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 249         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 250         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 251         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 252         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 253         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 254         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 255         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 256         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 257         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 258         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 259         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 260         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 261         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 262         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 263         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 264         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 265         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
 266         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
 267         INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
 268         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
 269         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
 270         INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
 271         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
 272         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
 273         INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
 274         INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
 275         INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
 276         INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
 277         INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
 278         INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
 279         INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
 280         INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
 281         INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
 282         INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
 283         INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
 284         INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
 285         INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
 286         INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
 287         INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
 288         INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
 289         INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
 290         INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
 291         INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
 292         INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
 293         INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
 294         INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
 295         INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
 296         INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
 297         INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
 298         INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
 299         INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
 300         INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
 301         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
 302         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
 303         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
 304         {0, 0}
 305 };
 306
 307 #define PCI_VENDOR_INTEL        0x8086
 308
 309 void intel_detect_pch(struct drm_device *dev)
 310 {
 311         struct drm_i915_private *dev_priv = dev->dev_private;
 312         device_t pch;
 313
 314         /*
 315          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 316          * make graphics device passthrough work easy for VMM, that only
 317          * need to expose ISA bridge to let driver know the real hardware
 318          * underneath. This is a requirement from virtualization team.
 319          */
 320         pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA);
 321         if (pch) {
 322                 if (pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
 323                         unsigned short id;
 324                         id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
 325                         dev_priv->pch_id = id;
 326
 327                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 328                                 dev_priv->pch_type = PCH_IBX;
 329                                 dev_priv->num_pch_pll = 2;
 330                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 331                                 WARN_ON(!IS_GEN5(dev));
 332                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 333                                 dev_priv->pch_type = PCH_CPT;
 334                                 dev_priv->num_pch_pll = 2;
 335                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 336                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 337                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 338                                 /* PantherPoint is CPT compatible */
 339                                 dev_priv->pch_type = PCH_CPT;
 340                                 dev_priv->num_pch_pll = 2;
 341                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 342                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 343                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 344                                 dev_priv->pch_type = PCH_LPT;
 345                                 dev_priv->num_pch_pll = 0;
 346                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 347                                 WARN_ON(!IS_HASWELL(dev));
 348                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 349                                 dev_priv->pch_type = PCH_LPT;
 350                                 dev_priv->num_pch_pll = 0;
 351                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 352                                 WARN_ON(!IS_HASWELL(dev));
 353                         }
 354                         BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
 355                 }
 356 #if 0
 357                 pci_dev_put(pch);
 358 #endif
 359         }
 360 }
 361
 362 bool i915_semaphore_is_enabled(struct drm_device *dev)
 363 {
 364         if (INTEL_INFO(dev)->gen < 6)
 365                 return 0;
 366
 367         if (i915_semaphores >= 0)
 368                 return i915_semaphores;
 369
 370 #ifdef CONFIG_INTEL_IOMMU
 371         /* Enable semaphores on SNB when IO remapping is off */
 372         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 373                 return false;
 374 #endif
 375
 376         return 1;
 377 }
 378
 379 static int i915_drm_freeze(struct drm_device *dev)
 380 {
 381         struct drm_i915_private *dev_priv = dev->dev_private;
 382
 383         drm_kms_helper_poll_disable(dev);
 384
 385 #if 0
 386         pci_save_state(dev->pdev);
 387 #endif
 388
 389         /* If KMS is active, we do the leavevt stuff here */
 390         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 391                 int error = i915_gem_idle(dev);
 392                 if (error) {
 393                         device_printf(dev->dev,
 394                                 "GEM idle failed, resume might fail");
 395                         return error;
 396                 }
 397                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 398
 399 #if 0
 400                 intel_modeset_disable(dev);
 401 #endif
 402
 403                 drm_irq_uninstall(dev);
 404         }
 405
 406         i915_save_state(dev);
 407
 408         intel_opregion_fini(dev);
 409
 410         /* Modeset on resume, not lid events */
 411         dev_priv->modeset_on_lid = 0;
 412
 413         return 0;
 414 }
 415
 416 static int
 417 i915_suspend(device_t kdev)
 418 {
 419         struct drm_device *dev;
 420         int error;
 421
 422         dev = device_get_softc(kdev);
 423         if (dev == NULL || dev->dev_private == NULL) {
 424                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 425                 return -ENODEV;
 426         }
 427
 428         DRM_DEBUG_KMS("starting suspend\n");
 429         error = i915_drm_freeze(dev);
 430         if (error)
 431                 return (error);
 432
 433         error = bus_generic_suspend(kdev);
 434         DRM_DEBUG_KMS("finished suspend %d\n", error);
 435         return (error);
 436 }
 437
 438 static int i915_drm_thaw(struct drm_device *dev)
 439 {
 440         struct drm_i915_private *dev_priv = dev->dev_private;
 441         int error = 0;
 442
 443         DRM_LOCK(dev);
 444         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 445                 i915_gem_restore_gtt_mappings(dev);
 446         }
 447
 448         i915_restore_state(dev);
 449         intel_opregion_setup(dev);
 450
 451         /* KMS EnterVT equivalent */
 452         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 453                 dev_priv->mm.suspended = 0;
 454
 455                 error = i915_gem_init_hw(dev);
 456
 457                 if (HAS_PCH_SPLIT(dev))
 458                         ironlake_init_pch_refclk(dev);
 459
 460                 DRM_UNLOCK(dev);
 461                 lockmgr(&dev->mode_config.mutex, LK_EXCLUSIVE);
 462                 drm_mode_config_reset(dev);
 463                 lockmgr(&dev->mode_config.mutex, LK_RELEASE);
 464                 drm_irq_install(dev);
 465
 466                 lockmgr(&dev->mode_config.mutex, LK_EXCLUSIVE);
 467                 /* Resume the modeset for every activated CRTC */
 468                 drm_helper_resume_force_mode(dev);
 469                 lockmgr(&dev->mode_config.mutex, LK_RELEASE);
 470
 471                 if (IS_IRONLAKE_M(dev))
 472                         ironlake_enable_rc6(dev);
 473                 DRM_LOCK(dev);
 474         }
 475
 476         intel_opregion_init(dev);
 477
 478         dev_priv->modeset_on_lid = 0;
 479
 480         DRM_UNLOCK(dev);
 481
 482         return error;
 483 }
 484
 485 static int
 486 i915_resume(device_t kdev)
 487 {
 488         struct drm_device *dev;
 489         int ret;
 490
 491         dev = device_get_softc(kdev);
 492         DRM_DEBUG_KMS("starting resume\n");
 493 #if 0
 494         if (pci_enable_device(dev->pdev))
 495                 return -EIO;
 496
 497         pci_set_master(dev->pdev);
 498 #endif
 499
 500         ret = -i915_drm_thaw(dev);
 501         if (ret != 0)
 502                 return (ret);
 503
 504         drm_kms_helper_poll_enable(dev);
 505         ret = bus_generic_resume(kdev);
 506         DRM_DEBUG_KMS("finished resume %d\n", ret);
 507         return (ret);
 508 }
 509
 510 static int
 511 i915_probe(device_t kdev)
 512 {
 513
 514         return drm_probe(kdev, i915_pciidlist);
 515 }
 516
 517 int i915_modeset;
 518
 519 static int
 520 i915_attach(device_t kdev)
 521 {
 522         struct drm_device *dev;
 523
 524         dev = device_get_softc(kdev);
 525         if (i915_modeset == 1)
 526                 i915_driver_info.driver_features |= DRIVER_MODESET;
 527         dev->driver = &i915_driver_info;
 528         return (drm_attach(kdev, i915_pciidlist));
 529 }
 530
 531 const struct intel_device_info *
 532 i915_get_device_id(int device)
 533 {
 534         const struct intel_gfx_device_id *did;
 535
 536         for (did = &pciidlist[0]; did->device != 0; did++) {
 537                 if (did->device != device)
 538                         continue;
 539                 return (did->info);
 540         }
 541         return (NULL);
 542 }
 543
 544 static device_method_t i915_methods[] = {
 545         /* Device interface */
 546         DEVMETHOD(device_probe,         i915_probe),
 547         DEVMETHOD(device_attach,        i915_attach),
 548         DEVMETHOD(device_suspend,       i915_suspend),
 549         DEVMETHOD(device_resume,        i915_resume),
 550         DEVMETHOD(device_detach,        drm_detach),
 551         DEVMETHOD_END
 552 };
 553
 554 static driver_t i915_driver = {
 555         "drm",
 556         i915_methods,
 557         sizeof(struct drm_device)
 558 };
 559
 560 extern devclass_t drm_devclass;
 561 DRIVER_MODULE_ORDERED(i915kms, vgapci, i915_driver, drm_devclass, 0, 0,
 562     SI_ORDER_ANY);
 563 MODULE_DEPEND(i915kms, drm, 1, 1, 1);
 564 MODULE_DEPEND(i915kms, agp, 1, 1, 1);
 565 MODULE_DEPEND(i915kms, iicbus, 1, 1, 1);
 566 MODULE_DEPEND(i915kms, iic, 1, 1, 1);
 567 MODULE_DEPEND(i915kms, iicbb, 1, 1, 1);
 568
 569 int intel_iommu_enabled = 0;
 570 TUNABLE_INT("drm.i915.intel_iommu_enabled", &intel_iommu_enabled);
 571
 572 int i915_semaphores = -1;
 573 TUNABLE_INT("drm.i915.semaphores", &i915_semaphores);
 574 static int i915_try_reset = 1;
 575 TUNABLE_INT("drm.i915.try_reset", &i915_try_reset);
 576 unsigned int i915_lvds_downclock = 0;
 577 TUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock);
 578 int i915_vbt_sdvo_panel_type = -1;
 579 TUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type);
 580 unsigned int i915_powersave = 1;
 581 TUNABLE_INT("drm.i915.powersave", &i915_powersave);
 582 int i915_enable_fbc = 0;
 583 TUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc);
 584 int i915_enable_rc6 = 0;
 585 TUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6);
 586 int i915_panel_use_ssc = -1;
 587 TUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc);
 588 int i915_panel_ignore_lid = 0;
 589 TUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid);
 590 int i915_modeset = 1;
 591 TUNABLE_INT("drm.i915.modeset", &i915_modeset);
 592 int i915_enable_ppgtt = -1;
 593 TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
 594 int i915_enable_hangcheck = 1;
 595 TUNABLE_INT("drm.i915.enable_hangcheck", &i915_enable_hangcheck);
 596
 597 static int i8xx_do_reset(struct drm_device *dev)
 598 {
 599         struct drm_i915_private *dev_priv = dev->dev_private;
 600
 601         if (IS_I85X(dev))
 602                 return -ENODEV;
 603
 604         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 605         POSTING_READ(D_STATE);
 606
 607         if (IS_I830(dev) || IS_845G(dev)) {
 608                 I915_WRITE(DEBUG_RESET_I830,
 609                            DEBUG_RESET_DISPLAY |
 610                            DEBUG_RESET_RENDER |
 611                            DEBUG_RESET_FULL);
 612                 POSTING_READ(DEBUG_RESET_I830);
 613                 msleep(1);
 614
 615                 I915_WRITE(DEBUG_RESET_I830, 0);
 616                 POSTING_READ(DEBUG_RESET_I830);
 617         }
 618
 619         msleep(1);
 620
 621         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 622         POSTING_READ(D_STATE);
 623
 624         return 0;
 625 }
 626
 627 static int i965_reset_complete(struct drm_device *dev)
 628 {
 629         u8 gdrst;
 630         gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
 631         return (gdrst & 0x1);
 632 }
 633
 634 static int i965_do_reset(struct drm_device *dev)
 635 {
 636         int ret;
 637         u8 gdrst;
 638
 639         /*
 640          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 641          * well as the reset bit (GR/bit 0).  Setting the GR bit
 642          * triggers the reset; when done, the hardware will clear it.
 643          */
 644         gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
 645         pci_write_config(dev->dev, I965_GDRST,
 646                               gdrst | GRDOM_RENDER |
 647                               GRDOM_RESET_ENABLE, 1);
 648         ret =  wait_for(i965_reset_complete(dev), 500);
 649         if (ret)
 650                 return ret;
 651
 652         /* We can't reset render&media without also resetting display ... */
 653         gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
 654         pci_write_config(dev->dev, I965_GDRST,
 655                               gdrst | GRDOM_MEDIA |
 656                               GRDOM_RESET_ENABLE, 1);
 657
 658         return wait_for(i965_reset_complete(dev), 500);
 659 }
 660
 661 static int ironlake_do_reset(struct drm_device *dev)
 662 {
 663         struct drm_i915_private *dev_priv = dev->dev_private;
 664         u32 gdrst;
 665         int ret;
 666
 667         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 668         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 669                    gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
 670         ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 671         if (ret)
 672                 return ret;
 673
 674         /* We can't reset render&media without also resetting display ... */
 675         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 676         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 677                    gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 678         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 679 }
 680
 681 static int gen6_do_reset(struct drm_device *dev)
 682 {
 683         struct drm_i915_private *dev_priv = dev->dev_private;
 684         int ret;
 685
 686         dev_priv = dev->dev_private;
 687
 688         /* Hold gt_lock across reset to prevent any register access
 689          * with forcewake not set correctly
 690          */
 691         lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
 692
 693         /* Reset the chip */
 694
 695         /* GEN6_GDRST is not in the gt power well, no need to check
 696          * for fifo space for the write or forcewake the chip for
 697          * the read
 698          */
 699         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 700
 701         /* Spin waiting for the device to ack the reset request */
 702         ret = _intel_wait_for(dev,
 703             (I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0,
 704             500, 1, "915rst");
 705
 706         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 707         if (dev_priv->forcewake_count)
 708                 dev_priv->gt.force_wake_get(dev_priv);
 709         else
 710                 dev_priv->gt.force_wake_put(dev_priv);
 711
 712         /* Restore fifo count */
 713         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 714
 715         lockmgr(&dev_priv->gt_lock, LK_RELEASE);
 716         return ret;
 717 }
 718
 719 int intel_gpu_reset(struct drm_device *dev)
 720 {
 721         struct drm_i915_private *dev_priv = dev->dev_private;
 722         int ret = -ENODEV;
 723
 724         switch (INTEL_INFO(dev)->gen) {
 725         case 7:
 726         case 6:
 727                 ret = gen6_do_reset(dev);
 728                 break;
 729         case 5:
 730                 ret = ironlake_do_reset(dev);
 731                 break;
 732         case 4:
 733                 ret = i965_do_reset(dev);
 734                 break;
 735         case 2:
 736                 ret = i8xx_do_reset(dev);
 737                 break;
 738         }
 739
 740         /* Also reset the gpu hangman. */
 741         if (dev_priv->stop_rings) {
 742                 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
 743                 dev_priv->stop_rings = 0;
 744                 if (ret == -ENODEV) {
 745                         DRM_ERROR("Reset not implemented, but ignoring "
 746                                   "error for simulated gpu hangs\n");
 747                         ret = 0;
 748                 }
 749         }
 750
 751         return ret;
 752 }
 753
 754 /**
 755  * i915_reset - reset chip after a hang
 756  * @dev: drm device to reset
 757  *
 758  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 759  * reset or otherwise an error code.
 760  *
 761  * Procedure is fairly simple:
 762  *   - reset the chip using the reset reg
 763  *   - re-init context state
 764  *   - re-init hardware status page
 765  *   - re-init ring buffer
 766  *   - re-init interrupt state
 767  *   - re-init display
 768  */
 769 int i915_reset(struct drm_device *dev)
 770 {
 771         drm_i915_private_t *dev_priv = dev->dev_private;
 772         int ret;
 773
 774         if (!i915_try_reset)
 775                 return 0;
 776
 777         DRM_LOCK(dev);
 778
 779         i915_gem_reset(dev);
 780
 781         ret = -ENODEV;
 782         if (time_uptime - dev_priv->last_gpu_reset < 5)
 783                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 784         else
 785                 ret = intel_gpu_reset(dev);
 786
 787         dev_priv->last_gpu_reset = time_uptime;
 788         if (ret) {
 789                 DRM_ERROR("Failed to reset chip.\n");
 790                 DRM_UNLOCK(dev);
 791                 return ret;
 792         }
 793
 794         /* Ok, now get things going again... */
 795
 796         /*
 797          * Everything depends on having the GTT running, so we need to start
 798          * there.  Fortunately we don't need to do this unless we reset the
 799          * chip at a PCI level.
 800          *
 801          * Next we need to restore the context, but we don't use those
 802          * yet either...
 803          *
 804          * Ring buffer needs to be re-initialized in the KMS case, or if X
 805          * was running at the time of the reset (i.e. we weren't VT
 806          * switched away).
 807          */
 808         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 809                         !dev_priv->mm.suspended) {
 810                 struct intel_ring_buffer *ring;
 811                 int i;
 812
 813                 dev_priv->mm.suspended = 0;
 814
 815                 i915_gem_init_swizzling(dev);
 816
 817                 for_each_ring(ring, dev_priv, i)
 818                         ring->init(ring);
 819
 820 #if 0   /* XXX: HW context support */
 821                 i915_gem_context_init(dev);
 822 #endif
 823                 i915_gem_init_ppgtt(dev);
 824
 825                 /*
 826                  * It would make sense to re-init all the other hw state, at
 827                  * least the rps/rc6/emon init done within modeset_init_hw. For
 828                  * some unknown reason, this blows up my ilk, so don't.
 829                  */
 830
 831                 DRM_UNLOCK(dev);
 832
 833                 drm_irq_uninstall(dev);
 834                 drm_irq_install(dev);
 835         } else {
 836                 DRM_UNLOCK(dev);
 837         }
 838
 839         return 0;
 840 }
 841
 842 /* We give fast paths for the really cool registers */
 843 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
 844         ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
 845          ((reg) < 0x40000) &&            \
 846          ((reg) != FORCEWAKE))
 847
 848 static bool IS_DISPLAYREG(u32 reg)
 849 {
 850         /*
 851          * This should make it easier to transition modules over to the
 852          * new register block scheme, since we can do it incrementally.
 853          */
 854         if (reg >= VLV_DISPLAY_BASE)
 855                 return false;
 856
 857         if (reg >= RENDER_RING_BASE &&
 858             reg < RENDER_RING_BASE + 0xff)
 859                 return false;
 860         if (reg >= GEN6_BSD_RING_BASE &&
 861             reg < GEN6_BSD_RING_BASE + 0xff)
 862                 return false;
 863         if (reg >= BLT_RING_BASE &&
 864             reg < BLT_RING_BASE + 0xff)
 865                 return false;
 866
 867         if (reg == PGTBL_ER)
 868                 return false;
 869
 870         if (reg >= IPEIR_I965 &&
 871             reg < HWSTAM)
 872                 return false;
 873
 874         if (reg == MI_MODE)
 875                 return false;
 876
 877         if (reg == GFX_MODE_GEN7)
 878                 return false;
 879
 880         if (reg == RENDER_HWS_PGA_GEN7 ||
 881             reg == BSD_HWS_PGA_GEN7 ||
 882             reg == BLT_HWS_PGA_GEN7)
 883                 return false;
 884
 885         if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
 886             reg == GEN6_BSD_RNCID)
 887                 return false;
 888
 889         if (reg == GEN6_BLITTER_ECOSKPD)
 890                 return false;
 891
 892         if (reg >= 0x4000c &&
 893             reg <= 0x4002c)
 894                 return false;
 895
 896         if (reg >= 0x4f000 &&
 897             reg <= 0x4f08f)
 898                 return false;
 899
 900         if (reg >= 0x4f100 &&
 901             reg <= 0x4f11f)
 902                 return false;
 903
 904         if (reg >= VLV_MASTER_IER &&
 905             reg <= GEN6_PMIER)
 906                 return false;
 907
 908         if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
 909             reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
 910                 return false;
 911
 912         if (reg >= VLV_IIR_RW &&
 913             reg <= VLV_ISR)
 914                 return false;
 915
 916         if (reg == FORCEWAKE_VLV ||
 917             reg == FORCEWAKE_ACK_VLV)
 918                 return false;
 919
 920         if (reg == GEN6_GDRST)
 921                 return false;
 922
 923         switch (reg) {
 924         case _3D_CHICKEN3:
 925         case IVB_CHICKEN3:
 926         case GEN7_COMMON_SLICE_CHICKEN1:
 927         case GEN7_L3CNTLREG1:
 928         case GEN7_L3_CHICKEN_MODE_REGISTER:
 929         case GEN7_ROW_CHICKEN2:
 930         case GEN7_L3SQCREG4:
 931         case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
 932         case GEN7_HALF_SLICE_CHICKEN1:
 933         case GEN6_MBCTL:
 934         case GEN6_UCGCTL2:
 935                 return false;
 936         default:
 937                 break;
 938         }
 939
 940         return true;
 941 }
 942
 943 static void
 944 ilk_dummy_write(struct drm_i915_private *dev_priv)
 945 {
 946         /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
 947          * chip from rc6 before touching it for real. MI_MODE is masked, hence
 948          * harmless to write 0 into. */
 949         I915_WRITE_NOTRACE(MI_MODE, 0);
 950 }
 951
 952 #define __i915_read(x, y) \
 953 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
 954         u##x val = 0; \
 955         if (IS_GEN5(dev_priv->dev)) \
 956                 ilk_dummy_write(dev_priv); \
 957         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 958                 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE); \
 959                 if (dev_priv->forcewake_count == 0) \
 960                         dev_priv->gt.force_wake_get(dev_priv); \
 961                 val = DRM_READ##y(dev_priv->mmio_map, reg);     \
 962                 if (dev_priv->forcewake_count == 0) \
 963                         dev_priv->gt.force_wake_put(dev_priv); \
 964                 lockmgr(&dev_priv->gt_lock, LK_RELEASE); \
 965         } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
 966                 val = DRM_READ##y(dev_priv->mmio_map, reg + 0x180000);  \
 967         } else { \
 968                 val = DRM_READ##y(dev_priv->mmio_map, reg);     \
 969         } \
 970         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
 971         return val; \
 972 }
 973
 974 __i915_read(8, 8)
 975 __i915_read(16, 16)
 976 __i915_read(32, 32)
 977 __i915_read(64, 64)
 978 #undef __i915_read
 979
 980 #define __i915_write(x, y) \
 981 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
 982         u32 __fifo_ret = 0; \
 983         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
 984         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 985                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 986         } \
 987         if (IS_GEN5(dev_priv->dev)) \
 988                 ilk_dummy_write(dev_priv); \
 989         if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
 990                 DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
 991                 I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
 992         } \
 993         if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
 994                 DRM_WRITE##y(dev_priv->mmio_map, reg + 0x180000, val);  \
 995         } else {                                                        \
 996                 DRM_WRITE##y(dev_priv->mmio_map, reg, val);             \
 997         }                                                               \
 998         if (unlikely(__fifo_ret)) { \
 999                 gen6_gt_check_fifodbg(dev_priv); \
1000         } \
1001         if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
1002                 DRM_ERROR("Unclaimed write to %x\n", reg); \
1003                 DRM_WRITE32(dev_priv->mmio_map, GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED);  \
1004         } \
1005 }
1006
1007 __i915_write(8, 8)
1008 __i915_write(16, 16)
1009 __i915_write(32, 32)
1010 __i915_write(64, 64)
1011 #undef __i915_write