2 * Copyright (c) 1997 Semen Ustimenko
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/dev/tx/if_txvar.h,v 1.14.2.1 2002/10/29 01:43:50 semenu Exp $
27 * $DragonFly: src/sys/dev/netif/tx/if_txvar.h,v 1.3 2004/06/02 14:42:55 eirikn Exp $
33 /*#define EPIC_DIAG 1*/
34 /*#define EPIC_USEIOSPACE 1*/
35 /*#define EPIC_EARLY_RX 1*/
38 #define ETHER_MAX_LEN 1518
41 #define ETHER_MIN_LEN 64
44 #define ETHER_CRC_LEN 4
46 #define TX_RING_SIZE 16 /* Leave this a power of 2 */
47 #define RX_RING_SIZE 16 /* And this too, to do not */
48 /* confuse RX(TX)_RING_MASK */
49 #define TX_RING_MASK (TX_RING_SIZE - 1)
50 #define RX_RING_MASK (RX_RING_SIZE - 1)
51 #define ETHER_MAX_FRAME_LEN (ETHER_MAX_LEN + ETHER_CRC_LEN)
53 /* This is driver's structure to define EPIC descriptors */
54 struct epic_rx_buffer {
55 struct mbuf * mbuf; /* mbuf receiving packet */
58 struct epic_tx_buffer {
59 struct mbuf * mbuf; /* mbuf contained packet */
62 /* PHY, known by tx driver */
63 #define EPIC_UNKN_PHY 0x0000
64 #define EPIC_QS6612_PHY 0x0001
65 #define EPIC_AC101_PHY 0x0002
66 #define EPIC_LXT970_PHY 0x0003
67 #define EPIC_SERIAL 0x0004
69 /* Driver status structure */
77 struct callout_handle stat_ch;
81 bus_space_tag_t sc_st;
82 bus_space_handle_t sc_sh;
84 struct epic_rx_buffer rx_buffer[RX_RING_SIZE];
85 struct epic_tx_buffer tx_buffer[TX_RING_SIZE];
87 /* Each element of array MUST be aligned on dword */
88 /* and bounded on PAGE_SIZE */
89 struct epic_rx_desc *rx_desc;
90 struct epic_tx_desc *tx_desc;
91 struct epic_frag_list *tx_flist;
93 u_int32_t tx_threshold;
99 u_int32_t pending_txs;
102 struct mii_softc *physc;
114 #define sc_if arpcom.ac_if
115 #define sc_macaddr arpcom.ac_enaddr
117 #define CSR_WRITE_4(sc, reg, val) \
118 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
119 #define CSR_WRITE_2(sc, reg, val) \
120 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
121 #define CSR_WRITE_1(sc, reg, val) \
122 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
123 #define CSR_READ_4(sc, reg) \
124 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
125 #define CSR_READ_2(sc, reg) \
126 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
127 #define CSR_READ_1(sc, reg) \
128 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
130 #define PHY_READ_2(sc, phy, reg) \
131 epic_read_phy_reg((sc), (phy), (reg))
132 #define PHY_WRITE_2(sc, phy, reg, val) \
133 epic_write_phy_reg((sc), (phy), (reg), (val))
135 /* Macro to get either mbuf cluster or nothing */
136 #define EPIC_MGETCLUSTER(m) \
137 { MGETHDR((m),MB_DONTWAIT,MT_DATA); \
139 MCLGET((m),MB_DONTWAIT); \
140 if( 0 == ((m)->m_flags & M_EXT) ) { \